An AI computing power platform data acceleration system and method based on software and hardware collaboration

Abstract

This invention discloses a data acceleration system and method for an AI computing platform based on hardware and software collaboration. It adjusts the parameters of the baseboard management controller of the computing device through out-of-band protocols and the operating system parameters through in-band protocols to adapt to hardware performance modes. The raw data is cleaned, filtered, and standardized, and the dataset is divided into multiple independent data chunks. A big data processing framework receives the data chunks, dynamically adjusts the number of parallel processing threads based on the real-time load of hardware resources, and allocates computing resources through a task scheduling algorithm. A unified acceleration device adapts to heterogeneous computing hardware such as CPUs, GPUs, and AI accelerator cards, enabling cross-platform hardware and software collaboration. This invention achieves data acceleration for the computing platform through the collaboration of automated equipment optimization, data preprocessing, and parallel processing.

Description

Technical Field

[0001] This invention belongs to the field of Internet technology and relates to an AI computing power platform data acceleration system and method based on software and hardware collaboration. Background Technology

[0002] The rapid development of artificial intelligence technology has placed higher demands on the performance of computing platforms. Existing AI computing platforms often face performance bottlenecks when processing large-scale data. Traditional data processing solutions typically separate hardware resource configuration from software data processing workflows. Hardware-level adjustments often rely on manual intervention or static strategies, failing to adapt dynamically to real-time business scenarios. Software-level data processing workflows also lack the ability to perceive the underlying hardware status.

[0003] This decoupled hardware and software architecture leads to low resource utilization. When business scenarios switch between model training and model inference, the system cannot automatically match the optimal hardware performance mode. For example, the baseboard management controller parameters of the computing equipment and the system parameters of the operating system cannot be optimized in tandem. Simultaneously, there is a lack of effective elastic linkage between data preprocessing and subsequent parallel computing tasks. This makes it difficult to achieve end-to-end data acceleration when facing sudden high-load tasks. Therefore, an acceleration solution that enables deep hardware and software collaboration is needed. Summary of the Invention

[0004] To address the problems existing in the background technology, this invention proposes an AI computing power platform data acceleration system and method based on software and hardware collaboration.

[0005] The first aspect of this application provides a data acceleration system for an AI computing power platform based on hardware and software collaboration, including: a device system optimization component, a data preprocessing component, and a parallel processing component; The device system tuning component is used to adjust the baseboard management controller parameters of the computing power device through out-of-band protocols and to adjust the system parameters of the operating system through in-band protocols, so as to dynamically configure the hardware performance mode according to the business scenario. The data preprocessing component is used to clean, filter, and convert the format of the raw data, and to divide the large-scale dataset into multiple data chunks; The parallel processing component is used to receive data chunks output by the data preprocessing component using the big data processing framework, dynamically adjust the number of parallel processing threads according to the hardware resource load, and allocate computing resources to execute data processing tasks through a task scheduling algorithm.

[0006] Optionally, the device system tuning component is specifically configured as follows: Adjust the parameters of the baseboard management controller of the computing power device via out-of-band protocol; Adjusting the operating system's system parameters via in-band protocols; Based on whether a node is a training node or an inference node, the CPU performance mode is automatically switched; and the CPU mode is optimized in conjunction with memory, hard disk, and network card parameters.

[0007] Optionally, the data preprocessing component is specifically configured as follows: The data is cleaned, deduplicated, and standardized. Data blocks are dynamically segmented based on hardware optimization results.

[0008] Optionally, the parallel processing component is specifically configured as follows: The thread pool is dynamically and elastically adjusted based on real-time hardware load. The load status is fed back to the device system tuning component to form a closed-loop collaboration.

[0009] Optionally, the system further includes: The task scheduling component is used to monitor the file storage directory using workflow management tools, trigger data extraction, transformation and loading processes based on file arrival events, and dynamically generate data cleaning or transformation tasks based on file metadata.

[0010] A second aspect of this application provides a data acceleration method for an AI computing platform based on hardware and software collaboration, comprising: The parameters of the baseboard management controller and operating system of the computing power device are adjusted by adjusting the out-of-band protocol and the in-band protocol respectively to adapt to the hardware performance mode of the current business scenario. The raw input data is cleaned, filtered, and standardized in format, and the processed dataset is then divided into multiple independent data chunks. The data chunks are received using a big data processing framework, the number of parallel processing threads is dynamically adjusted according to the real-time load of hardware resources, and computing resources are allocated to execute data processing tasks through a task scheduling algorithm. Data acceleration of the computing platform is achieved through the coordinated work of automated equipment system optimization, data preprocessing, and parallel processing.

[0011] Optionally, the step of adjusting the parameters of the computing power device includes: The baseboard management controller of the computing power device is connected via an out-of-band network to determine the node attributes of the computing power device. If the computing device is an inference node, the CPU performance mode is adjusted to balanced mode; if the computing device is a training node, the CPU performance mode is adjusted to high-performance mode. The parameters of memory, hard disk, and network card components are adjusted in conjunction with the central processing unit's adjustment strategy, and the operating system's cache size is dynamically adjusted according to the size of the deployment model.

[0012] Optionally, the step of processing the raw data includes: Identify missing and outlier values ​​in the raw data and perform automatic correction. Identify and clean up duplicate metadata based on data generation rules and timestamps; The cleaned data is converted into key-value pairs or standard data formats, and a single large batch of data is split into multiple small batches of data slices.

[0013] Optionally, the parallel processing steps include: Configure the default number of threads in the thread pool; Monitor the actual number of executing threads, and create a new thread pool when the actual number of executing threads exceeds the default number of threads; Dynamically read the load status of each computing node, adjust the number of threads for parallel processing using elastic resource management strategies, and define and manage complex extraction, transformation, and loading processes using workflow management tools.

[0014] Optionally, the method further includes the step of adapting to heterogeneous computing hardware: The heterogeneous computing hardware includes a central processing unit server, a graphics processing unit computing device, and an artificial intelligence accelerator card; By adjusting the baseboard management controller parameters and software system parameters of the aforementioned heterogeneous computing hardware using a unified acceleration device, cross-platform hardware and software collaborative operation can be achieved.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention effectively solves the problem of fragmented resource allocation and data processing in existing technologies by constructing a deep hardware-software collaborative acceleration mechanism. The system can dynamically adjust the operating mode of computing devices based on the characteristics of real-time business scenarios. This adjustment encompasses end-to-end optimization from underlying hardware parameters to upper-level software strategies. At the hardware level, the system implements linked configuration of baseboard management controller parameters and operating system parameters. This linkage ensures that computing devices maintain optimal energy efficiency in different scenarios such as model training or model inference. Hardware resources are no longer in a static or passive response state but can proactively adapt to changes in business needs. At the software level, a flexible linkage is established between data preprocessing and parallel computing tasks. This relationship eliminates data flow delays and stutters in traditional architectures, enabling the data processing flow to adaptively adjust according to the real-time load of computing resources. The system can still maintain a high-efficiency response speed when facing sudden high-load tasks.

[0016] Through the aforementioned collaborative mechanism, this invention significantly improves the overall resource utilization of the computing platform. The system achieves end-to-end data acceleration from hardware configuration to software processing, avoiding performance losses caused by hardware-software mismatch. This enables the platform to improve resource utilization, maintain smooth operation under high loads, and automatically switch between training and inference when processing large-scale data. Attached Figure Description

[0017] Figure 1 This is a flowchart of an AI computing power platform data acceleration system based on hardware and software collaboration in one embodiment of the present invention; Figure 2 This is a schematic diagram of a data acceleration method for an AI computing platform based on hardware and software collaboration, according to one embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In one embodiment, such as Figure 1 As shown, a data acceleration system for an AI computing platform based on hardware and software collaboration is provided. This system corresponds one-to-one with the data acceleration methods for AI computing platforms based on hardware and software collaboration in the following embodiments. The system includes: a device system optimization component, a data preprocessing component, and a parallel processing component. Detailed descriptions of each functional module are as follows: The device system optimization component is used to adjust the baseboard management controller parameters of the computing power device through out-of-band protocols and the system parameters of the operating system through in-band protocols, so as to dynamically configure the hardware performance mode according to the business scenario. The data preprocessing component is used to clean, filter, and convert the format of the raw data, and to divide the large-scale dataset into multiple data chunks. The parallel processing component is used to receive the data chunks output by the data preprocessing component using a big data processing framework, dynamically adjust the number of parallel processing threads according to the hardware resource load, and allocate computing resources to execute data processing tasks through a task scheduling algorithm.

[0020] In one embodiment, the device system tuning component is used to adjust the baseboard management controller parameters of the computing power device through out-of-band protocols and adjust the system parameters of the operating system through in-band protocols, so as to dynamically configure the hardware performance mode according to the business scenario.

[0021] Specifically, the device system tuning component achieves fine-grained dynamic tuning of computing power devices through the collaborative operation of out-of-band and in-band protocols. Out-of-band protocols are primarily used to access and configure the hardware infrastructure management functions of computing power devices at a level outside the operating system. Specifically, the device system tuning component connects to the baseboard management controller of the computing power device using out-of-band protocols. The baseboard management controller is an independent subsystem embedded in the hardware device, responsible for monitoring the physical status of the device, such as temperature, voltage, and fan speed.

[0022] Through out-of-band protocols, the device system tuning component can directly adjust the parameters of the baseboard management controller. For example, when a business scenario requires high-performance computing, the component can issue instructions to adjust the power management strategy of the baseboard management controller, enabling the hardware to enter high-performance mode. This adjustment is independent of the operating system's running state, ensuring the stability and optimization of basic hardware parameters even when the operating system is under heavy load or malfunctions. Simultaneously, the device system tuning component interacts with the operating system's internal parameters through in-band protocols. In-band protocols are mechanisms for adjusting system configurations within the normal operating system channel. The device system tuning component uses in-band protocols to access and modify the operating system's system parameters. These system parameters include, but are not limited to, processor scheduling policies, memory allocation mechanisms, and input / output scheduling priorities.

[0023] In practice, the device system tuning component comprehensively utilizes both protocols based on the real-time needs of the business scenario. For example, in a large-scale model training scenario, the component first adjusts the cooling strategy of the baseboard management controller to a powerful mode via an out-of-band protocol to ensure the hardware does not overheat under high load. Subsequently, the component adjusts the operating system's memory swapping strategy via an in-band protocol to reduce unnecessary disk reads and writes and improve computational efficiency. Through this hardware-software collaborative tuning approach, the system can dynamically configure the hardware performance mode best suited to the current business scenario, thereby maximizing resource utilization while ensuring system stability.

[0024] Furthermore, the device system optimization component includes an out-of-band management module and an in-band management module; the out-of-band management module is used to connect to the baseboard management controller of the computing power device through an out-of-band network, and adjust the CPU performance mode to a balanced mode or a high-performance mode according to the attribute of the computing power device as an inference node or a training node; the in-band management module is used to dynamically adjust the operating system cache size according to the size of the deployed model, and adjust the parameters of memory, hard disk and network card in conjunction with the CPU adjustment strategy.

[0025] Specifically, the device system optimization component consists of an out-of-band management module and an in-band management module, which together enable fine-grained control of the computing power devices. The out-of-band management module connects to the baseboard management controller of the computing power devices via an independent out-of-band network. This connection method is independent of the operating system, ensuring hardware management under any system load. The out-of-band management module formulates corresponding hardware optimization strategies based on the role of the computing power devices in the cluster, i.e., as inference nodes or training nodes. When a device is designated as a training node, the out-of-band management module adjusts the CPU's performance mode to high-performance mode through the baseboard management controller to meet the demands of large-scale data computation. When a device is designated as an inference node, the out-of-band management module may adjust the CPU to a balanced mode, ensuring both response speed and energy efficiency.

[0026] The in-band management module is responsible for parameter optimization within the operating system. First, the in-band management module detects the size of the deployed model. For deep learning models with a large number of parameters, the module dynamically increases the operating system's cache size to reduce disk read / write frequency and accelerate model loading. For smaller models, the cache size is appropriately reduced to free up memory resources for other tasks. More importantly, the in-band management module works in conjunction with the CPU's adjustment strategy. When the CPU's frequency or number of cores changes, the module coordinates adjustments to memory read / write frequency, hard disk I / O scheduling strategies, and network card interrupt aggregation parameters. This coordination ensures synchronized optimization of computing, storage, and network resources, preventing overall performance degradation due to a single resource bottleneck.

[0027] For example, when the system detects that a node needs to load a very large-scale natural language processing model for training, the out-of-band management module intervenes first. Through the out-of-band network instruction board management controller, it locks the node's CPU in high-performance mode and increases the speed of the cooling fan. Immediately afterwards, the in-band management module detects the deployment request for a large model, immediately requests the operating system to expand the page cache, and adjusts the memory prefetching strategy. Simultaneously, based on the fact that the CPU is already in high-performance mode, the in-band management module instructs the driver to enable high-performance timing mode for memory and optimizes the network card's multi-queue mapping to match the CPU's multi-core processing capabilities.

[0028] Through the refined tuning mechanism described above, this invention achieves precise matching between hardware resource configuration and business load. The out-of-band management module ensures rapid switching and stability of the hardware's basic state, while the in-band management module enables deep collaboration between software resources and hardware states. This dual-mode management architecture eliminates the latency caused by the disconnect between software and hardware in traditional tuning, significantly improving the adaptability and processing efficiency of computing devices in different business scenarios, and providing a solid underlying guarantee for efficient data flow and computation.

[0029] In one embodiment, the data preprocessing component is used to clean, filter, and convert the format of the raw data, and to divide the large-scale dataset into multiple data chunks.

[0030] Specifically, the data preprocessing component is dedicated to standardizing the input raw data. First, it performs data cleaning, identifying and removing noisy and redundant information from the raw data. The cleaning process includes removing malformed data records and filling in or correcting missing key fields. Next, it performs data filtering, selecting valid data that meets the requirements based on preset business rules. For example, data points outside the normal physical range or data entries that do not conform to business logic will be automatically filtered out. Finally, it performs format conversion, transforming the cleaned and filtered data into the standardized format required by the target processing framework.

[0031] After cleaning, filtering, and format conversion, the data preprocessing component divides the large-scale dataset into multiple data chunks. The chunking strategy is dynamically adjusted based on the data characteristics and the needs of subsequent computational tasks. For example, for time-series data, the preprocessing component might chunk it according to time windows. For image data, it might chunk it according to batch size. This chunking method transforms the massive dataset into manageable small data units. The chunks are then transmitted to subsequent parallel computing modules via high-speed data channels; this pipelined processing eliminates idle waiting time in data processing.

[0032] In practice, the data preprocessing component works closely with the device system optimization component. When the device system optimization component configures the computing equipment in high-performance mode, the data preprocessing component employs more complex cleaning algorithms to ensure data quality. Conversely, when the equipment is in energy-saving mode, the data preprocessing component optimizes the data partitioning strategy to reduce memory usage. Through this hardware-software collaborative mechanism, the data preprocessing component significantly improves the throughput of data processing. The system achieves dynamic matching between data preparation and computing resources, avoiding computational interruptions caused by inconsistent data formats or excessive data volume. This enables the entire computing platform to process massive amounts of data efficiently and stably.

[0033] Furthermore, the data preprocessing component includes a data cleaning module and a data segmentation module; the data cleaning module is used to perform missing value handling, outlier correction, and timestamp-based metadata deduplication operations; the data segmentation module is used to segment a single batch of data into multiple slices and distribute the slices to multiple schedulers for parallel processing.

[0034] Specifically, the data preprocessing component consists of a data cleaning module and a data segmentation module, responsible for transforming raw data into standardized data that can be directly processed by the computing framework. The data cleaning module is the first line of defense for data quality. It first handles missing values, identifying missing fields in data records and filling or removing them according to preset strategies. Then, it corrects outliers, using statistical methods to identify data points deviating from the normal range and correcting them to a reasonable range. Furthermore, the data cleaning module performs timestamp-based metadata deduplication. For duplicate data records with the same timestamp and key identifiers, the data cleaning module intelligently merges or deletes them to ensure data uniqueness and accuracy.

[0035] After data cleaning, the data segmentation module takes over. This module is responsible for dividing the massive batch of data into multiple smaller data slices. The segmentation strategy is dynamically adjusted based on the computing power of the subsequent parallel processing components. The segmented data slices are distributed to multiple schedulers via high-speed communication channels. Each scheduler manages one or more computing nodes, and the data segmentation module distributes the slices evenly to achieve load balancing. This distribution mechanism allows multiple computing nodes to process different data slices simultaneously, greatly improving the concurrency of data processing.

[0036] For example, when the system receives a batch of sensor data from IoT devices, the data cleaning module is activated first. It filters out records with missing timestamps due to network transmission interruptions and corrects abnormal values ​​caused by sensor malfunctions. For identical data reported repeatedly within the same millisecond, the data cleaning module performs deduplication. After cleaning, the data segmentation module divides the cleaned data into several data chunks according to a fixed-size or dynamic load strategy. These data chunks are quickly distributed to multiple idle schedulers in the cluster. The schedulers then initiate corresponding computing tasks to analyze the data chunks.

[0037] Through the collaborative work of the data cleaning and data segmentation modules, the data preprocessing component effectively solves the problem of dirty and disorganized raw data. The data cleaning module ensures the accuracy of the analysis results, avoiding erroneous conclusions caused by the inclusion of junk data. The data segmentation module breaks through the serial bottleneck of big data processing by distributing tasks to multiple schedulers for parallel processing, significantly shortening data preparation time. This efficient preprocessing mechanism provides high-quality input for upper-level parallel computing, improving the overall system throughput and response speed.

[0038] In one embodiment, the parallel processing component is used to receive data chunks output by the data preprocessing component using a big data processing framework, dynamically adjust the number of parallel processing threads according to the hardware resource load, and allocate computing resources to execute data processing tasks through a task scheduling algorithm.

[0039] The parallel processing component receives data chunks output from the data preprocessing component using a big data processing framework. This framework, as the core distributed computing engine, manages multiple computing nodes within the computing cluster. The parallel processing component distributes the received data chunks to these nodes for distributed processing. During processing, the parallel processing component continuously monitors the load on hardware resources. Monitored metrics include CPU utilization, GPU utilization, memory usage, and network bandwidth throughput.

[0040] Based on real-time hardware resource load, the parallel processing component dynamically adjusts the number of parallel processing threads. When high utilization of the CPU or GPU is detected, the component automatically increases the number of parallel processing threads to fully utilize idle computing resources. Conversely, when memory usage approaches its limit or network bandwidth becomes congested, the parallel processing component reduces the number of parallel processing threads to prevent system crashes due to resource exhaustion. This dynamic adjustment mechanism ensures efficient utilization of computing resources and system stability.

[0041] When allocating computing resources, the parallel processing component employs a task scheduling algorithm. This algorithm intelligently assigns tasks to the most suitable computing nodes based on the size of the data chunks, the complexity of the computational task, and the current load of the computing nodes. For example, for computationally intensive tasks, the algorithm prioritizes assigning them to nodes with higher CPU performance. For tasks with large amounts of data, the algorithm prioritizes assigning them to nodes with larger memory capacities.

[0042] In practice, the parallel processing component and the device system tuning component work together. When the device system tuning component configures the computing power device to high-performance mode, the parallel processing component adopts a more aggressive task scheduling strategy to maximize task concurrency. This collaborative mechanism allows data processing tasks to adaptively adjust based on the real-time hardware status. The system achieves elastic scaling of computing resources, avoiding processing bottlenecks caused by uneven resource allocation. This significantly improves the efficiency of big data processing and the reliability of the system.

[0043] Furthermore, the parallel processing component includes a thread pool management module and a load balancing module; the thread pool management module is used to configure a default number of threads and create a new thread pool when the actual number of executing threads exceeds the default number of threads; the load balancing module is used to dynamically read the load status of the execution device and dynamically adjust the number of threads for parallel processing according to the load status.

[0044] Specifically, the parallel processing component consists of a thread pool management module and a load balancing module, which jointly manage the concurrent execution and resource scheduling of computational tasks. The thread pool management module first configures a default number of threads, which serves as the baseline concurrency level at system startup. When a data processing task is submitted to the system, it is assigned to an idle thread in the thread pool for execution. If, at any given moment, the actual number of threads requiring execution exceeds the preset default number, the thread pool management module automatically detects this congestion. To prevent tasks from queuing, the thread pool management module immediately creates a new thread pool instance. This multi-threaded pool architecture allows for elastic scaling of the system's processing capacity, ensuring that sudden high-concurrency tasks do not lead to system crashes or task loss.

[0045] While the multi-threaded pool runs, the load balancing module continuously monitors the health of the entire system. This module dynamically reads the load status of the execution devices, collecting metrics such as CPU utilization, memory usage, and I / O latency. Based on this real-time data, the load balancing module intelligently determines whether the current number of threads is reasonable. If it detects excessive device load, it sends an instruction to the thread pool management module to reduce the number of threads processing in parallel, thereby freeing up system resources. Conversely, if it detects low device load and available computing power, it instructs the number of threads to be increased, tapping into the hardware's potential performance. This dynamic adjustment mechanism enables fine-grained management of computing resources.

[0046] For example, when the system receives a batch of complex image recognition tasks, the thread pool management module initially processes the first few images using the default number of threads. As the task queue grows rapidly, the actual number of executing threads instantly exceeds the default value. The thread pool management module immediately creates additional thread pools to distribute the tasks. At this time, the load balancing module detects a surge in CPU utilization, determining that the system is on the verge of overload. To maintain stability, the load balancing module instructs the thread pool management module to pause the creation of new threads and appropriately reclaim some idle threads. After the peak task period, the load decreases, and the system automatically returns to a high-concurrency state.

[0047] Through the coordinated operation of the thread pool management module and the load balancing module, the parallel processing component achieves efficient and stable task processing capabilities. The thread pool management module solves the problem of task backlog by effectively handling traffic peaks by creating new thread pools. The load balancing module acts as a system regulator, preventing excessive context switching overhead or resource exhaustion caused by too many threads. This dynamic adjustment strategy, combining hardware and software, allows the system to maximize the utilization of computing resources while ensuring stability, significantly improving the throughput and response speed of big data processing.

[0048] In one embodiment, the device system optimization component, data preprocessing component, and parallel processing component are connected in sequence, and data acceleration throughout the entire process is achieved through the coordinated optimization of software and hardware parameters.

[0049] Specifically, the device system optimization component, data preprocessing component, and parallel processing component are sequentially connected to form a complete data processing pipeline. This connection is reflected not only in the unidirectional flow of data but also in the closed-loop feedback of control commands. The device system optimization component is located at the bottom layer, responsible for providing the hardware-level performance foundation for the entire system. The data preprocessing component is located in the middle layer, responsible for preparing high-quality data for upper-level computations. The parallel processing component is located at the top layer, responsible for executing core data computation tasks. The three components communicate with each other through a unified control bus.

[0050] During operation, the three components achieve end-to-end data acceleration through collaborative optimization of hardware and software parameters. The device system tuning component first identifies the current business scenario, such as model training or model inference. Based on the business scenario, the device system tuning component adjusts the baseboard management controller parameters of the computing equipment through out-of-band protocols and adjusts the system parameters of the operating system through in-band protocols. This adjustment provides an optimized operating environment for the data preprocessing and parallel processing components. For example, when the device system tuning component configures the hardware to high-throughput mode, the data preprocessing component will correspondingly adjust its data cleaning and partitioning strategies to match the higher data throughput capabilities.

[0051] The data preprocessing component cuts the processed data into chunks and passes them to the parallel processing component. The parallel processing component dynamically adjusts the number of parallel processing threads based on hardware resource load and allocates computing resources using a task scheduling algorithm. The parallel processing component then feeds back the current resource usage to the device system tuning component. If the parallel processing component detects resource constraints, it notifies the device system tuning component to further optimize hardware parameters. This closed-loop feedback mechanism enables the three components to work collaboratively as a whole.

[0052] For example, when the system receives a large-scale data analysis task, the device system tuning component first adjusts the power mode of the computing device to high-performance mode and optimizes the operating system's input / output scheduling strategy. After receiving the raw data, the data preprocessing component, based on the optimized system parameters, uses a more efficient data segmentation algorithm to divide the data into data chunks suitable for parallel processing. Upon receiving the data chunks, the parallel processing component dynamically increases the number of parallel processing threads based on the current CPU and memory load and allocates the task to idle computing nodes.

[0053] Through this deep hardware and software collaboration, the system achieves end-to-end acceleration from data input to result output. This avoids the drawbacks of traditional architectures where components operate independently and resources cannot be shared. Data processing bottlenecks are effectively eliminated, and the overall system efficiency is significantly improved. This collaborative optimization mechanism enables the computing platform to flexibly adapt to different business scenarios, providing stable and efficient computing services.

[0054] Furthermore, the AI ​​computing power platform data acceleration system based on hardware and software collaboration also includes a task scheduling component; the task scheduling component is used to monitor the file storage directory using workflow management tools, trigger data extraction, transformation and loading processes based on file arrival events, and dynamically generate data cleaning or transformation tasks based on file metadata.

[0055] Specifically, the task scheduling component utilizes a workflow management tool to monitor the specified file storage directory in real time. The workflow management tool continuously scans the file list and status information in the directory. The monitoring granularity is precise down to the file creation time, size changes, and attribute updates.

[0056] When a new data file is detected being written to the storage directory, the file system generates a file arrival event. The task scheduling component captures this event and uses it as a trigger signal. Once triggered, the task scheduling component immediately initiates a predefined data extraction, transformation, and loading process. The data extraction phase is responsible for reading the raw data from the source file. The data transformation phase standardizes the data format. The data loading phase writes the processed data to the target database or cache.

[0057] Upon initiating the process, the task scheduling component reads the file's metadata. This metadata includes file type, data source identifier, number of records, and field structure information. Based on these metadata characteristics, the task scheduling component intelligently analyzes the data processing requirements. If the metadata indicates that the data contains a large number of missing fields, the task scheduling component dynamically generates targeted data cleaning tasks. If the metadata shows inconsistent data formats, the task scheduling component dynamically generates format conversion tasks. These dynamically generated tasks are inserted into the workflow to ensure the flexibility and accuracy of data processing.

[0058] For example, when a sensor data file is transferred to the storage directory, the task scheduling component immediately detects the file arrival event. It first triggers the data extraction process, reading the binary stream from the file. Subsequently, the task scheduling component parses the metadata in the file header and discovers an inconsistency in the timestamp format of the batch of data. Based on this discovery, the task scheduling component dynamically generates a timestamp standardization conversion task. This conversion task is automatically added to the workflow queue and executed in subsequent conversion stages.

[0059] By introducing a task scheduling component, the system achieves automated data processing. Utilizing an event-triggered mechanism, it eliminates the latency and resource waste associated with traditional polling methods. The ability to dynamically generate tasks based on file metadata enables the system to adapt to diverse data sources and complex business scenarios. This intelligent scheduling strategy ensures the efficiency and accuracy of the data processing flow, providing timely and reliable data support for upper-layer AI computing.

[0060] In one embodiment, the device system optimization component specifically includes an out-of-band management module and an in-band management module. The core function of this component is to execute differentiated hardware performance configuration strategies based on the node attributes of the computing device, i.e., training nodes or inference nodes, and to achieve parameter linkage between the central processing unit, memory, and network interface card.

[0061] Specifically, the out-of-band management module is connected to the baseboard management controller of the computing device via an out-of-band network. When the system detects that the computing device has been assigned as a training node, the out-of-band management module issues an instruction to adjust the performance mode of the central processing unit (CPU) to high-performance mode, locking the CPU to run at its highest frequency to meet the high computing power requirements of large-scale matrix operations. When the system detects that the computing device has been assigned as an inference node, the out-of-band management module adjusts the CPU performance mode to balanced mode, effectively controlling power consumption and heat dissipation while ensuring low latency response.

[0062] More importantly, the in-band management module triggers synchronized adjustments to peripheral hardware parameters after adjusting the CPU mode. When the CPU is switched to high-performance mode, the in-band management module automatically recognizes this state and adjusts memory and network interface card (NIC) parameters accordingly: for memory, the memory frequency is adjusted to high-bandwidth mode, and the memory prefetching strategy is optimized; for the NIC, the NIC interrupt aggregation parameters are adjusted, increasing the interrupt timer in high-throughput scenarios to reduce the context switching overhead caused by the CPU frequently processing NIC interrupts. Conversely, when the CPU switches to balanced mode, the memory and NIC parameters also revert to power-saving mode. This end-to-end parameter linkage of the CPU, memory, and NIC ensures optimal matching of hardware resources.

[0063] In one embodiment, the data preprocessing component includes a data cleaning module and a data segmentation module. A key improvement of this component is that the data segmentation module no longer employs a fixed-size segmentation strategy, but instead dynamically adjusts the segment size based on hardware performance parameters fed back from the device system optimization component.

[0064] Specifically, the data segmentation module first obtains the current hardware performance metrics output by the device system tuning component. If the current hardware is in high-performance mode (training node scenario), the data segmentation module determines that the system has high throughput capabilities, and therefore segments the large-scale dataset into larger data blocks, for example, adjusting them from the default 64MB to 128MB or 256MB, to reduce metadata overhead for task scheduling and maximize bandwidth utilization. If the current hardware is in balanced mode (inference node scenario), the data segmentation module segments the data into smaller data blocks, for example, adjusting them to 32MB, to reduce memory usage per processing cycle, improve task response speed, and adapt to the low latency requirements of inference services. Through a dynamic adaptation mechanism between hardware performance and data block size, the system achieves a precise match between data processing granularity and hardware capacity.

[0065] In one embodiment, the parallel processing component includes a thread pool management module and a load balancing module. This component utilizes a big data processing framework to receive dynamically adjusted data chunks output by the data preprocessing component.

[0066] Specifically, the thread pool management module configures the initial number of parallel processing threads based on the size and type of the received data chunks. The load balancing module continuously monitors the real-time load of each computing node. During operation, if the actual number of executing threads exceeds the default number, or if the hardware load is not at its bottleneck, the load balancing module dynamically creates new thread pools using elastic resource management strategies to further tap into the hardware's potential; otherwise, it reclaims thread resources. The parallel processing component feeds back the processed load status to the device system tuning component, forming a closed-loop collaborative system of hardware tuning, data processing, load feedback, and further tuning.

[0067] Specific limitations regarding the data acceleration system for AI computing power platforms based on hardware-software collaboration can be found in the limitations of the data acceleration method for AI computing power platforms based on hardware-software collaboration mentioned above, and will not be repeated here. Each module in the aforementioned data acceleration system for AI computing power platforms based on hardware-software collaboration can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0068] In one embodiment, such as Figure 2 As shown, a data acceleration method for an AI computing platform based on hardware and software collaboration is provided, including the following specific steps: S10: Adjust the baseboard management controller parameters and operating system parameters of the computing power device through out-of-band and in-band protocols respectively to adapt to the hardware performance mode of the current business scenario.

[0069] S20: Clean, filter, and standardize the input raw data, and then divide the processed dataset into multiple independent data chunks.

[0070] S30: Receive the data chunks using a big data processing framework, dynamically adjust the number of parallel processing threads based on the real-time load of hardware resources, and allocate computing resources to execute data processing tasks through a task scheduling algorithm.

[0071] S40: Through the collaborative work of automated equipment system optimization, data preprocessing, and parallel processing, the computing platform accelerates data.

[0072] Specifically, adjusting the baseboard management controller (BMD) parameters and operating system parameters of the computing power device via out-of-band and in-band protocols to adapt to the hardware performance mode of the current business scenario refers to directly accessing and configuring the BMD of the computing power device using an out-of-band protocol channel independent of the operating system. The BMD is responsible for managing the underlying physical state of the hardware. Through this protocol, the system can adjust the CPU frequency, voltage, and heat dissipation strategy to a balanced mode or a high-performance mode depending on whether the business focuses on model training or model inference. Simultaneously, the kernel parameters of the operating system are modified using an in-band protocol running within the operating system. This includes adjusting memory management strategies, process scheduling priorities, and input / output interrupt handling methods. The adjustment of the in-band protocol and the hardware configuration of the out-of-band protocol work in tandem to ensure a perfect fit between the software operating environment and the hardware physical state, thereby providing the optimal hardware performance mode for subsequent data processing.

[0073] The process involves cleaning, filtering, and standardizing the input raw data, and then dividing the processed dataset into multiple independent data chunks. Specifically, this means performing strict data quality control before the data enters the computing core. The cleaning process includes identifying and removing invalid records, correcting outlier values, and filling in missing fields. The filtering process selects high-value data subsets based on preset business rules. The format standardization process converts data from different sources and with different structures into a unified format that the computing framework can recognize. After completing the above preprocessing, the system uses an intelligent segmentation algorithm to divide the massive dataset into smaller, independent data chunks according to data characteristics and computing requirements. These data chunks are independent of each other, facilitating subsequent parallel distribution and processing.

[0074] The process involves using a big data processing framework to receive data chunks, dynamically adjusting the number of parallel processing threads based on real-time hardware load, and allocating computing resources to execute data processing tasks through a task scheduling algorithm. Specifically, the big data processing framework acts as the core execution engine, receiving data chunks from the preprocessing stage. The framework integrates a real-time monitoring mechanism that continuously collects data on CPU utilization, GPU usage, remaining memory capacity, and network bandwidth usage. Based on this real-time load data, the framework dynamically increases or decreases the number of parallel processing threads. When resources are abundant, threads are added to improve concurrency; when resources are scarce, threads are reduced to prevent system overload. Simultaneously, the task scheduling algorithm intelligently allocates data chunks to the most suitable computing nodes based on the current load and task characteristics of each computing node, achieving load balancing within the cluster.

[0075] The aforementioned data acceleration of the computing platform is achieved through the coordinated work of automated equipment system optimization, data preprocessing, and parallel processing. Specifically, this refers to the establishment of a closed-loop feedback control system. Equipment system optimization lays an efficient hardware foundation for data preprocessing and parallel processing. Data preprocessing provides high-quality, standardized data input for parallel processing. The load feedback generated by parallel processing, in turn, guides equipment system optimization to further optimize hardware parameters. These three stages are no longer isolated steps but form a tightly coupled organic whole. Through this end-to-end collaborative optimization, the system eliminates bottlenecks such as hardware-software mismatch, poor data flow, and uneven resource allocation found in traditional architectures, thereby significantly improving the data processing speed and operational efficiency of the entire computing platform.

[0076] In one embodiment, step S10, i.e., the step of adjusting the computing power device parameters, further includes the following steps: S11: Determine the node attributes of the computing power device by connecting to the baseboard management controller of the computing power device via an out-of-band network; S12: If the computing device is an inference node, adjust the CPU performance mode to balanced mode; if the computing device is a training node, adjust the CPU performance mode to high-performance mode. S13: Adjusts the parameters of memory, hard disk and network card components in conjunction with the central processing unit's adjustment strategy, and dynamically adjusts the operating system's cache size according to the size of the deployment model.

[0077] Specifically, the step of adjusting the parameters of the computing power device refers to establishing a fine-grained hardware resource configuration process based on business attributes. This process first establishes a communication connection with the baseboard management controller built into the computing power device using an out-of-band network channel independent of the operating system. The baseboard management controller, as the core of hardware-level management, provides low-level access permissions to the physical state of the device. Through this connection, the system reads the device's configuration information and accurately determines the node attribute of the current computing power device in the cluster, that is, identifies whether the device is an inference node used to process real-time requests or a training node used for model iterative optimization.

[0078] After identifying the node attributes, the system executes a differentiated CPU performance mode adjustment strategy. When the computing device is determined to be an inference node, considering that inference services are typically latency-sensitive but have large load fluctuations, the system adjusts the CPU performance mode to a balanced mode. This mode provides sufficient computing power while also taking into account power consumption control and heat dissipation management. When the computing device is determined to be a training node, given that model training tasks are computationally intensive and long-lasting, the system adjusts the CPU performance mode to a high-performance mode. This mode locks in a high-frequency operating state to ensure that the computing cores are always in an optimal performance output state, avoiding performance fluctuations caused by dynamic frequency adjustments.

[0079] After adjusting the CPU parameters, the system further implements end-to-end parameter coordination. Based on the CPU's adjustment strategy, the system synchronously adjusts the parameters of memory, hard drive, and network interface card (NIC) components. For example, in high-performance mode, the system increases the memory's operating frequency, optimizes the hard drive's I / O scheduling algorithm, and adjusts the NIC's interrupt aggregation strategy to eliminate bottlenecks imposed by peripheral components on CPU performance. Simultaneously, the system monitors the size of the deployed model in real time. For models with a large number of parameters, the system dynamically increases the operating system's cache size to reduce frequent disk read operations. For smaller models, the cache is appropriately reduced to free up memory resources for data computation.

[0080] For example, when a server is configured as a training node for a large-scale language model, the out-of-band management module first sets the CPU's power policy to high-performance mode via the out-of-band network instruction board management controller. Subsequently, the system detects that the number of model parameters deployed is extremely large and immediately adjusts the page cache size to the maximum threshold via in-band protocol instructions to the operating system. Simultaneously, the memory controller is configured to low-latency mode, and the network card driver is configured to multi-queue high-throughput mode. This deep coordination of hardware and software parameters enables the device to handle heavy training tasks optimally, significantly improving the overall operating efficiency and stability of the computing platform.

[0081] In one embodiment, step S20, i.e., processing the original data, further includes the following steps: S21: Identify missing and outlier values ​​in the raw data and perform automatic correction. S22: Identify and clean up duplicate metadata based on data generation rules and timestamps; S23: Convert the cleaned data into key-value pairs or standard data format, and split a single large batch of data into multiple small batch data slices.

[0082] Specifically, the steps for processing the raw data refer to building an automated, highly reliable data quality improvement and preparation process. This process first performs a deep scan of the input raw data to identify any data quality issues. The system automatically detects missing values ​​in the data records—that is, null values ​​or invalid placeholders in certain key fields—using preset statistical models or business rules. Simultaneously, the system uses numerical distribution analysis to identify outliers that deviate from the normal range. After identification, the system performs automatic correction operations, such as filling missing values ​​with interpolation of preceding and following data, or replacing outlier values ​​with boundary values, thereby ensuring data integrity and logical consistency.

[0083] After numerical correction, the system further performs metadata deduplication and cleanup. This step makes a comprehensive judgment based on the business rules that generated the data and the timestamp carried by each record. The system analyzes the unique identifier of the data and combines it with the order of the timestamps to identify duplicate records caused by network retransmission or collection errors. For redundant metadata with the same identifier and overlapping or extremely close timestamps, the system performs a cleanup operation, retaining only the latest or most complete record. This step effectively eliminates data redundancy and reduces the burden of subsequent storage and computation.

[0084] After data cleaning, the system performs format conversion and data segmentation. The system uniformly converts the cleaned heterogeneous data into a key-value pair structure or an industry-standard data format. This standardization process allows data from different sources to be uniformly recognized by the computing framework. Subsequently, for large-scale data received in a single batch, the system uses a dynamic segmentation algorithm to divide it into multiple smaller, more manageable independent data slices. These data slices maintain the logical integrity of the data and are sized to suit subsequent parallel computing units.

[0085] For example, when the system receives a batch of time-series data from industrial sensors, it first identifies extreme anomalies in some temperature readings caused by signal interference and corrects them to the average value of nearby times. Next, the system finds three identical device status reports within the same millisecond. Based on timestamp deduplication rules, the system retains the first record and deletes the subsequent two. Finally, the system encapsulates the cleaned data into a standard key-value pair format and divides it into dozens of data chunks of fixed size. These data chunks are then distributed to the computing cluster, achieving efficient data flow and processing.

[0086] This invention transforms raw, dirty data into high-quality, computationally ready data. Automatic correction and deduplication mechanisms significantly improve data accuracy, preventing erroneous data from misleading model training. Format standardization and data partitioning break through the serial bottleneck of data processing, providing a foundation for large-scale parallel computing, thereby improving the overall data throughput efficiency and response speed of the computing platform.

[0087] In one embodiment, step S30, i.e., the parallel processing, further includes the following steps: S31: Configure the default number of threads in the thread pool; S32: Monitor the actual number of executing threads. When the actual number of executing threads exceeds the default number of threads, create a new thread pool. S33: Dynamically read the load status of each computing node, adjust the number of threads for parallel processing using elastic resource management strategies, and define and manage complex extraction, transformation, and loading processes using workflow management tools.

[0088] Specifically, the parallel processing steps refer to building a high-efficiency computing execution system with elastic scalability and automated process management. This system first initializes a thread pool and configures it with a default number of threads. This default number is a baseline concurrency level set based on the system's basic hardware configuration and average business load, used to handle daily computing tasks. The thread pool, as the core container for task execution, is responsible for receiving, queuing, and executing tasks.

[0089] During system operation, a real-time monitoring mechanism continuously tracks changes in the actual number of executing threads. When peak business periods arrive and the task queue rapidly accumulates, causing the actual number of required execution threads to exceed the preset default number, the system immediately triggers a scaling mechanism. At this point, the system does not simply block tasks but dynamically creates new thread pool instances. This new thread pool takes over the overflowing tasks and works in parallel with the original thread pool. This multi-threaded pool architecture effectively avoids the performance bottleneck of a single thread pool when resources are exhausted, ensuring task processing capabilities in high-concurrency scenarios.

[0090] To further optimize resource utilization, the system employs a flexible resource management strategy. This strategy works by dynamically reading the real-time load of each computing node in the cluster. Monitoring metrics include CPU utilization, remaining memory space, and I / O latency. Based on this load data, the system intelligently adjusts the number of threads for parallel processing. When node load is low, the number of threads is increased to fully utilize idle computing power; when node load is too high, the number of threads is reduced to prevent system crashes. This dynamic adjustment mechanism enables fine-grained allocation of computing resources. Furthermore, this step utilizes a workflow management tool to define and manage complex extraction, transformation, and loading processes. The workflow management tool orchestrates the entire data processing process as a visual task dependency graph. It coordinates every step of data extraction, format conversion, and final loading into the target storage. Through the workflow management tool, the system can automatically handle dependencies between tasks, ensuring data is processed in the correct order and logic, thereby achieving fully automated scheduling.

[0091] For example, when the system receives a sudden surge of massive image data, the default thread pool quickly reaches full capacity. The system then creates a second thread pool to alleviate the pressure. Simultaneously, the elastic resource management strategy detects low memory usage on some computing nodes and instructs the addition of processing threads on these nodes. The workflow management tool ensures that subsequent preprocessing tasks are automatically triggered after the image extraction task is completed. This collaborative mechanism significantly improves the system's throughput and stability.

[0092] In one embodiment, the AI ​​computing power platform data acceleration method based on software and hardware collaboration further includes a step of adapting to heterogeneous computing hardware: The heterogeneous computing hardware includes a central processing unit server, a graphics processing unit computing device, and an artificial intelligence accelerator card; By adjusting the baseboard management controller parameters and software system parameters of the aforementioned heterogeneous computing hardware using a unified acceleration device, cross-platform hardware and software collaborative operation can be achieved.

[0093] Specifically, the AI ​​computing platform data acceleration method based on hardware and software collaboration also includes a step of adapting to heterogeneous computing hardware. This step aims to address the differences in architecture and performance characteristics among different computing units. The heterogeneous computing hardware includes central processing unit servers, graphics processing unit computing devices, and artificial intelligence accelerator cards. These hardware devices are respectively adept at handling general-purpose computing, massively parallel computing, and specific artificial intelligence tensor operations.

[0094] To achieve unified management of these different hardware components, the system introduces a unified acceleration device. This device acts as an intermediary layer for software and hardware interaction, providing a unified configuration interface upwards and being compatible with different hardware control protocols downwards. Through this unified acceleration device, the system can overcome hardware differences and execute standardized adjustment commands. It can not only access and adjust the parameters of the baseboard management controllers of various hardware components, but also synchronously configure the matching software system parameters.

[0095] In practice, this method first identifies the type of hardware being accessed. If it's a central processing unit (CPU) server, the unified acceleration device adjusts its core frequency and power management strategy via out-of-band protocols and configures the operating system's process scheduler. If it's a graphics processing unit (GPU) computing device, the system adjusts its core clock frequency and memory frequency and loads the corresponding graphics driver optimization parameters. If it's an AI accelerator card, the system configures its dedicated hardware acceleration engine and adjusts the runtime software library parameters.

[0096] For example, when a graphics processing unit (GPU) and an AI accelerator card are deployed simultaneously in a cluster, a unified acceleration device comes into play. It first adjusts the GPU's cooling fan strategy to a high-speed mode via the baseboard management controller to handle high loads. Simultaneously, it stabilizes the voltage of the AI ​​accelerator card within its optimal operating range. At the software level, the system allocates a dedicated memory pool for the GPU and loads specific computational graph optimization libraries for the AI ​​accelerator card. This cross-platform hardware and software collaboration allows computing resources with different architectures to leverage their respective performance advantages, creating synergy.

[0097] This invention breaks down management barriers between heterogeneous hardware. A unified acceleration device enables consistent parameter adjustments for the central processing unit, graphics processing unit, and AI accelerator card. This cross-platform collaborative mechanism ensures that software configuration and hardware performance remain aligned. It significantly improves the management efficiency of heterogeneous computing environments, reduces performance losses caused by software-hardware incompatibility, and provides a stable and efficient underlying operating environment for AI computing platforms.

[0098] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0099] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A data acceleration system for an AI computing platform based on hardware and software collaboration, characterized in that, include: Equipment system optimization components, data preprocessing components, and parallel processing components; The device system tuning component is used to adjust the baseboard management controller parameters of the computing power device through out-of-band protocols and to adjust the system parameters of the operating system through in-band protocols, so as to dynamically configure the hardware performance mode according to the business scenario. The data preprocessing component is used to clean, filter, and convert the format of the raw data, and to divide the large-scale dataset into multiple data chunks; The parallel processing component is used to receive data chunks output by the data preprocessing component using the big data processing framework, dynamically adjust the number of parallel processing threads according to the hardware resource load, and allocate computing resources to execute data processing tasks through a task scheduling algorithm.

2. The AI ​​computing power platform data acceleration system based on hardware and software collaboration according to claim 1, characterized in that, The device system tuning component is specifically configured as follows: Adjust the parameters of the baseboard management controller of the computing power device via out-of-band protocol; Adjusting the operating system's system parameters via in-band protocols; Based on whether a node is a training node or an inference node, the CPU performance mode is automatically switched; and the CPU mode is optimized in conjunction with memory, hard disk, and network card parameters.

3. The hardware-software collaboration based AI computing power platform data acceleration system of claim 1, wherein, The data preprocessing component is specifically configured as follows: The data is cleaned, deduplicated, and standardized. Data blocks are dynamically segmented based on hardware optimization results.

4. The hardware-software collaboration based AI computing power platform data acceleration system of claim 1, wherein, The parallel processing component is specifically configured as follows: The thread pool is dynamically and elastically adjusted based on real-time hardware load. The load status is fed back to the device system tuning component to form a closed-loop collaboration.

5. The hardware-software collaboration based AI computing power platform data acceleration system according to any one of claims 1 to 4, characterized in that, The system also includes: The task scheduling component is used to monitor the file storage directory using workflow management tools, trigger data extraction, transformation and loading processes based on file arrival events, and dynamically generate data cleaning or transformation tasks based on file metadata.

6. A hardware-software collaboration-based AI computing power platform data acceleration method, characterized in that, The system applied to any one of claims 1 to 5 comprises: The parameters of the baseboard management controller and operating system of the computing power device are adjusted by adjusting the out-of-band protocol and the in-band protocol respectively to adapt to the hardware performance mode of the current business scenario. The raw input data is cleaned, filtered, and standardized in format, and the processed dataset is then divided into multiple independent data chunks. The data chunks are received using a big data processing framework, the number of parallel processing threads is dynamically adjusted according to the real-time load of hardware resources, and computing resources are allocated to execute data processing tasks through a task scheduling algorithm. Data acceleration of the computing platform is achieved through the coordinated work of automated equipment system optimization, data preprocessing, and parallel processing.

7. The hardware-software co-operative AI computing power platform data acceleration method according to claim 6, characterized in that, The steps for adjusting the parameters of the computing power equipment include: The baseboard management controller of the computing power device is connected via an out-of-band network to determine the node attributes of the computing power device. If the computing device is an inference node, then adjust the CPU performance mode to balanced mode; If the computing device is a training node, then adjust the CPU performance mode to high-performance mode; The parameters of memory, hard disk, and network card components are adjusted in conjunction with the central processing unit's adjustment strategy, and the operating system's cache size is dynamically adjusted according to the size of the deployment model.

8. The data acceleration method for an AI computing platform based on hardware and software collaboration according to claim 3, characterized in that, The steps for processing the raw data include: Identify missing and outlier values ​​in the raw data and perform automatic correction. Identify and clean up duplicate metadata based on data generation rules and timestamps; The cleaned data is converted into key-value pairs or standard data formats, and a single large batch of data is split into multiple small batches of data slices.

9. The data acceleration method for an AI computing platform based on hardware and software collaboration according to claim 6, characterized in that, The parallel processing steps include: Configure the default number of threads in the thread pool; Monitor the actual number of executing threads, and create a new thread pool when the actual number of executing threads exceeds the default number of threads; Dynamically read the load status of each computing node, adjust the number of threads for parallel processing using elastic resource management strategies, and define and manage complex extraction, transformation, and loading processes using workflow management tools.

10. The hardware-software co-operative AI computing power platform data acceleration method according to claim 6, characterized in that, The method also includes a step of adapting to heterogeneous computing hardware: The heterogeneous computing hardware includes a central processing unit server, a graphics processing unit computing device, and an artificial intelligence accelerator card; By adjusting the baseboard management controller parameters and software system parameters of the heterogeneous computing hardware through a unified acceleration device, cross-platform hardware and software collaborative operation can be achieved.

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