A CPU-FPGA hybrid acceleration method for small file erasure code data recovery

Abstract

This invention presents a CPU-FPGA hybrid acceleration method for erasure coding data recovery of small files, belonging to the field of distributed storage and heterogeneous computing technology. By constructing a "pipelinless" pure combinational logic FPGA decoder, this invention eliminates the fill and drain overhead of traditional deep pipeline architectures. It combines a GF(2) domain Gaussian elimination matrix inversion strategy based on Cauchy matrix binary decomposition on the CPU side with a double-buffered delay masking mechanism, achieving low-latency, high-throughput hardware-software collaborative data recovery. The CPU handles the control-intensive matrix inversion task, while the FPGA focuses on the computationally intensive parallel data reconstruction task. The two are interconnected via a high-speed PCIe bus and employ a distributed-aggregated DMA mechanism to optimize small file transfer efficiency. This invention effectively solves the technical challenges of high startup latency, poor architectural flexibility, and low collaborative efficiency in erasure coding recovery in small file scenarios, and is suitable for low-latency cloud storage and edge computing infrastructure.

Description

Technical Field

[0001] This invention relates to the field of distributed storage and heterogeneous computing technology, specifically to a CPU-FPGA hybrid acceleration method for small file erasure coding data recovery. Background Technology

[0002] With the deepening development of big data and cloud computing applications, efficient storage and data reliability assurance of massive small files have become important issues in the field of distributed storage. Small files typically refer to unstructured data objects with a size significantly lower than the system's default block threshold (KB level), and are widely found in typical scenarios such as intermediate feature datasets for artificial intelligence, financial digital vouchers, and medical image archives. These scenarios not only face massive data volumes but also place stringent demands on the real-time response capabilities and throughput performance of storage systems. However, the inherent storage fragmentation and metadata management bottlenecks of small files make this problem extremely challenging.

[0003] To ensure data reliability, distributed storage systems typically employ multiple replicas or erasure coding techniques. While multiple replicas offer high read performance, they are expensive. Erasure coding, particularly based on Reed-Solomon coding, can significantly reduce storage redundancy under the same fault tolerance conditions, and is therefore widely integrated into mainstream distributed storage systems. Despite its clear advantages in storage efficiency, erasure coding still faces dual performance challenges in terms of computation and I / O in scenarios involving the frequent recovery of small files.

[0004] First, small file recovery faces a severe "long-tail latency" problem, and pure software solutions are insufficient to meet high-concurrency requirements. In a distributed environment, recovering a small file involves not only complex finite-field matrix multiplication and addition operations, but also intensive small I / O requests and metadata access. For systems using CPU software decoding, a massive number of small files can cause the CPU to frequently fall into context switching and interrupt handling, resulting in cache pollution and CPU thrashing, which seriously affects the service quality of online services.

[0005] Secondly, traditional hardware acceleration architectures suffer from a "pipeline efficiency gap" when processing small files. While accelerating erasure coding using GPUs or FPGAs has become a research hotspot, most existing solutions are designed for large data streams and generally employ deep pipeline structures to pursue maximum throughput. However, for KB-level small files, the data stream length is often less than the pipeline depth, causing the hardware to spend most of its time in a "fill and drain" waiting state, resulting in excessively high startup latency. When processing objects smaller than 16KB, the effective throughput of traditional FPGA accelerators drops precipitously, even becoming less efficient than pure software solutions.

[0006] Furthermore, existing architectures lack hardware-software co-optimization for small file characteristics. Erasure coding recovery involves two stages: "matrix inversion" and "data reconstruction." Matrix inversion involves complex conditional branching and dynamic control, which is a strength of CPUs; while data reconstruction is a massively parallel XOR operation, suitable for FPGA processing. Existing solutions often attempt to offload all tasks to hardware or retain them entirely in software, failing to perform reasonable heterogeneous task allocation based on task characteristics. This strategy leads to inefficient use of hardware resources and a significant increase in communication overhead.

[0007] Furthermore, the time consumed by frequent control interactions, interrupt responses, and data transfers between the CPU and FPGA in existing solutions may even exceed the time spent on erasure coding calculations themselves, leading to a phenomenon where "speeding up actually slows down." Off-chip caches or limited I / O channels introduced to address the bandwidth mismatch between the host and FPGA actually generate additional communication overhead and memory management costs in small file recovery, further exacerbating decoding response latency.

[0008] In summary, there is an urgent need for a new software and hardware collaborative architecture that can combine the advantages of software flexibility and hardware low latency, and effectively eliminate pipeline startup overhead, in order to solve multiple challenges in small file erasure coding data recovery, such as high startup latency, poor architectural flexibility, low collaborative efficiency, and large interaction overhead. Summary of the Invention

[0009] The technical problem to be solved by this invention is that existing erasure coding data recovery schemes face problems such as high pipeline startup latency, poor architectural flexibility, low hardware and software coordination efficiency, and large data interaction overhead in small file high-frequency recovery scenarios. This invention provides a CPU-FPGA hybrid acceleration method for small file erasure coding data recovery, which can eliminate pipeline startup overhead while achieving efficient hardware and software coordination, and significantly improve the speed and energy efficiency of small file data recovery.

[0010] To solve the above problems, the present invention is achieved through the following technical solution:

[0011] A CPU-FPGA hybrid acceleration method for erasure coding data recovery of small files includes the following steps:

[0012] Step 1: The CPU dynamically determines the index and number of data blocks to be recovered based on the erasure coding scheme parameters and data block failure modes, and extracts the survival submatrix corresponding to the available data blocks from the coding matrix.

[0013] Step 2: The CPU performs Gaussian elimination based on the GF(2) finite field on the survival submatrix to obtain the inverse matrix of the recovery coefficients; wherein, the Gaussian elimination method utilizes the characteristic that the Cauchy type Reed-Solomon code generating matrix can be expanded into a GF(2) binary matrix to transform the finite field multiplication and division into bitwise XOR and bitwise AND operations;

[0014] Step 3: The CPU transmits the inverse recovery coefficient matrix, control information, and surviving data blocks in batches to the FPGA via the PCIe high-speed interface and the distributed-aggregated direct memory access mechanism.

[0015] Step 4: The FPGA side uses a decoding unit based on pure combinational logic to perform a parallel XOR operation on the surviving data block according to the inverse matrix of the recovery coefficient, and completes the reconstruction of the failed data block within a single combinational logic propagation delay.

[0016] Step 5: The FPGA sends the recovered data blocks back to the CPU via the PCIe interface. The CPU integrates and reconstructs the received data blocks and performs verification to complete the data recovery.

[0017] Step 6: During the execution of steps 3 to 5, the FPGA side alternately performs data reception and decoding calculation between two independent buffers through a double buffering mechanism, so that the PCIe data transmission process and the FPGA decoding calculation process can be carried out in parallel, thereby achieving communication delay masking.

[0018] Furthermore, in step 2, the specific steps of the Gaussian elimination operation based on the GF(2) finite field are as follows:

[0019] (21) Construct an augmented matrix by horizontally concatenating the survival submatrix with the identity matrix of the same order to form an augmented matrix [A|I];

[0020] (22) Column-wise iterative elimination: For the i-th column of the augmented matrix, if the pivot position Aug[i][i] is 0, then search for the first row below the i-th row where Aug[j][i] is 1 and swap it with the i-th row; if there is no pivot with a value of 1, then determine that the matrix is ​​singular on GF(2) and terminate.

[0021] (23) After establishing the pivot, for all rows where index k is not equal to i and Aug[k][i] is 1, perform a bitwise XOR operation Aug[k]←Aug[k]⊕Aug[i] to complete the elimination;

[0022] (24) After the iteration, the left half of the augmented matrix is ​​transformed into the identity matrix, and the right half is the inverse matrix of the recovery coefficient.

[0023] Furthermore, in step 4, the decoding unit based on pure combinational logic includes a data receiving module, a combinational logic calculation module, and a data sending module, and the three modules are coordinated by a finite state machine.

[0024] The data receiving module is used to receive the inverse recovery coefficient matrix and the surviving data block from the PCIe interface, and write them into the FPGA on-chip register file and on-chip memory, respectively.

[0025] The combinational logic calculation module expands complex finite field operations into an XOR gate array and uses pure combinational logic circuits to perform parallel XOR operations. For each data block to be recovered, according to the coefficient value of the corresponding row in the recovery coefficient inverse matrix, the surviving data blocks with a coefficient of 1 are XORed bit by bit. The calculation of all data blocks to be recovered is completed in parallel.

[0026] The data transmission module is used to transmit the reconstructed data blocks back to the CPU via the PCIe interface.

[0027] Furthermore, the finite state machine is divided into five states:

[0028] Idle waiting state: Initially idle state, waiting for a start signal from the PCIe interface. When a transmission request sent by the host is detected, it enters the data receiving state.

[0029] Data reception status: The recovery coefficient inverse matrix and surviving data blocks are received through the PCIe interface and written to the internal buffer. The data volume is monitored in real time during the reception process, and the combinational logic calculation state is entered after the conditions are met.

[0030] Combinational logic computation status: The combinational logic computation module is started to perform an XOR operation. After the data reconstruction is completed, the result is stored in the transmission buffer.

[0031] Sending ready state: Set the data packet header information and load it into the first-in-first-out (FIFO) queue;

[0032] Data transmission status: The recovered data is transmitted back to the host memory via the PCIe interface using direct memory access. After the data transmission is completed, the system returns to the idle waiting state.

[0033] Furthermore, in step 6, the specific implementation of the double buffering mechanism is as follows:

[0034] Two independent data buffers are set up on the FPGA side, denoted as buffer A and buffer B respectively;

[0035] When buffer A receives a new batch of recovery coefficient inverse matrix and surviving data blocks transmitted by the CPU via PCIe, buffer B simultaneously performs combinational logic decoding calculations on the previously received data.

[0036] After buffer B completes its calculations, it sends the recovered data block back to the CPU. Meanwhile, buffer A completes its data reception and enters the decoding calculation stage.

[0037] The roles of buffer A and buffer B are constantly switched, forming a continuous data transmission and decoding computation pipeline, which completely hides the PCIe communication latency within the FPGA parallel computing cycle.

[0038] Furthermore, in step 3, the distributed-aggregated direct memory access mechanism allows the CPU to submit multiple small data block descriptors with non-contiguous physical addresses in batches through a single instruction. The direct memory access engine automatically completes the aggregation and transmission of multiple data segments, reducing the number of CPU interrupt responses and the packet header overhead of the PCIe transaction layer.

[0039] Furthermore, the data packets transmitted between the CPU and the FPGA adopt a unified format, and each data packet consists of a packet header and a variable-length payload. The packet header includes a packet type field, a data block index field, a payload length field, a checksum field, and a sequence number field. The data receiving module on the FPGA completes the data distribution decision within a single clock cycle by parsing the packet type field in the packet header, routing the recovery coefficient inverse matrix to the register file and the surviving data blocks to the on-chip memory.

[0040] Furthermore, the decoding unit on the FPGA side adopts a parameterized design, which enables flexible adaptation to different erasure coding schemes through configuration parameters. The configuration parameters include the number of data blocks, the number of parity blocks, the finite field width, and the number of data block bytes processed in a single operation.

[0041] A CPU-FPGA hybrid acceleration system for erasure coding data recovery of small files is provided to execute the above method. It includes a CPU-side module and an FPGA-side module, which are interconnected via a PCIe high-speed bus.

[0042] The CPU module includes:

[0043] The data block location unit is used to dynamically determine the index and number of data blocks to be recovered based on erasure coding scheme parameters and data block failure modes, and to extract the survival submatrix from the coding matrix.

[0044] The matrix inversion unit is used to perform the inversion operation on the survival submatrix using Gaussian elimination over the GF(2) finite field to obtain the restoration coefficient inverse matrix;

[0045] The control information generation unit is used to generate control information including the index of the block to be recovered, the data length, and the matrix column positions.

[0046] The data integration and verification unit is used to receive the recovered data block returned by the FPGA, reassemble and verify the data integrity;

[0047] The FPGA terminal module includes:

[0048] The data receiving module is used to receive and cache the recovery coefficient inverse matrix, control information, and surviving data blocks from the PCIe interface;

[0049] The combinational logic decoding module uses a pure combinational logic circuit to construct an XOR gate array, which is used to perform parallel XOR operations on the surviving data blocks according to the inverse matrix of the recovery coefficients, and complete data reconstruction within a single combinational logic propagation delay.

[0050] The data transmission module is used to transmit the reconstructed data blocks back to the CPU via the PCIe interface;

[0051] A finite state machine is used to coordinate the workflow of the data receiving module, the combinational logic decoding module, and the data sending module.

[0052] The dual-buffered storage module sets up two independent data buffers to alternately perform data reception and decoding calculations, thereby masking PCIe communication latency.

[0053] Furthermore, the PCIe high-speed bus adopts a distributed-aggregated direct memory access engine, which supports batch transmission of multiple small data blocks with non-contiguous physical addresses.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] 1. The FPGA decoder architecture adopts pure combinational logic, which expands the complex finite field operation into a single-cycle XOR gate array. This fundamentally eliminates the high startup latency problem of "filling and emptying" that exists in traditional deep pipeline architecture when processing small files. In the case of extremely small files, the core decoding speed can be significantly improved compared with mainstream software solutions.

[0056] 2. Adopting the heterogeneous collaborative design concept of "software and hardware decoupling and leveraging each other's strengths", the CPU undertakes the control-intensive matrix inversion and metadata management tasks, while the FPGA focuses on the computation-intensive parallel data reconstruction tasks, effectively balancing flexibility and computational efficiency, and avoiding the waste of resources caused by completely offloading all tasks to hardware or keeping them all on the software side.

[0057] 3. By using a double-buffered delay masking mechanism, data reception and decoding calculations are performed alternately between two buffers, completely hiding the time-consuming PCIe data transmission process within the high-speed parallel computing cycle of the FPGA, thus achieving full-load operation of the pipeline.

[0058] 4. By utilizing the distributed-aggregated direct memory access mechanism, multiple small data blocks with non-contiguous physical addresses can be transferred in batches at one time, significantly reducing the number of CPU interrupt responses and the packet header overhead of the PCIe transaction layer, thus solving the context switching overhead problem in high-frequency small file transfer scenarios.

[0059] 5. The CPU-side Gaussian elimination inversion strategy based on Cauchy matrix binary decomposition transforms complex finite field multiplication and division into bitwise XOR and comparison operations that the CPU excels at. This not only avoids the waste of resources in implementing complex control logic on the FPGA, but also provides efficient pre-calculation support for recovery coefficients for high-speed parallel computing on the hardware side.

[0060] 6. The FPGA-side decoding unit adopts a parameterized design. The same set of hardware logic can be flexibly adapted to different erasure coding schemes by modifying the configuration parameters without modifying the core computing logic, which significantly improves the portability of the architecture and its adaptability to the ever-changing cloud storage environment. Attached Figure Description

[0061] Figure 1 This is a block diagram of the overall design of the CPU-FPGA hybrid acceleration architecture of the present invention;

[0062] Figure 2 This is a timing diagram of the CPU-FPGA collaborative data recovery workflow of the present invention;

[0063] Figure 3 This is a schematic diagram of the dual-buffered pipeline processing flow of the present invention;

[0064] Figure 4 This is a hardware architecture diagram of the FPGA decoding unit of the present invention;

[0065] Figure 5 This is the state transition diagram of the finite state machine for the FPGA decoding module of this invention;

[0066] Figure 6 This is a schematic diagram illustrating the XOR parallel computation principle of combinational logic in this invention. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0068] I. System Architecture and Functional Division

[0069] The CPU-FPGA hybrid acceleration system for erasure coding data recovery of small files proposed in this invention is based on the core design concept of "heterogeneous collaboration and leveraging each other's strengths": control-intensive tasks are retained on the CPU, while computationally intensive tasks are offloaded to the FPGA. For example... Figure 1As shown, the system consists of a CPU module and an FPGA module, which are interconnected via a PCIe high-speed bus.

[0070] The CPU-side module mainly includes a data block positioning unit, a matrix inversion unit, a control information generation unit, and a data integration and verification unit. The FPGA-side module includes a data receiving module, a combinational logic decoding module, a data sending module, a finite state machine, and a double-buffered memory module.

[0071] During erasure coding data recovery, different functional modules have varying requirements for computing resources and flexibility. To optimize resource allocation and system efficiency, this invention follows the principle of "hardware-software decoupling," assigning the recovery task to the CPU and FPGA for separate processing. Specifically:

[0072] The CPU undertakes the following tasks: (1) Determining the location of data blocks: Based on the encoding parameters and fault modes, dynamically determine the index of the data blocks to be recovered. This task belongs to dynamic control type calculation; (2) Matrix inversion: Use Gaussian elimination to calculate the inverse matrix of the encoding matrix in real time on the GF(2) finite field. This task belongs to high complexity dynamic change calculation; (3) Control information transmission: Send the inverse matrix and control information to the FPGA through the PCIe interface; (4) Data integration and verification: Receive the data blocks returned by the FPGA, reassemble and verify the data integrity.

[0073] The FPGA performs the following tasks: (1) Control and matrix caching: receive and cache the inverse matrix and related control information; (2) Survivor data prefetching: receive and cache the survivor data blocks for computation; (3) Parallel data reconstruction: based on the cached inverse matrix and survivor data blocks, reconstruct the failed data blocks in real time in parallel. This task belongs to parallel high-throughput computation; (4) Data return: return the recovered data blocks to the CPU through the PCIe interface.

[0074] II. Data Processing and Transmission Flow

[0075] like Figure 2 As shown, to achieve efficient collaboration between the CPU and FPGA, this invention designs a pipelined data processing and transmission flow, specifically consisting of the following sequential steps:

[0076] (1) Matrix inversion and control information generation (CPU side): The CPU dynamically determines the index and number of data blocks to be recovered based on the erasure coding scheme parameters (n,k) and the fault condition, and uses Gaussian elimination to obtain the inverse matrix of the coding matrix in real time over the GF(2) domain. At the same time, control information is generated, including the index of the block to be recovered, the data length, and the matrix column position. This stage is implemented in the software layer to ensure flexible adaptation to different coding conditions and data modes.

[0077] (2) Data transmission to FPGA (CPU→FPGA): The CPU uses the PCIe interface to transmit the inverse matrix, control information, and surviving data blocks to the FPGA. To improve the efficiency of small file transmission, this design adopts a distributed-aggregated direct memory access mechanism, which allows the host to submit multiple non-contiguous physical memory block descriptors at one time, thereby significantly reducing the number of CPU interrupt responses and the data packet header overhead of the PCIe transaction layer.

[0078] (3) FPGA Parallel Data Reconstruction (FPGA Side): After receiving and buffering the data transmitted from the CPU, the FPGA uses the on-chip cache to perform real-time parallel data recovery calculations based on the inverse matrix. The FPGA adopts a pure combinational logic architecture to perform XOR operations in a finite field, processing multiple data blocks in parallel, which greatly reduces the computational latency.

[0079] (4) Data return and verification integration (FPGA→CPU): The data blocks calculated by the FPGA are returned to the CPU through the PCIe interface. The CPU integrates and reconstructs the received data blocks into a complete file, and verifies the integrity and correctness of the data through the erasure coding verification mechanism. If the verification passes, the data recovery is completed; if the verification fails, the alternative recovery strategy or error reporting is triggered.

[0080] III. Matrix Inversion Strategy on the CPU

[0081] This invention employs a CPU-side Gaussian elimination inversion strategy based on Cauchy matrix binary decomposition. It should be noted that the Cauchy-type Reed-Solomon encoding used in this invention has an important characteristic: its generator matrix can be transformed into a binary matrix containing only 0 and 1 elements through binary expansion. Specifically, each element in the finite field GF(2^w) can be represented as a w-bit binary vector, and the multiplication operation over the field can be decomposed into matrix-vector multiplication over the GF(2) field, i.e., a series of bitwise XOR operations. Therefore, this invention uses the GF(2) implementation method for matrix inversion and decoding calculations, which is essentially a binary decomposition implementation of the GF(2^w) operation. This decomposition method not only simplifies the hardware implementation but also significantly reduces the logic resource consumption of the FPGA.

[0082] Gaussian elimination has the following engineering advantages over the GF(2) field: GF(2) is a finite field consisting of two elements {0,1}, where addition and subtraction are equivalent to bitwise XOR, multiplication is equivalent to bitwise AND, and the only invertible element is 1. Therefore, Gaussian elimination over GF(2) does not require division in the real number field, only XOR and AND operations; row elimination is simplified to bitwise XOR of the row and the pivot row, without the need for multiplication by a coefficient or normalization. On an n×n matrix, the overall complexity of Gaussian elimination for inversion is O(n³), which is more suitable for engineering applications than other methods.

[0083] The specific steps for implementing Gaussian elimination on the CPU side are as follows:

[0084] Step (21): Construct the augmented matrix. Horizontally concatenate the n×n matrix A to be inverted with the n×n identity matrix I to form an n×2n augmented matrix Aug=[A|I].

[0085] Step (22): Iterate through columns to eliminate variables. For the i-th column (i from 0 to n-1): First, check if the pivot position Aug[i][i] is 0. If it is 0, search for the first row where Aug[j][i] is 1 in rows i+1 to n-1. If found, swap rows i and j. If not found, determine that matrix A is a singular matrix on GF(2) and is not invertible, and terminate the operation.

[0086] Step (23): Elimination operation after establishing the pivot. For all row indices k (k ranges from 0 to n-1 and k ≠ i), if Aug[k][i] is 1, then perform a bitwise XOR operation: Aug[k] ← Aug[k] ⊕ Aug[i]. This operation eliminates all 1 elements in the i-th column except for the pivot.

[0087] Step (24): Extract the inverse matrix. After the iteration, the left half (first n columns) of the augmented matrix has been transformed into the identity matrix I, and the right half (last n columns) is the desired inverse matrix A⁻¹.

[0088] In the specific implementation, C / C++ language is used in conjunction with SIMD instructions for optimization. By leveraging the bitwise parallelism of SIMD instructions, the entire row XOR operation is processed in parallel at the word width or vector granularity, and the actual computational complexity can be reduced to O(n³ / w), where w is the number of bits processed in parallel each time.

[0089] IV. FPGA-based Pure Combinational Logic Decoder Design

[0090] like Figure 4 As shown, the decoding unit on the FPGA side is responsible for quickly reconstructing the lost data block based on the received inverse recovery coefficient matrix and the surviving data block. The decoding unit includes a data receiving module, a combinational logic calculation module, and a data sending module, which are coordinated by a finite state machine.

[0091] The data receiving module is responsible for receiving the inverse matrix of the recovery coefficients and the surviving data blocks from the PCIe interface and buffering them in the storage area within the FPGA. The state machine of the data receiving module parses the message type and boundaries, writes the coefficients to the register file, writes the data to the on-chip memory, and performs arrival integrity checks based on count and length.

[0092] The combinational logic computation module is the core of the FPGA decoder. This module expands complex finite field operations into a pure combinational logic XOR gate array, without introducing pipelined registers. The specific computation process is as follows:

[0093] Let the size of the inverse matrix M of the recovery coefficients be R×C, where R corresponds to the number of data blocks to be recovered and C corresponds to the number of surviving data blocks. The matrix elements take values ​​in the GF(2) domain, that is, only 0 or 1. The input data buffer stores C surviving data blocks, and the output buffer is used to store R recovered data blocks.

[0094] For each data block k to be recovered (k ranges from 0 to R-1), initialize the output buffer ParityBlock[k] to 0. Iterate through all surviving data blocks j (j ranges from 0 to C-1). If the inverse matrix of the recovery coefficients M[k][j] is 1, then execute ParityBlock[k]←ParityBlock[k]⊕DataBuf[j], where ⊕ represents a bitwise XOR operation.

[0095] The FPGA implements the above calculation process as a pure combinational logic circuit. Each output port is connected to the corresponding data input and XOR gate tree. The calculation of all data blocks to be recovered is completed in parallel, realizing data reconstruction within a single combinational logic propagation delay. This structure significantly shortens the data recovery latency and is especially suitable for frequent, small-scale data recovery tasks.

[0096] The data sending module is responsible for transmitting the calculation results back to the CPU via PCIe. The sending module writes the results into a hardware first-in-first-out queue, which is then packaged by the sending state machine according to the PCIe timing sequence and written back to the host memory via direct memory access.

[0097] like Figure 5 As shown, the finite state machine on the FPGA side is divided into five states to coordinate the data reception, calculation, and transmission processes:

[0098] (1) Idle waiting state (STATE_IDLE): Initial idle state, waiting for a start signal from the PCIe interface. When a transmission request sent by the host is detected, the finite state machine transitions to the data receiving state.

[0099] (2) Data Reception State (STATE_RECEIVE): The FPGA receives the inverse recovery coefficient matrix and the surviving data block through the PCIe interface and writes them into the internal buffer. During the reception process, the finite state machine monitors the amount of data in real time, and enters the combinational logic calculation state once the conditions are met. To improve efficiency, a double buffering mechanism is used to alternately complete the data reception and calculation tasks.

[0100] (3) Combinational Logic Calculation State (STATE_COMPUTE): The combinational logic calculation module is started to perform an XOR operation to complete data reconstruction. Since pure combinational logic is used, the calculation is completed within a single clock propagation delay. After the calculation is completed, the result is stored in the transmission buffer for transmission back to the CPU.

[0101] (4) Sending preparation state (STATE_PREPARE_TX): Performs pre-send preparation work, including setting data packet header information, configuring direct memory access parameters and loading the send first-in-first-out queue.

[0102] (5) Data Sending State (STATE_SEND): The finite state machine transmits the recovered data back to the host memory via the PCIe interface using direct memory access. After completing the data sending, the finite state machine returns to the idle waiting state to wait for the next task.

[0103] V. PCIe High-Speed ​​Interface and Delay Masking Mechanism

[0104] An efficient host interface is crucial for the performance of a CPU-FPGA hybrid architecture. This invention uses the PCIe bus as the data exchange channel and, considering the characteristics of high-frequency, low-data-volume transmission of small files, has implemented multi-level optimization designs from interface configuration and data encapsulation to transmission strategies.

[0105] The FPGA employs a high-performance PCIe hard-core IP, configured for high bandwidth and low latency, and incorporates direct memory access technology to significantly reduce the CPU's involvement in data transfer. The system defines a unified data packet format, with each packet containing a header and payload. The header includes a packet type field (identifying an inverse matrix, data block, or control command), a data block index field, a payload length field, a checksum field, and a sequence number field. The FPGA's data receiving module, by parsing the packet type field in the header, can complete data distribution decisions within a single clock cycle.

[0106] To further reduce the overhead of small file transfers, the CPU employs a distributed-aggregated direct memory access mechanism. This mechanism allows for the batch transfer of multiple small data blocks with non-contiguous physical addresses using a single instruction. Combined with a dedicated receive buffer on the FPGA, it automatically completes the transmission and reception of multiple data segments on the PCIe link without requiring CPU intervention on a packet-by-packet basis.

[0107] like Figure 3 As shown, to completely eliminate the impact of PCIe communication latency on computing performance, a dual-buffering mechanism is designed inside the FPGA to achieve latency masking. By alternating data reception and decoding calculations between two independent buffers, the system can completely hide the time-consuming PCIe data transmission process within the high-speed parallel computing cycle of the FPGA, thereby achieving full-load pipeline operation.

[0108] The specific process of the double-buffered pipeline is as follows: First, the CPU completes the matrix inversion operation and transmits the recovered coefficient inverse matrix and the surviving data block to FPGA buffer A via direct memory access; simultaneously, FPGA buffer B performs real-time decoding calculations on the previous batch of data. After the calculation is completed, buffer B immediately sends the recovered data block back to the CPU. At the same time, the CPU begins the inversion calculation of the next batch of matrices and sends the new data to buffer B for preloading. Subsequently, buffer A enters the decoding stage, and the roles of the two buffers are continuously exchanged, forming a continuous data transmission and processing pipeline.

[0109] VI. Parametric Design and Hardware Implementation

[0110] The core computing engine on the FPGA side adopts a parametric design concept, enabling the same hardware logic to support different RS(k,m) erasure coding configurations without modifying the core computing logic. The core configuration parameters of the parametric module include: the number of data blocks K, the number of parity blocks M (maximum fault tolerance), the finite field width W, and the number of data blocks processed in a single operation BLOCK_SIZE.

[0111] The FPGA side of this invention employs a multi-clock domain design to balance PCIe interface bandwidth and internal erasure coding computation load. The system includes multiple clock domains: a PCIe reference clock domain to drive the PCIe physical layer reference clock; a high-speed data path clock domain for the PCIe direct memory access engine and cache; a user logic clock domain for the erasure coding computation core and state machine; and a system management clock domain for system management and control logic. Asynchronous first-in-first-out queues ensure reliable data transmission and timing convergence between the clock domains.

[0112] VII. Examples

[0113] The following describes the complete small file recovery process using RS(8,4) erasure coding configuration as an example. RS(8,4) represents 8 data blocks and 4 parity blocks, which can tolerate a maximum of 4 blocks failing simultaneously.

[0114] Suppose a distributed storage system stores a small 32-byte file, which is encoded into 12 blocks: 8 data blocks and 4 parity blocks. Four data blocks have been lost, and the original data needs to be recovered using the remaining 8 available blocks.

[0115] Step 1: The data block location unit on the CPU side determines the indices of the four data blocks that need to be recovered based on the RS(8,4) parameter and the failure modes of the four failed blocks, and extracts the 8×8 survival submatrix corresponding to the eight available blocks from the 12×8 encoding matrix.

[0116] Step 2: The matrix inversion unit on the CPU expands the 8×8 GF(2^8) survival submatrix into a 64×64 GF(2) binary matrix using Cauchy binary decomposition, and then performs the inversion operation using Gaussian elimination. Specifically, a 128-column augmented matrix [A|I] is constructed, and iterative pivot search, row swapping, and XOR elimination are performed column by column to finally obtain a 64×64 recovery coefficient inverse matrix. This process is accelerated using SIMD instructions and is completed efficiently on the CPU.

[0117] Step 3: The CPU encapsulates the inverse recovery coefficient matrix and control information into a data packet of a unified format, and together with 8 surviving data blocks, transmits them to the FPGA in a single batch via scatter-aggregate direct memory access.

[0118] Step 4: The FPGA-side data receiving module parses the data packet header, writes the inverse matrix coefficients to the on-chip register file, and writes the surviving data blocks to the on-chip memory. The finite state machine transitions from the idle waiting state to the data receiving state, and after confirming that the data is ready, it enters the combinational logic calculation state. The combinational logic calculation module uses an XOR gate array to perform parallel XOR operations on the surviving data blocks based on the coefficients of each row in the recovery coefficient inverse matrix. The calculations of the four data blocks to be recovered are completed in parallel, requiring only a single combinational logic propagation delay.

[0119] Step 5: The finite state machine enters the transmit preparation state, configures the data packet header, and then enters the data transmit state, sending the four recovered data blocks back to the CPU via the PCIe interface. The CPU's data integration and verification unit verifies the data integrity, and the recovery process is complete.

[0120] Step Six: When multiple small files need to be recovered consecutively, the double buffering mechanism is automatically activated. While buffer A is receiving data from the second file, buffer B simultaneously performs decoding calculations on the first file. The two buffers work alternately, completely masking PCIe transmission latency during the calculation process, achieving continuous high-throughput data recovery.

[0121] It should be noted that although the embodiments described above are illustrative, they are not intended to limit the invention. Therefore, the invention is not limited to the specific embodiments described above. Any other embodiments obtained by those skilled in the art under the guidance of this invention without departing from its principles are considered to be within the protection scope of this invention.

Claims

1. A CPU-FPGA hybrid acceleration method for small file erasure code data recovery, characterized in that, The steps include the following: Step 1: The CPU dynamically determines the index and number of data blocks to be recovered based on the erasure coding scheme parameters and data block failure modes, and extracts the survival submatrix corresponding to the available data blocks from the coding matrix. Step 2: The CPU performs Gaussian elimination based on the GF(2) finite field on the survival submatrix to obtain the inverse matrix of the recovery coefficients; wherein, the Gaussian elimination method utilizes the characteristic that the Cauchy type Reed-Solomon code generating matrix can be expanded into a GF(2) binary matrix to transform the finite field multiplication and division into bitwise XOR and bitwise AND operations; Step 3: The CPU transmits the inverse recovery coefficient matrix, control information, and surviving data blocks in batches to the FPGA via the PCIe high-speed interface and the distributed-aggregated direct memory access mechanism. Step 4: The FPGA side uses a decoding unit based on pure combinational logic to perform a parallel XOR operation on the surviving data block according to the inverse matrix of the recovery coefficient, and completes the reconstruction of the failed data block within a single combinational logic propagation delay. Step 5: The FPGA sends the recovered data blocks back to the CPU via the PCIe interface. The CPU integrates and reconstructs the received data blocks and performs verification to complete the data recovery. Step 6: During the execution of steps 3 to 5, the FPGA side alternately performs data reception and decoding calculation between two independent buffers through a double buffering mechanism, so that the PCIe data transmission process and the FPGA decoding calculation process can be carried out in parallel, thereby achieving communication delay masking.

2. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: In step 2, the specific steps of the Gaussian elimination operation based on the GF(2) finite field are as follows: (21) Construct an augmented matrix by horizontally concatenating the survival submatrix with the identity matrix of the same order to form an augmented matrix [A|I]; (22) Column-wise iterative elimination: For the i-th column of the augmented matrix, if the pivot position Aug[i][i] is 0, then search for the first row below the i-th row where Aug[j][i] is 1 and swap it with the i-th row; if there is no pivot with a value of 1, then determine that the matrix is ​​singular on GF(2) and terminate. (23) After establishing the pivot, for all rows where index k is not equal to i and Aug[k][i] is 1, perform a bitwise XOR operation Aug[k]←Aug[k]⊕Aug[i] to complete the elimination; (24) After the iteration, the left half of the augmented matrix is ​​transformed into the identity matrix, and the right half is the inverse matrix of the recovery coefficient.

3. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: In step 4, the decoding unit based on pure combinational logic includes a data receiving module, a combinational logic calculation module, and a data sending module, and the three modules are coordinated by a finite state machine. The data receiving module is used to receive the inverse recovery coefficient matrix and the surviving data block from the PCIe interface, and write them into the FPGA on-chip register file and on-chip memory, respectively. The combinational logic calculation module expands the finite field operation into an XOR gate array and uses pure combinational logic circuits to perform parallel XOR operations. For each data block to be recovered, according to the coefficient value of the corresponding row in the recovery coefficient inverse matrix, the surviving data blocks with a coefficient of 1 are XORed bit by bit. The calculation of all data blocks to be recovered is completed in parallel. The data transmission module is used to transmit the reconstructed data blocks back to the CPU via the PCIe interface.

4. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 3, characterized in that: The finite state machine is divided into five states: Idle waiting state, initial idle state, waiting for the start signal from the PCIe interface. When a transmission request sent by the host is detected, it switches to the data receiving state. In the data reception state, the recovery coefficient inverse matrix and surviving data blocks are received through the PCIe interface and written to the internal buffer. During the reception process, the data volume is monitored in real time, and the combinational logic calculation state is entered after the conditions are met. In the combinational logic calculation state, the combinational logic calculation module is started to perform an XOR operation to complete the data reconstruction, and the result is stored in the transmission buffer. The send preparation state is set, the data packet header information is set, and the send first-in-first-out queue is loaded. The data transmission status is as follows: the recovered data is transmitted back to the host memory via the PCIe interface using direct memory access. After the data transmission is completed, the system returns to the idle waiting state.

5. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: In step 6, the specific implementation of the double buffering mechanism is as follows: Two independent data buffers are set up on the FPGA side, denoted as buffer A and buffer B respectively; When buffer A receives a new batch of recovery coefficient inverse matrix and surviving data blocks transmitted by the CPU via PCIe, buffer B simultaneously performs combinational logic decoding calculations on the previously received data. After buffer B completes its calculations, it sends the recovered data block back to the CPU. Meanwhile, buffer A completes its data reception and enters the decoding calculation stage. The roles of buffer A and buffer B are constantly exchanged, forming a continuous data transmission and decoding computation pipeline.

6. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: In step 3, the distributed-aggregated direct memory access mechanism allows the CPU to submit multiple small data block descriptors with non-contiguous physical addresses in batches through a single instruction. The direct memory access engine automatically completes the aggregation and transmission of multiple data segments, reducing the number of CPU interrupt responses and the packet header overhead of the PCIe transaction layer.

7. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: The data packets transmitted between the CPU and FPGA adopt a unified format. Each data packet consists of a header and a variable-length payload. The header includes a packet type field, a data block index field, a payload length field, a checksum field, and a sequence number field. The data receiving module on the FPGA completes the data distribution decision within a single clock cycle by parsing the packet type field in the header.

8. The CPU-FPGA hybrid acceleration method for small file erasure coding data recovery according to claim 1, characterized in that: The decoding unit on the FPGA side adopts a parameterized design, which enables flexible adaptation to different erasure coding schemes by configuring parameters. The configuration parameters include the number of data blocks, the number of parity blocks, the width of the finite field, and the number of data block bytes processed in a single operation.

9. A CPU-FPGA hybrid acceleration system for erasure coding data recovery of small files, used to execute the method described in any one of claims 1 to 8, characterized in that: It includes a CPU module and an FPGA module, which are interconnected via a PCIe high-speed bus; The CPU module includes: The data block location unit is used to dynamically determine the index and number of data blocks to be recovered based on erasure coding scheme parameters and data block failure modes, and to extract the survival submatrix from the coding matrix. The matrix inversion unit is used to perform the inversion operation on the survival submatrix using Gaussian elimination over the GF(2) finite field to obtain the restoration coefficient inverse matrix; The control information generation unit is used to generate control information including the index of the block to be recovered, the data length, and the matrix column positions. The data integration and verification unit is used to receive the recovered data block returned by the FPGA, reassemble and verify the data integrity; The FPGA terminal module includes: The data receiving module is used to receive and cache the recovery coefficient inverse matrix, control information, and surviving data blocks from the PCIe interface; The combinational logic decoding module uses a pure combinational logic circuit to construct an XOR gate array, which is used to perform parallel XOR operations on the surviving data blocks according to the inverse matrix of the recovery coefficients, and complete data reconstruction within a single combinational logic propagation delay. The data transmission module is used to transmit the reconstructed data blocks back to the CPU via the PCIe interface; A finite state machine is used to coordinate the workflow of the data receiving module, the combinational logic decoding module, and the data sending module. The dual-buffered storage module sets up two independent data buffers to alternately perform data reception and decoding calculations, thereby masking PCIe communication latency.

10. The CPU-FPGA hybrid acceleration system for small file erasure coding data recovery according to claim 9, characterized in that: The PCIe high-speed bus is equipped with a distributed-aggregated direct memory access engine, which supports batch transmission of multiple small data blocks with non-contiguous physical addresses. The FPGA module adopts a multi-clock domain design, including a PCIe reference clock domain, a high-speed data path clock domain, a user logic clock domain, and a system management clock domain. Data synchronization between the clock domains is achieved through an asynchronous first-in-first-out queue.

Images