A solid state disk data integrity checking and fault tolerance protection method

Abstract

This application provides a method for data integrity verification and fault tolerance protection of a solid-state drive (SSD), relating to the field of electronic digital data processing technology. The method involves configuring a region fault level register for the SSD and allocating data to be written to a storage region with an initial fault level value. A verification credential is generated by a controller, and the storage region is retransmitted in a step-by-step manner based on the total number of verification credential responses to determine the fault level value of the region fault level register. Adaptive decoding for fault level awareness is performed based on the fault level value to obtain configured decoding parameters. When the fault level value reaches an isolation threshold, address remapping for fault awareness is performed based on the configured decoding parameters to obtain a global bypass routing table. The storage region is reset based on the global bypass routing table to obtain the fault tolerance protection signal for the SSD. This application can simultaneously drive adaptive decoding and address remapping to achieve integrity verification and fault tolerance protection of the SSD under complex fault scenarios.

Description

Technical Field

[0001] This application relates to the field of electronic digital data processing technology, and more specifically, to a method for data integrity verification and fault tolerance protection of solid-state drives. Background Technology

[0002] Electrical and digital data processing involves core aspects of data storage, transmission, computation, and control within computer systems, forming the foundation of modern information processing technology. Solid-state drives (SSDs), as mainstream storage devices, directly impact system reliability and data security through their data integrity verification and fault-tolerance mechanisms. During data writing and reading, SSDs are susceptible to failures such as bit flips and message loss due to the physical characteristics of flash memory (e.g., erase / write wear, read interference, data retention errors).

[0003] Data integrity verification and fault tolerance protection methods for solid-state drives (SSDs) mainly include: end-to-end verification mechanisms based on cyclic redundancy check (CRC) or error correction codes, redundancy protection schemes based on independent hard drive redundant arrays, and wear leveling and bad block management technologies based on flash translation layers. However, existing verification and retransmission mechanisms typically employ source-end retransmission, requiring a global retransmission from the data source when verification fails. This results in high transmission latency, high bandwidth consumption, and an inability to dynamically adjust fault response strategies based on error frequency. Furthermore, these mechanisms fail to correlate with the actual fault evolution state of the storage medium, leading to a mismatch between error correction capabilities and media health. Moreover, fault detection, address remapping, and wear leveling are independent of each other, lacking a unified metric to drive them, making it difficult to achieve adaptive isolation of faulty areas and dynamic optimization scheduling of resources. Therefore, how to simultaneously drive adaptive decoding and address remapping to achieve SSD integrity verification and fault tolerance protection under complex fault scenarios is a challenge facing the industry. Summary of the Invention

[0004] This application provides a method for data integrity verification and fault tolerance protection of solid-state drives (SSDs), which can simultaneously drive adaptive decoding and address remapping to achieve integrity verification and fault tolerance protection of SSDs under complex failure scenarios.

[0005] This application provides a method for data integrity verification and fault tolerance protection of a solid-state drive, the method comprising the following steps: Configure a region fault level register for the solid-state drive and allocate the data to be written to a storage region with an initial fault level value; After the data is written, a verification certificate is generated by the controller. Based on the total number of responses to the verification certificate, the storage area is retransmitted in a step-by-step manner to determine the level value of the area fault level register. When reading data, a low-density parity decoder is used to perform fault level-aware adaptive decoding based on the level value to obtain the configured decoding parameters. When the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global bypass routing table; The storage area is reset according to the global bypass routing table to obtain the fault tolerance protection signal of the solid-state drive.

[0006] In this embodiment, the media wear coefficient of each storage area of ​​the solid-state drive is extracted based on the host-side flash conversion layer to form the solid-state drive configuration area fault level register.

[0007] In this embodiment, data sensitivity matching is used to allocate the data to be written to a storage area with an initial grade value.

[0008] In this embodiment, generating a verification credential via the controller after data writing specifically includes: The controller performs cyclic redundancy check on the written data and generates a check code. The verification code is packaged with the write area identifier and the write offset address to obtain the verification credential.

[0009] In this embodiment, determining the fault level register value by performing skip-based retransmissions of the storage area based on the total number of responses to the verification credentials specifically includes: The controller records the total number of responses to the verification credentials. When the total number of responses is lower than a preset threshold, a copy of the written data is read and a single-hop retransmission is performed along the write path to obtain the cumulative number of failures in the storage area. The level value of the regional fault level register is obtained by incrementally adding the cumulative number of failures and the initial level value of the regional fault level register.

[0010] In this embodiment, when reading data, a low-density parity-check decoder is used to perform fault level-aware adaptive decoding based on the level value, and the configured decoding parameters specifically include: Map the level values ​​to a linear adjustment range; Within the linear adjustment interval, a normalized constraint factor is calculated based on the proportional relationship between the level value and the interval endpoints. The configured decoding parameters are obtained by dynamically configuring nodes based on the normalized constraint factor using a low-density parity-check decoder.

[0011] In this embodiment, the isolation threshold refers to the boundary value that triggers isolation when the level value of the region fault level register exceeds the maximum tolerable number of failures threshold. The isolation threshold is the product of the media wear coefficient of the solid-state drive and the preset safety coefficient, wherein the media wear coefficient is the ratio of the current number of erases to the maximum number of erases.

[0012] In this embodiment, when the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global bypass routing table, specifically including: After the controller detects that the level value has reached the isolation threshold, the reliability weight of the fault area is determined by the configured decoding parameters. Based on the reliability weight, a remapping is performed to migrate the logical address range of the faulty area to the target detour area; The global detour routing table is determined by recording all logical address ranges of the target detour area.

[0013] In this embodiment, the fault tolerance protection signal of the solid-state drive is obtained by halving the level value based on the global detour routing table. Specifically, this includes: The storage area is reset based on all logical address segments in the global bypass routing table, and then the level value of the area fault level register in the reset area is read by the controller. The level value of the area fault level register in the reset area is halved in binary, and the halved level value is written back to the area fault level register to obtain the data write status of the reset area. A fault-tolerant protection signal is generated based on the data write status.

[0014] In this embodiment, the solid-state drive includes: a controller, a region fault level register, a backup buffer, a low-density parity decoder, a global bypass routing table, and a host-side flash translation layer.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: The technical solution provided in this application enables integrity verification and fault tolerance protection of solid-state drives (SSDs) under complex fault scenarios. Firstly, by configuring a region fault level register for the SSD and allocating data to be written to a storage region with an initial fault level value, an initial mapping relationship between media wear and data lifecycle can be established. Then, after data writing, a verification certificate is generated by the controller. Based on the total number of verification certificate responses, the storage region is retransmitted in a step-by-step manner, and the fault level register value is determined, enabling sub-cycle-level fault detection and failure accumulation quantification along the write path. Secondly, when reading data, a low-density parity decoder is used to perform adaptive decoding based on the fault level value to obtain the configured decoding parameters, allowing the storage region to be... The actual severity of the fault is directly mapped to the error correction strength of the decoder, enabling real-time matching of decoding capability with media health status and overcoming over-correction or under-correction defects caused by fixed constraint factors. Then, when the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global detour routing table. This table can transmit the reliability weights contained in the decoding parameters to the address management module across steps, achieving accurate isolation of the fault area and dynamic path detour, forming a unified driver for error correction information and remapping decisions. Finally, the storage area is reset based on the global detour routing table to obtain the fault tolerance protection signal of the solid-state drive, completing the level decay and resource recovery after the fault area reset, so that the reliability improvement brought by media refresh is positively utilized for level regression.

[0016] In summary, the technical solution adopted in this application can simultaneously drive adaptive decoding and address remapping to achieve integrity verification and fault tolerance protection of solid-state drives under complex failure scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a solid-state drive data integrity verification and fault tolerance protection method provided in this application; Figure 2 This is a structural diagram of a solid-state drive provided in this application; Figure 3 This is an exemplary flowchart for determining the level value of the area fault level register according to the present application; Figure 4 This is an exemplary flowchart of determining a global detour routing table according to the present application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] To better understand the technical solution of this application, the above technical solution will be described in detail below with reference to the accompanying drawings and specific embodiments. Figure 1 As shown in the figure, this is a flowchart of a solid-state drive data integrity verification and fault tolerance protection method according to this embodiment of the present application. The method includes the following steps: In step S1, a region fault level register is configured for the solid-state drive, and the data to be written is allocated to a storage region with an initial level value.

[0021] It should be noted that the solid-state drive includes: a controller, a region fault level register, a backup buffer, a low-density parity decoder, a global bypass routing table, and a host-side flash translation layer; preferably, refer to Figure 2 As shown in the figure, this is a schematic diagram of the solid-state drive (SSD) provided in this application. The host-side flash translation layer 100 refers to a software layer implemented in the host operating system kernel mode or user-mode driver, used to perform logical address to physical address mapping, garbage collection, region reset, and maintenance of the global bypass routing table. The controller 200 refers to the microprocessor unit inside the SSD responsible for executing host-side read / write commands, managing flash media operations, and coordinating the work of various hardware modules, used to receive write data and read requests sent by the host. The backup buffer 201 refers to the internal buffer of the SSD controller for each input... The first-in-first-out (FIFO) buffer queue configured at the output port is used to temporarily store copies of written data that have been sent but have not yet received confirmation of the verification credential; the low-density parity decoder 202 refers to the hardware decoding module built into the solid-state drive controller for error correction of read data; the area fault level register 203 refers to the read-only and writable register unit inside the solid-state drive controller for the storage area, used to store the current fault level value of the storage area. The register unit has a bit width of 8 bits and a value range of 0 to 255; the global bypass routing table 300 refers to the dynamic mapping table maintained by the host-side flash translation layer.

[0022] In practical implementation, the host-side flash conversion layer extracts the media wear coefficient of each storage area of ​​the solid-state drive (SSD) to configure the SSD's area fault level register. Specifically, the host-side flash conversion layer sends a query command (using the NVMe protocol) to obtain the number of erased regions and the bit error count during read operations. The ratio of the erased regions to the maximum erasable count is then used as the media wear coefficient, which can be set to 3000 erases. The media wear coefficient ranges from 0 to 1. This coefficient is then written to the corresponding register unit in the SSD controller's area fault level register via the host-side flash conversion layer's memory-mapped input / output interface, completing the area fault level register configuration. It should be noted that the media wear coefficient reflects the physical aging degree of the storage media and provides a reasonable benchmark for data matching and allocation.

[0023] In addition, in specific implementation, data sensitivity matching is used to allocate the data to be written to storage areas with initial grade values. Data sensitivity matching refers to the process of calculating a data sensitivity value based on the update frequency and historical verification failure rate of the data to be written, and then performing nearest neighbor matching between this data sensitivity value and the initial grade values ​​of each storage area. This data sensitivity matching can be implemented as follows: First, obtain the expected update frequency of the data to be written from the host-side file system or key-value storage engine; simultaneously, query the historical verification failure records of the data's logical address to obtain the historical verification failure rate; then, sum the expected update frequency and the historical verification failure rate with weights to obtain the target sensitivity value of the data, where the weight of the expected update frequency can be set to 0.7 and the weight of the historical verification failure rate can be set to 0.3; finally, multiply the target sensitivity value by 255 and round down to obtain the target grade matching value of the data. Then, the storage region with the smallest difference between the initial level value and the target level matching value, and whose current region state is empty, is searched in the region fault level register. This storage region is selected as the target region. If multiple regions with the same difference exist, the region with fewer erase cycles is selected as the target region to balance wear. Finally, the host-side flash translation layer maps the logical address of the data to be written to the physical address of the target region and triggers the write operation. It should be noted that data sensitivity matching automatically allocates frequently updated hot data to storage regions with low media wear and low error rates, which can reduce effective data migration during garbage collection due to lifecycle mismatch.

[0024] In step S2, after the data is written, a verification certificate is generated by the controller, and the storage area is retransmitted in a step-by-step manner based on the total number of responses to the verification certificate, thereby determining the level value of the area fault level register.

[0025] In this embodiment, generating a verification credential via the controller after data writing specifically includes: The controller performs cyclic redundancy check on the written data and generates a check code. The verification code is packaged with the write area identifier and the write offset address to obtain the verification credential.

[0026] In specific implementation, firstly, the controller reads the complete data block from the output of the data write path after the write operation is completed, and uses this data block as the input source for cyclic redundancy check (CRC). The controller calls the internally integrated CRC calculation unit to perform bit-by-bit operations on the complete data block to calculate a fixed-length checksum. This fixed length is determined by the solid-state drive's design specifications and is typically 32-bit or 64-bit. This fixed-length checksum is used as the checksum. Then, the controller extracts the unique ID of the storage region corresponding to the current write operation from the transaction record of the current write operation, and uses this unique ID as the write region identifier. Additionally, the controller extracts the offset of the starting write position within the storage region relative to the region's starting address from the transaction record of the current write operation, and uses this offset as the write offset address. The controller concatenates the checksum, the write region identifier, and the write offset address into a continuous data packet in a predetermined order: first, the write region identifier; then, the write offset address; and finally, the checksum. The controller uses this data packet as a verification credential and sends it to the credential cache queue maintained by the host-side flash translation layer.

[0027] It should be noted that Cyclic Redundancy Check (CRBC) is a data integrity verification process. It generates a checksum by performing a polynomial division operation on the data block. The receiver can repeat the same operation and compare the checksum with the result to determine if an error has occurred. The verification credential is a data structure containing three fields, used to report the result of a write operation to the host. The write area identifier locates the storage area where the write operation occurred, the write offset address locates the starting position of the data within the area, and the checksum verifies whether the data was written correctly. The credential cache queue is a first-in-first-out circular buffer used to temporarily store verification credentials that have not yet been confirmed by the host, preventing credential loss. After sending a verification credential, the controller does not immediately delete the corresponding data copy in the local backup buffer, but waits for an acknowledgment signal from the host before deleting it, ensuring that the copy remains available during skip-step retransmissions.

[0028] Preferred, Reference Figure 3 As shown, this diagram is an exemplary flowchart for determining the level value of the region fault level register according to the present application. In this embodiment, determining the level value of the region fault level register by performing skip-type retransmissions on the storage region based on the total number of responses to the verification credentials can be achieved through the following steps: In step S21, the total number of responses to the verification credentials is recorded by the controller; In step S22, when the total number of responses is lower than a preset threshold, a copy of the written data is read and a single-hop retransmission is performed along the write path to obtain the cumulative number of failures in the storage area. In step S23, the cumulative number of failures and the initial level value of the regional fault level register are incrementally added together to obtain the level value of the regional fault level register.

[0029] In practice, firstly, the controller starts a timer to listen for the acknowledgment signal returned by the host after each verification credential is sent. The controller counts the number of verification credentials that have not received acknowledgment signals and uses this number as the response missing count. Then, the controller reads the preset response threshold corresponding to the storage region. This preset response threshold is a fixed value set based on the average verification response latency and tolerable error rate experienced by the solid-state drive during normal operation; typically, two consecutive verification credentials without acknowledgment are considered abnormal. When the response missing count is lower than the preset response threshold, the controller reads the data copy temporarily stored during the last write operation from the backup buffer corresponding to the storage region and retransmits the data copy along the original write path. This retransmission only passes through the previous node and does not need to return to the data source, completing a single-hop retransmission. After the single-hop retransmission is completed, the controller increments the failure count register of the storage region and uses the incremented value as the cumulative failure count of the storage region. Finally, the controller reads the current level value of the storage region from the region fault level register, adds the cumulative failure count as an increment to the current level value, and writes the incremented result back to the region fault level register to obtain the updated level value of the region fault level register.

[0030] It should be noted that the total number of responses refers to the number of times a verification credential is not received within a specified time after the controller issues it. This number indicates the reliability of the write path. The preset threshold is a configurable integer; setting it to a smaller value allows for faster response to occasional errors, avoiding unnecessary retransmissions triggered by a single transient failure. Its value should be between 2 and 5. Skip-step retransmission means that the retransmission operation only occurs between adjacent nodes in the data path, without notifying the original data source to resend the entire data block, thus reducing retransmission latency. The cumulative number of failures is an continuously accumulating quantity used to quantify the frequency of failures occurring in the storage area over a period of time. This frequency directly determines the rate at which the fault level register value rises, allowing areas with high failure frequencies to obtain higher fault levels, thereby triggering more aggressive error correction and isolation measures.

[0031] In step S3, when reading data, a low-density parity decoder is used to perform fault level-aware adaptive decoding based on the level value to obtain the configured decoding parameters.

[0032] In this embodiment, when reading data, a low-density parity-check decoder is used to perform fault level-aware adaptive decoding based on the level value, and the configured decoding parameters specifically include: Map the level values ​​to a linear adjustment range; Within the linear adjustment interval, a normalized constraint factor is calculated based on the proportional relationship between the level value and the interval endpoints. The configured decoding parameters are obtained by dynamically configuring nodes based on the normalized constraint factor using a low-density parity-check decoder.

[0033] In practice, the controller first reads the current fault level value of the storage area from the area fault level register and inputs it as an integer. The controller internally stores a lower limit and an upper limit of a linear adjustment range. The lower limit corresponds to the normalized constraint factor value at the lowest fault level, and the upper limit corresponds to the normalized constraint factor value at the highest fault level. The specific values ​​of the lower and upper limits are determined by the design parameters of the low-density parity-check decoder. Typically, the lower limit is set to a coefficient less than 1 to enhance error correction, and the upper limit is set to 1 to maintain the original decoding strength. The controller maps the current level value to a linear range from the lower limit to the upper limit. The mapping method is as follows: first, calculate the difference between the current level value and the lowest fault level, then divide by the difference between the highest and lowest fault levels to obtain a proportional coefficient between 0 and 1. This proportional coefficient is then multiplied by the difference between the upper and lower limits, and finally added back to the lower limit to obtain the mapped value. Then, the controller uses the mapped value as a normalization constraint factor. The controller sends the normalization constraint factor to the check node update unit of the low-density parity-check decoder. During check node calculation, this update unit multiplies the minimum value output of the normalized minimum sum algorithm with the normalization constraint factor, replacing the fixed-coefficient multiplication operation in the original normalized minimum sum algorithm. Finally, the controller waits for the low-density parity-check decoder to complete the iterative updates of all check nodes and variable nodes, and saves the normalization constraint factor as part of the decoder's current configuration, thus obtaining the configured decoding parameters.

[0034] It should be noted that the linear adjustment interval refers to the range of values ​​for which the normalized constraint factor changes linearly with the grade value. The lower and upper limits of this interval are pre-calibrated through simulation, so that when the grade value is low, the decoder uses a near-standard normalized minimum sum algorithm to reduce latency, and when the grade value is high, the decoder uses a smaller constraint factor to enhance error correction capability. The normalized constraint factor is the multiplication coefficient in the (0,1) interval, used to compensate for the amplitude underestimation problem of the minimum sum algorithm compared to the belief propagation algorithm. Dynamic node configuration refers to the low-density parity-check decoder adjusting the amplitude of the output message of each check node in real time according to the normalized constraint factor during the check node update process, without changing the decoder's hardware structure or reloading the firmware. The configured decoding parameters include the normalized constraint factor and other parameters such as the number of iterations currently used by the decoder and the scheduling order. These decoding parameters can be used to determine the reliability weight of the fault region.

[0035] In step S4, when the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global bypass routing table.

[0036] It should be noted that the isolation threshold refers to the boundary value at which isolation is triggered when the fault level register value of the region exceeds the maximum tolerable failure count threshold. The isolation threshold is the product of the solid-state drive's media wear coefficient and a preset safety factor. The media wear coefficient is the ratio of the current number of erases to the maximum number of erasables. The preset safety factor is determined by the reliability test results of the solid-state drive at the time of manufacture and is used to adjust the aggressiveness of isolation according to the application scenario. Its value is within the range (0,1). For example, for enterprise-grade solid-state drives, the preset safety factor can be set to a smaller value to trigger isolation earlier to protect data security, while for consumer-grade solid-state drives, it can be set to a larger value to extend lifespan. Assuming that a certain storage region has currently been erased 1500 times and the maximum number of erasables for the flash memory media is 3000 times, then the media wear coefficient is 1500 divided by 3000, which equals 0.5. If this solid-state drive is used in an enterprise-level data center scenario, the preset safety factor is set to 0.8 based on the reliability test results. The isolation threshold is calculated as follows: First, the product of the media wear factor and the preset safety factor is calculated, i.e., 0.5 multiplied by 0.8 equals 0.4. Then, this product is multiplied by the maximum quantization range of the area fault level register, 255, resulting in 0.4 multiplied by 255 equals 102. Finally, the value is rounded down to obtain the isolation threshold of 102. When the current level value of the area fault level register corresponding to the storage area is greater than or equal to 102, the controller determines that the storage area has entered a semi-permanent fault state and triggers fault-aware address remapping. In addition, if the solid-state drive is used in a consumer-grade scenario, the preset safety factor can be set to 0.95. Then, the isolation threshold corresponding to the same media wear factor of 0.5 is 0.5 multiplied by 0.95 multiplied by 255 and rounded down to equal 121, which means a higher level value is required to trigger isolation, thereby extending the lifespan of the storage area. When the current level value of the area fault level register is greater than or equal to the isolation threshold, the controller determines that the storage area has entered a semi-permanent fault state and needs to trigger fault-aware address remapping.

[0037] Preferred, Reference Figure 4 As shown, this diagram is an exemplary flowchart for determining the global bypass routing table according to the present application. In this embodiment, when the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain the global bypass routing table. This can be achieved through the following steps: In step S41, after the controller detects that the level value has reached the isolation threshold, the reliability weight of the fault area is determined by the configured decoding parameters. In step S42, remapping is performed based on the reliability weight to migrate the logical address segment of the fault area to the target detour area; In step S43, a global detour routing table is determined by recording all logical address ranges of the target detour area.

[0038] In specific implementation, firstly, the controller continuously compares the current level value of the region fault level register with the isolation threshold. When the current level value is detected to be greater than or equal to the isolation threshold, the controller reads the configured decoding parameters obtained in step three, extracts the normalized constraint factor from the configured decoding parameters, and uses the normalized constraint factor as the reliability weight of the fault region. Then, the controller sends a fault isolation request to the host-side flash conversion layer, and transmits the reliability weight along with it. The host-side flash conversion layer maintains a backup region pool, in which each storage region has a pre-calculated health score. The host-side flash conversion layer traverses all storage regions in the backup region pool, calculates the difference between the health score and the reliability weight of each backup region, and selects the backup region with the smallest difference as the target bypass region. The host-side flash conversion layer reads the starting address and length of the logical address segment of the original fault region, completely migrates the logical address segment to the physical address space of the target bypass region, deletes the mapping entry of the original fault region in the mapping table of logical address and physical address, adds a new mapping entry, and keeps the logical address segment of the new mapping entry unchanged, while updating the physical address to the address of the target bypass region. Finally, the host-side flash translation layer writes the newly added mapping entries into the global bypass routing table, while retaining the status information that the original faulty area has been marked as unavailable, and uses the updated mapping table as the new global bypass routing table.

[0039] It should be noted that the reliability weight is derived from the normalized constraint factor in the configured decoding parameters. The smaller the normalized constraint factor, the higher the fault level of the area, and the lower the corresponding reliability weight. During remapping, it tends to select the backup area with a higher health score. The backup area pool is a resource set consisting of a group of unused or reset healthy storage areas pre-divided by the host-side flash translation layer. The health score of each backup area is calculated by weighting the media wear coefficient and the original bit error rate of the area. The higher the score, the healthier the media. The global bypass routing table is a dynamic lookup table maintained by the host-side flash translation layer. The table entries contain logical address ranges, remapped physical area addresses, and area status flags. All subsequent read requests first query this routing table when accessing the address. If a remapped entry is matched, it automatically redirects to the target bypass area, achieving transparent bypassing of faulty areas.

[0040] In step S5, the storage area is reset according to the global bypass routing table to obtain the fault tolerance protection signal of the solid-state drive.

[0041] In this embodiment, the fault tolerance protection signal of the solid-state drive is obtained by halving the level value based on the global detour routing table. Specifically, this includes: The storage area is reset based on all logical address segments in the global bypass routing table, and then the level value of the area fault level register in the reset area is read by the controller. The level value of the area fault level register in the reset area is halved in binary, and the halved level value is written back to the area fault level register to obtain the data write status of the reset area. A fault-tolerant protection signal is generated based on the data write status.

[0042] In practice, firstly, the host-side flash translation layer reads the logical address segments of all storage regions marked as faulty and having undergone address remapping from the global bypass routing table, extracts the physical addresses of these storage regions, and forms a list of regions to be reset. The host-side flash translation layer sends a reset command to the controller, which includes the physical address of the first storage region in the list of regions to be reset. After receiving the reset command, the controller performs a full-area erase operation on the storage region. After the erase operation is completed, the controller reads the current level value of the region fault level register corresponding to the storage region and uses this current level value as the level value before the reset. Then, the controller sends the level value before the reset to a shifter that shifts the binary level value one bit to the right, padding the high-order bits with zeros to obtain a new integer, which is used as the halved level value. The controller writes the halved level value back to the original region fault level register, overwriting the original level value. The controller checks whether the storage region has been completely erased successfully. If the erasure is successful, the controller marks the status of the storage region as available and uses the status of the storage region as the data write status for the reset region. Finally, the controller encapsulates the data write status into a status signal, which includes the physical address of the storage area, the halved level value, and a flag indicating whether the area is available. This status signal is then sent to the host flash conversion layer as a fault-tolerant protection signal. The host flash conversion layer adds the storage area back into the spare area pool based on the fault-tolerant protection signal.

[0043] It's important to note that binary halving refers to shifting the binary representation of the fault grade value one bit to the right, equivalent to dividing by two and rounding down. This operation causes areas with higher fault grades to drop significantly after reset, while areas with lower fault grades approach zero, reflecting the non-linear characteristics of reliability recovery after media erasure. Binary halving is suitable for fault grades that are powers of 2. For other fault grades, an equivalent operation of dividing by 2 and rounding down can be used. The fault grade value before reset represents the fault grade of that area after multiple writes and fault accumulation. Halving the fault grade value after reset means that a complete erase operation can eliminate half of the historical fault impact. The fault tolerance protection signal is a signal notifying the host-side flash memory conversion layer that a faulty area has been reset and restored to usability. The host-side flash memory conversion layer can then reinstate the faulty area into the resource scheduling scope, thereby achieving fault tolerance management of solid-state drive storage resources.

[0044] In summary, the technical solution adopted in this application can simultaneously drive adaptive decoding and address remapping to achieve integrity verification and fault tolerance protection of solid-state drives under complex failure scenarios.

[0045] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0046] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compactdisc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0047] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

Claims

1. A method for solid state drive data integrity verification and fault tolerance protection, characterized in that, The method includes the following steps: Configure a region fault level register for the solid-state drive and allocate the data to be written to a storage region with an initial fault level value; After the data is written, a verification certificate is generated by the controller. Based on the total number of responses to the verification certificate, the storage area is retransmitted in a step-by-step manner to determine the level value of the area fault level register. When reading data, a low-density parity decoder is used to perform fault level-aware adaptive decoding based on the level value to obtain the configured decoding parameters. When the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global bypass routing table; The storage area is reset according to the global bypass routing table to obtain the fault tolerance protection signal of the solid-state drive.

2. The method of claim 1, wherein, Based on the host-side flash conversion layer, the media wear coefficient of each storage area of ​​the solid-state drive is extracted to configure the region fault level register of the solid-state drive.

3. The method for data integrity verification and fault tolerance protection of a solid-state drive as described in claim 1, characterized in that, Data sensitivity matching is used to allocate the data to be written to storage areas with initial grade values.

4. The method of claim 1, wherein, After the data is written, the controller generates a verification credential, which specifically includes: The controller performs cyclic redundancy check on the written data and generates a checksum. The verification code is packaged with the write area identifier and the write offset address to obtain the verification credential.

5. The method of claim 1, wherein, Based on the total number of responses to the verification credentials, skip-based retransmissions are performed on the storage area to determine the fault level register value. Specifically, this includes: The controller records the total number of responses to the verification credentials. When the total number of responses is lower than a preset threshold, a copy of the written data is read and a single-hop retransmission is performed along the write path to obtain the cumulative number of failures in the storage area. The level value of the regional fault level register is obtained by incrementally adding the cumulative number of failures and the initial level value of the regional fault level register.

6. The method of claim 1, wherein, When reading data, a low-density parity decoder is used to perform fault-level-aware adaptive decoding based on the stated level value, resulting in configured decoding parameters, specifically including: Map the level values ​​to a linear adjustment range; Within the linear adjustment interval, a normalized constraint factor is calculated based on the proportional relationship between the level value and the interval endpoints. The configured decoding parameters are obtained by dynamically configuring nodes based on the normalized constraint factor using a low-density parity-check decoder.

7. The method of claim 1, wherein, The isolation threshold refers to the boundary value that triggers isolation when the level value of the region fault level register exceeds the maximum tolerable number of failures threshold. The isolation threshold is the product of the media wear coefficient of the solid-state drive and the preset safety coefficient, wherein the media wear coefficient is the ratio of the current number of erases to the maximum number of erases.

8. The method of claim 1, wherein, When the level value reaches the isolation threshold, fault-aware address remapping is performed based on the configured decoding parameters to obtain a global bypass routing table, specifically including: After the controller detects that the level value has reached the isolation threshold, the reliability weight of the fault area is determined by the configured decoding parameters. Based on the reliability weight, a remapping is performed to migrate the logical address range of the faulty area to the target detour area; The global detour routing table is determined by recording all logical address ranges of the target detour area.

9. The method of claim 1, wherein, Based on the global detour routing table, the level value is halved for optimization, resulting in the following fault tolerance protection signal for the solid-state drive: The storage area is reset based on all logical address segments in the global bypass routing table, and then the level value of the area fault level register in the reset area is read by the controller. The level value of the area fault level register in the reset area is halved in binary, and the halved level value is written back to the area fault level register to obtain the data write status of the reset area. A fault-tolerant protection signal is generated based on the data write status.

10. The method for data integrity verification and fault tolerance protection of a solid-state drive as described in claim 1, characterized in that, The solid-state drive includes: a controller, a region fault level register, a backup buffer, a low-density parity decoder, a global bypass routing table, and a host-side flash translation layer.

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