Chip signal interruption monitoring processing method and system, and electronic device

Abstract

The application provides a chip signal interruption monitoring processing method and system and electronic equipment, and relates to the field of chip interruption monitoring. The method dynamically monitors chip interruption source signals by constructing a monitoring configuration table mapping a mark value, an interruption serial number and a priority, supports dynamically modifying the configuration table during operation, and can realize full-quantity interruption source coverage through a small number of monitoring channels in a time division multiplexing manner, thereby greatly reducing chip hardware resources. The method can greatly reduce the storage space of long-time monitoring and improve the storage efficiency of monitoring data by compressing the monitoring process. Meanwhile, the method can accurately restore the physical occurrence and ending time sequence of interruptions, restore the interruption nesting relationship, verify whether the interruption priority execution meets the expectation, calculate the interruption processing time length through a time stamp to evaluate the system performance, and provide data support for chip problem positioning, chip application development and software optimization in complex scenarios.

Description

Technical Field

[0001] This invention relates to the field of chip interrupt monitoring, and in particular to a chip signal interrupt monitoring and processing method, system and electronic device. Background Technology

[0002] Existing chip interrupt monitoring technologies are mainly divided into two categories: full recording and fixed sampling. The full recording scheme records all interrupt sources indiscriminately; the fixed sampling scheme only monitors fixed channels.

[0003] The full recording scheme requires hardware channels for all interrupt sources, but actual debugging only focuses on a few critical interrupts, resulting in a waste of area and power consumption in FPGA / chip design; the fixed sampling scheme monitors fixed objects, and when switching debugging targets, code changes or chip replacements are required, which cannot adapt to the needs of dynamic configuration. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a chip signal interrupt monitoring and processing method, system, and electronic device. This method dynamically monitors chip interrupt source signals by constructing a monitoring configuration table that maps marker values ​​to interrupt sequence numbers and priorities. It supports dynamic modification of the configuration table during operation and can achieve full interrupt source coverage with a small number of monitoring channels through time-division multiplexing, significantly reducing chip hardware resources. This method also significantly reduces the storage space required for long-term monitoring by compressing the monitoring process, improving monitoring data storage efficiency. Simultaneously, it can accurately reconstruct the physical occurrence and termination sequence of interrupts, restore interrupt nesting relationships, verify whether interrupt priority execution meets expectations, and calculate interrupt processing time using timestamps to evaluate system performance. This provides data support for chip problem localization, chip application development, and software optimization in complex scenarios.

[0005] In a first aspect, embodiments of the present invention provide a chip signal interruption monitoring and processing method, the method comprising: Based on the number of interrupt sequence numbers configured for chip interrupt source signals, multiple different flag values ​​are set, and a monitoring configuration table is constructed by mapping each flag value to the target interrupt sequence number and priority of the chip interrupt source signal. When multiple target interrupt source signals are detected to have changed, the target flag value and timestamp of each target interrupt source signal are obtained, and the target priority of each target interrupt source signal is obtained from the monitoring configuration table using the target flag value; The actual interrupt processing order of each target interrupt source signal is obtained using the timestamp, and the target interrupt processing order of each target interrupt source signal is obtained using the target priority. The interrupt monitoring and processing results are obtained by comparing the actual interrupt processing order with the target interrupt processing order.

[0006] Optionally, multiple different flag values ​​can be set based on the interrupt sequence number configuration quantity of the chip interrupt source signal, including: The number of interrupt sequence numbers is determined based on the total number of interrupt sources in the chip's interrupt source signals; wherein, the total number of interrupt sources and the number of interrupt sequence numbers are divisible by an integer, and the total number of interrupt sources is greater than the number of interrupt sequence numbers. The number of interrupt sequence numbers is used as the starting flag value, and multiple different flag values ​​are set sequentially based on the calculation result of the starting flag value being decremented according to a preset step size.

[0007] Optionally, a monitoring configuration table is constructed based on the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal, including: The number of different target interrupt numbers in the chip's interrupt source signals is obtained by configuring the number of interrupt numbers. Calculate and obtain the priority of the target interrupt number based on the corresponding sequence number value; Based on the number of flag values, a mapping relationship is constructed between each flag value and the target interrupt sequence number and priority, and a monitoring configuration table is constructed through the mapping relationship.

[0008] Optionally, when multiple target interrupt source signals are detected to have changed, the target flag value and timestamp of each target interrupt source signal are obtained, including: When multiple target interrupt source signals are detected to have changed, the data packet reported by each target interrupt source signal is acquired. The status character of each target interrupt source signal is determined based on the first character in the data packet, the timestamp string of each target interrupt source signal is determined based on the last 15 characters in the data packet, and the interrupt source status string of each target interrupt source signal is determined based on the string between the status character and the timestamp string in the data packet. The target marker value of each target interrupt source signal is obtained by using the position marker value of the non-zero character in the interrupt source status string; Obtain the timestamp of each target interrupt source signal based on the hexadecimal conversion result of the timestamp string.

[0009] Optionally, the step of obtaining the target marker value for each target interrupt source signal using the position marker value of a non-zero character in the interrupt source status string includes: Determine if the number of interrupt sequence numbers configured is the same as the length of the interrupt source status string; If so, the position marker values ​​of each character in the interrupt source status string are set sequentially in ascending order, starting from the last character of the interrupt source status string and ending from the first character of the interrupt source status string. Get the position marker value of the non-zero character in the interrupt source status string, and get the target marker value that is the same as the position marker value from the monitoring configuration table.

[0010] Optionally, the actual interrupt processing order of each target interrupt source signal can be obtained using timestamps, including: The actual interrupt execution time of each target interrupt source signal is determined based on the decimal conversion result of the timestamp; After sorting the actual interrupt execution times in ascending order, the actual interrupt processing order of each target interrupt source signal is obtained based on the sorting result.

[0011] Optionally, the target interrupt processing order for each target interrupt source signal is obtained using the target priority, including: The expected interrupt priority value of each target interrupt source signal is obtained based on the numerical conversion result of the target priority. After sorting the expected interrupt priority values ​​in descending order, the target interrupt processing order for each target interrupt source signal is obtained based on the sorting result.

[0012] Optionally, interrupt monitoring and processing results can be obtained based on the comparison between the actual interrupt processing order and the target interrupt processing order, including: Using the target flag value of each target interrupt source signal, obtain the first execution sequence array corresponding to the actual interrupt processing order and the second execution sequence array corresponding to the target interrupt processing order, respectively. If the first execution sequence array is the same as the second execution sequence array, then the multiple target interrupt source signals correspond to the normal interrupt execution state; If the first execution sequence array is different from the second execution sequence array, then the multiple target interrupt source signals correspond to the interrupt execution exception state; Interrupt monitoring and processing results are obtained from multiple target interrupt source signals based on the normal and abnormal states of interrupt execution.

[0013] Secondly, the present invention provides a chip signal interruption monitoring and processing system, the system comprising: Configuration processing module: used to set multiple different flag values ​​based on the number of interrupt sequence numbers configured for the chip interrupt source signal, and to build a monitoring configuration table through the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal; Interrupt source signal processing module: When multiple target interrupt source signals are detected to have changed, it obtains the target flag value and timestamp of each target interrupt source signal, and uses the target flag value to obtain the target priority of each target interrupt source signal from the monitoring configuration table; Processing order acquisition module: used to obtain the actual interrupt processing order of each target interrupt source signal using timestamps, and to obtain the target interrupt processing order of each target interrupt source signal using target priority; Interrupt monitoring and processing module: Used to obtain the interrupt monitoring and processing results of multiple target interrupt source signals based on the comparison between the actual interrupt processing order and the target interrupt processing order.

[0014] Thirdly, embodiments of the present invention also provide an electronic device, which includes a processor and a memory. The memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the steps of the chip signal interruption monitoring and processing method provided in the first aspect.

[0015] This invention provides a chip signal interruption monitoring and processing method, system, and electronic device. During the monitoring of chip interrupt signals, the method first sets multiple different flag values ​​based on the number of interrupt sequence numbers configured for the chip interrupt source signals. A monitoring configuration table is constructed using the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal. When multiple target interrupt source signals are detected to have changed, the target flag value and timestamp of each target interrupt source signal are obtained, and the target priority of each target interrupt source signal is obtained from the monitoring configuration table using the target flag value. Then, the actual interrupt processing order of each target interrupt source signal is obtained using the timestamp, and the target interrupt processing order of each target interrupt source signal is obtained using the target priority. Finally, the interrupt monitoring and processing result is obtained based on the comparison between the actual interrupt processing order and the target interrupt processing order. This method dynamically monitors chip interrupt source signals by constructing a monitoring configuration table that maps marker values ​​to interrupt sequence numbers and priorities. It supports dynamic modification of the configuration table during operation and can achieve full interrupt source coverage with a small number of monitoring channels through time-division multiplexing, significantly reducing chip hardware resources. By compressing the monitoring process, this method can significantly reduce the storage space required for long-term monitoring, improving the efficiency of monitoring data storage. At the same time, it can accurately reconstruct the physical occurrence and termination sequence of interrupts, restore interrupt nesting relationships, verify whether interrupt priority execution meets expectations, and calculate interrupt processing duration through timestamps to evaluate system performance. This provides data support for chip problem localization, chip application development, and software optimization in complex scenarios.

[0016] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A flowchart of a chip signal interruption monitoring and processing method provided in an embodiment of the present invention; Figure 2 A flowchart of another chip signal interruption monitoring and processing method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a chip signal interruption monitoring and processing system provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0020] icon: 100 - Configuration processing module; 200 - Interrupt source signal processing module; 300 - Processing sequence acquisition module; 400 - Interrupt monitoring and processing module; 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] To facilitate understanding of this embodiment, a chip signal interruption monitoring and processing method disclosed in this embodiment of the invention will first be introduced. This method, based on core logic of software-configurable monitoring channels, parallel interrupt filtering, global timestamp recording, and dynamic priority detection, solves the problems of resource waste in traditional full-scale recording and poor flexibility in fixed sampling, achieving dynamic, efficient, and accurate monitoring of chip interrupts; specifically, the method is as follows: Figure 1 As shown, it includes: Step S101: Based on the number of interrupt sequence numbers configured for the chip interrupt source signal, set multiple different flag values, and construct a monitoring configuration table through the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal.

[0023] Based on the number of interrupt sequence numbers configured on the chip, a mapping relationship between monitoring channel marker values ​​and target interrupt sequence numbers and expected interrupt priorities is established via the APB / AXI bus in a software-programmable manner, generating a dynamically rewritable monitoring configuration table. For example, the marker values ​​of the monitoring channels correspond to 16 physical monitoring channel numbers (e.g., 1 to 16), the target interrupt sequence numbers are different interrupt numbers to be monitored selected from 256 total interrupt sources (e.g., 0, 7, 36, 45), and the expected interrupt priorities are the pre-configured 16 levels of interrupt priorities. This configuration table supports real-time modification during chip operation, allowing switching of monitored interrupt sources without resynthesizing the code or replacing the chip.

[0024] Step S102: When multiple target interrupt source signals are detected to have changed, obtain the target flag value and timestamp of each target interrupt source signal, and use the target flag value to obtain the target priority of each target interrupt source signal from the monitoring configuration table.

[0025] The interrupt routing selection network uses 16 parallel comparators to filter and compare 256 interrupt sources in the chip in real time, accurately locking 16 target interrupt sources in the configuration table. When a state flip of a target interrupt source is detected (0 to 1 corresponds to an interrupt response event, 1 to 0 corresponds to an interrupt processing end event), the timestamped recording unit obtains the monitoring channel flag value and 15-bit global timestamp corresponding to the interrupt source. At the same time, based on the monitoring channel flag value, the expected interrupt priority pre-configured for the interrupt source is retrieved from the monitoring configuration table.

[0026] Step S103: Use timestamps to obtain the actual interrupt processing order of each target interrupt source signal, and use target priority to obtain the target interrupt processing order of each target interrupt source signal.

[0027] Based on the global timestamps of the interrupt response and processing completion of each target interrupt source, the start and end times of interrupt processing are sorted to determine the actual interrupt processing order (including interrupt nesting time and processing duration). In addition, according to the expected interrupt priorities pre-stored in the monitoring configuration table, the target interrupt processing order is determined by following the rule of prioritizing the processing of high-priority interrupts.

[0028] Step S104: Obtain the interrupt monitoring and processing results based on the comparison between the actual interrupt processing order and the target interrupt processing order.

[0029] The actual interrupt handling sequence is compared with the target interrupt handling sequence to complete interrupt monitoring. If they match, the interrupt priority execution is considered to be in line with design expectations, and monitoring data is recorded normally. If they do not match (e.g., a lower-priority interrupt finishes processing before a higher-priority interrupt), an interrupt priority anomaly flag is automatically generated, and an anomaly signal is reported. The duration of each interrupt handling is calculated by combining timestamp data to reconstruct the interrupt nesting relationship, and finally, a complete monitoring result containing interrupt timing, priority status, processing duration, and anomaly information is output.

[0030] Optionally, multiple different flag values ​​can be set based on the interrupt sequence number configuration quantity of the chip interrupt source signal, including the following steps: Step S201: Determine the number of interrupt sequence numbers to be configured based on the total number of interrupt sources of the chip interrupt source signal; wherein, the total number of interrupt sources and the number of interrupt sequence numbers are divisible by an integer, and the total number of interrupt sources is greater than the number of interrupt sequence numbers to be configured.

[0031] Based on the total number of interrupt sources built into the chip (e.g., 256), the number of interrupt sequence numbers configured (i.e., the number of physical monitoring channels, such as 16 or 32) should be reasonably determined. The total number of interrupt sources and the number of interrupt sequence numbers configured should be divisible by an integer, and the total number of interrupt sources should be much greater than the number of interrupt sequence numbers configured. This ensures that, based on a small number of physical monitoring channels, full coverage of all interrupt sources of the chip can be achieved through time-division multiplexing, thus saving chip hardware resources while ensuring the integrity of the monitoring range.

[0032] Step S202: Using the number of interrupt sequence numbers as the starting flag value, and calculating the result of decreasing the starting flag value according to the preset step size, set multiple different flag values ​​in sequence.

[0033] Starting with the number of interrupt sequence numbers configured, the initial marker value is continuously decremented at a fixed step size (step size of 1). The result of each decrement is then assigned as an independent marker value for each physical monitoring channel, ultimately forming a continuous, unique, and ordered sequence of monitoring channel marker values ​​(1, 2, 3, ..., 16). Each marker value corresponds one-to-one with a physical monitoring channel and serves as a unique identifier for subsequently constructing the monitoring configuration table, indexing the target interrupt sequence number and expected interrupt priority, thus ensuring the accuracy of monitoring configuration and data reading.

[0034] Optionally, a monitoring configuration table is constructed by mapping each flag value to the target interrupt sequence number and priority of the chip interrupt source signal, including the following steps: Step S301: Use the interrupt sequence number configuration quantity to obtain multiple different target interrupt sequence numbers in the chip interrupt source signal.

[0035] Using a preset number of interrupt sequence numbers (i.e., 16 physical monitoring channels) as the selection quantity, the corresponding number of target interrupt sequence numbers are selected from the 0~255 interrupt sequence numbers corresponding to all 256 interrupt sources of the chip. This selection process is completed by software programmable through the APB / AXI bus and can be dynamically adjusted while the chip is running, without the need to modify the hardware or resynthesize the code.

[0036] Step S302: Calculate and obtain the priority of the target interrupt number based on the sequence number value corresponding to the target interrupt number.

[0037] The expected interrupt priority is configured in a software-programmable manner through the expected interrupt priority register for each selected target interrupt number. The priority adopts 16 configurable levels. The priority value is preset according to the chip interrupt architecture design and debugging requirements, rather than being directly calculated based on the interrupt number value. The configuration result is stored in the configuration register group in real time and associated with the target interrupt number one by one.

[0038] Step S303: Construct a mapping relationship between each tag value and the target interrupt sequence number and priority according to the number of tag values, and construct a monitoring configuration table through the mapping relationship.

[0039] Based on the total number of monitoring channel marker values ​​(consistent with the number of interrupt sequence number configurations), a one-to-one mapping relationship is established for each unique monitoring channel marker value, binding the marker value, target interrupt sequence number, and expected interrupt priority. All mapping relationships are integrated into a combined monitoring configuration table consisting of a 16×8-bit interrupt sequence number configuration table and a 16×4-bit expected interrupt priority configuration table. This configuration table is stored in the configuration register group and supports dynamic rewriting of the mapping content during chip runtime to adapt to the monitoring needs of different debugging scenarios.

[0040] Optionally, when multiple target interrupt source signals are detected to have changed, the target flag value and timestamp of each target interrupt source signal are obtained, including the following steps: Step S401: When multiple target interrupt source signals are detected to have changed, acquire the data packet reported by each target interrupt source signal.

[0041] When the parallel comparator in the chip detects a state flip (0 to 1 corresponds to an interrupt response, 1 to 0 corresponds to the end of interrupt processing), the compressed storage unit will report a monitoring data packet in the corresponding format according to the configuration of the dynamic compression enable register, and obtain the reported data packet corresponding to the state change of each target interrupt source in real time.

[0042] Step S402: Determine the status character of each target interrupt source signal based on the first character in the data packet, determine the timestamp string of each target interrupt source signal based on the last 15 characters in the data packet, and determine the interrupt source status string of each target interrupt source signal based on the string between the status character and the timestamp string in the data packet.

[0043] The reported data packets are decomposed into the following fields: the first identifier bit of the data packet is used as a status character to distinguish between compressed and full packets; the last 15 bits of the data packet are extracted as a timestamp string, corresponding to the timing data of the global 15-bit free-running timer; the middle field between the status character and the timestamp string is extracted as the interrupt source status string. It should be noted that the full packet has a 16-bit interrupt source status, while the compressed packet has a 4-bit interrupt source number (the 4-bit interrupt source number corresponds to 16 monitored interrupts).

[0044] In practical scenarios, the format for a full packet is {1'b0, 16-bit status of the monitored interrupt source, 15-bit timestamp}, totaling 32 bits; the format for a compressed packet is {1'b1, 4-bit interrupt number corresponding to the monitored interrupt source, 15-bit timestamp}, totaling 20 bits. The first bit serves as a status character, with 1 indicating a compressed packet and 0 indicating a full packet.

[0045] For example, if 16 out of 256 interrupts are monitored, and the 3rd interrupt out of those 16 occurs, the 16-bit interrupt source status of the full packet will be 16'b0000_0000_0000_0100; the 4-bit monitored interrupt source number of the compressed packet will be 4'b0011, meaning the 3rd out of the 16 interrupts has flipped.

[0046] In layman's terms, the purpose of this is as follows: General-purpose buses are typically 32 / 64-bit. In this case, a full data packet conforms to the format requirements and can be directly mounted on the bus without conversion, facilitating reuse across multiple projects. However, compressed data packets are suitable for storage in private memory or transmission via proprietary protocols. In these cases, there are no data bit width limitations, so less data can save memory and reduce dynamic power consumption.

[0047] It should be noted that this method supports dynamic compression enabling. When the dynamic compression enabling register is 0, the entire packet is always reported.

[0048] Step S403: Obtain the target marker value for each target interrupt source signal using the position marker value of the non-zero character in the interrupt source status string.

[0049] The interrupt source status string is checked bit by bit, and the position of the non-zero character in the string is located. This position is mapped one-to-one with the mark value of the monitoring channel. In this way, the target mark value corresponding to each target interrupt source that has changed status is extracted, and the precise association between the interrupt source and the monitoring channel is completed.

[0050] Step S404: Obtain the timestamp of each target interrupt source signal based on the hexadecimal conversion result of the timestamp string.

[0051] The extracted 15-bit timestamp string is converted from binary to decimal / hexadecimal. The conversion result is the global timestamp of the moment when the target interrupt source state changes. This timestamp is used for subsequent interrupt timing sorting, processing time calculation and priority anomaly verification.

[0052] Optionally, the step of obtaining the target marker value for each target interrupt source signal using the position marker value of a non-zero character in the interrupt source status string includes the following steps: Step S501: Determine whether the number of interrupt sequence numbers configured is the same as the length of the interrupt source status string.

[0053] Determine whether the length of the currently parsed interrupt source status string is exactly equal to the preset number of interrupt sequence numbers (total number of physical monitoring channels: 16). This check is used to identify that the data packet is in full packet format (16-bit interrupt source status) to ensure the accuracy of subsequent location marker value allocation and matching with monitoring channels.

[0054] Step S502: If so, starting from the last character of the interrupt source status string and ending from the first character of the interrupt source status string, set the position marker values ​​of each character in the interrupt source status string in ascending order.

[0055] If the two are of the same length (determined to be a full packet data), the last character of the interrupt source status string is used as the starting point for counting the marker value, and the first character of the string is used as the ending point. Following the rule of continuously increasing natural numbers, a unique position marker value is assigned to each character in the string. This position marker value forms a one-to-one correspondence with the target marker value of the monitoring channel in the monitoring configuration table (a continuous sequence from 1 to 16). If it is a compressed packet, the middle 4-digit interrupt source number can also be used to directly specify one of the 16 corresponding physical monitoring channels.

[0056] Step S503: Obtain the position marker value of the non-zero character in the interrupt source status string, and obtain the target marker value that is the same as the position marker value from the monitoring configuration table.

[0057] Traverse the interrupt source status string, locate the character position with a non-zero value and obtain its corresponding position mark value; use the position mark value as the retrieval index to match and obtain the target mark value of the monitoring channel with the same value in the pre-built monitoring configuration table, and complete the precise binding of the status change interrupt source with the corresponding monitoring channel.

[0058] Optionally, the actual interrupt handling order of each target interrupt source signal can be obtained using timestamps, including the following steps: Step S601: Determine the actual interrupt execution time of each target interrupt source signal based on the decimal conversion result of the timestamp.

[0059] The 15-bit global timestamps corresponding to the state changes of each target interrupt source are converted from binary to decimal to obtain standardized timestamp values. These values ​​accurately correspond to the actual clock execution time when the target interrupt source responds to an interrupt (0->1) or the interrupt processing ends (1->0), providing an accurate timing reference for interrupt timing sequencing.

[0060] Step S602: After sorting the actual interrupt execution times in ascending order, obtain the actual interrupt processing order of each target interrupt source signal based on the sorting result.

[0061] The interrupt response time and interrupt processing completion time of all target interrupt sources are uniformly sorted in ascending order by the decimal timestamp value. Based on this timing sorting result, the actual triggering order and actual processing completion order of each interrupt are determined, and finally a complete actual interrupt processing order is formed, which can intuitively reflect the interrupt nesting relationship and the actual execution timing.

[0062] Optionally, the target interrupt processing order for each target interrupt source signal is obtained using the target priority, including the following steps: Step S701: Obtain the expected interrupt priority value of each target interrupt source signal based on the numerical conversion result of the target priority.

[0063] The target interrupt priorities pre-stored in the monitoring configuration table (written by software to a 16×4-bit expected interrupt priority register, supporting 16 configurable levels) are standardized and converted to generate the expected interrupt priority value corresponding to each target interrupt source. This priority value is a quantified priority parameter that directly represents the preset priority level of the interrupt and is the core basis for determining the ideal execution order.

[0064] Step S702: After sorting the expected interrupt priority values ​​in descending order, obtain the target interrupt processing order for each target interrupt source signal based on the sorting result.

[0065] All target interrupt sources are sorted according to the rule of decreasing interrupt priority from high to low; the target interrupt processing order is generated based on the sorting result, that is, high priority interrupts should be processed first. This order is the standard reference for subsequent verification of whether the interrupt priority execution is compliant.

[0066] Optionally, the interrupt monitoring and processing results are obtained based on the comparison between the actual interrupt processing order and the target interrupt processing order, including the following steps: Step S801: Using the target flag value of each target interrupt source signal, obtain the first execution sequence array corresponding to the actual interrupt processing order and the second execution sequence array corresponding to the target interrupt processing order, respectively.

[0067] Using the target marker value of the monitoring channel corresponding to each target interrupt source as a unique identifier, the actual interrupt processing order determined by timestamp sorting is organized into a first execution sequence array; at the same time, the target interrupt processing order determined by expected priority sorting is organized into a second execution sequence array; the two arrays achieve accurate mapping of interrupt channels through target marker values, which is used for subsequent timing compliance comparison.

[0068] Step S802: If the first execution sequence array is the same as the second execution sequence array, then the multiple target interrupt source signals correspond to the interrupt execution normal state.

[0069] The first execution sequence array and the second execution sequence array are matched and verified bit by bit. If the two arrays are completely identical, it indicates that the actual processing completion order of multiple target interrupt sources is completely consistent with the preset priority requirements. The current interrupt execution status is determined to be normal, and only the monitoring data is stored normally without triggering abnormal alarms.

[0070] Step S803: If the first execution sequence array is different from the second execution sequence array, then the multiple target interrupt source signals correspond to the interrupt execution abnormal state.

[0071] If there is a difference between the two sets of arrays (such as the lower priority interrupt finishing processing earlier than the higher priority interrupt), it indicates that the actual execution timing of the interrupt violates the design expectation, and the current interrupt execution status is determined to be abnormal; the interrupt monitoring and processing unit immediately generates an interrupt priority abnormal flag and actively reports the abnormal signal to the chip.

[0072] Step S804: Obtain the interrupt monitoring and processing results of multiple target interrupt source signals based on the normal interrupt execution state and the abnormal interrupt execution state.

[0073] By integrating information such as the normal / abnormal status of interrupt execution, priority exception flag, global timestamp, interrupt processing duration, and interrupt nesting relationship, a complete interrupt monitoring and processing result is generated. This result can be directly used for chip debugging, interrupt logic verification, and code problem localization, realizing the visualization and quantitative evaluation of interrupt execution status.

[0074] like Figure 2Another chip signal interrupt monitoring and processing method is shown in this flowchart. This flowchart fully presents a dynamically configurable, low-resource-overhead chip interrupt monitoring and processing architecture. Its core logic uses a software-programmable monitoring configuration table to dynamically filter chip interrupt sources, capture timing data, and verify priorities. Finally, it reports the monitoring results to the processor, overcoming the resource waste of traditional full-data recording schemes and the lack of flexibility of fixed-sampling schemes. The functions and interaction logic of each module are restated as follows: 1. Chip Interrupt Source: The signal source for monitoring and operations. As the physical unit for generating all interrupt requests within the chip (e.g., 256 interrupt sources), its signal flow is divided into two parallel paths: Business path: The interrupt source sends an interrupt request signal directly to the chip processor, triggering the processor's interrupt response and processing flow, which is the core link of the chip's normal business logic; Monitoring Path: The interrupt source signal is simultaneously captured by the interrupt monitoring system and enters the subsequent monitoring and processing link to achieve real-time tracking of interrupt status changes. Note: The state flip of the interrupt source signal (0-1 indicates an interrupt response event, 1-0 indicates an interrupt processing completion event) is the core condition for triggering the monitoring system to work.

[0075] 2. Monitoring Configuration Table: The programmable core of dynamic monitoring. This module provides software-programmable configuration rules for the entire monitoring system, corresponding to steps S101, S301~S303 mentioned above. Its functions and extensions are described below: Configuration logic: The chip processor writes configuration data through the APB / AXI bus, and uses the tag values ​​of a small number of physical monitoring channels (such as 16) as indexes to establish a one-to-one mapping relationship between the tag values ​​and the target interrupt sequence number (selected from 256 interrupt sources) and the expected interrupt priority, forming a configuration table that can be dynamically rewritten. Dynamic adaptability: It supports real-time modification of mapping relationships during chip operation, and can switch the monitored interrupt source without resynthesizing the code or replacing the chip, thus solving the defect of fixed sampling scheme monitoring objects. Resource optimization mechanism: Through time-division multiplexing logic, full coverage of 256 interrupt sources is achieved with 16 physical channels, which greatly reduces hardware resource overhead and overcomes the area and power consumption waste problems of the full recording scheme.

[0076] 3. Interrupt Source Signal Processing: Real-time capture and parsing of interrupt status. This module is the core data processing unit of the monitoring link. It receives configuration information from the monitoring configuration table and the raw signals from the chip interrupt source, and completes the following core operations: Target interrupt screening: Using a parallel comparator array, the 256 interrupt source signals are compared in real time according to the target interrupt number in the monitoring configuration table to accurately locate the target interrupt source to be monitored; State change detection: Continuously monitor the state transition of the target interrupt source signal. When a state change is detected, generate a reporting data packet containing state information and a timestamp. Data parsing and extraction: The data packet is split into fields to extract the first status character, the 15-digit timestamp string, and the intermediate interrupt source status string; further, by locating the position marker value of the non-zero character in the interrupt source status string, the target marker value in the monitoring configuration table is matched, and the timestamp string is converted into a decimal value to provide standardized data for subsequent timing and priority processing.

[0077] 4. Interrupt Handling Sequence: Construction of Actual and Ideal Timing. This module constructs two sets of interrupt handling sequences based on the flag value and timestamp output by the interrupt source signal processing unit: Actual interrupt handling sequence: Based on the decimal timestamp values ​​of each target interrupt source, the interrupt response and processing completion events are sorted in ascending order to restore the actual execution sequence of the interrupts (including interrupt nesting sequence and processing duration), and the first execution sequence array is organized with the target marker value as the index. Target interrupt handling order: Based on the expected interrupt priorities stored in the monitoring configuration table, the target interrupt sources are sorted in descending order to generate an ideal execution order in which high-priority interrupts are processed first, and then organized into a second execution sequence array with the target tag value as the index.

[0078] 5. Interruption Monitoring Processing and Reporting: Generation and feedback of verification results. This module is the final output unit of the monitoring link, and its core functions are: Timing compliance verification: Perform a bit-by-bit matching verification between the first execution sequence array (actual order) and the second execution sequence array (target order); Status determination and result generation: If the two sets of arrays are completely identical, the interrupt execution status is determined to be normal, and the system only stores the monitoring data; if the two sets of arrays are different (such as the low-priority interrupt finishing processing earlier than the high-priority interrupt), the interrupt execution status is determined to be abnormal, and an interrupt priority abnormal flag is generated. Results reporting: The complete monitoring and processing results, including interrupt timing, priority status, processing time, and exception information, are reported to the chip processor. This complements the service interruption requests sent directly by the interrupt source, providing quantitative basis for chip debugging and interrupt logic optimization.

[0079] 6. Chip Processor: The receiving end for business processing and monitoring results. As the control core of the chip, it simultaneously receives two types of signals: The service interrupt request sent directly by the chip interrupt source executes the normal interrupt response and processing logic; The monitoring results output by the interrupt monitoring and processing reporting module are used to perform secondary verification of the interrupt execution timing and priority, assisting in locating interrupt anomalies and ensuring the stability and reliability of the chip's interrupt logic.

[0080] The monitoring process is explained in detail below with specific data. When the first interrupt is the 5th interrupt being monitored, the timestamp at this time is 15'd100. Then the 32-bit data reported at this time is 32'b0000_0000_0000_1000_0000_0000_0110_0100. When the timestamp is 15'd200, the monitored interrupt number 12 arrives, and the 32-bit data reported at this time is 32'b0000_0100_0000_1000_0000_0000_1100_1000; When the timestamp is 15'd300, the 15th monitored interrupt arrives, and the 32-bit data reported at this time is 32'b0010_0100_0000_1000_0000_0001_0010_1100; When the timestamp is 15'd400, the monitored 12th interrupt is completed, and the 32-bit data reported at this time is 32'b0010_0000_0000_1000_0000_0001_1001_0000; When the timestamp is 15'd500, the monitored interrupt number 5 is completed, and the 32-bit data reported at this time is 32'b0010_0000_0000_0000_0000_0001_1111_0100; When the timestamp is 15'd600, the monitored 15th interrupt is completed, and the 32-bit data reported at this time is 32'b0000_0000_0000_0000_0000_0010_0101_1000; Based on the data reported during this period, the following conclusions can be drawn: The monitored interrupt number 5 arrived first, and the second one completed, taking 400 clock cycles; The monitored interrupt number 12 arrived second and completed first, taking 200 clock cycles; When the monitored 12th interrupt arrives, the interrupt monitoring and processing unit detects two concurrent interrupts in the current path. It immediately checks the expected interrupt priority registers for interrupts 5 and 12, finding that interrupt 5 has a priority of 3 and interrupt 12 has a priority of 1, meaning interrupt 5 has a higher priority than interrupt 12. Therefore, when interrupt 12 completes, a priority exception flag is generated, and the interrupt is automatically reported to the chip processor.

[0081] The monitored interrupt number 15 arrived last and completed last, taking 300 clock cycles; Based on the actual monitoring results, it can be inferred that the priority of interrupt 12 is greater than that of interrupt 5, which is greater than that of interrupt 15, and that there is a nested phenomenon in the interrupt handling process.

[0082] When the dynamic compression enable register is 1, the reported data are as follows: Interrupt number 5 arrives at time 16'd100, and the reported data is 20'b1_0101_000000001100100; Interrupt number 12 arrives at time 16'd200, and the reported data is 20'b1_1100_000000011001000; Interrupt number 15 arrives at time 16'd300, and the reported data is 20'b1_1111_000000100101100; Interrupt number 12 ended at time 16'd400, and the reported data at this time was 20'b1_1100_000000110010000; Interrupt number 5 ended at time 16'd500, and the reported data at this time was 20'b1_0101_000000111110100; Interrupt number 15 ended at time 16'd600, and the reported data at this time was 20'b1_1111_000001001011000; Therefore, when there are few instances of batch interrupts changing states simultaneously within the system, enabling dynamic compression can reduce a significant amount of data.

[0083] As can be seen from the above chip signal interrupt monitoring and processing method, this method dynamically monitors chip interrupt source signals by constructing a monitoring configuration table that maps marker values ​​to interrupt sequence numbers and priorities. It supports dynamic modification of the configuration table during operation and can achieve full interrupt source coverage with a small number of monitoring channels through time-division multiplexing, significantly reducing chip hardware resources. This method can significantly reduce the storage space for long-term monitoring by compressing the monitoring process, thereby improving the efficiency of monitoring data storage. At the same time, it can accurately restore the physical occurrence and termination sequence of interrupts, restore the interrupt nesting relationship, verify whether the interrupt priority execution meets expectations, and calculate the interrupt processing duration through timestamps to evaluate system performance. This provides data support for chip problem localization, chip application development, and software optimization in complex scenarios.

[0084] Corresponding to the above embodiments of the chip signal interruption monitoring and processing method, this embodiment of the invention also provides a chip signal interruption monitoring and processing system, such as... Figure 3 As shown, the system includes: Configuration processing module 100: is used to set multiple different flag values ​​based on the number of interrupt sequence numbers configured for the chip interrupt source signal, and to construct a monitoring configuration table through the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal; Interrupt source signal processing module 200: When multiple target interrupt source signals are detected to have changed, it obtains the target flag value and timestamp of each target interrupt source signal, and uses the target flag value to obtain the target priority of each target interrupt source signal from the monitoring configuration table; Processing order acquisition module 300: used to acquire the actual interrupt processing order of each target interrupt source signal using timestamps, and to acquire the target interrupt processing order of each target interrupt source signal using target priority; Interrupt monitoring and processing module 400: Used to obtain the interrupt monitoring and processing results of multiple target interrupt source signals based on the comparison results between the actual interrupt processing order and the target interrupt processing order.

[0085] As can be seen from the above chip signal interrupt monitoring and processing system, this system dynamically monitors chip interrupt source signals by constructing a monitoring configuration table that maps marker values ​​to interrupt sequence numbers and priorities. It supports dynamic modification of the configuration table during operation and can achieve full interrupt source coverage with a small number of monitoring channels through time-division multiplexing, significantly reducing chip hardware resources. By compressing the monitoring process, the system can significantly reduce the storage space required for long-term monitoring, improving the efficiency of monitoring data storage. At the same time, it can accurately restore the physical occurrence and termination sequence of interrupts, restore interrupt nesting relationships, verify whether interrupt priority execution meets expectations, and calculate interrupt processing time through timestamps to evaluate system performance. This provides data support for chip problem localization, chip application development, and software optimization in complex scenarios.

[0086] The chip signal interruption monitoring and processing system provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned chip signal interruption monitoring and processing method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned chip signal interruption monitoring and processing method embodiment.

[0087] This embodiment also provides an electronic device, the structural schematic diagram of which is shown below. Figure 4 As shown, the device includes a processor 101 and a memory 102; wherein, the memory 102 is used to store one or more computer instructions, which are executed by the processor to implement the steps of the chip signal interruption monitoring and processing method described above.

[0088] Figure 4 The electronic device shown also includes a bus 103 and a communication interface 104, with the processor 101, communication interface 104 and memory 102 connected via the bus 103.

[0089] The memory 102 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The bus 103 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 4 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0090] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and to send encapsulated IPv4 packets or IPv4 packets to the user terminal through the network interface.

[0091] Processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. The processor 101 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 102. The processor 101 reads the information in memory 102 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0092] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the chip signal interruption monitoring and processing method described in the foregoing embodiments.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, devices, and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0094] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0095] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0096] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0097] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip signal interruption monitoring and processing method, characterized in that, The method includes: Based on the number of interrupt sequence numbers configured for the chip interrupt source signal, multiple different flag values ​​are set, and a monitoring configuration table is constructed by mapping each flag value to the target interrupt sequence number and priority of the chip interrupt source signal. When multiple target interruption source signals are detected to have changed, the target flag value and timestamp of each target interruption source signal are obtained, and the target priority of each target interruption source signal is obtained from the monitoring configuration table using the target flag value; The actual interrupt processing order of each target interrupt source signal is obtained using the timestamp, and the target interrupt processing order of each target interrupt source signal is obtained using the target priority; The interrupt monitoring and processing results are obtained based on the comparison between the actual interrupt processing order and the target interrupt processing order. The interrupt sequence number configuration based on the chip interrupt source signal can be set with multiple different flag values, including: The number of interrupt sequence numbers is determined based on the total number of interrupt sources in the chip's interrupt source signal; wherein, the total number of interrupt sources and the number of interrupt sequence numbers are divisible by an integer, and the total number of interrupt sources is greater than the number of interrupt sequence numbers. Using the number of interrupt sequence numbers as the starting flag value, and calculating the result of decreasing the starting flag value according to a preset step size, multiple different flag values ​​are set sequentially; A monitoring configuration table is constructed by mapping each tag value to the target interrupt sequence number and priority of the chip interrupt source signal, including: The number of interrupt sequence numbers is configured to obtain multiple different target interrupt sequence numbers from the chip interrupt source signals; The priority of the target interrupt number is calculated and obtained based on the sequence number value corresponding to the target interrupt number; Based on the number of the stated marker values, a mapping relationship is constructed between each marker value and the target interrupt sequence number and the priority, and the monitoring configuration table is constructed using the mapping relationship.

2. The chip signal interruption monitoring and processing method according to claim 1, characterized in that, When changes are detected in multiple target interrupt source signals, the target flag value and timestamp of each target interrupt source signal are obtained, including: When multiple target interrupt source signals are detected to have changed, the data packet reported by each target interrupt source signal is acquired. The status character of each target interrupt source signal is determined based on the first character in the data packet, the timestamp string of each target interrupt source signal is determined based on the last 15 characters of the data packet, and the interrupt source status string of each target interrupt source signal is determined based on the string between the status character and the timestamp string in the data packet. The target marker value of each target interrupt source signal is obtained by using the position marker value of the non-zero character in the interrupt source status string; The timestamp of each target interrupt source signal is obtained based on the hexadecimal conversion result of the timestamp string.

3. The chip signal interruption monitoring and processing method according to claim 2, characterized in that, The step of obtaining the target marker value of each target interrupt source signal using the position marker value of the non-zero character in the interrupt source status string includes: Determine whether the number of interrupt sequence numbers configured is the same as the length of the interrupt source status string; If so, the position marker values ​​of each character in the interrupt source status string are set sequentially in ascending order, starting from the last character of the interrupt source status string and ending from the first character of the interrupt source status string. Obtain the position marker value of the non-zero character in the interrupt source status string, and obtain the target marker value that is the same as the position marker value from the monitoring configuration table.

4. The chip signal interruption monitoring and processing method according to claim 1, characterized in that, The actual interrupt processing order of each target interrupt source signal is obtained using the timestamp, including: The actual interrupt execution time of each target interrupt source signal is determined based on the decimal conversion result of the timestamp; After sorting the actual interrupt execution times in ascending order, the actual interrupt processing order of each target interrupt source signal is obtained based on the sorting result.

5. The chip signal interruption monitoring and processing method according to claim 1, characterized in that, Obtaining the target interrupt processing order for each target interrupt source signal using the target priority includes: The expected interrupt priority value of each target interrupt source signal is obtained based on the numerical conversion result of the target priority; After sorting the expected interrupt priority values ​​in descending order, the target interrupt processing order of each target interrupt source signal is obtained based on the sorting result.

6. The chip signal interruption monitoring and processing method according to claim 1, characterized in that, The interrupt monitoring and processing results are obtained based on the comparison between the actual interrupt processing order and the target interrupt processing order, including: Using the target flag value of each target interrupt source signal, obtain the first execution sequence array corresponding to the actual interrupt processing order and the second execution sequence array corresponding to the target interrupt processing order, respectively; If the first execution sequence array is the same as the second execution sequence array, then the plurality of target interrupt source signals correspond to the interrupt execution normal state; If the first execution sequence array is different from the second execution sequence array, then the plurality of target interrupt source signals correspond to an interrupt execution abnormal state; The interrupt monitoring and processing results of the multiple target interrupt source signals are obtained based on the normal interrupt execution state and the abnormal interrupt execution state.

7. A chip signal interruption monitoring and processing system, characterized in that, The system includes: Configuration processing module: used to set multiple different flag values ​​based on the number of interrupt sequence numbers configured for the chip interrupt source signal, and to construct a monitoring configuration table through the mapping relationship between each flag value and the target interrupt sequence number and priority of the chip interrupt source signal; Interrupt source signal processing module: When multiple target interrupt source signals are detected to have changed, it obtains the target flag value and timestamp of each target interrupt source signal, and uses the target flag value to obtain the target priority of each target interrupt source signal from the monitoring configuration table; Processing order acquisition module: used to acquire the actual interrupt processing order of each target interrupt source signal using the timestamp, and to acquire the target interrupt processing order of each target interrupt source signal using the target priority; Interrupt monitoring and processing module: used to obtain the interrupt monitoring and processing results of the multiple target interrupt source signals based on the comparison result between the actual interrupt processing order and the target interrupt processing order; In the process of setting multiple different flag values ​​based on the interrupt sequence number configuration quantity of the chip interrupt source signal, the configuration processing module is further configured to: determine the interrupt sequence number configuration quantity according to the total number of all interrupt sources of the chip interrupt source signal; wherein, the total number of all interrupt sources and the interrupt sequence number configuration quantity satisfy an integer division relationship, and the total number of all interrupt sources is greater than the interrupt sequence number configuration quantity; and set multiple different flag values ​​sequentially based on the calculation result of the interrupt sequence number configuration quantity as the starting flag value and decreasing the starting flag value according to a preset step size. In the process of constructing a monitoring configuration table by mapping each marker value to the target interrupt sequence number and its priority of the chip interrupt source signal, the configuration processing module is also used to: obtain multiple different target interrupt sequences in the chip interrupt source signal using the number of interrupt sequence numbers configured; calculate and obtain the priority of the target interrupt sequence number based on the sequence number value corresponding to the target interrupt sequence number; construct a mapping relationship between each marker value and the target interrupt sequence number and the priority according to the number of marker values, and construct the monitoring configuration table through the mapping relationship.

8. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the steps of the chip signal interruption monitoring and processing method according to any one of claims 1 to 6.

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