Data caching method, sector adjustment circuit, controller, cache module and device

Abstract

The present disclosure provides a data caching method, a sector adjustment circuit, a controller, a caching module and an apparatus, and belongs to the technical field of computers. The caching module comprises: a sector adjustment circuit, a controller and a plurality of cache lines, each cache line comprising a plurality of sectors; the sector adjustment circuit is configured to, in a case where a hit result of an access request for the caching module represents a cache line hit but a sector miss, adjust a sector prefetch size carried in the access request to obtain an adjusted sector prefetch size; and the controller is configured to obtain target data from a downstream storage module of the caching module according to the adjusted sector prefetch size, and fill the target data into at least part of the sectors of the cache line corresponding to the access request. The embodiment of the present disclosure can flexibly adjust the size of the preloaded data, and has a small software and hardware overhead.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data caching method, a sector adjustment circuit, a controller, a cache module, and a data processing device. Background Technology

[0002] In computer system caching design, a cache line is the smallest unit of cache operation. To reduce bandwidth waste in the cache interface, a cache line can be further divided into multiple smaller sectors, and each sector of the cache line can be fetched independently, thereby reducing unnecessary data transfer.

[0003] In related technologies, if a processor accesses multiple different sectors of a cache line within a short period, and each access only retrieves data corresponding to one sector downstream, subsequent access requests are more likely to result in cache hits but sector misses. This necessitates sending access requests downstream, leading to low throughput utilization for downstream access. Therefore, there is an urgent need for a data caching method that can flexibly adjust the preloaded data size while minimizing hardware and software overhead. Summary of the Invention

[0004] This disclosure provides a data caching method, a sector adjustment circuit, a controller, a caching module, and a data processing device.

[0005] In a first aspect, this disclosure provides a caching module, which includes a sector adjustment circuit, a controller, and multiple cache lines, each cache line including multiple sectors; the sector adjustment circuit is used to adjust the sector prefetch size carried in the access request when the hit result of the access request for the caching module indicates that the cache line is hit but the sector is not hit, to obtain an adjusted sector prefetch size; the controller is used to obtain target data from the downstream storage module of the caching module according to the adjusted sector prefetch size, and fill the target data into at least a portion of the sectors of the cache line corresponding to the access request.

[0006] Secondly, this disclosure provides a data caching method applicable to a sector adjustment circuit of a cache module. The cache module further includes a controller and multiple cache lines, each cache line comprising multiple sectors. The data caching method includes: adjusting the sector prefetch size carried in the access request when the hit result of an access request to the cache module indicates that the cache line is hit but the sector is not hit, to obtain an adjusted sector prefetch size; wherein the adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

[0007] Thirdly, this disclosure provides a data caching method applicable to the controller of a cache module. The cache module further includes a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors. The data caching method includes: obtaining target data from a downstream storage module of the cache module based on a sector prefetch size to fill at least a portion of the sectors of the cache line corresponding to the access request; wherein the sector prefetch size includes the sector prefetch size carried in the access request, or an adjusted sector prefetch size determined by the sector adjustment circuit adjusting the sector prefetch size carried in the access request, the sector adjustment circuit being used to execute the data caching method described above.

[0008] Fourthly, this disclosure provides a sector adjustment circuit disposed in a cache module, the cache module further including a controller and multiple cache lines, each cache line including multiple sectors; the sector adjustment circuit is used to adjust the sector prefetch size carried in the access request when the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, to obtain an adjusted sector prefetch size; wherein, the adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module, so as to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

[0009] Fifthly, this disclosure provides a controller disposed in a cache module, the cache module further comprising a sector adjustment circuit and multiple cache lines, each cache line comprising multiple sectors; the controller is configured to obtain target data from a downstream storage module of the cache module based on a sector prefetch size to fill at least a portion of the sectors of the cache line corresponding to the access request; wherein the sector prefetch size includes the sector prefetch size carried in the access request, or an adjusted sector prefetch size determined by the sector adjustment circuit adjusting the sector prefetch size carried in the access request, the sector adjustment circuit employing any of the above-mentioned sector adjustment circuits.

[0010] In a sixth aspect, this disclosure provides a data processing apparatus, which includes at least one cache module and at least one processing module. The processing module is used to obtain data to be processed from the cache module and / or to store the processing result in the cache module. The cache module adopts any of the above-mentioned cache modules.

[0011] The cache module provided in this embodiment includes a sector adjustment circuit, a controller, and multiple cache lines, each cache line including multiple sectors. The sector adjustment circuit can adjust the sector prefetch size carried in the access request when the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, to obtain an adjusted sector prefetch size. The controller can obtain target data from the downstream storage module of the cache module according to the adjusted sector prefetch size and fill the target data into at least a portion of the sectors of the cache line corresponding to the access request.

[0012] Therefore, this embodiment only adds a sector adjustment circuit at the hardware level. It can adjust the sector prefetch size through a relatively simple adjustment logic, with low hardware overhead and improved flexibility of sector prefetch size. Based on this, the controller can prefetch the target data corresponding to the adjusted sector prefetch size and fill it into at least part of the sectors of the cache line corresponding to the access request. Compared with prefetching data based on a fixed sector prefetch size, the adjusted sector prefetch size is a prefetch size that is more suitable for the access behavior or access pattern of the cache module. Therefore, it helps to improve the subsequent sector hit rate, thereby effectively reducing the number of prefetches, improving prefetch efficiency and throughput utilization in the downstream access direction.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0014] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed example embodiments described below with reference to the accompanying drawings.

[0015] Figure 1 This is a block diagram of a caching module provided in an embodiment of the present disclosure.

[0016] Figure 2 This is a schematic diagram of a caching module provided in an embodiment of the present disclosure.

[0017] Figure 3A flowchart of a data caching method provided in an embodiment of this disclosure.

[0018] Figure 4 A flowchart of another data caching method provided in an embodiment of this disclosure.

[0019] Figure 5 This is a block diagram of a sector adjustment circuit provided in an embodiment of the present disclosure.

[0020] Figure 6 This is a block diagram of a controller provided in an embodiment of the present disclosure.

[0021] Figure 7 This is a block diagram of a data processing apparatus provided in an embodiment of the present disclosure. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0024] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0026] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0027] In modern computer system cache design, a cache line is the smallest unit of cache access performed by processors such as the Central Processing Unit (CPU) or Graphics Processing Unit (GPU). When a memory address is accessed, the entire cache line is loaded into the cache. To reduce bandwidth waste at the cache module interface, the concept of a sector was introduced. A cache line is divided into multiple fine-grained sectors. Multiple sectors can share a cache line tag, and each sector can be assigned a unique bit to indicate whether it is valid. This approach allows each sector in a cache line to be fetched independently, minimizing unnecessary data transfer. For example, if a cache line is 128 bytes in size, comprising four sectors of 32 bytes each, accessing only one sector of the cache line will not require loading data from other sectors downstream.

[0028] If multiple different sectors of a cache line are accessed within a short period, and only one sector is loaded downstream each time, subsequent access requests may experience cache hits but sector misses, requiring further downstream requests and resulting in low throughput utilization in the request direction. Therefore, for this access pattern, preloading the entire cache line is advantageous. Thus, a method is needed to determine or adjust the sector prefetch size.

[0029] In related technologies, sector prefetch size can be determined or adjusted using software solutions. For example, a fixed sector prefetch size can be set for each requester or each access request to control the size of sectors fetched downstream. However, since access patterns can vary greatly, some access patterns may be suitable for larger sector prefetch sizes, while others may be suitable for smaller ones. Determining a reasonable sector prefetch size is logically complex and costly. Alternatively, sector prefetch size can be determined or adjusted using hardware solutions, but this requires complex hardware logic and increases hardware area overhead, resulting in higher hardware costs.

[0030] In view of this, the present disclosure provides a data caching method, a sector adjustment circuit, a controller, a caching module, and a data processing device, which can flexibly adjust the size of preloaded data and have low software and hardware overhead.

[0031] This disclosure provides a caching module.

[0032] Figure 1 This is a block diagram of a caching module provided in an embodiment of this disclosure. (Refer to...) Figure 1 The cache module 100 includes a sector adjustment circuit 110, a controller 120, and multiple cache lines 130, each cache line 130 including multiple sectors 131.

[0033] The sector adjustment circuit 110 is used to adjust the sector prefetch size carried in the access request when the hit result of the access request for the cache module 100 indicates that the cache line is hit but the sector is not hit, so as to obtain the adjusted sector prefetch size.

[0034] The controller 120 is configured to obtain target data from the downstream storage module of the cache module 100 according to the adjusted sector prefetch size, and fill the target data into at least a portion of the sectors of the cache line corresponding to the access request.

[0035] Caching is a storage mechanism primarily used to provide high-speed access to saved data or computation results. Based on this mechanism, a caching module is set up to provide temporary storage for frequently accessed data. When this data is needed again, it can be quickly retrieved from the cache module instead of directly from the downstream storage module, thereby reducing access time and improving access efficiency.

[0036] In this embodiment of the disclosure, the caching module includes multiple cache lines, each cache line includes multiple sectors, and each sector can serve as a minimum data management unit, thereby enabling finer-grained data management.

[0037] For example, a cache line may include 8 sectors, namely sector 0, sector 1, sector 2, ..., sector 7.

[0038] For example, an access request may be a read request sent from an upstream module (such as a central processing unit) to read data from a specified address.

[0039] For example, the access request may carry a cacheline ID and a sector ID to indicate the cacheline to be accessed and the sector to be accessed in that cacheline.

[0040] In some optional embodiments, upon receiving an access request, the hit result of the access request can be determined, and the hit result can characterize whether the access request can read the corresponding data from the cached data (i.e., the data stored in the cache module).

[0041] It should be noted that the hit result can include three cases: cache line miss, cache line hit but sector miss, and cache line hit and sector hit. Among them, cache line miss includes cases such as invalid cache line or address mismatch. Cache line hit but sector miss means that the cache line exists and is valid, but the sector to be accessed is missing cached data. Cache line hit and sector hit means that the cache line exists and is valid, and the sector to be accessed also contains valid cached data.

[0042] Furthermore, in this embodiment of the disclosure, the access request carries a sector prefetch size, which is related to the size of the data prefetched from the downstream storage module. In other words, the sector prefetch size is used to indicate the size, amount, and dimensions of the data prefetched from the downstream storage module.

[0043] Downstream storage modules refer to storage modules that are logically farther from the processor and accessed at a lower level than cache modules. For example, for a CPU, if the cache module corresponds to the L2 cache level, then the downstream storage module can correspond to the L3 cache level. For example, for a GPU, if the cache module corresponds to the L1 cache dedicated to each streaming multiprocessor (SM) in the GPU, then the downstream storage module can correspond to the GPU's global on-chip L2 cache.

[0044] It should be noted that the above examples of the cache module and downstream storage module are merely illustrative and are not intended to limit the scope of this disclosure.

[0045] In some optional embodiments, if the hit result indicates that both the cache line and the sector are hit, the controller can read the corresponding data from the corresponding sector based on the sector prefetch size carried in the access request and feed it back to the party that initiated the access request.

[0046] In some optional embodiments, when the hit result indicates that the cache line is hit but the sector is not hit, the sector adjustment circuit in the cache module can be used to adjust the sector prefetch size carried in the access request to obtain the adjusted sector prefetch size. Based on this, the controller can prefetch the corresponding data from the downstream storage module according to the adjusted sector prefetch size and fill the prefetched data into the corresponding sector of the cache line.

[0047] Therefore, in this embodiment, different hit results may occur for access requests. Furthermore, for different hit results, the sector prefetch size carried in the access request can be adjusted using a sector adjustment circuit. This allows the controller to prefetch target data of a more reasonable size from the downstream storage module based on the adjusted sector prefetch size and fill the target data into the corresponding sector of the cache line corresponding to the access request. Compared to related technologies that prefetch data according to a fixed sector prefetch size, this approach offers greater flexibility and improves prefetch efficiency.

[0048] In summary, the cache module of this embodiment adds only a sector adjustment circuit at the hardware level. It can adjust the sector prefetch size through a relatively simple adjustment logic, with low hardware overhead and improved flexibility of sector prefetch size. Based on this, the controller can prefetch the target data corresponding to the adjusted sector prefetch size and fill it into at least a portion of the sectors of the cache line corresponding to the access request. Compared with prefetching data based on a fixed sector prefetch size, the adjusted sector prefetch size is a prefetch size that is more closely matched to the access behavior or access pattern of the cache module. Therefore, it helps to improve the subsequent sector hit rate, thereby effectively reducing the number of prefetches, improving prefetch efficiency and throughput utilization for downstream access directions.

[0049] The caching module of this embodiment will be described in detail below.

[0050] In some optional embodiments, the sector adjustment circuit may include a judgment unit and a processing unit. The judgment unit can identify whether the hit result indicates a cache line hit but a sector miss. The processing unit, if the judgment unit determines that the hit result is a cache line hit but a sector miss, can invoke preset adjustment logic to adjust the sector prefetch size carried in the access request. The adjustment logic includes the sum of conditions for triggering sector prefetch size adjustment at the logical level, the adjustment method, etc. The adjustment logic can be encapsulated into several preset adjustment strategies, enabling the sector adjustment circuit to conveniently and accurately adjust the sector prefetch size based on the corresponding preset adjustment strategies.

[0051] For example, the controller can transmit an indication signal representing a cache line hit but a sector miss to the judgment unit via a register or similar means. Based on this indication signal, the judgment unit can determine that the hit result is a cache line hit but a sector miss. The judgment unit can be implemented using hardware devices such as logic gates and numerical comparators. Furthermore, if the sector adjustment circuit supports multiple different adjustment logics, the processing unit can further include sub-units such as multiplexers and adders. The multiplexer can select the adjustment logic to be used from multiple adjustment logics, and the adder can adjust the sector prefetch size carried in the access request based on the adjusted sector prefetch size value determined by the adjustment logic, thereby obtaining the adjusted sector prefetch size and sending it to the controller.

[0052] Furthermore, in some optional embodiments, the sector adjustment circuit may also include a counting unit, which can count the number of times a cache line is hit but a sector is not hit, so that the processing unit can combine the number of times with the corresponding adjustment logic to adjust the sector prefetch size carried in the access request; wherein, the counting unit may be implemented based on at least some of the hardware devices such as flip-flops, logic gates, and counters, and the embodiments of this disclosure do not limit this.

[0053] It should be noted that the above description of the composition of the sector adjustment circuit is merely an example. Any hardware device capable of implementing the corresponding functions and processing logic can be applied to the hardware implementation of the sector adjustment circuit, and this disclosure does not impose any limitations on this.

[0054] In some optional embodiments, the sector adjustment circuit is further configured to adjust the sector prefetch size carried in the access request based on a preset adjustment strategy to obtain the adjusted sector prefetch size; wherein, the preset adjustment strategy is configured to adjust the sector prefetch size carried in the access request according to the number of times the cache line is hit but the sector is not hit, and the value of any sector prefetch size is a power of 2.

[0055] In this case, the adjusted sector prefetch size is larger than the original sector prefetch size. In other words, when a cache line is hit but a sector is not, considering access locality, the likelihood of repeatedly accessing that cache line is high. Therefore, by adjusting the sector prefetch size carried in the access request to a larger size through the sector adjustment circuit, multiple sectors in the cache line can be pre-filled, which helps to improve the subsequent hit rate, improve access efficiency, and reduce the number of accesses to downstream storage modules.

[0056] Therefore, the preset adjustment strategy adjusts the sector prefetch size based on the frequency of cache line hits but sector misses. For any given cache line, if cache line hits but sector misses occur frequently, it indicates that access to that cache line is relatively intensive in the short term. To improve the sector hit rate, the sector prefetch size carried in the access requests corresponding to that cache line can be adjusted by the sector adjustment circuit. In other words, the frequency of cache line hits but sector misses reflects the access behavior characteristics for the corresponding cache line. Based on this, a reasonable preset adjustment strategy can be set and implemented using the sector adjustment circuit, thereby flexibly adjusting the size of the preloaded data.

[0057] Furthermore, the preset adjustment strategy corresponds to a set of adjustment logic for sector prefetch size. This adjustment logic can be implemented as corresponding hardware logic (such as combinational logic, sequential circuits, state machines, dedicated paths, etc.) using the sector adjustment circuit, thereby utilizing the low latency and high reliability of the hardware unit to perform flexible adjustment of sector prefetch size.

[0058] In some optional embodiments, the preset adjustment strategy corresponds to multiple levels of sector prefetch size, and the value of the sector prefetch size is positively correlated with the level; accordingly, the preset adjustment strategy includes at least one of a first adjustment strategy, a second adjustment strategy, and a third adjustment strategy: for the cache line corresponding to the access request, the first adjustment strategy is used to adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level in response to the first occurrence of a cache line hit but a sector miss; for the cache line corresponding to the access request, the second adjustment strategy is used to adjust the sector prefetch size carried in the access request according to the first preset level difference in response to each occurrence of a cache line hit but a sector miss; for the cache line corresponding to the access request, the third adjustment strategy is used to adjust the sector prefetch size carried in the access request according to the second preset level difference in response to the first occurrence of a cache line hit but a sector miss, and to adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level in response to the second occurrence of a cache line hit but a sector miss.

[0059] The first preset level difference and the second preset level difference are used to characterize the level difference between the level corresponding to the adjusted sector prefetch size and the level corresponding to the sector prefetch size before adjustment. The first preset level difference and the second preset level difference may have the same or different values.

[0060] Therefore, the preset adjustment strategy corresponds to multiple adjustable sector prefetch sizes, each sector prefetch size corresponds to a level, and the value of the sector prefetch size at any level is a power of 2. As the level increases, the value of the corresponding sector prefetch size also increases accordingly.

[0061] For example, the preset adjustment strategy corresponds to three levels of sector prefetch size, with the first level having a sector prefetch size of 2. 0 =1, the prefetch size of the sector at the second level is 2. 1 =2, the prefetch size of the sector at the third level is 2. 2 =4.

[0062] For example, the preset adjustment strategy corresponds to four levels of sector prefetch size, with the first level having a sector prefetch size of 2. 0 =1, the prefetch size of the sector at the second level is 2. 1 =2, the prefetch size of the sector at the third level is 2. 2 =4, the prefetch size of the sector at level 4 is 2. 3 =8.

[0063] For example, the preset adjustment strategy corresponds to five levels of sector prefetch size, with the first level having a sector prefetch size of 2. 0 =1, the prefetch size of the sector at the second level is 2. 1 =2, the prefetch size of the sector at the third level is 2. 2 =4, the prefetch size of the sector at level 4 is 2. 3 =8, the prefetch size of the sector at level 5 is 2. 4 =16.

[0064] It should be noted that the above examples of adjustable sector prefetch sizes and their corresponding levels are merely illustrative and are not intended to limit the scope of this disclosure. The highest-level sector prefetch size can be less than or equal to the total number of sectors in a cache line, or it can be greater than the total number of sectors in a cache line. Data prefetching may be performed on a single cache line or across multiple cache lines.

[0065] For example, the sector prefetch size corresponds to N levels, where N is an integer greater than 1. An access request is used to initiate a read request for cacheline(i), carrying a sector prefetch size of size(k), corresponding to the k-th level (1≤k≤N). Based on this, under the first adjustment strategy, if a cache line hit occurs for the first time but a sector miss occurs, regardless of the value of the sector prefetch size carried in the access request, the sector adjustment circuit adjusts the sector prefetch size size(k) carried in the access request to the sector prefetch size size(N) corresponding to the highest level N, i.e., the sector prefetch size of the N-th level. Under the second adjustment strategy, if the first preset level difference is d1, then as long as a cache line hit occurs but a sector miss occurs... In the event of a sector miss, the sector adjustment circuit adjusts the sector prefetch size (k) carried in the access request to the sector prefetch size (k+d1) corresponding to the (k+d1)th level. When using the third adjustment strategy, if the difference between the second preset levels is d2, and a cache line hit occurs for the first time but a sector miss occurs, the sector adjustment circuit adjusts the sector prefetch size (k) carried in the access request to the sector prefetch size (k+d2) corresponding to the (k+d2)th level. If a cache line hit occurs for the second time but a sector miss occurs, regardless of the value of the sector prefetch size carried in the access request, the sector adjustment circuit adjusts the sector prefetch size to the sector prefetch size (N) corresponding to the highest level N. The values ​​of d1 and d2 can be the same or different.

[0066] Therefore, the embodiments of this disclosure provide a variety of optional preset adjustment strategies, such as the aforementioned first adjustment strategy, second adjustment strategy and third adjustment strategy.

[0067] The first adjustment strategy adjusts the sector prefetch size to the maximum value (corresponding to the highest level) when the cache line to be accessed first encounters a situation where the cache line is hit but the sector is not hit. This allows a large amount of data to be obtained through a single prefetch to fill the cache line, which is beneficial to improving the sector hit rate of the cache line in subsequent access processes, resulting in higher bus efficiency and bandwidth utilization.

[0068] The second adjustment strategy increases the sector prefetch size step by step using an arithmetic progression, which can balance the sector hit rate of the cache line with the reduction of caching of useless data and squeezing out of useful data, thus making it less likely to cause cache pollution.

[0069] The third adjustment strategy sets up two ways to increase the sector prefetch size. For the first case where a cache line is hit but a sector is missed, the sector prefetch size is increased by the second preset level difference to improve the sector hit rate efficiently. If a cache line is hit but a sector is missed a second time, it means that the probability of subsequent access requests to that cache line is relatively high. Therefore, to improve the sector hit rate of subsequent accesses, the sector prefetch size is directly adjusted to the maximum value. By increasing the sector prefetch size in this way, the prefetch granularity can be adjusted more finely, which helps to balance sector hit rate, bus efficiency and bandwidth utilization.

[0070] In some optional embodiments, the first preset level difference and the second preset level difference are both of the same level; correspondingly, for the cache line corresponding to the access request, the second adjustment strategy is used to respond to the situation where the cache line is hit but the sector is not hit each time, and to use the sector prefetch size corresponding to the sector prefetch size carried in the access request as the adjusted sector prefetch size after increasing the level by one level; for the cache line corresponding to the access request, the third adjustment strategy is used to respond to the situation where the cache line is hit but the sector is not hit for the first time, and to use the sector prefetch size corresponding to the sector prefetch size carried in the access request as the adjusted sector prefetch size after increasing the level by one level.

[0071] For example, the first preset level difference is a level. Based on this, when the second adjustment strategy is adopted, for a certain cache line, as long as there is a cache line hit but a sector miss, the sector adjustment circuit will increase the level corresponding to the sector prefetch size carried in the access request by one level, and use the sector prefetch size corresponding to the increased level as the adjusted sector prefetch size.

[0072] For example, the second preset level difference is one level. Based on this, when the third adjustment strategy is adopted, for a certain cache line, when the cache line hits but the sector misses for the first time, the sector adjustment circuit increases the level corresponding to the sector prefetch size carried in the access request by one level, and uses the sector prefetch size corresponding to the increased level as the adjusted sector prefetch size. If the cache line hits but the sector misses for the second time, the sector adjustment circuit directly adjusts to the maximum value or the highest level of sector prefetch size, regardless of the sector prefetch size carried in the access request.

[0073] Therefore, setting the first and second preset level differences to large values ​​would lead to premature caching of a large amount of data that may not be accessed in the short term, thus wasting cache resources. Therefore, setting the first and second preset level differences to a single level allows for a more gradual increase in sector prefetch size, improving hit rate and prefetch efficiency to some extent while reducing premature caching of useless data.

[0074] Furthermore, a time interval can be preset. Correspondingly, when employing the third adjustment strategy, for a given cache line, if a cache line hit but sector miss occurs for the first time at time T1, the sector adjustment circuit increases the prefetch level corresponding to the sector prefetch size carried in the access request by one level, and uses the increased prefetch size as the adjusted sector prefetch size. If the cache line hits but sector misses for the second time at time T2, and if T2 - T1 ≤ time interval, then regardless of the prefetch level carried in the access request... If the sector prefetch size is set to a certain value, it is directly adjusted to the maximum value or the highest level of sector prefetch size. Conversely, if T2 - T1 > the time interval, it means that the interval between the two access behaviors is relatively long. Therefore, it can be considered that the situation of cache line hit but sector miss at time T2 is a new and first occurrence of cache line hit but sector miss. Based on this, the sector adjustment circuit increases the level of the sector prefetch size carried in the access request corresponding to time T2 by one level, and uses the sector prefetch size corresponding to the increased level as the adjusted sector prefetch size.

[0075] The value of the time interval can be determined based on experience, statistical data, and simulation data, and this embodiment does not impose any restrictions on it. Furthermore, by using the time interval, the time range for adjusting the sector prefetch size can be further limited, thereby making fuller use of the locality of access and helping to reduce the caching of useless data.

[0076] In some optional embodiments, a sector hit indicator can be set for each cache line; for any cache line: when a cache line miss occurs for the first time, the sector hit indicator is initialized to a first indicator; when a cache line hit occurs for the first time but a sector miss occurs, the sector hit indicator is adjusted from the first indicator to a second indicator; when a cache line hit occurs for the second time but a sector miss occurs, the sector hit indicator is reset from the second indicator to the first indicator; for the cache line corresponding to the access request, the sector adjustment circuit is further configured to, in the case of a preset adjustment strategy of a third adjustment strategy, adjust the sector prefetch size carried in the access request according to a second preset level difference in response to the sector hit indicator value being adjusted from the first indicator to the second indicator, and, in response to the sector hit indicator value being adjusted from the second indicator to the first indicator, adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level. The first identifier and the second identifier have different values. For example, the first identifier can be "0" and the corresponding second identifier can be "1", or vice versa. This disclosure does not limit this.

[0077] For example, a sector hit indicator flag, cacheline_sector_miss_flag, is set for each cacheline. When a cacheline experiences its first cache line miss, cacheline_sector_miss_flag is set to 0. When the cacheline experiences its first cache hit but sector miss (cacheline_sector_miss_flag = 0), cacheline_sector_miss_flag is set to 1. When the cacheline experiences its second cache hit but sector miss (cacheline_sector_miss_flag = 1), cacheline_sector_miss_flag is reset to 0. Correspondingly, when the value of `cacheline_sector_miss_flag` is adjusted from 0 to 1, it indicates that the cache line has experienced a cache hit but a sector miss for the first time. Therefore, the sector adjustment circuit can increase the sector promotion size carried in the access request by one level. When the value of `cacheline_sector_miss_flag` is adjusted from 1 to 0, it indicates that the cache line has experienced a cache hit but a sector miss for the second time. Therefore, the sector adjustment circuit can directly increase the sector promotion size to the highest level, making the adjusted sector prefetch size correspond to the maximum value. Based on this, by observing the changes in the sector hit indicator value, the sector adjustment circuit can easily and accurately determine whether it is the first time a cache line has been hit but a sector miss or the second time a cache line has been hit but a sector miss. Then, it can adjust the sector prefetch size carried in the access request accordingly. The sector adjustment circuit requires less processing time and is highly efficient.

[0078] Therefore, it can be seen that for the first and second adjustment strategies, there is no need to increase the storage information of the cache lines. For the third adjustment strategy, only a small amount of storage information needs to be added (i.e., each cache line adds 1 bit to represent the sector hit indicator). The degree of modification at the hardware level is small, and the required hardware overhead is also correspondingly small.

[0079] Furthermore, regardless of the preset adjustment strategy employed, the corresponding adjustment logic involves determining whether a cache line hit occurs but a sector miss occurs, and if so, simply adjusting the sector prefetch size carried in the access request. In other words, the sector prefetch size adjustment logic based on the preset adjustment strategy is essentially a simple judgment logic, requiring less processing time and having a smaller area overhead. Therefore, it does not significantly increase the hardware cost of the cache module, making hardware implementation relatively simple, with correspondingly lower implementation costs and hardware overhead.

[0080] In some optional embodiments, after determining the adjusted sector prefetch size, the sector adjustment circuit can send the adjusted sector prefetch size to the controller via a preset bus, so that the controller can obtain the corresponding target data from the downstream storage module based on the adjusted sector prefetch size and fill the target data into at least part of the sectors of the cache line corresponding to the access request.

[0081] It should be noted that if the sector prefetch size carried in the access request does not need to be adjusted, the controller can obtain the target data from the downstream storage module of the cache module based on the sector prefetch size carried in the access request, and fill at least a portion of the sectors of the cache line corresponding to the access request with the target data.

[0082] Therefore, the controller in the cache module can obtain the corresponding target data from the downstream storage module based on the sector prefetch size carried in the access request, or the sector prefetch size adjusted by the sector adjustment circuit. This target data is then used to fill at least a portion of the sectors in the cache line corresponding to the access request. The adjusted sector prefetch size is a prefetch size that better matches the access behavior or access pattern of the cache module. Therefore, when prefetching target data based on the adjusted sector prefetch size, the subsequent sector hit rate can be improved, thereby effectively reducing the number of prefetches, improving prefetch efficiency, and increasing throughput utilization in the downstream access direction.

[0083] In some optional embodiments, a selection register can be set inside or outside the cache module. By configuring the input signal of the selection register, one of a plurality of preset adjustment strategies can be selected as the preset adjustment strategy that takes effect for the current access request. As for which preset adjustment strategy to select, it can be determined based on at least one of the following information: experience, statistical data, simulation data, access patterns, etc., and the embodiments of this disclosure do not impose any restrictions on this.

[0084] Figure 2 This is a schematic diagram of a caching module provided in an embodiment of this disclosure. (Refer to...) Figure 2The cache module 200 includes a sector adjustment circuit 210, a controller 220, multiple cache lines 230, and a selection register 240. Each cache line 230 includes n+1 sectors (sector 0 to sector n). The user can generate a strategy selection signal according to requirements and input it into the selection register 240 to select one of the preset adjustment strategies (such as the first adjustment strategy, the second adjustment strategy, or the third adjustment strategy), thereby enabling the sector adjustment circuit 210 to adjust the sector prefetch size based on the selected preset adjustment strategy.

[0085] Upon receiving an access request, the cache module 200 first determines whether the hit result is a cache line hit but a sector miss. If it is, the sector adjustment circuit 210 adjusts the sector prefetch size carried in the access request according to the selected preset adjustment strategy to obtain the adjusted sector prefetch size, and sends the adjusted sector prefetch size to the controller 220. The controller 220 obtains the target data from the downstream storage module 300 according to the adjusted sector prefetch size, and fills the obtained target data into the corresponding sector of the cache line.

[0086] In some alternative embodiments, the controller needs to populate the sectors of the cache line in groups to ensure hardware compatibility.

[0087] For example, if a cache line consists of 8 sectors, namely sectors 0 to 7, the controller can fill the cache line in groups such as sector 0 and sector 1, sector 2 and sector 3, sector 4 and sector 5, and sector 6 and sector 7. Alternatively, it can fill the cache line in groups such as sector 0 to sector 3 and sector 4 to sector 7. However, it cannot use grouping methods that violate hardware alignment principles, such as grouping sector 1 and sector 2 together or grouping sector 3 to sector 6 together.

[0088] In some optional embodiments, the controller is further configured to determine, based on the adjusted sector prefetch size, the sector group in the cache line corresponding to the access request and the target sector group where the sector to be accessed is located, wherein the number of sector groups is one or more, and each sector group includes multiple sectors; determine the target sector to be prefetched based on the target sector group and the valid identifier of each sector in the target sector group; determine the prefetch request based on the target sector and send the prefetch request to the downstream storage module; receive the target data corresponding to the target sector returned by the downstream storage module and fill the target data into the target sector.

[0089] It should be noted that the above processing method is adopted mainly because after adjusting the sector prefetch size, some sector data may have already been prefetched. Therefore, it is not necessary to repeatedly fetch this part of the sector data, thereby reducing the amount of data transmission and reducing the waste of bandwidth resources.

[0090] For example, taking a cache line that includes sectors 0 to 7 as an example, if the sector prefetch size during the first prefetch is 2, and sectors 0 and 1 are filled by the first prefetch, if the sector prefetch size is adjusted to 4, then during the second prefetch, the corresponding sector group consisting of sectors 0 to 3 will be prefetched. Since the data of sectors 0 and 1 has already been obtained during the first prefetch, it is not necessary to obtain this part of the data again this time. Only the data of sectors 2 and 3 needs to be prefetched.

[0091] It should be noted that in the relevant technology, since the sector prefetch size is not adjusted, there is no problem of repeatedly prefetching sector data. Therefore, there is no need to remove the already prefetched sector data. The corresponding sector data can be prefetched directly according to the sector prefetch size.

[0092] In some optional embodiments, a sector's validity identifier can indicate whether the sector is in a valid state. A sector in a valid state already contains the corresponding data, while a sector in an invalid state either does not store data, or the stored data is incorrect or unusable. Therefore, during data prefetching, the validity identifier of a sector can be used to determine whether data for that sector needs to be prefetched.

[0093] In some optional embodiments, the controller is further configured to determine the sector grouping granularity based on the adjusted sector prefetch size; determine each sector group in the cache line corresponding to the access request based on the sector grouping granularity; and determine the sector group in the cache line corresponding to the access request where the sector to be accessed is located as the target sector group.

[0094] The sector grouping granularity can be understood as the number of sectors contained in a single sector group.

[0095] For example, the adjusted sector prefetch size can be used as the sector grouping granularity, and then sector grouping can be performed.

[0096] Therefore, after the sector prefetch size is adjusted, the original sector grouping becomes invalid. Thus, the controller needs to redetermine how many sectors a sector group contains based on the adjusted sector prefetch size, thereby clarifying the sector grouping granularity. Then, based on the sector grouping granularity, the corresponding cache lines are grouped to obtain multiple new sector groups. On this basis, the sector group containing the sector to be accessed is determined as the target sector group, so that after the target data is obtained, it can be accurately filled into the target sector group.

[0097] In some optional embodiments, the value of the valid identifier is either a valid value or an invalid value; accordingly, the controller is also configured to determine the sectors in the target sector group whose valid identifier is invalid as target sectors.

[0098] In other words, for a target sector group, some sectors may already contain valid data. Furthermore, the valid identifier value can accurately and efficiently identify which sectors are valid and which are invalid. Based on this, for the identified valid sectors (i.e., those with valid identifiers), there is no need to repeatedly retrieve data from the downstream storage module; only the invalid sectors (i.e., those with invalid identifiers) need to be prefetched and populated with the corresponding data. This processing method can further reduce the bandwidth overhead between the cache module and the downstream storage module.

[0099] In some optional embodiments, the controller can use the adjusted sector prefetch size as the number of sectors contained in each sector group. The sector to be accessed is the sector indicated by the access request, and the sector group in which this sector belongs is the target sector group. Furthermore, for the target sector group, since some sectors may already contain data, and if the valid identifier of these sectors indicates that they are in a valid state, then for these sectors, it is not necessary to repeatedly retrieve data from the downstream storage module. Therefore, only the sectors in the target sector group whose valid identifier indicates that they are in an invalid state need to be retrieved; these sectors are the target sectors. In this way, repeated data retrieval can be reduced, thereby reducing the waste of bandwidth resources and improving data processing efficiency.

[0100] It should be noted that since the sector prefetch size is a power of 2, using the sector prefetch size as the number of sectors contained in a sector group conforms to the hardware-level sector grouping rules and will not cause hardware incompatibility issues.

[0101] The embodiments of this disclosure are described below using an example where each cache line includes 8 sectors.

[0102] For example, each cache line includes 8 sectors, namely sector0, sector1, sector2, ..., sector7. If the cache line to be accessed has no data loaded, the access pattern is to access sectors0 to sector7 of the cache line sequentially through 8 access requests (request0 to request7), with an access length of 1 for each request (i.e., accessing one sector at a time). Correspondingly, the selectable values ​​for the sector prefetch size are 1, 2, 4, and 8, corresponding to the 1st, 2nd, 3rd, and 4th levels, respectively.

[0103] If the sector prefetch size carried by each access request is set to 1, then for each access request, there will be a situation where the cache line is hit but the sector is not hit. If the sector prefetch size is not adjusted, it means that 8 line fill requests need to be sent to the downstream storage module to obtain the corresponding access data.

[0104] Furthermore, if the sector prefetch size carried by each access request is set to 2, then each access request prefetches the corresponding data downstream in granularity of 2 sectors and fills the corresponding sectors. Here, sector0 and sector1 are grouped together, sector2 and sector3 together, sector4 and sector5 together, and sector6 and sector7 together. For example, if request0 wants to access sector0 and the result is a cache line miss, then data is prefetched from the downstream storage module and filled into sector0 and sector1; if request1 wants to access sector1 and the result is a cache line hit and a sector hit, then the cached data in sector1 can be directly returned; if request2 wants to access sector2 and the result is a cache line hit but a sector miss, then data is prefetched from the downstream storage module and filled into sector2 and sector3, and so on. Therefore, without adjusting the sector prefetch size, a total of 4 linefill requests need to be sent to the downstream storage module.

[0105] Furthermore, if the sector prefetch size carried by each access request is set to 4, then each access request prefetches the corresponding data downstream in 4-sector granularities and fills the corresponding sectors. Sectors 0 to 3 form one group, and sectors 4 to 7 form another. For example, request 0 accesses sector 0, and the result is a cache line miss, so data is prefetched from the downstream storage module and filled into sectors 0 to 3; request 1 accesses sector 1, and the result is a cache line hit and a sector hit, so the cached data in sector 1 is directly returned; ...; request 4 accesses sector 4, and at this time, the cache line in sector 4 has not yet been loaded, so the result is a cache line hit but a sector miss, so data is prefetched from the downstream storage module and filled into sectors 4 to 7, and so on. Therefore, without adjusting the sector prefetch size, 8 access requests require sending 2 linefill requests to the downstream storage module.

[0106] To address the above issues, if the cache module of this embodiment is used, and its sector adjustment circuit adjusts the sector prefetch size according to different hit results, the number of linefill requests sent to downstream storage modules can be effectively reduced, thereby improving prefetch efficiency and utilization of throughput in downstream access directions. The following explanation uses the aforementioned cache behavior comprising eight sectors as an example.

[0107] First, let's take the sector adjustment circuit using the first adjustment strategy as an example for illustrative explanation.

[0108] For example, if the sector prefetch size carried by each access request is set to 1, upon receiving request0, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 1 carried in request0, prefetches the corresponding target data and fills it into sector0, without adjusting the sector prefetch size carried in request0. Upon receiving request1, it is determined that it wants to access sector1, at which time the cache line in sector1 has not yet been loaded. The data shows that the cache line hit was successful, but the sector hit was not, and this was the first time this hit result occurred. Therefore, the sector adjustment circuit in the cache module, according to the adjustment logic of the first adjustment strategy, directly adjusted the sector prefetch size carried in request1 to the highest level corresponding to the sector prefetch size 8, and sent the adjusted sector prefetch size 8 to the controller. The controller then sent a linefill request to the downstream storage module based on the adjusted sector prefetch size 8, prefetched the corresponding target data, and filled sectors 1 to 7. Among them, sector 0 has already been filled in the processing of request 0, so it does not need to be prefetched again. The subsequent hit results of requests 2 to 7 are all cache line hits and sector hits, so there is no need to send a linefill request to the downstream again. Therefore, in the current situation, a total of 2 linefill requests need to be sent to the downstream storage module.

[0109] For example, if the sector prefetch size carried by each access request is set to 2, upon receiving request0, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 2 carried in request0, with sector0 and sector1 grouped together, sector2 and sector3 grouped together, sector4 and sector5 grouped together, and sector6 and sector7 grouped together. The controller prefetches the corresponding target data and fills it into sector0 and sector1, without adjusting the sector prefetch size carried in request0. Upon receiving request1, it is determined that it wants to access sector1. At this time, sector1 of the cache line has already been loaded with data. Therefore, the hit result is a cache line hit and a sector hit, so the cached data in sector1 can be returned directly. Upon receiving request2, it is determined that it needs to access sector2. At this time, sector2 of the cache line has not yet been loaded with data, so the hit result is a cache line hit but a sector miss. Since this is the first occurrence of this hit result, the sector adjustment circuit, according to the adjustment logic of the first adjustment strategy, directly adjusts the sector prefetch size carried in request2 to the highest level corresponding to sector prefetch size 8, and sends the adjusted sector prefetch size 8 to the controller. The controller sends a linefill request to the downstream storage module based on the adjusted sector prefetch size 8, prefetching the corresponding target data and filling sectors2 to 7. Sector0 and sector1 have already been filled in the processing of request0, so there is no need to prefetch them again. The hit results of subsequent requests 3 to 7 are all cache line hits and sector hits, so the controller does not need to send linefill requests downstream again. Therefore, it can be seen that in the current situation, a total of 2 linefill requests need to be sent to the downstream storage module.

[0110] For example, if the sector prefetch size carried by each access request is set to 4, upon receiving request0, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 4 carried in request0, with sectors0 to 3 grouped together and sectors4 to 7 grouped together. The controller prefetches the corresponding target data and fills sectors0 to 3, without adjusting the sector prefetch size carried in request0. Upon receiving request1, it is determined that it wants to access sector1. At this time, sector1 of the cache line has already been loaded with data, so the hit result is a cache line hit and a sector hit. The cached data in sector 1 can be returned directly; ...; Upon receiving request 4, it is determined that it needs to access sector 4. At this time, sector 4 of the cache line has not yet been loaded with data, so the hit result is a cache line hit but a sector miss, and this is the first time this hit result has occurred. Therefore, the sector adjustment circuit, according to the adjustment logic of the first adjustment strategy, directly adjusts the sector prefetch size carried in request 4 to the sector prefetch size 8 corresponding to the highest level, and sends the adjusted sector prefetch size 8 to the controller. The controller sends a linefill request to the downstream storage module according to the adjusted sector prefetch size 8, prefetches the corresponding target data, and fills sectors 4 to 7; among them, sectors 0 to 3 have already been filled in the processing of request 0, so there is no need to prefetch them again this time. The hit results of subsequent requests 5 to 7 are all cache line hits and sector hits, and the controller does not need to send linefill requests to the downstream again. It can be seen that in the current situation, a total of 2 linefill requests need to be sent to the downstream storage module.

[0111] In summary, for the first adjustment strategy, regardless of whether the sector prefetch size carried in the access request is 1, 2, or 4, the number of linefill requests sent to the downstream storage module can be reduced.

[0112] Secondly, the second adjustment strategy adopted by the sector adjustment circuit will be used as an example for illustrative explanation.

[0113] For example, if the sector prefetch size carried by each access request is set to 1, and the first preset level difference is one level, based on this, when request0 is received, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 1 carried in request0, prefetches the corresponding target data and fills it into sector0, and does not adjust the sector prefetch size carried in request0. When request1 is received, it is determined that it wants to access sector1. At this time, the cache line in sector1 has not yet been loaded with data, so the hit result is a cache line hit but a sector miss. Therefore, according to the adjustment logic of the second adjustment strategy, the sector adjustment circuit adjusts the sector prefetch size 1 (corresponding to the first level) carried in request1 to the sector prefetch size 2 corresponding to the second level. And according to the alignment of sector0 and sector1 as a group, sector2 and sector3 as a group, sector4 and sector5 as a group, and sector6 and sector7 as a group, the adjusted sector prefetch size 2 is sent to the controller. The controller sends a linefill request to the downstream storage module according to the adjusted sector prefetch size 2, prefetches the corresponding target data and fills it into sector1. Among them, sector0 has already been filled in the processing of request0, so there is no need to prefetch it again this time. Upon receiving request2, it is determined that it wants to access sector2. At this time, sector2 of the cache line has not yet been loaded with data. Therefore, the hit result is a cache line hit but a sector miss. Thus, the sector adjustment circuit adjusts the sector prefetch size 1 carried in request2 to the sector prefetch size 2 corresponding to the second level (i.e., still following the aforementioned pairwise alignment method) according to the adjustment logic of the second adjustment strategy. The adjusted sector prefetch size 2 is sent to the controller. The controller sends a linefill request to the downstream storage module based on the adjusted sector prefetch size 2, prefetches the corresponding target data, and fills it into sector2 and sector3. Upon receiving request3, it is determined that it wants to access sector3. At this time, sector3 of the cache line has already been loaded with data. Therefore, the hit result is a cache line hit and a sector hit. The cached data in sector3 can be directly returned. And so on. It can be seen that in the current situation, a total of 5 linefill requests need to be sent to the downstream storage module.

[0114] For example, if the sector prefetch size carried by each access request is set to 2, and the first preset level difference is one level, when request0 is received, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 2 carried in request0, and according to the alignment of sector0 and sector1 as a group, sector2 and sector3 as a group, sector4 and sector5 as a group, and sector6 and sector7 as a group, prefetching the corresponding target data and filling it into sector0 and sector1, without adjusting the sector prefetch size carried in request0; when request1 is received, it is determined that it wants to access sector1. At this time, the cache line in sector1 has already been loaded with data, so the hit result is a cache line hit and a sector hit, and the cached data in sector1 can be directly returned; when request2 is received, ... Upon receiving request Request 3, it is determined that Request 2 needs to access. Since data has not yet been loaded into Sector 2 of the cache line, the hit result is a cache line hit but a sector miss. Therefore, the sector adjustment circuit, according to the adjustment logic of the second adjustment strategy, adjusts the sector prefetch size 2 (corresponding to the second level) carried in Request 2 to the sector prefetch size 4 corresponding to the third level, and sends the adjusted sector prefetch size 2 to the controller. The controller, based on the adjusted sector prefetch size 2 and aligned according to the grouping of Sector 0 to Sector 3 and Sector 4 to Sector 7, sends a linefill request to the downstream storage module to prefetch the corresponding target data and fill it into Sector 2 and Sector 3. Sector 0 and Sector 1 have already been filled during the processing of Request 0, so there is no need for repeated prefetching. Upon receiving Request 3, it is determined that Request 3 needs to access. Since data has already been loaded into Sector 3 of the cache line, the hit result is a cache line hit and a sector hit, so the cached data in Sector 3 can be directly returned.Upon receiving request4, it is determined that it requests access to sector 4. At this point, sector 4 of the cache line has not yet been loaded with data. Therefore, the cache line hit result is a sector miss, but the sector is not. Thus, the sector adjustment circuit, according to the adjustment logic of the second adjustment strategy, adjusts the sector prefetch size 2 (corresponding to the second level) carried in request4 to the sector prefetch size 4 corresponding to the third level, and sends the adjusted sector prefetch size 4 to the controller. The controller, based on the adjusted sector prefetch size 4 and aligned according to sector 0 to sector 3 as a group and sector 4 to sector 7 as a group, sends linefill requests to the downstream storage module to prefetch the corresponding target data and fill sectors 4 to 7. Upon receiving requests 5 to 7, the data in the corresponding sectors is directly returned. Therefore, in the current situation, a total of 3 linefill requests need to be sent to the downstream storage module.

[0115] For example, if the sector prefetch size carried by each access request is set to 4, and the first preset level difference is one level, when request0 is received, it is determined that it wants to access sector 0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 4 carried in request0, and according to the alignment of sector 0 to sector 3 as a group and sector 4 to sector 7 as a group, prefetching the corresponding target data and filling it into sectors 0 to sector 3, without adjusting the sector prefetch size carried in request0; when request1 is received, it is determined that it wants to access sector 1. At this time, the cache line in sector 1 has already been loaded with data, so the hit result is a cache line miss. The result is a cache line hit and a sector hit, so the cached data in sector1 can be returned directly; ...; Upon receiving request4, it is determined that it needs to access sector4. At this time, sector4 of the cache line has not yet been loaded with data, so the hit result is a cache line hit but a sector miss. Therefore, the sector adjustment circuit adjusts the sector prefetch size 4 (corresponding to the 3rd level) carried in request4 to the sector prefetch size 8 corresponding to the 4th level, according to the adjustment logic of the second adjustment strategy. The adjusted sector prefetch size 4 is sent to the controller, and the controller sends a linefill request to the downstream storage module according to the adjusted sector prefetch size 4, prefetches the corresponding target data and fills it into sectors4 to 7; Upon receiving requests5 to 7, the data in the corresponding sector can be returned directly. Thus, it can be seen that in the current situation, a total of 2 linefill requests need to be sent to the downstream storage module.

[0116] In summary, for the second adjustment strategy, regardless of whether the sector prefetch size carried in the access request is 1, 2, or 4, the number of linefill requests sent to the downstream storage module can be reduced.

[0117] In addition, the sector adjustment circuit using the third adjustment strategy is used as an example for illustrative explanation.

[0118] For example, if the sector prefetch size carried by each access request is set to 1, and the second preset level difference is one level, when request0 is received, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 1 carried in request0, prefetches the corresponding target data and fills it into sector0, without adjusting the sector prefetch size; when request1 is received, it is determined that it wants to access sector1. Since no data has been loaded into sector 1 of the cache line, the hit result is a cache line hit but a sector miss, and this is the first time this hit result has occurred. Therefore, the sector adjustment circuit, according to the adjustment logic of the third adjustment strategy, adjusts the sector prefetch size 1 (corresponding to the first level) carried in request 1 to the sector prefetch size 2 corresponding to the second level, and sends the adjusted sector prefetch size 2 to the controller. The controller, based on the adjusted sector prefetch size 2, groups sectors 0 and 1 together, sectors 2 and 3 together, and sectors 4 and 5 together. For the alignment of sector 6 and sector 7 as a group, a linefill request is sent to the downstream storage module to prefetch the corresponding target data and fill it into sector 1. The data in sector 0 has already been filled during the processing of request 0, so there is no need to prefetch it again. Upon receiving request 2, it is determined that it needs to access sector 2. At this point, sector 2 of the cache line has not yet been loaded with data. Therefore, the hit result is a cache line hit but a sector miss, and this is the second time this hit result has occurred. Therefore, the sector adjustment circuit, according to the adjustment logic of the third adjustment strategy, adjusts r... The sector prefetch size 1 carried in request2 is adjusted to the sector prefetch size 8 corresponding to the highest level (i.e., the 4th level). The adjusted sector prefetch size 8 is sent to the controller. The controller sends a linefill request to the downstream storage module based on the adjusted sector prefetch size 8, prefetches the corresponding target data, and fills sectors 2 to 7. The data in sectors 0 and 1 has already been filled in the previous access process, so there is no need to prefetch it again. When request 5 to request 7 are received, the data in the corresponding sector can be returned directly. Therefore, in the current case, a total of 3 linefill requests need to be sent to the downstream storage module.

[0119] For example, if the sector prefetch size carried by each access request is set to 2, and the second preset level difference is one level, when request0 is received, it is determined that it wants to access sector0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 2 carried in request0, prefetches the corresponding target data and fills it into sector0 and sector1, and does not adjust the sector prefetch size carried in request0; when request1 is received, it is determined that it wants to access sector1, and the cache line... Data is already loaded in sector 1, so the hit result is a cache line hit and a sector hit, and the cached data in sector 1 can be returned directly. Upon receiving request 2, it is determined that it wants to access sector 2. At this time, data has not yet been loaded in sector 2 of the cache line, so the hit result is a cache line hit but a sector miss, and this is the first occurrence of this hit result. Therefore, the sector adjustment circuit, according to the adjustment logic of the third adjustment strategy, adjusts the sector prefetch size 2 (corresponding to the second level) carried in request 2 to the sector prefetch size 4 corresponding to the third level, and sends the adjusted sector prefetch size 4 to the controller. The controller then adjusts the sector prefetch size according to the adjusted sector... Prefetch size 4, and align it into groups of sectors 0 to 3 and sectors 4 to 7. Send linefill requests to downstream storage modules to prefetch the corresponding target data and fill sectors 2 and 3. Data in sectors 0 and 1 has already been filled during the processing of request 0, so no further prefetching is needed. Upon receiving request 4, it is determined that it requests access to sector 4. At this point, sector 4 of the cache line has not yet been loaded with data. Therefore, the hit result is a cache line hit but a sector miss, and this is the second time this hit result has occurred. According to the adjustment logic of the third adjustment strategy, the sector adjustment circuit adjusts the sector prefetch size 2 carried in request4 to the sector prefetch size 8 corresponding to the highest level (i.e., the 4th level). The adjusted sector prefetch size 8 is then sent to the controller. The controller sends a linefill request to the downstream storage module based on the adjusted sector prefetch size 8, prefetches the corresponding target data, and fills sectors 4 to 7. The data in sectors 0 to 3 has already been filled during previous access processing, so it does not need to be prefetched again. Upon receiving requests 5 to 7, the data in the corresponding sectors is directly returned. Therefore, in the current situation, a total of 3 linefill requests need to be sent to the downstream storage module.

[0120] For example, if the sector prefetch size carried by each access request is set to 4, and the second preset level difference is one level, when request0 is received, it is determined that it wants to access sector 0. At this time, the cache line has not yet been loaded with data, so the hit result is a cache line miss. Therefore, the controller sends a linefill request to the downstream storage module according to the sector prefetch size of 4 carried in request0, and according to the alignment of sector 0 to sector 3 as a group and sector 4 to sector 7 as a group, prefetching the corresponding target data and filling it into sectors 0 to sector 3, without adjusting the sector prefetch size carried in request0; when request1 to request3 are received, the data in the corresponding sector can be returned directly; when request4 is received, it is determined that it wants to access sector 0. When accessing sector 4, no data has been loaded into sector 4 of the cache line at this point. Therefore, the hit result is a cache line hit but a sector miss, and this is the first time this hit result has occurred. Therefore, the sector adjustment circuit, according to the adjustment logic of the third adjustment strategy, adjusts the sector prefetch size 4 (corresponding to the 3rd level) carried in request 4 to the sector prefetch size 8 corresponding to the 4th level. The adjusted sector prefetch size 8 is sent to the controller. The controller sends a linefill request to the downstream storage module based on the adjusted sector prefetch size 8, prefetches the corresponding target data, and fills sectors 4 to 7. The data in sectors 0 to 3 has already been filled during the processing of request 0, so there is no need to prefetch it again. Upon receiving requests 5 to 7, the data in the corresponding sectors is directly returned. Therefore, in the current situation, a total of 2 linefill requests need to be sent to the downstream storage module.

[0121] In summary, for the third adjustment strategy, regardless of whether the sector prefetch size carried in the access request is 1, 2, or 4, the number of linefill requests sent to downstream storage modules can be reduced.

[0122] It should be noted that the above descriptions of access requests and access modes are merely illustrative examples, and the embodiments disclosed herein do not impose any limitations on them.

[0123] This disclosure provides a data caching method that can be applied to the sector adjustment circuit of a cache module. The cache module further includes a controller and multiple cache lines, each cache line including multiple sectors. The cache module can be any of the cache modules described in this disclosure.

[0124] Figure 3 A flowchart illustrating a data caching method provided in an embodiment of this disclosure. (Refer to...) Figure 3 The data caching method may include the following steps.

[0125] Step S31: If the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, adjust the sector prefetch size carried in the access request to obtain the adjusted sector prefetch size.

[0126] The adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module in order to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

[0127] It should be noted that the processing procedure of the sector adjustment circuit can be found in the relevant content of the cache module in the embodiments of this disclosure, and will not be described in detail here.

[0128] In summary, in this embodiment, the sector adjustment circuit in the cache module can execute sector prefetch size adjustment logic according to a preset adjustment strategy. Based on this, upon receiving an access request, the hit result of the access request can be determined. If the hit result indicates that the cache line is hit but the sector is not, the sector prefetch size carried in the access request can be flexibly adjusted according to the preset adjustment strategy to obtain the adjusted sector prefetch size. Based on the adjusted sector prefetch size, target data is obtained from the downstream storage module of the cache module, and the target data is used to fill at least a portion of the sectors in the cache line corresponding to the access request. Therefore, the sector prefetch size can be flexibly adjusted through the sector adjustment circuit, which is beneficial for improving the sector hit rate for access requests with different access modes, thereby effectively reducing the number of prefetches, improving prefetch efficiency, and increasing throughput utilization in the downstream access direction.

[0129] This disclosure provides a data caching method that can be applied to the controller of a caching module. The caching module further includes a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors. The caching module can be any of the caching modules described in this disclosure.

[0130] Figure 4 A flowchart illustrating another data caching method provided in this disclosure. (Refer to...) Figure 4 The data caching method may include the following steps.

[0131] Step S41: Obtain target data from the downstream storage module of the cache module based on the sector prefetch size to fill at least a portion of the sectors of the cache line corresponding to the access request.

[0132] The sector prefetch size includes the sector prefetch size carried in the access request, or the adjusted sector prefetch size determined by the sector adjustment circuit by adjusting the sector prefetch size carried in the access request. The sector adjustment circuit is used to execute the data caching method applied to the sector adjustment circuit as described in the embodiments of this disclosure.

[0133] It should be noted that the controller's processing procedure can be found in the relevant content of the cache module in the embodiments of this disclosure, and will not be described in detail here.

[0134] In summary, in this embodiment, the controller in the cache module can obtain corresponding target data from the downstream storage module based on the sector prefetch size carried in the access request, or the sector prefetch size adjusted by the sector adjustment circuit. This target data is then used to fill at least a portion of the sectors of the cache line corresponding to the access request. The adjusted sector prefetch size is a prefetch size that better matches the access behavior or access pattern of the cache module. Therefore, when prefetching target data based on the adjusted sector prefetch size, the subsequent sector hit rate can be improved, thereby effectively reducing the number of prefetches, improving prefetch efficiency, and increasing throughput utilization in the downstream access direction.

[0135] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0136] In addition, the embodiments of this disclosure also provide a sector adjustment circuit, a controller, and a data processing device, all of which can be used to implement any of the data caching methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding records of the caching module section and will not be repeated here.

[0137] This disclosure provides a sector adjustment circuit, which can be disposed in a cache module. The cache module further includes a controller and multiple cache lines, each cache line including multiple sectors. The cache module can be any of the cache modules described in this disclosure.

[0138] Figure 5 This is a block diagram of a sector adjustment circuit provided in an embodiment of the present disclosure.

[0139] Reference Figure 5 This disclosure provides a sector adjustment circuit 510, which can be set in a cache module (not shown in the figure). The cache module also includes a controller and multiple cache lines, each cache line including multiple sectors.

[0140] The sector adjustment circuit 510 is used to adjust the sector prefetch size carried in the access request when the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, so as to obtain the adjusted sector prefetch size.

[0141] The adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module in order to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

[0142] It should be noted that the processing procedure of the sector adjustment circuit can be found in the relevant content of the cache module in the embodiments of this disclosure, and will not be described in detail here.

[0143] In summary, in this embodiment of the present disclosure, a sector adjustment circuit is added to the cache module to perform sector prefetch size adjustment logic according to a preset adjustment strategy. Based on this, when an access request is received, the hit result of the access request can be determined. If the hit result indicates that the cache line is hit but the sector is not hit, the sector prefetch size carried in the access request can be flexibly adjusted according to the preset adjustment strategy to obtain the adjusted sector prefetch size. Based on the adjusted sector prefetch size, the target data is obtained from the downstream storage module of the cache module, and the target data is used to fill at least a portion of the sectors in the cache line corresponding to the access request. Therefore, this embodiment only adds a sector adjustment circuit at the hardware level to implement a relatively simple adjustment logic with low hardware overhead. Based on this, the target data corresponding to the adjusted sector prefetch size can be prefetched and filled into at least a portion of the sectors of the cache line corresponding to the access request. This can improve the flexibility of the sector prefetch size and improve the sector hit rate for access requests with different access modes, thereby effectively reducing the number of prefetches, improving prefetch efficiency and throughput utilization for downstream access directions.

[0144] This disclosure provides a controller that can be disposed in a cache module. The cache module further includes a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors. The cache module can be any of the cache modules described in this disclosure.

[0145] Figure 6 This is a block diagram of a controller provided in an embodiment of the present disclosure.

[0146] Reference Figure 6 This disclosure provides a controller 610 that can be set in a cache module (not shown in the figure). The cache module also includes a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors.

[0147] The controller 610 is used to retrieve target data from the downstream storage module of the cache module based on the sector prefetch size to fill at least a portion of the sectors of the cache line corresponding to the access request.

[0148] The sector prefetch size includes the sector prefetch size carried in the access request, or the adjusted sector prefetch size determined by the sector adjustment circuit by adjusting the sector prefetch size carried in the access request. The sector adjustment circuit adopts the sector adjustment circuit described in any one of the embodiments of this disclosure.

[0149] It should be noted that the controller's processing procedure can be found in the relevant content of the cache module in the embodiments of this disclosure, and will not be described in detail here.

[0150] In summary, the cache module of this embodiment includes a controller. This controller can obtain corresponding target data from the downstream storage module based on the sector prefetch size carried in the access request, or the sector prefetch size adjusted by the sector adjustment circuit. This target data is then used to fill at least a portion of the sectors of the cache line corresponding to the access request. The adjusted sector prefetch size is a prefetch size that better matches the access behavior or access pattern of the cache module. Therefore, when prefetching target data based on the adjusted sector prefetch size, the subsequent sector hit rate can be improved, thereby effectively reducing the number of prefetches, improving prefetch efficiency, and increasing throughput utilization in the downstream access direction.

[0151] This disclosure provides a data processing apparatus.

[0152] Figure 7 This is a block diagram of a data processing apparatus provided in an embodiment of the present disclosure.

[0153] Reference Figure 7 This disclosure provides a data processing apparatus 700, which includes at least one cache module 710 and at least one processing module 720. The processing module 720 is used to obtain data to be processed from the cache module 710 and / or to store the processing result in the cache module 710.

[0154] The cache module 710 adopts the cache module described in any one of the embodiments of this disclosure.

[0155] In some optional embodiments, the processing module 720 includes one or more processors, and the multiple processors may be arranged in the form of a processing array, which is not limited in this embodiment. The processors may include general-purpose processors and / or dedicated processors. General-purpose processors include at least one of CPUs and microcontrollers, while dedicated processors include at least one of GPUs, neural network processors, tensor processors, intelligent processing units, language processing units, data processing units, field-programmable gate arrays, application-specific integrated circuits, and programmable logic devices.

[0156] In this embodiment, a sector adjustment circuit is added to the cache module to adjust the sector prefetch size. Based on this, for an access request received by the cache module, if the hit result of the access request indicates that the cache line is hit but the sector is not hit, the sector prefetch size carried in the access request can be flexibly adjusted to obtain the adjusted sector prefetch size. This allows the controller in the cache module to obtain target data from the downstream storage module of the cache module based on the adjusted sector prefetch size, and to fill at least a portion of the sectors in the cache line corresponding to the access request based on the target data.

[0157] Therefore, the cache module in this embodiment only adds a sector adjustment circuit at the hardware level, and the sector prefetch size can be adjusted through relatively simple adjustment logic. This results in low hardware overhead and improved flexibility in sector prefetch size. Based on this, the controller can prefetch the corresponding target data based on the adjusted sector prefetch size and fill at least a portion of the sectors in the cache line corresponding to the access request. Compared to prefetching data based on a fixed sector prefetch size, the adjusted sector prefetch size is a prefetch size that better matches the access behavior or access pattern of the cache module, helping to improve the subsequent sector hit rate, thereby effectively reducing the number of prefetches, improving prefetch efficiency, and increasing throughput utilization in downstream access directions. This, in turn, helps improve the processing efficiency of the processing module.

[0158] The aforementioned cache module, sector adjustment circuit, controller, and data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device, or stored in the computer device's memory as software, so that the processor can call and execute the corresponding operations of each module.

[0159] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0160] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods and apparatus (systems) according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0161] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0162] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0163] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0164] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A caching module, characterized in that, It includes sector adjustment circuitry, a controller, and multiple cache lines, each cache line containing multiple sectors; The sector adjustment circuit is used to adjust the sector prefetch size carried in the access request according to a preset adjustment strategy when the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, so as to obtain the adjusted sector prefetch size. The preset adjustment strategy is selected from multiple preset adjustment strategies according to the input signal of the selection register. The controller is configured to obtain target data from the downstream storage module of the cache module according to the adjusted sector prefetch size, and fill the target data into at least a portion of the sectors of the cache line corresponding to the access request.

2. The module according to claim 1, characterized in that, The sector adjustment circuit is also used to adjust the sector prefetch size carried in the access request according to a preset adjustment strategy to obtain the adjusted sector prefetch size. The preset adjustment strategy is used to adjust the sector prefetch size carried in the access request based on the number of times the cache line is hit but the sector is not hit, and the value of any sector prefetch size is a power of 2.

3. The module according to claim 2, characterized in that, The preset adjustment strategy corresponds to multiple levels of sector prefetch size, and the value of the sector prefetch size is positively correlated with the level. The preset adjustment strategy includes at least one of the following: a first adjustment strategy, a second adjustment strategy, and a third adjustment strategy: For the cache line corresponding to the access request, the first adjustment strategy is used to adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level in response to the first occurrence of a cache line hit but a sector miss. For the cache line corresponding to the access request, the second adjustment strategy is used to adjust the sector prefetch size carried in the access request according to the first preset level difference in response to the situation where the cache line is hit but the sector is not hit each time. For the cache line corresponding to the access request, the third adjustment strategy is used to adjust the sector prefetch size carried in the access request according to the second preset level difference in response to the first occurrence of a cache line hit but a sector miss, and to adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level in response to the second occurrence of a cache line hit but a sector miss. The first preset level difference and the second preset level difference are used to characterize the level difference between the level corresponding to the adjusted sector prefetch size and the level corresponding to the sector prefetch size before adjustment. The first preset level difference and the second preset level difference may have the same or different values.

4. The module according to claim 3, characterized in that, Both the first preset level difference and the second preset level difference have a value of one level; For the cache line corresponding to the access request, the second adjustment strategy is used to respond to the situation where the cache line is hit but the sector is not hit each time, by increasing the level of the sector prefetch size carried in the access request by one level as the adjusted sector prefetch size; For the cache line corresponding to the access request, the third adjustment strategy is used to respond to the situation where the cache line is hit for the first time but the sector is not hit, by increasing the sector prefetch size corresponding to the sector prefetch size carried in the access request by one level as the adjusted sector prefetch size.

5. The module according to claim 3 or 4, characterized in that, A sector hit indicator is set for each of the aforementioned cache lines; For any of the aforementioned cache lines: in the event of the first cache line miss, the sector hit indicator is initialized to the first indicator; in the event of the first cache line hit but sector miss, the sector hit indicator is adjusted from the first indicator to the second indicator; in the event of the second cache line hit but sector miss, the sector hit indicator is reset from the second indicator to the first indicator. For the cache line corresponding to the access request, the sector adjustment circuit is further configured to, when the preset adjustment strategy is the third adjustment strategy, adjust the sector prefetch size carried in the access request according to the second preset level difference in response to the value of the sector hit indicator being adjusted from the first indicator to the second indicator; and, in response to the sector hit indicator being adjusted from the second indicator to the first indicator, adjust the sector prefetch size carried in the access request to the sector prefetch size corresponding to the highest level.

6. The module according to any one of claims 1-4, characterized in that, The controller is further configured to determine, based on the adjusted sector prefetch size, the sector group in the cache line corresponding to the access request and the target sector group where the sector to be accessed is located, wherein the number of sector groups is one or more, and each sector group includes multiple sectors; determine the target sector to be prefetched based on the target sector group and the valid identifier of each sector in the target sector group; determine the prefetch request based on the target sector, and send the prefetch request to the downstream storage module; The system receives the target data corresponding to the target sector returned by the downstream storage module and fills the target sector with the target data.

7. The module according to claim 6, characterized in that, The controller is further configured to determine the sector grouping granularity based on the adjusted sector prefetch size; determine each sector group in the cache line corresponding to the access request based on the sector grouping granularity; and determine the sector group containing the sector to be accessed in the cache line corresponding to the access request as the target sector group.

8. The module according to claim 6, characterized in that, The value of the valid identifier can be either a valid value or an invalid value; The controller is further configured to identify the sectors in the target sector group that are validly identified as having the invalid value as the target sector.

9. A data caching method, characterized in that, A sector adjustment circuit is applied to a cache module, the cache module further including a controller and multiple cache lines, each cache line including multiple sectors, the method comprising: If the hit result of the access request to the cache module indicates that the cache line is hit but the sector is not hit, the sector prefetch size carried in the access request is adjusted according to a preset adjustment strategy to obtain the adjusted sector prefetch size. The preset adjustment strategy is selected from multiple preset adjustment strategies based on the input signal of the selection register. The adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module, so as to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

10. A data caching method, characterized in that, A controller applied to a cache module, the cache module further including a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors, the method comprising: Based on the sector prefetch size, the target data is obtained from the downstream storage module of the cache module to fill at least a portion of the sectors of the cache line corresponding to the access request; Wherein, the sector prefetch size includes the sector prefetch size carried in the access request, or the adjusted sector prefetch size determined by the sector adjustment circuit by adjusting the sector prefetch size carried in the access request, and the sector adjustment circuit is used to execute the data caching method as described in claim 9.

11. A sector adjustment circuit, characterized in that, The cache module is configured to include a controller and multiple cache lines, each cache line comprising multiple sectors. The sector adjustment circuit is used to adjust the sector prefetch size carried in the access request according to a preset adjustment strategy when the hit result of the access request for the cache module indicates that the cache line is hit but the sector is not hit, so as to obtain the adjusted sector prefetch size. The preset adjustment strategy is selected from multiple preset adjustment strategies according to the input signal of the selection register. The adjusted sector prefetch size is used to instruct the controller to obtain target data from the downstream storage module of the cache module, so as to fill at least a portion of the sectors of the cache line corresponding to the access request based on the target data.

12. A controller, characterized in that, The cache module is configured to include a sector adjustment circuit and multiple cache lines, each cache line including multiple sectors. The controller is configured to obtain target data from the downstream storage module of the cache module based on the sector prefetch size to fill at least a portion of the sectors of the cache line corresponding to the access request; Wherein, the sector prefetch size includes the sector prefetch size carried in the access request, or the adjusted sector prefetch size determined by the sector adjustment circuit by adjusting the sector prefetch size carried in the access request, wherein the sector adjustment circuit adopts the sector adjustment circuit as described in claim 11.

13. A data processing apparatus, characterized in that, It includes at least one cache module and at least one processing module, wherein the processing module is used to obtain data to be processed from the cache module, and / or to store the processing result in the cache module; The caching module is the caching module as described in any one of claims 1-8.

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