A method for index optimization management of a ring queue, an electronic device, and a storage medium

Abstract

The application discloses an index optimization management method of a ring queue, an electronic device and a storage medium, relates to the technical field of computer virtualization, and comprises the following steps: dividing a plurality of storage levels according to an access delay, and mapping index management of the ring queue to the plurality of storage levels according to an access frequency, so that indexes with high-frequency access are stored in low-delay storage; allocating read indexes and write indexes in a core cache layer to cache lines isolated from each other, so as to eliminate cache consistency overhead caused by pseudo-sharing; when a preset synchronization condition is met, synchronizing current indexes of the core cache layer to a main memory synchronization layer, so as to reduce unnecessary synchronization operations; dynamically adjusting an update condition of an expected cache layer according to a credibility score of an index snapshot, so as to reduce the number of main memory access times on the premise of guaranteeing snapshot accuracy; and judging the state of the ring queue according to the current indexes and the index snapshot and performing an access operation, so as to avoid accessing the main memory in most scenarios.

Description

Technical Field

[0001] This application relates to the field of computer virtualization technology, and in particular to an index optimization management method for a circular queue, an electronic device, and a storage medium. Background Technology

[0002] With the widespread application of virtualization technology, VirtIO (a general virtualization I / O device standard) is an important implementation of paravirtualization technology. Its circular queue is the core component of data plane communication and undertakes the key task of data transmission between the virtual machine and the host machine. The performance of the circular queue directly affects the efficiency of I / O (input / output) operations in the virtualization environment, and the performance of the queue index management, as the core link of the circular queue operation, is particularly important. At present, the index management scheme of VirtIO circular queue still has the following technical problems in practical applications: (1) The cache consistency overhead is large. The read and write indexes of VirtIO circular queue are allocated continuously in memory and are not aligned with cache lines, which are easy to be in the same or adjacent cache lines. When the virtual machine driver and the virtualization manager update different indexes respectively, the cache consistency protocol state transition (such as from shared state to exclusive state) will be frequent, resulting in an increase in cache miss rate, a large amount of bus bandwidth being occupied, and a reduction in I / O processing efficiency. The cache consistency overhead is large. (2) Frequent main memory access, and there is still room for optimization of I / O latency. Currently, only a single-level local copy index optimization of "main memory to local copy" is used, which fails to make full use of multi-level cache hierarchy; the batch synchronization threshold is statically configured and cannot dynamically adapt to load changes, so main memory is still accessed frequently under high load and latency increases under low load; the synchronization process relies on full memory barrier, which causes processor pipeline refresh and memory access blockage, resulting in high overhead and restricting further improvement of throughput and I / O latency. Summary of the Invention

[0003] This application provides a method, electronic device, and storage medium for optimizing the index management of a circular queue, in order to at least solve the problems in the related art where VirtIO circular queue index management suffers from high cache coherency overhead, frequent main memory access, high processor overhead caused by static configuration of synchronization thresholds and full memory barriers, thereby restricting I / O efficiency and latency optimization.

[0004] This application provides an index optimization management method for a circular queue. The method includes: logically dividing multiple storage spaces in the current system into multiple storage layers based on different access latencies, wherein the multiple storage layers include at least a core cache layer, a expected cache layer, and a main memory synchronization layer; mapping the index management of the circular queue to multiple storage layers based on different access frequencies; allocating different types of indexes in the core cache layer to different isolated cache lines, wherein the different types of indexes include read indexes and write indexes; in response to triggering a preset synchronization condition, synchronizing the first current index in the core cache layer as the corresponding first current global index to the main memory synchronization layer; determining the confidence score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the confidence score; in response to triggering the preset update condition, updating the expected cache layer with the second current global index in the main memory synchronization layer as the corresponding first current index snapshot; and in response to receiving an access request, determining the current state of the circular queue based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and determining whether to execute the access operation corresponding to the access request based on the current state.

[0005] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program and implementing at least the following steps of an index optimization management method for a circular queue: logically dividing multiple storage spaces in the current system into multiple storage levels according to different access latencies, wherein the multiple storage levels include at least a core cache layer, a pre-defined cache layer, and a main memory synchronization layer; mapping the index management of the circular queue to the multiple storage levels according to different access frequencies; allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; and responding to a preset... The synchronization condition involves synchronizing the first current index in the core cache layer as the corresponding first current global index to the main memory synchronization layer; determining the credibility score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the credibility score; in response to triggering the preset update condition, updating the expected cache layer by using the second current global index in the main memory synchronization layer as the corresponding first current index snapshot; and in response to receiving an access request, determining the current state of the circular queue based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and determining whether to execute the access operation corresponding to the access request based on the current state.

[0006] This application also provides a computer-readable storage medium storing a computer program, wherein when executed by a processor, the computer program implements at least the following steps: a circular queue index optimization management method comprising: logically dividing multiple storage spaces in the current system into multiple storage levels according to different access latencies, wherein the multiple storage levels include at least a core cache layer, a pre-emptive cache layer, and a main memory synchronization layer; mapping the index management of the circular queue to the multiple storage levels according to different access frequencies; allocating different types of indexes in the core cache layer to different cache lines isolated from each other, wherein the different types of indexes include read indexes and write indexes; responding to... Triggering a preset synchronization condition, the first current index in the core cache layer is used as the corresponding first current global index and synchronized to the main memory synchronization layer; determining the credibility score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the credibility score; in response to triggering the preset update condition, the second current global index in the main memory synchronization layer is used as the corresponding first current index snapshot and updated to the expected cache layer; in response to receiving an access request, the current state of the circular queue is determined based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and based on the current state, it is determined whether to execute the access operation corresponding to the access request.

[0007] This application divides the storage into multiple storage tiers based on access latency and maps the index management of the circular queue to multiple storage tiers based on access frequency, so that frequently accessed indexes reside in low-latency storage; it allocates read and write indexes in the core cache layer to isolated cache lines to eliminate cache consistency overhead caused by false sharing; when preset synchronization conditions are met, it synchronizes the current index of the core cache layer to the main memory synchronization layer to reduce unnecessary synchronization operations; it dynamically adjusts the update conditions of the expected cache layer based on the confidence score of the index snapshot to reduce the number of main memory accesses while ensuring the accuracy of the snapshot; and it determines the state of the circular queue and performs access operations based on the current index and the index snapshot to avoid accessing main memory in most scenarios. Attached Figure Description

[0008] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a flowchart illustrating the index optimization management method for the circular queue in the first embodiment; Figure 2 This is a schematic diagram showing the distribution and latency of the three storage levels in the first embodiment; Figure 3 This is a diagram showing the interconnection structure of the three storage levels in the processor in the first embodiment; Figure 4 This is a diagram of the internal structure of the electronic device in the second embodiment. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0011] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] In the first embodiment, such as Figure 1As shown, a method for optimizing the index management of a circular queue is provided. This method includes: logically dividing multiple storage spaces in the current system into multiple storage layers based on different access latencies, wherein the multiple storage layers include at least a core cache layer, a expected cache layer, and a main memory synchronization layer; mapping the index management of the circular queue to multiple storage layers based on different access frequencies; allocating different types of indexes in the core cache layer to different isolated cache lines, wherein the different types of indexes include read indexes and write indexes; in response to triggering a preset synchronization condition, synchronizing the first current index in the core cache layer as the corresponding first current global index to the main memory synchronization layer; determining the confidence score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the confidence score; in response to triggering the preset update condition, updating the expected cache layer with the second current global index in the main memory synchronization layer as the corresponding first current index snapshot; and in response to receiving an access request, determining the current state of the circular queue based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and determining whether to execute the access operation corresponding to the access request based on the current state.

[0014] Specifically, the above method, on the one hand, completely eliminates the false sharing problem caused by mutual interference between read and write indexes through cache line isolation; on the other hand, by introducing a dynamic snapshot mechanism based on preset update conditions and reliability, queue status determination can be completed at the expected cache layer, avoiding frequent access to main memory. This reduces the overhead of the cache consistency protocol and the number of main memory accesses, thereby reducing I / O operation latency and improving system throughput.

[0015] In a specific embodiment, when the preset synchronization condition is a read synchronization condition, the first current index is the first current read index, and the first current global index is the first current global read index; when the preset synchronization condition is a write synchronization condition, the first current index is the first current write index, and the first current global index is the first current global write index. When the preset update condition is a read update condition, the second current global index is the second current global read index, and the first current index snapshot is the first current read index snapshot; when the preset update condition is a write update condition, the second current global index is the second current global write index, and the first current index snapshot is the first current write index snapshot. When the access request is a read request, the second current index is the second current read index, and the second current index snapshot is the second current write index snapshot; when the access request is a write request, the second current index is the second current write index, and the second current index snapshot is the second current read index snapshot.

[0016] Furthermore, based on the different access latencies, the multiple storage spaces in the current system are logically divided into multiple storage layers, including: the first cache space with the lowest access latency among the multiple storage spaces is determined as the core cache layer; the main memory space with the highest access latency among the multiple storage spaces is determined as the main memory synchronization layer; and the second and third cache spaces with access latencies higher than the first cache space but lower than the main memory space among the multiple storage spaces are determined as the expected cache layers.

[0017] Specifically, the above method maps the L1 cache with the lowest access latency to the core cache layer, the L2 / L3 cache with medium access latency to the expected cache layer, and the main memory with the highest access latency to the main memory synchronization layer. This hierarchical partitioning based on access latency ensures that the most frequently accessed indexes reside in the fastest storage medium. Figure 2 As shown, on the most common operation path, the access latency can be reduced from 100ns in main memory to 1ns in L1 cache or 3-10ns in L2 / L3 cache, laying a physical foundation for subsequent performance optimization.

[0018] In a specific implementation, the core cache layer (mapping L1 cache) aims to update the index frequently and avoid false cache sharing. In terms of storage structure, the front-end cache contains `current_write_idx` (current write index), `last_sync_write` (last main memory synchronization value), and an update counter; the back-end cache corresponds to fields such as `current_read_idx` (current read index), using 128-byte cache line alignment to ensure that read and write indexes belong to independent L1 cache lines. Simultaneously, updates to the read and write indexes use `atomic_read_relaxed` / `atomic_set_relaxed`, eliminating memory barrier overhead. After accumulating 16 updates or a 500ns interval without synchronization under normal conditions, synchronization to main memory is achieved via `smp_store_release`, balancing latency and consistency. It should be noted that this strategy can ensure that the read and write index variables are maintained by the system in the processor L1 cache. The logic of the mapping between the core cache layer and the physical processor L1 cache is as follows: (1) Memory alignment and cache line isolation. The current_write_idx and current_read_idx of the core cache layer are aligned to 128 bytes through the __cacheline_aligned_in_smp macro, ensuring that their storage area occupies an L1 cache line (64 bytes) independently, and is separated from other data (such as expected cache data) by at least 64 bytes. This layout makes the processor's L1 cache replacement algorithm more inclined to retain core cache data with high frequency access. (2) High frequency access characteristics matching. The update frequency of the read and write index of the core cache layer is highly matched with the access speed of the L1 cache: current_*_idx is updated every I / O operation. In fact, it is updated once every 1-2 operations on average. This high frequency access mode will be identified as hot data by the cache controller in the processor and will be preferentially retained in the L1 cache. (3) Data volume control: Each structure in the core cache layer contains only 4-5 fields, such as index value, counter and timestamp, with a total size of less than 64 bytes, which can be completely stored in an L1 cache line to avoid cross-cache line access and reduce efficiency.

[0019] In a specific embodiment, the expected cache layer (mapping L2 / L3 cache) aims to reduce interaction with main memory by introducing read / write index snapshots. In terms of storage structure, the front-end cache contains expected_read_idx (back-end read index snapshot) and confidence (snapshot confidence score 0-100); the back-end cache corresponds to expected_write_idx and is aligned to 64 bytes. Its core working mechanism includes: (1) Snapshot update: the front-end updates the snapshot every 32 writes and the back-end every 16 reads, extending the interval when the confidence is high (≥80) and shortening the interval when the confidence is low (≤30); (2) Pre-judgment logic: the classic circular queue judges the queue status by reading and writing the queue index. The above method can judge the queue status by index snapshot (such as next_write==expected_read_idx), thus eliminating the need to access main memory. In addition, the logic of strong mapping between this layer and L2 / L3 cache is to match the latency characteristics of L2 / L3 by designing the access frequency (updating every 16 and 32 operations), such as Figure 3 As shown, the shared functionality adapts to multi-core access, and the capacity can support multi-queue snapshot storage.

[0020] In a specific embodiment, the main memory synchronization layer (mapped main memory) aims to maintain globally consistent index values. In terms of storage structure design, the tail memory of the VirtIO circular queue is reused, including available_idx (global write index), used_idx (global read index), and bias_threshold (synchronization threshold, 1 / 4 of the queue capacity). The core cache layer and the main memory synchronization layer are synchronized when the following three conditions are met: (1) the index deviation between the core cache layer and the main memory synchronization layer is greater than the synchronization threshold; (2) the expected cache snapshot confidence is consistently lower than 30; (3) no synchronization occurs within 1ms under abnormal conditions. During synchronization, the expected cache layer update is merged at the same time, that is, two operations are completed in one main memory access. Lightweight barriers of release / acquire are used for normal synchronization, and full barriers are used for abnormal scenarios.

[0021] Furthermore, based on different access frequencies, the index management of the circular queue is mapped to multiple storage levels, including: allocating the current index with the highest access frequency in the circular queue to the core cache layer, where the current index includes the current read index and the current write index; allocating the global index with the lowest access frequency in the circular queue to the main memory synchronization layer, where the global index includes the global read index and the global write index; and allocating index snapshots in the circular queue with an access frequency higher than the global index but lower than the current index to the expected cache layer, where the index snapshots include read index snapshots and write index snapshots.

[0022] Specifically, the above method allocates storage differently based on the actual access frequency of the index. High-frequency accessed indexes reside in the core cache layer, medium-frequency accessed index snapshots reside in the expected cache layer, and low-frequency accessed global indexes exist only in the main memory synchronization layer. This achieves automated data layout, with hot data going to fast storage and cold data to slow storage, avoiding cache pollution and invalid main memory usage caused by treating all indexes equally. This maximizes the use of the processor cache, a valuable resource, on truly high-frequency accessed index data, thus achieving optimal hit rate and access efficiency with limited cache capacity.

[0023] Furthermore, different types of indexes in the core cache layer are allocated to different cache lines that are isolated from each other, including: defining a first structure and a second structure, wherein the first structure is used to store read indexes and the second structure is used to store write indexes; caching the first structure in the first cache line and caching the second structure in the second cache line, wherein the address difference between the end address of the first cache line and the start address of the second cache line is at least the size of one cache line, or the address difference between the end address of the second cache line and the start address of the first cache line is at least the size of one cache line.

[0024] Specifically, the above method solves the false sharing problem between read and write indexes by placing the read and write in two separate structures and ensuring that the memory addresses of the two structures are separated by at least one cache line. A cache line is typically 64 or 128 bytes, ensuring that the two can never fall into the same processor cache line. In a multi-core environment, when the front-end core updates the write index, it will not cause the cache line containing the read index in the back-end core cache to become invalid; and vice versa.

[0025] In a specific implementation, structures storing `writeindex` and `readindex` are defined in the virtual machine front-end driver and the host back-end program, respectively, and are forced to be aligned to 128 bytes using the `__cacheline_aligned_in_smp` macro. Memory is allocated to the two structures using kernel memory allocation functions (such as `kzalloc`), ensuring that the starting address of `frontend_cache` differs from the starting address of `backend_cache` by at least 128 bytes, thus ensuring that their current indices (`current_write_idx` and `current_read_idx`) reside in independent cache lines.

[0026] Furthermore, the index optimization management method for the circular queue also includes: determining to trigger a preset synchronization condition in response to the cumulative synchronization count of an index of the same type as the first current index reaching a preset synchronization count threshold; determining to trigger a preset synchronization condition in response to the current system being in a normal state and the time interval between the last synchronization and the index of the same type as the first current index reaching a preset first time threshold; determining to trigger a preset synchronization condition in response to the difference between the first current index and the current global index in the main memory synchronization layer being greater than a preset difference threshold; determining to trigger a preset synchronization condition in response to the confidence score corresponding to the current index snapshot in the expected cache layer being continuously less than a preset first confidence threshold within a preset time period; and determining to trigger a preset synchronization condition in response to the current system being in an abnormal state and the time interval between the last synchronization and the index of the same type as the first current index reaching a preset second time threshold; wherein, the second time threshold is greater than the first time threshold.

[0027] Specifically, the above method defines multiple, tiered triggering conditions for the synchronization operation from the core cache layer to the main memory synchronization layer. These conditions include cumulative synchronization count, time interval since the last synchronization, the difference between the first current index and the current global index in the main memory synchronization layer, reliability score, and system normal / abnormal state, enabling fine-grained control over synchronization timing. For example, under normal high-load scenarios, batch synchronization based on a synchronization count threshold merges multiple updates into a single main memory write, reducing the number of main memory accesses. Simultaneously, a time threshold serves as a safety net, preventing data from becoming outdated due to prolonged inconsistency. When reliability decreases or the system malfunctions (such as hot migration), timely degradation triggering of synchronization ensures data integrity. This avoids situations where synchronization is either too frequent or too infrequent.

[0028] Further, determining the credibility score corresponding to the current index snapshot in the expected cache layer includes: obtaining the credibility baseline value corresponding to the current index snapshot in the expected cache layer; comparing the current global index in the main memory synchronization layer with the current index snapshot in the expected cache layer to obtain a first comparison result; in response to the first comparison result being consistent, increasing the credibility baseline value by a first preset value to obtain the credibility score corresponding to the current index snapshot; in response to the first comparison result being inconsistent, subtracting a second preset value from the credibility baseline value to obtain the credibility score corresponding to the current index snapshot; wherein the second preset value is greater than the first preset value; and adjusting the preset value based on the credibility score. The trigger thresholds in the new conditions are adjusted, including: comparing the credibility score with preset credibility thresholds, wherein the preset credibility thresholds include at least a first credibility threshold and a second credibility threshold; in response to the credibility score being less than or equal to the first credibility threshold, decreasing the preset update count threshold in the trigger thresholds and immediately triggering the preset update condition; in response to the credibility score being greater than the first credibility threshold and less than the second credibility threshold, keeping the preset update count threshold in the trigger thresholds unchanged and immediately triggering the preset update condition; and in response to the credibility score being greater than or equal to the second credibility threshold, increasing the preset update count threshold in the trigger thresholds.

[0029] Specifically, the above method increases the confidence level by 10 when the index snapshot matches the global index and decreases it by 20 when they do not. It also dynamically adjusts the expected cache layer update threshold based on the confidence level, enabling the system to perceive the confidence level of the current index snapshot and automatically adjust the update frequency accordingly. For example, when the index snapshot accuracy is high, updates are reduced to further save main memory access; when the index snapshot accuracy is low, updates are proactively accelerated to quickly correct invalid index snapshots. This allows the system to maintain a high index snapshot hit rate even under different load patterns, such as sudden I / O or drastic changes in queue depth, avoiding incorrect queue status judgments due to the use of outdated snapshots.

[0030] In a specific implementation, the front-end updates `expected_read_idx` every 32 write operations, and the back-end updates `expected_write_idx` every 16 read operations. A confidence score for the index snapshot is also introduced: it increases by 10 when the index snapshot matches the global index, and decreases by 20 otherwise. When the confidence score is greater than 30 but less than 80, a snapshot update is forcibly triggered to avoid prolonged use of invalid snapshots. When the confidence score is greater than or equal to 80, the update interval is extended; for example, the write update count threshold is increased from 32 to 64 to reduce main memory access. When the confidence score is less than or equal to 30, the update interval is shortened; for example, the write update count threshold is reduced from 32 to 16 to ensure the validity of the index snapshot.

[0031] Furthermore, the index optimization management method for the circular queue also includes: determining to trigger a preset update condition in response to the cumulative number of updates of an index snapshot of the same type as the current index snapshot in the expected cache layer reaching a preset update count threshold; determining to trigger a preset update condition in response to the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer being greater than a preset difference threshold; determining to trigger a preset update condition in response to the confidence score corresponding to the current index snapshot in the expected cache layer being continuously less than a first confidence threshold within a preset time period; and determining to trigger a preset update condition in response to the current system being in an abnormal state and the time interval between the current index and the last synchronization of an index of the same type as the current index reaching a preset second time threshold.

[0032] Specifically, the above method defines independent triggering conditions for the update operation from the expected cache layer to the main memory synchronization layer. These conditions include the cumulative number of updates, the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer, the confidence score, and abnormal system states. This ensures that the index snapshot in the expected cache layer does not deviate too much from the actual value in main memory for an extended period, thus guaranteeing the effectiveness of the technique of judging the queue status based on the expected snapshot. The introduction of a preset difference threshold means that when the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer exceeds 1 / 4 of the queue capacity, the system will proactively update the expected cache layer, avoiding continuous erroneous judgments based on incorrect snapshots, thus balancing performance and correctness.

[0033] In a specific embodiment, a write update condition is triggered when the cumulative number of read index snapshot updates reaches 16; a read update condition is triggered when the cumulative number of write index snapshot updates reaches 32.

[0034] Further, based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, the current state of the circular queue is determined, including: comparing the current write index in the core cache layer with the current read index snapshot in the expected cache layer to obtain a second comparison result; in response to the second comparison result being consistent, determining the current state as a write-prohibited state; in response to the second comparison result being inconsistent, determining the current state as a write-enabled state; comparing the current read index in the core cache layer with the current write index snapshot in the expected cache layer to obtain a third comparison result; in response to the third comparison result being consistent, determining the current state as a read-prohibited state; in response to the third comparison result being inconsistent, determining the current state as a read-enabled state; based on the current... The status determines whether to execute the access operation corresponding to the access request, including: If the access request is a write request and the current status is write-allowed, execute the corresponding write operation and update the current write index in the core cache layer; if the access request is a read request and the current status is read-allowed, execute the corresponding read operation and update the current read index in the core cache layer; if the access request is a write request and the current status is write-prohibited, prohibit the execution of the corresponding write operation and trigger a preset update condition to update the current read index snapshot in the expected cache layer; if the access request is a read request and the current status is read-prohibited, prohibit the execution of the corresponding read operation and trigger a preset update condition to update the current write index snapshot in the expected cache layer.

[0035] Specifically, the above method compares the current write index of the core cache layer with the current read index snapshot of the expected cache layer to determine whether the current state allows writing; and compares the current read index of the core cache layer with the current write index snapshot of the expected cache layer to determine whether the current state allows reading. In normal scenarios, the system can complete the queue state judgment without accessing the main memory. Except when writing and reading are prohibited, the index snapshot update is triggered, thereby freeing the main memory access from each I / O operation.

[0036] Furthermore, the index optimization management method for the circular queue also includes: determining that the current system is in a normal state when the confidence score is greater than a first confidence threshold; determining that the current system is in an abnormal state when the confidence score is continuously less than or equal to the first confidence threshold within a preset time period; determining that the current system is in a normal state when the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer is less than or equal to a preset difference threshold; determining that the current system is in an abnormal state when the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer is greater than a preset difference threshold; and determining that the current system is in a normal operating state when no virtual machine hot migration or device reset event is detected. The system is configured to: respond to the detection of a virtual machine hot migration or device reset event, determine that the current system is in an abnormal state; respond to the current system being in a normal state, determine a first type of memory barrier as the target memory barrier, and use the first type of memory barrier to perform synchronization operations on the indexes in the circular queue; respond to the current system being in an abnormal state, determine a second type of memory barrier as the target memory barrier, and use the second type of memory barrier to perform synchronization operations on the indexes in the circular queue; wherein, the first type of memory barrier is used to ensure that data write operations are completed before index update operations, the second type of memory barrier is used to ensure the global order of memory access operations, and the instruction overhead corresponding to the first type of memory barrier is lower than the instruction overhead corresponding to the second type of memory barrier.

[0037] Specifically, the above method meticulously determines the system state through multiple dimensions and uses hierarchical memory barriers to finely classify index update operations based on the system state. A low-overhead lightweight barrier is used under normal conditions, while a high-overhead full barrier is used under abnormal conditions. Compared to uniformly using a full barrier, this reduces the overall overhead of memory barriers without sacrificing data consistency in abnormal scenarios.

[0038] In specific embodiments, different memory barrier strategies are adopted for updating the queue index: (1) Lightweight barrier type (normal synchronization scenario): When the front end synchronously writes the index to the main memory, a lightweight barrier is used to ensure that the data write instruction is completed before the index update instruction, so that the back end can see the complete data. (2) Full barrier type (abnormal synchronization scenario): Applied to abnormal scenarios, such as when the credibility score of the index is consistently lower than 30, virtual machine hot migration, or forced synchronization when the device is reset.

[0039] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0040] In a second embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it performs the following steps: logically dividing multiple storage spaces in the current system into multiple storage levels based on different access latency, wherein the multiple storage levels include at least a core cache layer, a pre-defined cache layer, and a main memory synchronization layer; mapping the index management of a circular queue to the multiple storage levels based on different access frequencies; allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; and responding to a preset trigger. The synchronization condition involves synchronizing the first current index in the core cache layer as the corresponding first current global index to the main memory synchronization layer; determining the credibility score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the credibility score; in response to triggering the preset update condition, updating the expected cache layer by using the second current global index in the main memory synchronization layer as the corresponding first current index snapshot; and in response to receiving an access request, determining the current state of the circular queue based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and determining whether to execute the access operation corresponding to the access request based on the current state.

[0041] When the program instructions are read and executed by one or more processors, they can also perform operations corresponding to the steps in the above method embodiments, as described above, and will not be repeated here. Reference Figure 4 This exemplifies the architecture of an electronic device, which may include a processor 410, a video display adapter 411, a disk drive 412, an input / output interface 413, a network interface 414, and a memory 420. The processor 410, video display adapter 411, disk drive 412, input / output interface 413, network interface 414, and memory 420 can communicate with each other via a communication bus 430.

[0042] The processor 410 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to achieve the technical solution provided in this application.

[0043] The memory 420 can be implemented as a read-only memory (ROM), random access memory (RAM), static storage device, dynamic storage device, etc. The memory 420 can store an operating system 421 for controlling the operation of the electronic device 400, and a basic input / output system (BIOS) 422 for controlling the low-level operations of the electronic device 400. Additionally, it can store a web browser 423, data storage management 424, and an icon / font processing system 425. The icon / font processing system 425 can be the application program that specifically implements the aforementioned steps in this embodiment. In summary, when implementing the technical solution provided in this application through software or firmware, the relevant program code is stored in the memory 420 and executed by the processor 410.

[0044] Input / output interface 413 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0045] Network interface 414 is used to connect a communication module (not shown in the figure) to enable communication and interaction between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0046] Bus 430 includes a pathway for transmitting information between various components of the device, such as processor 410, video display adapter 411, disk drive 412, input / output interface 413, network interface 414, and memory 420.

[0047] In addition, the electronic device 400 can also obtain information on specific acquisition conditions from the virtual resource object acquisition condition information database (not shown in the figure) for condition judgment.

[0048] It should be noted that although the above-described electronic device 400 only shows a processor 410, a video display adapter 411, a disk drive 412, an input / output interface 413, a network interface 414, a memory 420, and a bus 430, in specific implementations, the electronic device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the solution of this application, and does not necessarily include all the components shown in the figures.

[0049] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause an electronic device (which may be a personal computer, cloud server, or network device, etc.) to execute the methods of various embodiments or some parts of the embodiments of this application.

[0050] In a third embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: logically dividing multiple storage spaces in the current system into multiple storage levels according to different access latencies, wherein the multiple storage levels include at least a core cache layer, a pre-defined cache layer, and a main memory synchronization layer; mapping the index management of a circular queue to multiple storage levels according to different access frequencies; allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; and, in response to triggering a preset synchronization condition, configuring the core cache layer to perform the following steps: The first current index in the cache layer is used as the corresponding first current global index and synchronized to the main memory synchronization layer; the credibility score corresponding to the current index snapshot in the expected cache layer is determined, and the trigger threshold in the preset update condition is adjusted according to the credibility score; in response to triggering the preset update condition, the second current global index in the main memory synchronization layer is used as the corresponding first current index snapshot and updated to the expected cache layer; in response to receiving an access request, the current state of the circular queue is determined according to the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and the access operation corresponding to the access request is determined according to the current state.

[0051] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

[0054] In a fourth embodiment, a computer program product is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: logically dividing multiple storage spaces in the current system into multiple storage levels according to different access latencies, wherein the multiple storage levels include at least a core cache layer, a pre-defined cache layer, and a main memory synchronization layer; mapping the index management of a circular queue to the multiple storage levels according to different access frequencies; allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; and responding to the triggering of a preset synchronization condition, adjusting the core cache... The first current index in the memory layer is used as the corresponding first current global index and synchronized to the main memory synchronization layer; the credibility score corresponding to the current index snapshot in the expected cache layer is determined, and the trigger threshold in the preset update condition is adjusted according to the credibility score; in response to triggering the preset update condition, the second current global index in the main memory synchronization layer is used as the corresponding first current index snapshot and updated to the expected cache layer; in response to receiving an access request, the current state of the circular queue is determined according to the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and the access operation corresponding to the access request is determined according to the current state.

[0055] In a fourth embodiment, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it performs the following steps: logically dividing multiple storage spaces in the current system into multiple storage levels according to different access latencies, wherein the multiple storage levels include at least a core cache layer, a pre-emptive cache layer, and a main memory synchronization layer; mapping the index management of a circular queue to the multiple storage levels according to different access frequencies; allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; responding to Triggering a preset synchronization condition, the first current index in the core cache layer is used as the corresponding first current global index and synchronized to the main memory synchronization layer; determining the credibility score corresponding to the current index snapshot in the expected cache layer, and adjusting the trigger threshold in the preset update condition based on the credibility score; in response to triggering the preset update condition, the second current global index in the main memory synchronization layer is used as the corresponding first current index snapshot and updated to the expected cache layer; in response to receiving an access request, the current state of the circular queue is determined based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and based on the current state, it is determined whether to execute the access operation corresponding to the access request.

[0056] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0057] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer program product, and when the computer program is executed, it can include the processes of the embodiments of the methods described above.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A method for index optimization management of a ring queue, characterized in that, The method includes: Based on different access latencies, the multiple storage spaces in the current system are logically divided into multiple storage layers, wherein the multiple storage layers include at least a core cache layer, an expected cache layer, and a main memory synchronization layer. Based on the different access frequencies, the index management of the circular queue is mapped to the multiple storage levels; Different types of indexes in the core cache layer are assigned to different cache lines that are isolated from each other, wherein the different types of indexes include read indexes and write indexes; In response to triggering a preset synchronization condition, the first current index in the core cache layer is used as the corresponding first current global index and synchronized to the main memory synchronization layer. Determine the confidence score corresponding to the current index snapshot in the expected cache layer, and adjust the trigger threshold in the preset update conditions according to the confidence score; In response to triggering the preset update condition, the second current global index in the main memory synchronization layer is used as the corresponding first current index snapshot and updated to the expected cache layer; In response to receiving an access request, the current state of the circular queue is determined based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer, and based on the current state, it is determined whether to execute the access operation corresponding to the access request.

2. The method of claim 1, wherein, Based on different access latency, the current system's multiple storage spaces are logically divided into multiple storage levels, including: The first cache space with the lowest access latency among the multiple storage spaces is determined as the core cache layer; The main memory space with the highest access latency among the multiple storage spaces is identified as the main memory synchronization layer; The second and third cache spaces, which have access latency higher than the first cache space but lower than the main memory space, are identified as the expected cache layer.

3. The method of claim 1 or 2, wherein, The step of mapping the index management of the circular queue to the multiple storage levels according to different access frequencies includes: The most frequently accessed current index in the circular queue is assigned to the core cache layer, wherein the current index includes the current read index and the current write index; The global index with the lowest access frequency in the circular queue is allocated to the main memory synchronization layer, wherein the global index includes a global read index and a global write index; The index snapshots in the circular queue that are accessed more frequently than the global index but less frequently than the current index are allocated to the expected cache layer, wherein the index snapshots include read index snapshots and write index snapshots.

4. The method of claim 1, wherein, The step of allocating different types of indexes in the core cache layer to different cache lines that are isolated from each other includes: Define a first structure and a second structure, wherein the first structure is used to store the read index and the second structure is used to store the write index; The first structure is cached in a first cache line, and the second structure is cached in a second cache line, wherein the address difference between the end address of the first cache line and the start address of the second cache line is at least the size of one cache line, or the address difference between the end address of the second cache line and the start address of the first cache line is at least the size of one cache line.

5. The method of claim 1, wherein, The method further includes: In response to the cumulative number of synchronizations of an index of the same type as the first current index reaching a preset synchronization threshold, the preset synchronization condition is determined to be triggered; In response to the current system being in a normal state, and the time interval between the index of the same type as the first current index and the last synchronization reaching a preset first time threshold, the preset synchronization condition is determined to be triggered. In response to the fact that the difference between the first current index and the current global index in the main memory synchronization layer is greater than a preset difference threshold, the preset synchronization condition is determined to be triggered; In response to the confidence score corresponding to the current index snapshot in the expected cache layer being continuously less than a preset first confidence threshold within a preset time period, the preset synchronization condition is determined to be triggered. In response to the current system being in an abnormal state, and the time interval between the index of the same type as the first current index and the last synchronization reaching a preset second time threshold, the preset synchronization condition is determined to be triggered. Wherein, the second time threshold is greater than the first time threshold.

6. The method of claim 1 or 5, wherein, Determining the confidence score corresponding to the current index snapshot in the expected cache layer includes: Obtain the confidence baseline value corresponding to the current index snapshot in the expected cache layer; The current global index in the main memory synchronization layer is compared with the current index snapshot in the expected cache layer to obtain the first comparison result; In response to the first comparison result being consistent, the confidence benchmark value is increased by a first preset value and used as the confidence score corresponding to the current index snapshot; In response to the first comparison result being inconsistent, the confidence benchmark value is subtracted from the second preset value to obtain the confidence score corresponding to the current index snapshot; Wherein, the second preset value is greater than the first preset value; The step of adjusting the trigger threshold in the preset update conditions based on the confidence score includes: The credibility scores are compared with preset credibility thresholds, wherein the preset credibility thresholds include at least a first credibility threshold and a second credibility threshold. In response to the confidence score being less than or equal to the first confidence threshold, the preset update count threshold in the trigger threshold is reduced, and the preset update condition is triggered immediately; In response to the confidence score being greater than the first confidence threshold and less than the second confidence threshold, the preset update count threshold in the trigger threshold remains unchanged, and the preset update condition is triggered immediately; In response to the confidence score being greater than or equal to the second confidence threshold, the preset update count threshold in the trigger threshold is increased.

7. The method of claim 6, wherein, The method further includes: In response to the cumulative number of updates of an index snapshot of the same type as the current index snapshot in the expected cache layer reaching the preset update number threshold, the preset update condition is determined to be triggered; In response to the fact that the difference between the current index in the core cache layer and the current global index in the main memory synchronization layer is greater than a preset difference threshold, the preset update condition is determined to be triggered; In response to the confidence score corresponding to the current index snapshot in the expected cache layer being continuously less than the first confidence threshold within a preset time period, the preset update condition is determined to be triggered. In response to the current system being in an abnormal state, and the time interval between the last synchronization and the current index of the same type reaching a preset second time threshold, the preset update condition is determined to be triggered.

8. The method of claim 1, wherein, Determining the current state of the circular queue based on the second current index in the core cache layer and the second current index snapshot in the expected cache layer includes: The current write index in the core cache layer is compared with the current read index snapshot in the expected cache layer to obtain a second comparison result; In response to the second comparison result being consistent, the current state is determined to be a write-prohibited state; In response to the second comparison result being inconsistent, the current state is determined to be a write-enabled state; The current read index in the core cache layer is compared with the current write index snapshot in the expected cache layer to obtain a third comparison result; In response to the third comparison result being consistent, the current state is determined to be a read-prohibited state; In response to the inconsistency of the third comparison result, the current state is determined to be a read-allowed state; The step of determining whether to execute the access operation corresponding to the access request based on the current state includes: In response to the access request being a write request and the current state being the write-allowed state, the corresponding write operation is executed, and the current write index in the core cache layer is updated; In response to the access request being a read request and the current state being the read-allowed state, the corresponding read operation is executed, and the current read index in the core cache layer is updated; In response to the access request being a write request and the current state being the write-prohibited state, the corresponding write operation is prohibited, and the preset update condition is triggered to update the current read index snapshot in the expected cache layer; In response to the access request being a read request and the current state being the read-prohibited state, the corresponding read operation is prohibited, and the preset update condition is triggered to update the current write index snapshot in the expected cache layer.

9. An electronic device, comprising: include: Memory, used to store computer programs; A processor, configured to implement the steps of the index optimization management method for a circular queue as described in any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the index optimization management method for the circular queue as described in any one of claims 1 to 8.

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