A data request method, device and electronic equipment

Abstract

This application provides a data request method, apparatus, and electronic device. The method is applied to an electronic device including a subsystem and a first cache, connected via a bus. The method includes: when the electronic device is under concurrent heavy load, the subsystem sends at least one read request to the first cache via a first channel in the bus, and the subsystem sends at least one write request to the first cache via a second channel in the bus, wherein the first and second channels are independent of each other; when the first read request and the first write request arrive at the first cache, the subsystem caches the first write request in a cache space corresponding to a preset cache path number in the first cache, wherein the size of the cache space is adjustable; when the first write request is cached in the cache space, the subsystem executes the first read request to obtain the corresponding data. The technical solution shown in this application improves the access priority of read requests, reduces the return latency of read requests, and improves the system performance of the electronic device under concurrent heavy load.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to a data request method, apparatus and electronic device. Background Technology

[0002] In electronic devices, subsystems can generate read and write requests. For example, a subsystem might generate read and write requests based on a Central Processing Unit (CPU). After generating the read and write requests, the CPU can send them to the cache controller via the bus. If the cache controller does not find the read or write request in its cache, it sends it to the main memory controller via the bus so that the main memory controller can process it. In some bus protocols, read and write requests are transmitted on independent channels within the bus. Therefore, although the transmission of read and write requests on different independent channels does not affect each other, when the read and write requests arrive at the main memory controller, the main memory controller processes them sequentially; that is, the main memory controller processes the received read and write requests serially.

[0003] Concurrency overload refers to a situation in electronic devices where multiple tasks or processes run simultaneously, resulting in a high concentration of access and operation on system resources and a significant increase in system load. In concurrency overload scenarios, the CPU generates a large number of read and write requests. During the serial processing of these requests by the main memory controller, if the proportion of write requests is high, the main memory controller will spend more time processing write requests, leading to longer return latency for read requests and impacting the system performance of the electronic device.

[0004] Since users are more sensitive to the return latency of read requests than to the return latency of write requests, a longer return latency for read requests can negatively impact the user experience. Summary of the Invention

[0005] This application provides a data request method, apparatus, and electronic device that can improve the access priority of read requests and reduce the return latency of read requests in scenarios where the electronic device is under concurrent heavy load, thereby improving the system performance of the electronic device.

[0006] In a first aspect, embodiments of this application provide a data request method applied to an electronic device. The electronic device includes a subsystem and a first cache, which are connected via a bus. The method includes: when the electronic device is under concurrent heavy load, the subsystem sends at least one read request to the first cache via a first channel in the bus, and the subsystem sends at least one write request to the first cache via a second channel in the bus, wherein the first channel and the second channel are independent of each other; when the first read request in the read requests and the first write request in the write requests arrive at the first cache, the subsystem caches the first write request in a cache space corresponding to a preset number of cache paths in the first cache, wherein the size of the cache space is adjustable; when the first write request is cached in the cache space, the subsystem executes the first read request to obtain the data corresponding to the first read request.

[0007] The method provided in this application embodiment, in a scenario where the electronic device is under concurrent heavy load, if the subsystem simultaneously sends read requests and write requests to the first cache based on two independent channels in the bus, the subsystem caches the write requests received by the first cache to the cache space corresponding to the preset cache path number in the first cache, and executes the first read request. In this way, this application improves the access priority of the read request, reduces the return latency of the read request, and improves the system performance of the electronic device.

[0008] In one implementation, the electronic device further includes main memory. The subsystem, the first cache, and the main memory are connected via a bus. When the first write request is cached in the cache space, the subsystem executes a first read request to retrieve the data corresponding to the first read request. This includes: when the first write request is cached in the cache space, the subsystem executes the first read request to retrieve the data corresponding to the first read request from the main memory. Using this implementation, even if the first read request misses the first cache, the subsystem can retrieve the data corresponding to the first read request from the main memory. Thus, the access to main memory by the first read request is not affected by the first write request, reducing the return latency of the read request and improving the system performance of the electronic device.

[0009] In one implementation, before the subsystem sends at least one read request to the first cache via a first channel on the bus and at least one write request to the first cache via a second channel on the bus, under concurrent heavy load scenarios, the electronic device further includes: monitoring a first bandwidth and the cache hit rate corresponding to the first cache, and adjusting the size of the cache space based on the first bandwidth and the cache hit rate. The first bandwidth includes the amount of data accessed in main memory per unit time, or the amount of data accessed in the main memory controller corresponding to main memory per unit time. The cache hit rate is the ratio of the number of cache hits in the cache for read and write requests sent by the subsystem to the first cache to the total number of requests. By adjusting the cache space size based on the first bandwidth and the cache hit rate, this implementation avoids situations where write requests occupy too much space in the cache, affecting the cache hit rate in the first cache and thus impacting the system performance of the electronic device.

[0010] In one implementation, before the subsystem sends at least one read request to the first cache via a first channel in the bus and at least one write request to the first cache via a second channel in the bus when the electronic device is under concurrent heavy load, the implementation further includes: the electronic device determining that it is under concurrent heavy load if it determines that the first bandwidth is greater than a preset first bandwidth threshold. This implementation illustrates a specific method by which the electronic device determines that it is under concurrent heavy load. This allows for determining the appropriate timing for implementing the solution shown in this application, thus avoiding the application of the technical solution in other inapplicable scenarios and preventing impact on the system performance of the electronic device.

[0011] In one implementation, the electronic device monitors the cache hit rate corresponding to the first bandwidth and the first cache, and adjusts the cache space size based on the first bandwidth and the cache hit rate. This includes: when the electronic device determines that the first bandwidth is greater than or equal to a preset second bandwidth threshold, the subsystem controls the first cache to increase its cache space size, wherein the second bandwidth threshold is greater than or equal to the first bandwidth threshold; when the electronic device determines that the cache hit rate is less than the first hit rate threshold but greater than or equal to the second hit rate threshold, the subsystem controls the first cache to stop increasing its cache space size; and when the electronic device determines that the cache hit rate is less than the second hit rate threshold, the subsystem controls the first cache to decrease its cache space size. This implementation illustrates a specific method for adjusting the cache space size. By adjusting the cache space size based on the first bandwidth and the cache hit rate, the situation where write requests occupy too much space in the cache, affecting the cache hit rate in the first cache and thus impacting the system performance of the electronic device, can be avoided.

[0012] In one implementation, the concurrent overload scenario includes at least one target scenario, each target scenario having a corresponding first hit rate threshold and a corresponding second hit rate threshold. By adopting this implementation, setting corresponding hit rate thresholds based on different scenarios ensures the reasonableness of the cache space size. This avoids situations where write requests occupy too much space in the first cache, affecting the cache hit rate in the first cache and consequently impacting the system performance of the electronic device.

[0013] In one implementation, after the subsystem executes the first read request to obtain the data corresponding to the first read request, and the first write request is cached in the cache space, the subsystem further includes: if the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request. This implementation illustrates a specific method for the electronic device to release write requests. Based on this method, releasing write requests all at once when main memory is idle ensures that all write requests in the first cache can be written to main memory even if the first cache is not hit. This effectively reduces the switching time between read and write modes in main memory and improves the utilization efficiency of main memory.

[0014] In one implementation, when the electronic device determines that the first bandwidth is less than a second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request. This includes: when the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request and writes the first write request to main memory. This implementation illustrates a specific method for the electronic device to release write requests. Based on this method, when main memory is idle, releasing write requests all at once allows all cached write requests to be written to main memory, effectively reducing the switching time between read and write modes in main memory and improving the utilization efficiency of main memory.

[0015] In one implementation, after the subsystem executes the first read request to obtain the data corresponding to the first read request, and the first write request is cached in the cache space, the subsystem further includes: if the cache space is determined to be saturated, the subsystem releases the first write request cached in the cache space to execute the first write request. This implementation illustrates a specific method for an electronic device to release write requests. Based on this method, releasing write requests all at once when the cache space is saturated ensures that all write requests in the first cache can be written to main memory even if the first cache is not hit. This effectively reduces the switching time between read and write modes in main memory and improves the utilization efficiency of main memory.

[0016] In one implementation, when the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space to execute the first write request. This includes: when the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space to execute the first write request, and writes the first write request to main memory. This implementation illustrates a specific method for an electronic device to release write requests. Based on this method, when the cache space is saturated, releasing write requests all at once allows all cached write requests to be written to main memory, effectively reducing the switching time between read and write modes in main memory and improving the utilization efficiency of main memory.

[0017] In one implementation, after the subsystem caches the first write request to the cache space corresponding to the preset cache path number in the first cache, it further includes: if a second read request in the read requests reaches the first cache, and the first write request has not been released from the cache space, and if the memory address corresponding to the second read request is the same as the memory address corresponding to the first write request, then the subsystem obtains the data corresponding to the first write request that the second read request hit in the first cache. This implementation optimizes the instruction sequence for read-after-write operations.

[0018] In one implementation, the subsystem includes a cache controller. When the electronic device is under heavy concurrent load, the subsystem sends at least one read request to a first cache via a first channel in the bus, and at least one write request to the first cache via a second channel in the bus. This includes: when the electronic device is under heavy concurrent load, the cache controller sends at least one read request to the first cache via the first channel, and the cache controller sends at least one write request to the first cache via the second channel. This implementation illustrates the specific method by which the subsystem sends read and write requests to the first cache.

[0019] In one implementation, the subsystem executes a first read request to obtain the data corresponding to the first read request. This includes: the cache controller executing the first read request and, if the first read request hits the first cache, retrieving the data corresponding to the first read request from the first cache. This implementation illustrates the specific method by which the subsystem executes the first read request. In this way, this application improves the access priority of read requests, reduces the return latency of read requests, and improves the system performance of the electronic device.

[0020] In one implementation, the subsystem further includes a main memory controller. The subsystem executes a first read request to retrieve the data corresponding to the first read request from main memory. This includes: a cache controller executing the first read request and, if the first read request misses a first cache, sending the first read request to the main memory controller; and the main memory controller executing the first read request to retrieve the data corresponding to the first read request from main memory. This implementation illustrates the specific method by which the subsystem executes the first read request and retrieves the data corresponding to the first read request from main memory. In this way, the first read request's access to main memory is not affected by the first write request, reducing the return latency of the read request and improving the system performance of the electronic device.

[0021] In one implementation, the electronic device monitors the cache hit rate corresponding to the first bandwidth and the first cache, including: the subsystem obtaining at least one of the following through a built-in performance counter: the amount of data accessed to main memory, the amount of data accessed to the main memory controller, the number of hits in the first cache, and the number of misses in the first cache; the subsystem obtaining the amount of data accessed to main memory or the amount of data accessed to the main memory controller from the performance counter based on a built-in first monitor to calculate the first bandwidth; and the subsystem obtaining the number of cache hits and the number of cache misses from the performance counter based on a built-in second monitor to calculate the cache hit rate, wherein the first monitor includes a cache bandwidth monitor and the second monitor includes a cache utilization monitor. This implementation illustrates a specific method by which the electronic device monitors the first bandwidth and the cache hit rate. By adjusting the cache space size based on the first bandwidth and the cache hit rate, the situation where write requests occupy too much space in the first cache, affecting the cache hit rate and thus impacting the system performance of the electronic device, can be avoided.

[0022] In one implementation, when the electronic device determines that the first bandwidth is greater than or equal to a preset second bandwidth threshold, the subsystem controls the first cache to increase its cache space. This includes: when the first monitor determines that the first bandwidth is greater than or equal to the second bandwidth threshold, the cache controller controls the first cache to increase its cache space. This implementation illustrates a specific method by which the electronic device monitors changes in the first bandwidth. In this way, the electronic device can adjust the cache space size based on the first bandwidth to avoid situations where write requests occupy excessive space in the cache, affecting the cache hit rate and consequently impacting the system performance of the electronic device.

[0023] In one implementation, when the electronic device determines that the cache hit rate is less than a first hit rate threshold and greater than or equal to a second hit rate threshold, the subsystem controls the first cache to stop increasing its cache space size. This includes: when the second monitor determines that the cache hit rate is less than the first hit rate threshold and greater than or equal to the second hit rate threshold, the cache controller controls the first cache to stop increasing its cache space size. This implementation illustrates a specific method by which the electronic device monitors the cache hit rate. In this way, the electronic device can adjust the cache space size based on the cache hit rate to avoid situations where write requests occupy too much space in the cache, affecting the cache hit rate and consequently impacting the system performance of the electronic device.

[0024] In one implementation, when the electronic device determines that the cache hit rate is less than a second hit rate threshold, the subsystem controls the first cache to reduce its cache space size. This includes: when the second monitor determines that the cache hit rate is less than the second hit rate threshold, the cache controller controls the first cache to reduce its cache space size. This implementation illustrates a specific method by which the electronic device monitors the cache hit rate. In this way, the electronic device can adjust the cache space size based on the cache hit rate to avoid situations where write requests occupy too much space in the cache, affecting the cache hit rate and consequently impacting the system performance of the electronic device.

[0025] In one implementation, when the electronic device determines that the first bandwidth is less than a second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request. This includes: when the first monitor determines that the first bandwidth is less than the second bandwidth threshold, the cache controller releases the first write request cached in the cache space to execute the first write request, and if the first write request hits the first cache, the data corresponding to the first write request is written to the first cache. This implementation illustrates a specific method for the electronic device to release write requests. Based on this method, releasing write requests all at once when main memory is idle ensures that all write requests in the first cache can be written to main memory even if the first cache is not hit. This effectively reduces the switching time between read and write modes in main memory and improves the utilization efficiency of main memory.

[0026] In one implementation, when the electronic device determines that the first bandwidth is less than a second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request and writes the first write request to main memory. This includes: when the first monitor determines that the first bandwidth is less than the second bandwidth threshold, the cache controller releases the first write request cached in the cache space to execute the first write request, and if the first write request misses the first cache, it sends the first write request to the main memory controller; the main memory controller executes the first write request to write the data corresponding to the first write request into the main memory. This implementation illustrates a specific method for the electronic device to release write requests. Based on this method, when the main memory is idle, releasing write requests all at once can write all write requests in the first cache to the main memory, effectively reducing the switching time between read and write modes in the main memory and improving the utilization efficiency of the main memory.

[0027] In one implementation, when the subsystem determines that the cache space is saturated, it releases the first write request cached in the cache space to execute the first write request. This includes: when the cache controller determines that the cache space is saturated, it releases the first write request cached in the cache space to execute the first write request, and if the first write request hits the first cache, it writes the data corresponding to the first write request into the first cache. This implementation illustrates a specific method for an electronic device to release write requests. Based on this method, releasing write requests all at once when the cache space is saturated ensures that all write requests to the first cache can be written to main memory even if the first cache is not hit. This effectively reduces the switching time between read and write modes in main memory and improves the utilization efficiency of main memory.

[0028] In one implementation, when the subsystem determines that the cache space is saturated, it releases the first write request cached in the cache space to execute the first write request and writes the first write request to main memory. This includes: when the cache controller determines that the cache space is saturated, it releases the first write request cached in the cache space to execute the first write request, and if the first write request misses the first cache, it sends the first write request to the main memory controller; the main memory controller executes the first write request to write the data corresponding to the first write request into main memory. This implementation demonstrates a specific method for an electronic device to release write requests. Based on this method, when the cache space is saturated, releasing write requests all at once allows all cached write requests to be written to main memory, effectively reducing the switching time between read and write modes in main memory and improving the utilization efficiency of main memory.

[0029] In one implementation, the cache space is located in static random access memory (SRAM) on the first cache. This implementation illustrates a specific type of cache space. This further expands the scope of application of the technical solution of this application.

[0030] In one implementation, the bus protocol corresponding to the bus includes at least one of the Advanced Extensible Interface (AXI) protocol and the Consistent Hub Interface (CHI) protocol. This implementation illustrates the specific type of bus protocol, thus further demonstrating the applicability of the technical solution presented in this application.

[0031] Secondly, embodiments of this application provide a data request device, including a subsystem and a first cache, which are connected via a bus. The subsystem is configured to: send at least one read request to the first cache via a first channel in the bus, and send at least one write request to the first cache via a second channel in the bus, when the electronic device is under concurrent heavy load. The first channel and the second channel are independent of each other. The subsystem is further configured to: cache the first write request in a cache space corresponding to a preset cache path number in the first cache when the first read request in the read request and the first write request in the write request arrive at the first cache. The size of the cache space is adjustable. The subsystem is further configured to: execute the first read request to obtain the data corresponding to the first read request when the first write request is cached in the cache space.

[0032] The apparatus provided in this application provides that, in a scenario where the electronic device is under concurrent heavy load, if the subsystem simultaneously sends read requests and write requests to the first cache based on two independent channels in the bus, the subsystem caches the write requests received by the first cache to the cache space corresponding to the preset number of cache paths in the first cache, and executes the first read request. In this way, this application improves the access priority of read requests, reduces the return latency of read requests, and improves the system performance of the electronic device.

[0033] In one implementation, the device further includes main memory, and the subsystem, first cache, and main memory are connected via a bus. The subsystem is further configured to: if a first write request is cached in the cache space, execute a first read request to retrieve the corresponding data from main memory. Using this implementation, even if the first read request misses the first cache, the subsystem can retrieve the corresponding data from main memory. Thus, the first read request's access to main memory is not affected by the first write request, reducing the return latency of read requests and improving the system performance of the electronic device.

[0034] Thirdly, embodiments of this application provide another data request device applied to an electronic device. The electronic device includes a subsystem and a first cache, which are connected via a bus. The device includes: a sending module, configured to send at least one read request to the first cache via a first channel in the bus and at least one write request to the first cache via a second channel in the bus when the electronic device is under concurrent heavy load; a caching module, configured to cache the first write request to a cache space corresponding to a preset number of cache paths in the first cache when the first read request in the read request and the first write request in the write request arrive at the first cache; wherein the size of the cache space is adjustable; and an acquisition module, configured to execute the first read request to acquire the data corresponding to the first read request when the first write request is cached in the cache space.

[0035] Fourthly, embodiments of this application provide an electronic device, including: a subsystem and a memory, the subsystem and the memory being coupled together, the memory storing program instructions, and when the program instructions are executed by the subsystem, causing the subsystem to execute the data request method as described in the first aspect and any implementation thereof.

[0036] Fifthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the data request method as described in the first aspect and any implementation thereof.

[0037] In a sixth aspect, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to execute the data request method as described in the first aspect and any implementation thereof.

[0038] Understandably, the beneficial effects that the technical solutions provided in the third to sixth aspects above can achieve can be referred to the beneficial effects in the first aspect and any of its implementations, and will not be repeated here. Attached Figure Description

[0039] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating a scenario where a subsystem sends read and write requests to memory.

[0041] Figure 2 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application;

[0042] Figure 3 This is a schematic diagram of the software structure of the electronic device provided in the embodiments of this application;

[0043] Figure 4 This is the first flowchart of the data request method provided in the embodiments of this application;

[0044] Figure 5 This is the first interactive schematic diagram of the data request method provided in the embodiments of this application;

[0045] Figure 6 This is a schematic diagram showing the connection relationship between the subsystem, cache, and DDR memory provided in the embodiments of this application;

[0046] Figure 7 This is a schematic diagram of the first scenario in which the subsystem provided in this application sends read and write requests to the cache;

[0047] Figure 8 This is a schematic diagram of a second scenario in which the subsystem provided in this application sends read and write requests to the cache;

[0048] Figure 9 This is a schematic diagram of a third scenario where the subsystem provided in this application sends read and write requests to the cache;

[0049] Figure 10 This is a schematic diagram illustrating a scenario where the subsystem provided in this application sends read and write requests to the DDR controller;

[0050] Figure 11 This is a schematic diagram illustrating a scenario where the cache controller provided in this application caches the first write request to the cache space;

[0051] Figure 12 This is a flowchart of the cache space adjustment method provided in the embodiments of this application;

[0052] Figure 13 This is a schematic diagram illustrating a scenario where the cache space is released for the first write request, as provided in an embodiment of this application.

[0053] Figure 14 This is the second flowchart of the data request method provided in the embodiments of this application;

[0054] Figure 15 This is a schematic diagram of the structure of the data request device provided in the embodiments of this application;

[0055] Figure 16 This is a schematic diagram of the chip system provided in the embodiments of this application. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the protection scope of this application.

[0057] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0058] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] The application scenarios of the embodiments of this application will be described below with reference to the accompanying drawings.

[0060] A subsystem is a functional module in a computer system or a system on a chip (SoC). It consists of multiple hardware and software components and is used to perform specific tasks or functions.

[0061] Subsystems can include processor subsystems, memory subsystems, input / output subsystems, graphics subsystems, network subsystems, and storage subsystems. The various components within a subsystem can work together to achieve the functionality of the entire system.

[0062] A read request is a request sent by a subsystem to memory to request that memory provide data stored at a specific address.

[0063] A write request is a request sent by a subsystem to memory, requesting that memory write data to a specific memory address.

[0064] The following describes the process by which the subsystem sends read and write requests to memory.

[0065] Figure 1 This is a schematic diagram illustrating a scenario where a subsystem sends read and write requests to memory.

[0066] like Figure 1 As shown, subsystem 1 in the electronic device can generate at least one read request and at least one write request.

[0067] For example, subsystem 1 can generate read and write requests based on its processor subsystem. Specifically, the processor subsystem can be used to execute program instructions and process data. The processor subsystem may include CPU 2, which is the main component for executing program instructions and processing data. If CPU 2 needs to read data from memory, it can generate a read request. If CPU 2 needs to write data to memory, it can generate a write request.

[0068] This embodiment is only illustrated by the example of subsystem 1 generating read and write requests based on CPU 2. In fact, subsystem 1 can also generate read and write requests based on other components, which will be described in detail in subsequent embodiments of this application.

[0069] Subsystem 1 can process read and write requests based on its memory subsystem.

[0070] Specifically, the memory subsystem includes a cache controller 3 and a main memory controller 4. The cache controller 3 manages the read and write operations of the cache 5, and the main memory controller 4 manages the read and write operations of the main memory 6. The cache 5 and the main memory 6 are different types of memory. Subsequent embodiments of this application will provide a detailed description of the cache 5 and the main memory 6.

[0071] After CPU 2 generates read and write requests, it first needs to send the read and write requests to cache controller 3 via the bus. If cache controller 3 does not find the read and write requests in cache 5, it sends the read and write requests to main memory controller 4 via the bus so that main memory controller 4 can process the read and write requests.

[0072] It's important to note that a bus is a set of parallel wires or signal paths that form a communication channel connecting hardware components, allowing data, address, and control signals to be transmitted between different hardware components. When the CPU 2, cache controller 3, and main memory controller 4 transmit data via the bus, they must adhere to a bus protocol. A bus protocol describes the communication standards and rules that must be followed when different devices communicate and transmit data. The bus protocol defines detailed specifications for data transmission formats, timing, rates, control signals, etc., to ensure efficient information exchange between different devices. Some bus protocols specify that read requests correspond to independent read request channels, read response channels, and reordering queues on the bus, and similarly, write requests correspond to independent write request channels, write response channels, and reordering queues on the bus, so that read and write requests do not interfere with each other during data transmission.

[0073] Therefore, during the transmission of read and write requests, although they are transmitted through different independent channels without affecting each other, the main memory controller 4 processes them sequentially upon arrival. In other words, the main memory controller 4 processes the received read and write requests serially. Thus, in concurrent heavy-load scenarios of electronic devices, if the number of write requests is high, the main memory controller 4 will spend more time processing write requests, resulting in longer return delays for read requests and impacting the system performance of the electronic device.

[0074] For example, in a concurrent overload scenario, main memory controller 4 prioritizes processing three write requests (the actual number may be more; this is just an illustrative example). It then prioritizes writing the data corresponding to these three write requests to main memory 6. Main memory 6 can return a write response signal to main memory controller 4 after completing the write operation. Afterward, main memory 6 processes one read request to send the data corresponding to that read request to main memory controller 4. This results in a longer return latency for the read request.

[0075] It's important to note that return latency refers to the time interval from when subsystem 1 sends a read request to when subsystem 1 receives the data corresponding to the read request. Concurrent overload refers to a situation where multiple tasks or processes run simultaneously in an electronic device, resulting in a high concentration of access to and operation of system resources (such as CPU and memory), leading to a significant increase in system load. Concurrency refers to the process of multiple tasks or operations executing alternately within the same time period. Although these tasks and operations are not executed simultaneously at a microscopic level, they give the user the impression that they are executing simultaneously at a macroscopic level. Overload refers to a situation where the resource utilization of an electronic device is close to or exceeds its processing capacity when handling multiple concurrent tasks.

[0076] It should also be noted that, Figure 1 Only a portion of the channels in the bus are shown in the accompanying drawings. The drawings in this application do not constitute a limitation on the number or type of channels in the bus.

[0077] Since users are more sensitive to the return latency of read requests than to the return latency of write requests, a longer return latency for read requests will affect the user experience.

[0078] To address the issue of long return latency for read requests in concurrent heavy-load scenarios, which affects the system performance of electronic devices and the user experience, this application provides a data request method that can be applied to electronic devices.

[0079] In this application, the electronic devices include, but are not limited to, mobile phones, tablets, personal computers, personal digital assistants (PDAs), workstations, large-screen devices (e.g., smart screens, smart TVs), wearable devices (e.g., smart bracelets, smartwatches), handheld game consoles, home game consoles, virtual reality (VR) devices, augmented reality (AR) devices, mixed reality devices, and in-vehicle smart terminals. This application does not limit the specific technologies or device forms used in the electronic devices. The electronic devices involved in this application can be equipped with... Harmony This application does not restrict the use of other operating systems.

[0080] Figure 2 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application.

[0081] like Figure 2As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a Universal Serial Bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, antennas 01 and 02, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, buttons 190, a motor 191, a camera 192, a display screen 193, and a Subscriber Identification Module (SIM) card interface 194, etc. The sensor module 180 may include a touch sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a geomagnetic sensor 180D, an accelerometer sensor 180E, a proximity sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, etc.

[0082] Processor 110 may include one or more processing units, such as a central processing unit (CPU), application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). These different processing units may be independent devices or integrated into one or more processors.

[0083] In this embodiment, the subsystem may include a processor 110, and the processor subsystem within the subsystem may include a CPU. The graphics subsystem within the subsystem may include a GPU.

[0084] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0085] In this embodiment of the application, the memory subsystem in the subsystem may include a cache controller and a double data rate synchronous dynamic random access memory (DDR SDRAM) controller, hereinafter referred to as the DDR controller.

[0086] The cache controller performs functions such as address mapping, read / write operations, cache management, and memory refresh. Address mapping refers to the cache controller's ability to translate the logical address issued by the CPU into an actual address in physical memory. Read / write operations refer to the cache controller's ability to perform corresponding operations when the CPU needs to read or write data from memory. Cache management refers to the cache controller's ability to determine the portion of data that needs to be cached and when to move this data from the cache to main memory. Memory refresh refers to the cache controller's ability to periodically refresh its internal memory space.

[0087] The DDR controller performs functions such as command scheduling, protocol conversion, data transfer, memory initialization, and refresh. Command scheduling refers to the DDR controller's ability to schedule read and write requests from the CPU or other subsystems to improve the efficiency of accessing DDR memory. Protocol conversion refers to the DDR controller's ability to translate commands from the system bus into DDR protocol commands, enabling the DDR memory to understand and execute these commands. Data transfer refers to the DDR controller's ability to manage the data transferred between the system and the DDR memory. Memory initialization and refresh refers to the DDR controller's ability to initialize the DDR memory and periodically refresh the memory to maintain data integrity.

[0088] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. Thus, electronic device 100 can play or record video in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0089] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when electronic device 100 selects a frequency, the DSP can perform Fourier transforms on the frequency energy.

[0090] NPU stands for Neural Network (NN) computing processor. By borrowing the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it can rapidly process input information and continuously learn on its own. NPUs enable intelligent cognitive applications in electronic devices, such as image recognition, facial recognition, speech recognition, and text understanding.

[0091] In some embodiments, processor 110 may include one or more interfaces. Interfaces may include Inter-Integrated Circuit (I2C) interfaces, Inter-Integrated Circuit Sound (I2S) interfaces, Pulse Code Modulation (PCM) interfaces, Universal Asynchronous Receiver / Transmitter (UART) interfaces, Mobile Industry Processor Interface (MIPI) interfaces, General-Purpose Input / Output (GPIO) interfaces, Subscriber Identity Module (SIM) interfaces, and / or Universal Serial Bus (USB) interfaces, etc. These interfaces are used to connect to other components in electronic device 100.

[0092] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C buses. The processor 110 can couple to the touch sensor 180K, charger, flash, camera 192, etc., through different I2C bus interfaces. For example, the processor 110 can couple to the touch sensor 180K through the I2C interface, enabling the processor 110 and the touch sensor 180K to communicate through the I2C bus interface, thereby realizing the touch function of the electronic device 100.

[0093] The I2S interface can be used for audio communication. In some embodiments, the processor 110 may include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface to enable the function of answering phone calls through a Bluetooth headset.

[0094] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via the PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering phone calls through a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0095] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface to enable music playback through Bluetooth headphones.

[0096] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display screen 193 and the camera 192. The MIPI interface includes a Camera Serial Interface (CSI) and a Display Serial Interface (DSI). In some embodiments, the processor 110 and the camera 192 communicate via the CSI interface to enable the electronic device 100 to capture images. The processor 110 and the display screen 193 communicate via the DSI interface to enable the electronic device 100 to display images.

[0097] The GPIO interface can be configured via software. It can be configured as a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to a camera 192, a display screen 193, a wireless communication module 160, an audio module 170, a sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0098] It is understood that the interface connection relationships between the modules illustrated in the embodiments of the present invention are merely illustrative and do not constitute a structural limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may also employ different interface connection methods or combinations of multiple interface connection methods as described in the above embodiments.

[0099] The memory may include internal memory 121. Internal memory 121 may include one or more random access memory (RAM) and one or more non-volatile memory (NVM).

[0100] Random access memory can include static random-access memory (SRAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), and double data rate synchronous dynamic random-access memory (DDR SDRAM), such as fifth-generation DDR SDRAM (generally referred to as DDR5 SDRAM).

[0101] Non-volatile memory can include disk storage devices and flash memory. Flash memory can be classified according to its operating principle, such as NOR flash, NAND flash, and 3D NAND flash; according to the level of its storage cells, such as single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC); and according to its storage specification, such as universal flash storage (UFS) and embedded multimedia card (eMMC).

[0102] Random access memory (RAM) can be directly read and written by the processor 110. It can be used to store executable programs (such as machine instructions) of the operating system or other running programs, as well as user and application data. Non-volatile memory can also store executable programs and user and application data, and can be pre-loaded into RAM for direct read and write by the processor 110.

[0103] The external memory interface 120 can be used to connect to external non-volatile memory, thereby expanding the storage capacity of the electronic device 100. The external non-volatile memory communicates with the processor 110 through the external memory interface 120 to perform data storage functions.

[0104] This application embodiment involves the use of cache and DDR SDRAM (hereinafter referred to as DDR memory).

[0105] USB port 130 is a USB standard compliant interface, specifically a Mini USB port, Micro USB port, USB Type-C port, etc. USB port 130 can be used to connect a charger to charge electronic device 100, and can also be used for data transfer between electronic device 100 and peripheral devices. It can also be used to connect headphones for audio playback. This interface can also be used to connect other electronic devices, such as AR devices.

[0106] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.

[0107] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 193, camera 192, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0108] The wireless communication function of electronic device 100 can be implemented through antenna 01, antenna 02, mobile communication module 150, wireless communication module 160, modem processor, and baseband processor.

[0109] Antennas 01 and 02 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 01 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with tuning switches.

[0110] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low-noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves via antenna 01, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 01. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0111] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device or displays an image or video through the display screen 193. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0112] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including Wireless Local Area Networks (WLAN) (such as Wireless Fidelity (Wi-Fi) networks), Bluetooth (BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), and Infrared (IR) technologies. The wireless communication module 160 receives electromagnetic waves via antenna 02, modulates and filters the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, modulate and amplify them, and then convert them into electromagnetic waves for radiation via antenna 02.

[0113] In some embodiments, antenna 01 of electronic device 100 is coupled to mobile communication module 110, and antenna 02 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other devices via wireless communication technology. Wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. GNSS can include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or Satellite Based Augmentation Systems (SBAS).

[0114] Electronic device 100 implements display functions through a GPU, a display screen 193, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 193 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0115] Display screen 193 is used to display images, videos, etc. Display screen 193 includes a display panel. The display panel can be a liquid crystal display (LCD). The display panel can also be manufactured using organic light-emitting diodes (OLEDs), active-matrix organic light-emitting diodes (AMOLEDs), flexible light-emitting diodes (FLEDs), minimized, microled, micro-oled, quantum dot light-emitting diodes (QLEDs), etc. In some embodiments, the electronic device may include one or N displays 193, where N is a positive integer greater than 1.

[0116] Electronic device 100 can perform shooting functions through ISP, camera 192, video codec, GPU, display 193 and application processor.

[0117] The ISP (Image Signal Processor) is used to process data fed back from the camera 192. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization of image noise, brightness, and skin tone. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set within the camera 192.

[0118] Camera 192 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 192, where N is a positive integer greater than 1.

[0119] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170 and application processor.

[0120] The audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 may be located in the processor 110, or some functional modules of the audio module 170 may be located in the processor 110.

[0121] Touch sensor 180A, also known as a "touch device," can be disposed on display screen 193. The touch sensor 180A and display screen 193 together form a touchscreen, also known as a "touchscreen." Touch sensor 180A is used to detect touch operations applied to or near it. The touch sensor can transmit the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through display screen 193. In other embodiments, touch sensor 180A may also be disposed on the surface of electronic device 100, in a different location than display screen 193.

[0122] The gyroscope sensor 180B can be used to determine the motion attitude of the electronic device 100.

[0123] The 180C barometric pressure sensor is used to measure barometric pressure.

[0124] The geomagnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the geomagnetic sensor 180D to detect the opening and closing of the flip cover.

[0125] The 180E accelerometer can detect the magnitude of acceleration of electronic device 100 in various directions (typically three axes). When electronic device 100 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the posture of electronic devices and applied to applications such as screen orientation switching and pedometers.

[0126] A distance sensor 180F is used to measure distance. Electronic device 100 can measure distance via infrared or laser. In some embodiments, during a shooting scene, electronic device 100 can utilize the distance sensor 180F to measure distance for rapid focusing.

[0127] The proximity light sensor 180G may include, for example, a light-emitting diode and a light detector, such as a photodiode.

[0128] The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can utilize the characteristics of the collected fingerprints to achieve fingerprint unlocking, accessing application locks, taking photos with fingerprints, answering calls with fingerprints, etc.

[0129] Temperature sensor 180J is used to detect temperature. In some embodiments, electronic device 100 uses the temperature detected by temperature sensor 180J to execute a temperature handling strategy. For example, when the temperature reported by temperature sensor 180J exceeds a threshold, electronic device 100 performs thermal protection by reducing the performance of a processor located near temperature sensor 180J to reduce power consumption. In other embodiments, when the temperature is below another threshold, electronic device 100 heats battery 142 to prevent abnormal shutdown of electronic device 100 due to low temperature. In still other embodiments, when the temperature is below yet another threshold, electronic device 100 boosts the output voltage of battery 142 to prevent abnormal shutdown due to low temperature.

[0130] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Electronic device 100 can receive button input and generate key signal inputs related to user settings and function control of electronic device 100.

[0131] Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. For example, different vibration feedback effects can be corresponding to touch operations applied to different applications (such as taking photos, playing audio, etc.). Motor 191 can also correspond to different vibration feedback effects for touch operations applied to different areas of the display screen 193. Different application scenarios (such as time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also be customized.

[0132] The SIM card interface 194 is used to connect the SIM card.

[0133] The software system of electronic device 100 can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This embodiment of the invention uses the layered architecture Android system as an example to exemplify the software structure of electronic device 100.

[0134] Figure 3 This is a schematic diagram of the software structure of the electronic device provided in the embodiments of this application.

[0135] like Figure 3 As shown, the layered architecture divides the software into several layers, each with a clear role and function. Layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom: the application layer, the application framework layer, the Android runtime and system libraries, and the kernel layer.

[0136] The application layer can include a series of application packages.

[0137] like Figure 3 As shown, the application package may include applications such as battery management, camera, gallery, calendar, call, map, navigation, music, video, and SMS.

[0138] In this embodiment, the application may also include live streaming applications, financial applications, and social applications. These applications are prone to triggering electronic devices into concurrent heavy-load scenarios.

[0139] The application framework layer may include window managers, content providers, view systems, phone managers, resource managers, notification managers, etc.

[0140] The window manager is used to manage windowed applications. It can retrieve screen size, determine the presence of a status bar, lock the screen, and capture screenshots, among other things.

[0141] Content providers store and retrieve data, making that data accessible to applications. This data may include videos, images, audio, made and received phone calls, browsing history and bookmarks, phone books, etc.

[0142] A view system includes visual controls, such as controls for displaying text and controls for displaying images. View systems can be used to build applications. A display interface can consist of one or more views. For example, a display interface including a text notification icon could include views for displaying text and views for displaying images.

[0143] A phone manager is used to provide communication functions for electronic devices. For example, it manages call status (including connection and disconnection).

[0144] The file explorer provides applications with various resources, such as localized strings, icons, images, layout files, video files, and more.

[0145] The notification manager allows applications to display notifications in the status bar. These notifications can be used to deliver informational messages and can disappear automatically after a short pause, requiring no user interaction. For example, the notification manager can be used to notify users of completed downloads or message alerts. The notification manager can also display notifications as icons or scrolling text in the top status bar, such as notifications from background applications, or as dialog boxes on the screen. Examples include displaying text messages in the status bar, emitting sounds, vibrating electronic devices, and flashing indicator lights.

[0146] In this embodiment, the application framework layer may include a scenario service module. The scenario service module can be used to manage and provide services related to specific scenarios, such as services related to concurrent heavy-load scenarios. The scenario service module can automatically execute corresponding operations based on predefined rules and conditions to improve user experience.

[0147] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0148] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0149] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0150] System libraries can include multiple functional modules. For example: Surface Manager, Media Libraries, 3D graphics processing libraries (e.g., OpenGL ES), 2D graphics engines (e.g., SGL), etc.

[0151] The Surface Manager is used to manage the display subsystem and provides the blending of 2D and 3D layers for multiple applications.

[0152] The media library supports playback and recording of various common audio and video formats, as well as still image files. It supports multiple audio and video encoding formats, such as MPEG4, H.264, MP3, AAC, AMR, JPG, and PNG.

[0153] The 3D graphics processing library is used to implement 3D graphics drawing, image rendering, compositing, and layer processing.

[0154] A 2D graphics engine is a graphics engine for 2D drawing.

[0155] The kernel layer is the layer between hardware and software.

[0156] The kernel layer can include the base kernel, extended kernel, hardware abstraction layer (HAL), and driver layer.

[0157] The basic kernel can implement core functions such as memory management, task management, inter-process communication, and interrupt management based on the memory (Mem) interface, task (Task) interface, inter-process communication (IPC) interface, and interrupt interface.

[0158] The Hardware Abstraction Layer (HAL) can abstract the hardware operation interface, encapsulating the underlying driver interface into a unified Application Programming Interface (API). This simplifies the complexity of hardware operations for applications.

[0159] It should be noted that the embodiments of this application are only illustrated by taking the HAL layer as part of the kernel layer. In fact, the HAL layer can also be independent of the kernel layer, and the embodiments of this application do not limit this.

[0160] The driver layer includes at least the display driver, camera driver, audio driver, and sensor driver.

[0161] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0162] The data request method provided in this application embodiment can be implemented in an electronic device 100 having the above-described hardware and software structures.

[0163] Figure 4 This is the first flowchart of the data request method provided in the embodiments of this application.

[0164] Figure 5 This is the first interactive schematic diagram of the data request method provided in the embodiments of this application.

[0165] like Figure 4 and Figure 5 As shown, in some embodiments, the method includes the following steps S101-S107.

[0166] In step S101, the electronic device generates at least one read request and at least one write request based on the subsystem.

[0167] In one implementation, the subsystem can generate read and write requests based on its processor subsystem. The method by which the subsystem generates read and write requests based on the processor subsystem can be found in the foregoing embodiments, and will not be repeated here.

[0168] In one implementation, the subsystem can generate read and write requests based on its graphics subsystem. Specifically, the graphics subsystem can be used to process graphics and image data for rendering and displaying graphics. The graphics subsystem may include a GPU, which is the main component performing graphics computing tasks (such as pixel shading and vertex shading). If the GPU needs to read graphics data from memory, it can generate a read request. If the GPU needs to write graphics data to memory, it can generate a write request.

[0169] In one implementation, the subsystem can generate read and write requests based on its input / output subsystem. Specifically, the input / output subsystem can be used to manage input / output devices. The input / output subsystem may include an input / output controller, which can be used to manage read and write operations on the input / output devices. If the input / output controller needs to read data from memory, it can generate a read request. If the input / output controller needs to write data to memory, it can generate a write request.

[0170] In various situations, the subsystem can generate read requests and write requests. This application embodiment does not limit the specific way in which the subsystem generates read requests and write requests.

[0171] In step S102, the subsystem sends at least one read request and at least one write request to the cache, and if the read request and write request are not found in the cache, the read request and write request are sent to the main memory.

[0172] Specifically, after the subsystem generates read and write requests, it needs to interact with memory to retrieve data from memory or write data to memory.

[0173] Memory, also known as Random Access Memory (RAM), is a type of hardware in electronic devices used to temporarily store data and programs. Memory can store various types of data, including text, numbers, images, audio, and video.

[0174] Memory includes on-chip RAM and off-chip RAM.

[0175] On-chip memory is memory integrated inside the processor chip, located on the same silicon chip as the CPU core. This results in a shorter distance between the on-chip memory and the CPU core, allowing the CPU core to access the on-chip memory with lower latency.

[0176] On-chip memory includes, for example, cache, register file, single-port static random access memory (SPSRAM), dual-port static random access memory (DPSRAM), and scratchpad memory.

[0177] A cache is a small-capacity, high-speed memory that can be used to temporarily store data and instructions that are frequently accessed by the processor. In this way, the cache can reduce the number of times the subsystem accesses off-chip memory, thereby improving the overall performance of electronic devices.

[0178] Caches typically include Level 1 Cache (L1 Cache), Level 2 Cache (L2 Cache), and Level 3 Cache (L3 Cache). The Level 1 cache can be integrated within the CPU core and is used to store the most frequently accessed data and instructions by the subsystem (e.g., data in the instruction queue). The Level 2 cache can be integrated within the processor chip but not within the CPU core. It can be shared by multiple CPU cores and stores data and instructions missed in the Level 1 cache, further reducing the subsystem's access to off-chip memory. The Level 3 cache can also be integrated within the processor chip but not within the CPU core. It can be shared by multiple CPU cores and stores data and instructions missed in the Level 1 and Level 2 caches, further reducing the subsystem's access to off-chip memory.

[0179] It's important to clarify that a cache hit occurs when the data requested by the subsystem exists in the cache. In this case, the subsystem can directly retrieve or write data from the cache without accessing off-chip memory, thus reducing access latency. A cache miss occurs when the data requested by the subsystem does not exist in the cache. In this case, the subsystem cannot directly retrieve or write data from the cache and must access off-chip memory. This increases access latency and impacts the system performance of the electronic device.

[0180] This application involves the process of accessing the cache by read and write requests sent by the subsystem, which will be described in detail in subsequent embodiments of this application.

[0181] Off-chip memory, also known as main memory (hereinafter referred to as main memory in all embodiments), is memory located outside the processor chip and can be installed on the motherboard of an electronic device. Slots or interfaces on the motherboard can connect to the processor chip via a bus, allowing the subsystem to access the main memory. Although the distance between the main memory and the subsystem is relatively long, resulting in higher latency for subsystem access to main memory, main memory has the advantages of low cost and large capacity.

[0182] Main memory includes, for example, Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), DDR memory, and Static Random Access Memory (SRAM). This application does not limit the specific type of main memory.

[0183] DDR memory, by transmitting data on both the rising and falling edges of the clock signal, achieves double the signal transmission rate, significantly improving memory bandwidth and performance. DDR memory is a commonly used type of main memory, and subsequent embodiments in this application will use DDR memory as an example for illustrative purposes. It should be noted that DDR memory does not constitute a limitation on the type of main memory.

[0184] This application involves the process of accessing DDR memory by read and write requests sent by the subsystem, which will be described in detail in subsequent embodiments of this application.

[0185] During the interaction between the subsystem and memory, the subsystem first accesses the cache and then the DDR memory. This access process can be determined based on the connectivity between the subsystem, cache, and DDR memory. It's important to note that this access process is not only determined by the connectivity between the subsystem, cache, and DDR memory, but also by the different storage capacities of the cache and DDR memory.

[0186] The following describes the connection relationships between the subsystem, cache, and DDR memory.

[0187] Figure 6 This is a schematic diagram showing the connection relationship between the subsystem, cache, and DDR memory provided in the embodiments of this application.

[0188] like Figure 6As shown, the processor chip 101 has a subsystem 102 and a cache 103, and a DDR memory 104 is externally disposed on the processor chip 101. The subsystem 102, the cache 103, and the DDR memory 104 are connected via a bus 105.

[0189] It should be noted that, depending on the location of the bus, bus 105 can be divided into on-chip bus and off-chip bus. The on-chip bus is the bus integrated inside the processor chip 101. The off-chip bus is the bus that connects the processor chip 101 to external components, such as DDR memory 104.

[0190] The processor chip 101 includes a processor core 1011. The cache 103 includes a level 1 cache 1031, a level 2 cache 1032, and a level 3 cache 1033. The bus 105 includes a first on-chip bus 1051, a second on-chip bus 1052, a third on-chip bus 1053, and a first external bus 1054.

[0191] It should be noted that the first upper bus 1051, the second upper bus 1052, the third upper bus 1053, and the first external bus 1054 can be independent of each other or integrated on the same bus. In this embodiment, the different buses 105 are distinguished only by their corresponding connection relationships. This embodiment does not limit the specific configuration of the buses 105.

[0192] Subsystem 102 and L1 cache 1031 are located on processor core 1011 and are connected to each other via a first on-chip bus 1051.

[0193] The L2 cache 1032 and L3 cache 1033 are located on the processor chip 101 in an area other than the processor core 1011, and the distance between the L2 cache 1032 and the processor core 1011 is less than the distance between the L3 cache 1033 and the processor core 1011. Subsystem 102 and L2 cache 1032 are connected via a second on-chip bus 1052. Subsystem 102 and L3 cache 1033 are connected via a third on-chip bus 1053.

[0194] The processor chip 101 is connected to one end of the first external bus 1054 via an interface (not shown in the figure), and the DDR memory 104 is connected to the other end of the first external bus 1054 via an interface 1042, so as to realize the connection between the subsystem 102 and the DDR memory 104.

[0195] Based on the above connection relationship, subsystem 102 can access cache 103 and DDR memory 104 via bus 105.

[0196] It should be noted that the specific way in which subsystem 102 accesses cache 103 and DDR memory 104 based on bus 105 is specified by the bus protocol corresponding to bus 105.

[0197] In one implementation, the bus protocol corresponding to bus 105 may include at least one of the Advanced Extensible Interface (AXI) protocol and the Coherent Hub Interface (CHI) protocol. Different bus protocols correspond to different access methods, and this application embodiment does not limit the specific type of bus protocol.

[0198] The AXI protocol is a high-performance, low-latency bus protocol that defines multiple channels, including read address channels, read data channels, write address channels, write data channels, and write response channels. The read address channel transmits the address of a read request. The read data channel returns the data requested in the read request. The write address channel transmits the address of a write request. The write data channel transmits the data requested in the write request. The write response channel returns the result of the write request. Thus, based on multiple independent channels, the AXI protocol can not only transmit multiple data units at once, reducing communication overhead, but also enable parallel processing of multiple tasks, improving system throughput, and reducing bus conflicts and latency.

[0199] The CHI protocol has a layered architecture and is a packet-based bus protocol, comprising a protocol layer, a network layer, and a link layer. The protocol layer defines various event types and cache coherency mechanisms, supporting event types such as read / write operations, atomic operations, and exclusive access. Furthermore, the protocol layer ensures cache coherency across multiple processor cores. The network layer packages the events generated by the protocol layer into data packets and configures routing mechanisms for these packets. The link layer transmits these data packets over the physical link. Thus, the CHI protocol is suitable for multi-core systems and supports efficient parallel processing.

[0200] This application provides an exemplary illustration using bus 105 corresponding to the AXI protocol.

[0201] When bus 105 corresponds to the AXI protocol, subsystem 102 can send at least one read request to cache 103 based on the first channel in bus 105, and subsystem 102 can send at least one write request to cache 103 based on the second channel in bus 105. The first channel can be a read data channel defined by the AXI protocol, and the second channel can be a write data channel defined by the AXI protocol. The first channel and the second channel are independent of each other.

[0202] The following provides a further explanation of the process by which subsystem 102 sends read and write requests to cache 103.

[0203] Figure 7 This is a schematic diagram of the first scenario in which the subsystem provided in this application sends read and write requests to the cache.

[0204] like Figure 7 As shown, subsystem 102 includes CPU core 1021, cache controller 1022, and DDR controller 1023. CPU core 1021 and cache controller 1022 can be connected via a fourth on-chip bus 1055. Cache controller 1022 and DDR controller 1023 can be connected via a fifth on-chip bus 1056.

[0205] It's important to note that both on-chip and off-chip buses can be further divided into a data bus, an address bus, and a control bus. The data bus transmits data, and its width determines the amount of data transmitted at a time. For example, a 32-bit data bus can transmit 4 bytes of data at a time. The address bus transmits memory addresses, and its width determines the size of the addressable memory space. For example, a 32-bit address bus can address 4 gigabytes (GB) of memory. The control bus transmits control signals, including read / write commands, clock signals, and interrupt signals, which coordinate the operation of various components.

[0206] This application provides an example illustration where read and write requests are generated in CPU core 1021. If read and write requests are generated based on other parts of subsystem 102 (such as GPU), the transmission method can be referred to in this embodiment, and will not be described in detail here.

[0207] In this embodiment of the application, the cache controller 1022 is a key component for managing the read and write operations of the cache 103. The cache controller 1022 can convert the logical address in the CPU core 1021 into the actual address in the physical memory.

[0208] Specifically, after the CPU core 1021 generates read and write requests, both the read and write requests will include the corresponding target memory address. The CPU core 1021 can send the target memory address to the cache controller 1022 via the address bus in the fourth on-chip bus 1055, and send read and write request signals to the cache controller 1022 via the control bus in the fourth on-chip bus 1055, so as to instruct the cache controller 1022 to perform read and write operations.

[0209] It should be noted that the target memory address corresponding to the read request and the write request is not the same target memory address. In the subsequent embodiments of this application, no specific distinction is made when describing the relevant concepts of target memory address. In actual cases, the correspondence between the request and the address needs to be considered.

[0210] The cache controller 1022 can first send read requests and write requests to the first-level cache 1031.

[0211] Specifically, after receiving the target memory address, the cache controller 1022 parses the target memory address to determine whether the target data corresponding to the target memory address is located in the first-level cache 1031.

[0212] The following section provides a detailed explanation of how the cache controller 1022 resolves target memory addresses.

[0213] The cache controller 1022 can decompose the target memory address into parts such as a tag, an index, and an intra-block offset address. First, the cache controller 1022 determines the target cache group in cache 103 based on the index part. Second, the cache controller 1022 compares the tag part with preset tag parts in the target cache group to determine whether the target data is located in cache 103 based on tag matching. Finally, if the tag matches, the cache controller 1022 determines a cache hit and reads the target data from the target cache group based on the intra-block offset address. Therefore, if the cache controller 1022 determines that the target data corresponding to the target memory address is located in the L1 cache 1031 after parsing the target memory address, the cache controller 1022 will read and write the target data.

[0214] It should be noted that, in reality, concurrent read and write requests may not necessarily hit the L1 cache simultaneously. This embodiment only illustrates the case where both requests hit the L1 cache. Furthermore, subsequent embodiments of this application will exemplify both hit and miss effects for read and write requests, and will not elaborate further on these aspects in subsequent embodiments.

[0215] Figure 8 This is a schematic diagram of the second scenario in which the subsystem provided in this application sends read and write requests to the cache.

[0216] like Figure 8 As shown, if the cache controller 1022 determines, after parsing the target memory address, that the target data corresponding to the target memory address is not located in the L1 cache 1031, then the cache controller 1022 can send read and write requests to the L2 cache 1032. That is, the cache controller 1022 determines whether the target data corresponding to the target memory address is located in the L2 cache 1032.

[0217] Based on a similar parsing method, if the cache controller 1022 parses the target memory address and determines that the target data corresponding to the target memory address is located in the L2 cache 1032, then the cache controller 1022 reads the target data and writes the target data.

[0218] Figure 9 This is a schematic diagram of the third scenario in which the subsystem provided in this application sends read and write requests to the cache.

[0219] like Figure 9 As shown, if the cache controller 1022 determines, after parsing the target memory address, that the target data corresponding to the target memory address is not located in the L2 cache 1032, then the cache controller 1022 can send read and write requests to the L3 cache 1033. That is, the cache controller 1022 determines whether the target data corresponding to the target memory address is located in the L3 cache 1033.

[0220] Based on a similar parsing method, if the cache controller 1022 parses the target memory address and determines that the target data corresponding to the target memory address is located in the L3 cache 1033, then the cache controller 1022 reads the target data and writes the target data.

[0221] Figure 10 This is a schematic diagram illustrating a scenario where the subsystem provided in this application sends read and write requests to the DDR controller.

[0222] like Figure 10 As shown, if the cache controller 1022 determines, after parsing the target memory address, that the target data corresponding to the target memory address is not located in the L3 cache 1033, then the cache controller 1022 can send read and write requests to the DDR controller 1023, so that the DDR controller 1023 can send the read and write requests to the DDR memory 104. That is, the cache controller 1022 can send the target memory address to the DDR controller 1023 based on the address bus in the fifth on-chip bus 1056, and send read and write request signals to the DDR controller 1023 based on the control bus in the fifth on-chip bus 1056, to indicate that the DDR controller 1023 needs to perform read and write operations.

[0223] In step S103, the subsystem retrieves the data corresponding to the read request from the main memory and writes the data corresponding to the write request into the main memory.

[0224] Further explaining based on the foregoing embodiments, after receiving read and write requests, the DDR controller 1023 obtains the data corresponding to the read request from the DDR memory 104 and writes the data corresponding to the read request into the DDR memory 104. Specifically, based on a parsing method similar to the foregoing embodiments, after receiving the target memory address, the DDR controller 1023 parses the target memory address, reads the target data corresponding to the target memory address from the DDR memory 104 according to the parsed address, and writes the target data corresponding to the target memory address into the DDR memory 104 according to the parsed address.

[0225] In step S104, the electronic device monitors the cache hit rate corresponding to the first bandwidth and the cache, wherein the first bandwidth corresponds to the main memory or the main memory controller.

[0226] The first bandwidth includes the amount of data accessed per unit time in main memory (such as DDR memory 104), or the amount of data accessed per unit time in the main memory controller (such as DDR controller 1023). The cache hit rate is the proportion of read and write requests sent by subsystem 102 to cache 103 that are successfully hit in cache 103 out of the total number of requests.

[0227] In one implementation, step S104 includes steps S1041-S1042.

[0228] In step S1041, the subsystem obtains at least one of the following through its built-in performance counters: the amount of data accessed to main memory, the amount of data accessed to the main memory controller, the number of cache hits, and the number of cache misses.

[0229] The performance counter can be a hardware component located in the SoC used to monitor and analyze the SoC's operating status. In addition to acquiring data such as the amount of data in main memory, the number of cache hits, and the number of cache misses, the performance counter can also monitor data such as CPU utilization, memory usage, and network traffic. This application embodiment does not limit the data types that the performance counter can acquire.

[0230] In step S1042, the subsystem obtains the amount of data accessed to main memory from the performance counter based on the built-in first monitor to calculate the first bandwidth. The subsystem also obtains the number of cache hits and the number of cache misses from the performance counter based on the built-in second monitor to calculate the cache hit rate. The first monitor includes a cache bandwidth monitor, and the second monitor includes a cache utilization monitor.

[0231] The cache bandwidth monitor can be a tool or hardware component used to monitor the data transfer rate of the cache and components connected to the cache. The cache utilization monitor can also be a tool or hardware component used to monitor the usage of the cache system, including cache hit rate, cache miss rate, and cache occupancy. This application embodiment only illustrates the example where both the cache bandwidth monitor and the cache hit rate monitor are software tools within the CPU.

[0232] It should be noted that, in this embodiment, step S104 is not limited to being executed after step S103. This embodiment does not restrict the specific execution order of step S104.

[0233] In one implementation, when the operating system of the electronic device starts, its Basic Input / Output System (BIOS) or Unified Extensible Firmware (UEFI) initializes the hardware devices (e.g., CPU and memory). For example, the operating system initializes the cache based on the cache controller in the subsystem and initializes the DDR memory based on the DDR controller in the subsystem. After the hardware initialization is complete, the operating system starts a performance monitoring service based on the first and second monitors in the subsystem to obtain the initial bandwidth and cache hit rate.

[0234] In other words, the electronic device can execute step S104 after hardware initialization, and step S104 is executed continuously during the operation of the electronic device.

[0235] Monitoring the first bandwidth and cache hit rate of the electronic device can be used, on the one hand, to determine whether the electronic device has entered a concurrent heavy load scenario in subsequent embodiments, and on the other hand, to adjust the size of the cache space in subsequent embodiments. This will be further explained in subsequent embodiments of this application.

[0236] In this embodiment of the application, the electronic device may also monitor the first bandwidth and cache hit rate based on other types of hardware or software, and this embodiment of the application does not limit this.

[0237] In step S105, based on the first bandwidth, the electronic device determines that it has entered a concurrent overload scenario. In the concurrent overload scenario, the subsystem sends at least one read request and at least one write request to the cache.

[0238] In concurrent overload scenarios, multiple tasks or processes on an electronic device run simultaneously, requiring the system to handle a large number of concurrent requests, leading to a significant increase in system load. Examples of concurrent overload scenarios include online live streaming, financial trading, and social media trending topics. In online live streaming, a large number of users simultaneously watching, commenting, and tipping on live streaming applications generate a large number of read and write requests for the electronic device. In financial trading, a large number of users simultaneously buying and selling in financial applications generate a large number of read and write requests for the electronic device. In social media trending topics, a large number of users simultaneously accessing and interacting in social applications generate a large number of read and write requests for the electronic device. Concurrent overload scenarios have various types, and this application embodiment does not limit the specific type of concurrent overload scenario.

[0239] In one implementation, the electronic device determines to enter a concurrent overload scenario when it determines that the first bandwidth is greater than a preset first bandwidth threshold. It should be noted that the specific value of the first bandwidth threshold can be set according to actual conditions, and this application embodiment does not limit the specific value of the first bandwidth threshold.

[0240] It should be noted that the first bandwidth, whether it is the bandwidth corresponding to the main memory or the bandwidth corresponding to the main memory controller, can be used to determine whether the electronic device has entered a concurrent heavy load scenario. This is because the read and write requests received by the main memory controller will inevitably be processed based on the main memory controller. Therefore, the bandwidth corresponding to the main memory and the bandwidth corresponding to the main memory controller are related and can both be used to determine whether the bus load is large.

[0241] In one implementation, the first monitor can notify the scene service module of the electronic device of this event if it determines that the first bandwidth is greater than a preset first bandwidth threshold, so that the scene service module can determine that it has entered a concurrent overload scene.

[0242] Electronic devices can also determine whether to enter a concurrent heavy-load scenario based on various data such as CPU utilization, memory utilization, input / output latency, and application response time. Based on different methods of determining whether to enter a concurrent heavy-load scenario, this application can derive more embodiments. For example, the electronic device can monitor CPU utilization and determine whether to enter a concurrent heavy-load scenario based on CPU utilization. This application does not limit the specific method by which the electronic device determines whether to enter a concurrent heavy-load scenario; reference can be made between the various embodiments of this application, and further details are omitted here.

[0243] It should be noted that the specific method by which the subsystem sends at least one read request and at least one write request to the cache can be referred to the foregoing embodiments. That is, similar to the foregoing embodiments, when the electronic device is under concurrent heavy load, the cache controller sends at least one read request to the cache based on the first channel, and the cache controller sends at least one write request to the cache based on the second channel.

[0244] In step S106, when the first read request in the read request and the first write request in the write request arrive at the cache, the subsystem caches the first write request to the cache space corresponding to the preset cache way.

[0245] It should be noted that, since the subsystem will continuously send multiple read requests and multiple write requests to the cache, the first read request and the first write request in this application are only used to indicate the request that the cache currently needs to process.

[0246] In one implementation, the cache controller caches the first write request in the cache space corresponding to the preset Cache Way.

[0247] Cache Way can be used to represent the number of cache lines contained in each cache set.

[0248] A cache set is a logical partition within the cache. Each set contains multiple cache lines, and the size of each set is determined by the number of Ways. A cache line is the smallest unit of storage in the cache, typically containing a fixed amount of data. For example, a cache line might contain 64 bytes of data. For instance, with a default cache Way of 4, each cache set contains 4 Ways, corresponding to 4 × 64 = 256 bytes. If the number of cache sets is 16, the cache space size can be 4096 bytes.

[0249] Cache ways correspond to different organizational structures, such as direct-mapped caches, fully associative caches, and N-way set-associative caches. A direct-mapped cache means that each memory address can only be mapped to a unique cache block. In this structure, each memory address can be used to find the corresponding cache line based on its index. A fully associative cache means that each memory address can be mapped to any block in the cache. In this structure, all cache blocks share a global storage space, and searching for target data requires comparing the tags of all cache blocks. An N-way set-associative cache means that each memory address can be mapped to a specific cache set, and each cache set can contain N cache blocks (N is a positive integer). In this structure, the cache is divided into multiple sets, each with a fixed number of cache blocks. When searching for target data, the corresponding set must first be determined based on the index, and then the tags of the cache blocks within that set are compared.

[0250] Based on different organizational structures, the subsystem can cache the first write request in the cache space using different storage methods. This application embodiment does not limit the type of organizational structure corresponding to the Cache Way.

[0251] In one implementation, the cache space can be located in SRAM on the cache. In fact, the cache space can also be set up based on other types of memory, and the embodiments of this application do not limit the specific type of memory where the cache space is located.

[0252] Figure 11 This is a schematic diagram illustrating a scenario where the cache controller provided in this application caches the first write request to the cache space.

[0253] like Figure 11 As shown, in one implementation, the cache controller 1022 sends a first read request and a first write request to the first level cache 1031 based on the first on-chip bus 1051. When the first read request and the first write request arrive at the first level cache 1031, the cache controller 1022 caches the first write request into the cache space in the first level cache 1031.

[0254] In this way, the cache controller 1022 can process only the first read request, and the electronic device can provide more bus bandwidth for the first read request, which can improve the return latency of the first read request and thus improve the system performance of the electronic device.

[0255] It should be noted that the above embodiment is only illustrated by setting the cache space in the first-level cache 1031. In reality, the cache space can be set in the first-level cache 1031, the second-level cache, and the third-level cache (the second-level cache and the third-level cache are not in the same location). Figure 11 As shown in the figure, and for details, please refer to at least one of the above embodiments. The specific setting method of the cache space is not limited in the embodiments of this application.

[0256] In one implementation, the size of the cache space is adjustable, for example, based on a first bandwidth and a cache hit rate.

[0257] Since the first write request has been cached in the cache space in the aforementioned steps, if the first write request occupies a large space in the cache, it will lead to a decrease in the cache hit rate, which will also affect the system of the electronic device. Therefore, the size of the cache space needs to be dynamically adjusted adaptively to match the current scenario of the electronic device.

[0258] Figure 12 This is a flowchart of the cache space adjustment method provided in the embodiments of this application;

[0259] like Figure 12 As shown, in one implementation, the method for adjusting the cache space may include the following steps S001-S003.

[0260] In step S001, when the electronic device determines that the first bandwidth is greater than or equal to the second bandwidth threshold, the subsystem controls the cache to increase the size of the cache space.

[0261] The second bandwidth threshold is greater than or equal to the first bandwidth threshold.

[0262] In one implementation, when the first monitor determines that the first bandwidth is greater than or equal to the second bandwidth threshold, the cache controller controls the cache to increase the size of the cache space.

[0263] In this embodiment, when the first monitor determines that the first bandwidth has increased significantly, it indicates that the bus load corresponding to the main memory is too heavy. In this way, the return latency of the first read request can be improved by increasing the size of the cache space to store more first write requests.

[0264] It should be noted that since the electronic device is determined to be in a concurrent heavy-load scenario when the first bandwidth is greater than or equal to the first bandwidth threshold, in one implementation, the electronic device can immediately adjust the size of the cache space after entering the concurrent heavy-load scenario. That is, the second bandwidth threshold is set to be equal to the first bandwidth threshold, so that the size of the cache space is adjusted when the first bandwidth is greater than or equal to the second bandwidth threshold. In another implementation, the electronic device can also adjust the size of the cache space after entering the concurrent heavy-load scenario, and when the first bandwidth further increases to a certain extent. That is, the second bandwidth threshold is set to be greater than the first bandwidth threshold, so that the size of the cache space is adjusted when the first bandwidth is greater than or equal to the second bandwidth threshold.

[0265] The embodiments of this application do not limit the specific value of the second bandwidth threshold, and the specific value of the second bandwidth threshold can be set according to the actual situation.

[0266] In step S002, when the electronic device determines that the cache hit rate is less than the first hit rate threshold and greater than or equal to the second hit rate threshold, the subsystem controls the cache to stop increasing the size of the cache space.

[0267] In one implementation, if the second monitor determines that the cache hit rate is less than a first hit rate threshold and greater than or equal to a second hit rate threshold, the cache controller controls the cache to stop increasing the size of the cache space.

[0268] The concurrent heavy-load scenario includes at least one target scenario, each with a corresponding first hit rate threshold and a corresponding second hit rate threshold. By setting different hit rate thresholds for different scenarios, it is possible to more accurately determine whether the performance and power consumption of the electronic device are affected by the cache space in the current scenario, thereby allowing for appropriate adjustment of the cache space size.

[0269] In this embodiment, when the second monitor determines that the cache hit rate is less than the first hit rate threshold and greater than or equal to the second hit rate threshold, it can determine that if the cache space continues to increase, it will affect the system performance of the electronic device. Therefore, the second monitor can notify the cache controller to stop increasing the size of the cache space in order to ensure the overall performance of the electronic device.

[0270] In step S003, when the electronic device determines that the cache hit rate is less than the second hit rate threshold, the subsystem controls the cache to reduce the cache space size.

[0271] In one implementation, if the second monitor determines that the cache hit rate is less than a second hit rate threshold, the cache controller controls the cache to reduce the cache space size.

[0272] In this embodiment, when the second monitor determines that the cache hit rate is less than the second hit rate threshold, it can determine that the performance of the electronic device is being further affected. In this way, the second monitor can notify the cache controller to reduce the size of the cache space to improve the cache hit rate and thus ensure the overall performance of the electronic device.

[0273] In this way, the adjusted cache size can ensure the overall performance of the electronic device.

[0274] In step S107, if the first write request is cached in the cache space, the subsystem executes the first read request to obtain the data corresponding to the first read request.

[0275] Further explanation is based on the foregoing embodiments, such as... Figure 11 As shown, if the first write request is cached in the cache space, the cache controller 1022 can execute the first read request.

[0276] Specifically, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first read request is located in the first-level cache 1031. If the target data corresponding to the target memory address in the first read request is located in the first-level cache 1031, the cache controller 1022 can read the target data corresponding to the first read request from the first-level cache 1031. If the target data corresponding to the target memory address in the first read request is not located in the first-level cache 1031, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first read request is located in the second-level cache 1032. If the target data corresponding to the target memory address in the first read request is located in the second-level cache 1032, the cache controller 1022 can read the target data corresponding to the first read request from the second-level cache 1032. If the target data corresponding to the target memory address in the first read request is not located in the L2 cache 1032, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first read request is located in the L3 cache 1033. If the target data corresponding to the target memory address in the first read request is located in the L3 cache 1033, the cache controller 1022 can read the target data corresponding to the first read request from the L3 cache 1033. If the target data corresponding to the target memory address in the first read request is not located in the L3 cache 1033, the cache controller 1022 can send the first read request to the DDR controller 1023, so that the DDR controller 1023 can determine whether the target data corresponding to the target memory address in the first read request is located in the DDR memory 104, so that the DDR controller 1023 can obtain the target data corresponding to the first read request from the DDR memory 104.

[0277] It should be noted here that... Figure 11 The example provided only illustrates the case where the first read request misses in the L1 cache 1031, L2 cache 1032, and L3 cache 1033, but only hits in the DDR memory 104. In reality, the first read request can hit in any level of cache, and this application embodiment does not limit this.

[0278] Based on the above process, in concurrent scenarios, electronic devices cache the first write request to the cache space and execute the first read request, thereby increasing the access priority of the first read request, reducing the return latency of the read request, and improving the system performance of the electronic devices.

[0279] In one implementation, step S106 is followed by step S108.

[0280] In step S108, when the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space in order to execute the first write request.

[0281] Figure 13 This is a schematic diagram illustrating a scenario where the cache space is released for the first write request, as provided in an embodiment of this application.

[0282] like Figure 13 As shown, further based on the aforementioned embodiment, when the first monitor determines that the first bandwidth is less than the second bandwidth threshold, the cache controller 1022 releases the first write request cached in the cache space to execute the first write request. Specifically, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first write request is located in the first-level cache 1031. If the target data corresponding to the target memory address in the first write request is located in the first-level cache 1031, the cache controller 1022 can write the target data corresponding to the first write request into the first-level cache 1031. If the target data corresponding to the target memory address in the first write request is not located in the first-level cache 1031, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first write request is located in the second-level cache 1032. If the target data corresponding to the target memory address in the first write request is located in the second-level cache 1032, the cache controller 1022 can write the target data corresponding to the first write request into the second-level cache 1032. If the target data corresponding to the target memory address in the first write request is not located in the L2 cache 1032, the cache controller 1022 can determine whether the target data corresponding to the target memory address in the first write request is located in the L3 cache 1033. If the target data corresponding to the target memory address in the first write request is located in the L3 cache 1033, the cache controller 1022 can write the target data corresponding to the first write request into the L3 cache 1033. If the target data corresponding to the target memory address in the first write request is not located in the L3 cache 1033, the cache controller 1022 can send the first write request to the DDR controller 1023, so that the DDR controller 1023 can determine whether the target data corresponding to the target memory address in the first write request is located in the DDR memory 104, so that the DDR controller 1023 can write the target data corresponding to the first write request into the DDR memory 104.

[0283] It should be noted here that... Figure 13 The example provided only illustrates the case where the first write request misses in the first-level cache 1031, the second-level cache 1032, and the third-level cache 1033, but only hits in the DDR memory 104. In reality, the first write request can hit in any level of cache, and this application embodiment does not limit this.

[0284] Based on the above process, when the bus bandwidth is idle, the electronic device can release the first write request at once, which can effectively improve the storage efficiency of the DDR memory 104 and reduce the latency of the DDR memory 104 during the read / write mode switching process. In this way, the overall performance of the DDR memory 104 can be improved.

[0285] In one implementation, step S106 is followed by step S109.

[0286] In step S109, if the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space in order to execute the first write request.

[0287] Further based on the foregoing embodiments, when the cache controller 1022 determines that the cache space is saturated, it releases the first write request cached in the cache space in order to execute the first write request.

[0288] The method of executing the first write request in step S109 can be referred to the aforementioned step S108, and will not be repeated in this embodiment.

[0289] In one implementation, step S106 is followed by step S110.

[0290] In step S110, if the second read request in the read request reaches the first cache and the first write request has not been released in the cache space, and if the memory address corresponding to the second read request is the same as the memory address corresponding to the first write request, then the subsystem obtains the data corresponding to the first write request that the second read request hits in the first cache.

[0291] In this way, the second read request can quickly read the data written to the cache space by the first write request, reducing the return latency of the second read request. This embodiment can optimize the instruction sequence of read-after-write.

[0292] Figure 14 This is the second flowchart of the data request method provided in the embodiments of this application.

[0293] like Figure 14 As shown, the data request method provided in this application embodiment may include the following steps S201-S203.

[0294] In step S201, when the electronic device is under concurrent heavy load, the subsystem sends at least one read request to the first cache based on the first channel in the bus, and the subsystem sends at least one write request to the cache based on the second channel in the bus, wherein the first channel and the second channel are independent of each other.

[0295] In step S202, when the first read request in the read request and the first write request in the write request arrive at the cache, the subsystem caches the first write request to the cache space corresponding to the preset cache path number in the cache, wherein the size of the cache space is adjustable.

[0296] In step S203, if the first write request is cached in the cache space, the subsystem executes the first read request to obtain the data corresponding to the first read request.

[0297] The method provided in this application embodiment, in a scenario where the electronic device is under concurrent heavy load, if the subsystem simultaneously sends read requests and write requests to the cache based on two independent channels in the bus, the subsystem caches the write requests received by the cache to the cache space corresponding to the preset number of cache paths in the cache, and executes the first read request. In this way, this application improves the access priority of read requests, reduces the return latency of read requests, and improves the system performance of the electronic device.

[0298] The foregoing primarily describes the solutions provided by the embodiments of this application from the perspective of electronic devices. It is understood that, in order to achieve the aforementioned functions, the electronic device includes corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, based on the data request method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by software-driven hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0299] This application embodiment can divide the above-described electronic device into functional modules or functional units according to the above method examples. For example, each function can be divided into its own functional modules or functional units, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module or functional unit. The module or unit division in this application embodiment is illustrative and represents only one logical functional division; other division methods may be used in actual implementation.

[0300] Figure 15 This is a schematic diagram of the structure of the data request device provided in the embodiments of this application.

[0301] like Figure 15As shown, the data request device 200 provided in this application embodiment can be applied to the electronic device 100 in the above embodiments. The data request device 200 may include a display screen 201, a memory 202, a subsystem 203, and a communication module 204. These devices can be connected via one or more communication buses 205. The display screen 201 may include a display panel 2011 and a touch sensor 2012. The display panel 2011 displays images, and the touch sensor 2012 transmits detected touch operations to the application processor to determine the touch event type. The display panel 2011 provides visual output related to the touch operation. The subsystem 203 may include one or more processing units. For example, the subsystem 203 may include an application processor, a modem processor, a graphics processor, a controller, a video codec, a digital signal processor, a baseband processor, and / or a neural network processor. Different processing units may be independent devices or integrated into one or more processors. The memory 202 is connected to the subsystem 203 via a bus. The memory 202 is used to store various software programs and / or computer instructions. The memory 202 may include volatile memory and / or non-volatile memory, specifically including, for example, cache 2021 and main memory 2022. The main memory 2022 is, for example, DDR memory. When the subsystem executes computer instructions, the data request device 200 can perform various functions or steps in the above method embodiments.

[0302] Specifically, subsystem 203 is configured to: send at least one read request to cache 2021 via a first channel in the bus, and send at least one write request to cache 2021 via a second channel in the bus, wherein the first and second channels are independent of each other. Subsystem 203 is further configured to: cache the first write request in cache 2021 to a cache space corresponding to a preset cache path number in cache 2021 when the first read request and the first write request arrive at cache 2021, wherein the size of the cache space is adjustable. Subsystem 203 is further configured to: execute the first read request to retrieve the data corresponding to the first read request from main memory 2022 when the first write request is cached in the cache space.

[0303] The apparatus provided in this application provides that, in a scenario where the electronic device is under concurrent heavy load, if the subsystem simultaneously sends read requests and write requests to the cache based on two independent channels in the bus, the subsystem caches the write requests received by the cache to the cache space corresponding to the preset number of cache paths in the cache, and executes the first read request. In this way, this application improves the access priority of read requests, reduces the return latency of read requests, and improves the system performance of the electronic device.

[0304] This application embodiment also provides another data request device, which can be applied to the electronic device in the above embodiments. The electronic device includes a subsystem and a cache, connected via a bus. The device includes: a sending module, configured to send at least one read request to the cache via a first channel in the bus and at least one write request to the cache via a second channel in the bus when the electronic device is under concurrent heavy load; wherein the first and second channels are independent of each other; a caching module, configured to cache the first write request to a cache space corresponding to a preset number of cache paths when the first read request and the first write request arrive at the cache; wherein the size of the cache space is adjustable; and an acquisition module, configured to execute the first read request to acquire the data corresponding to the first read request when the first write request is cached in the cache space.

[0305] This application also provides an electronic device, which includes a subsystem and a memory coupled together. The memory stores program instructions, and when the program instructions are executed by the subsystem, the subsystem performs the various functions or steps as described in the above method embodiments.

[0306] Figure 16 This is a schematic diagram of the chip system provided in the embodiments of this application.

[0307] like Figure 16 As shown, this application embodiment also provides a chip system 300, such as a SoC, which includes at least one processor 301 and at least one interface circuit 302. The processor 301 and the interface circuit 302 can be interconnected via lines. For example, the interface circuit 302 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 302 can be used to send signals to other devices (e.g., the processor 301 or the touchscreen of an electronic device). Exemplarily, the interface circuit 302 can read instructions stored in the memory and send the instructions to the processor 301. When the instructions are executed by the processor 301, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, which are not specifically limited in this application embodiment.

[0308] This application also provides a computer-readable storage medium including computer instructions that, when executed on the electronic device, cause the electronic device to perform various functions or steps performed by the electronic device in the above method embodiments.

[0309] This application also provides a computer program product that, when run on an electronic device, causes the electronic device to perform various functions or steps performed by the electronic device in the above method embodiments.

[0310] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0311] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0312] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0313] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0314] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0315] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data request method, characterized in that, Applied to an electronic device, the electronic device including a subsystem and a first buffer, the subsystem and the first buffer being connected via a bus, the method includes: When the electronic device is under concurrent heavy load, the subsystem sends at least one read request to the first cache based on the first channel in the bus, and the subsystem sends at least one write request to the first cache based on the second channel in the bus, wherein the first channel and the second channel are independent of each other; When the first read request in the read request and the first write request in the write request arrive at the first cache, the subsystem caches the first write request in the cache space corresponding to the preset cache path number in the first cache, wherein the size of the cache space is adjustable; If the first write request is cached in the cache space, the subsystem executes the first read request to obtain the data corresponding to the first read request.

2. The data request method according to claim 1, characterized in that, The electronic device further includes main memory. The subsystem, the first cache, and the main memory are connected via the bus. When the first write request is cached in the cache space, the subsystem executes the first read request to obtain the data corresponding to the first read request, including: When the first write request is cached in the cache space, the subsystem executes the first read request to retrieve the corresponding data from the main memory.

3. The data request method according to claim 2, characterized in that, Before the subsystem sends at least one read request to the first cache based on the first channel of the bus, and before the subsystem sends at least one write request to the first cache based on the second channel of the bus, when the electronic device is under concurrent heavy load, the method further includes: The electronic device monitors the first bandwidth and the cache hit rate corresponding to the first cache, and adjusts the size of the cache space based on the first bandwidth and the cache hit rate. The first bandwidth includes the amount of data accessed to the main memory per unit time, or the amount of data accessed to the main memory controller corresponding to the main memory per unit time. The cache hit rate is the proportion of the number of times the read requests and write requests sent by the subsystem to the first cache hit the cache in the cache to the total number of requests.

4. The data request method according to claim 3, characterized in that, Before the subsystem sends at least one read request to the first cache based on the first channel of the bus, and before the subsystem sends at least one write request to the first cache based on the second channel of the bus, when the electronic device is under concurrent heavy load, the method further includes: When the electronic device determines that the first bandwidth is greater than a preset first bandwidth threshold, it determines that it is in the concurrent heavy load scenario.

5. The data request method according to claim 4, characterized in that, The electronic device monitors the first bandwidth and the cache hit rate corresponding to the first cache, and adjusts the size of the cache space based on the first bandwidth and the cache hit rate, including: When the electronic device determines that the first bandwidth is greater than or equal to a preset second bandwidth threshold, the subsystem controls the first cache to increase the size of the cache space, wherein the second bandwidth threshold is greater than or equal to the first bandwidth threshold; When the electronic device determines that the cache hit rate is less than a first hit rate threshold and greater than or equal to a second hit rate threshold, the subsystem controls the first cache to stop increasing the size of the cache space. When the electronic device determines that the cache hit rate is less than the second hit rate threshold, the subsystem controls the first cache to reduce the cache space size.

6. The data request method according to claim 5, characterized in that, The concurrent heavy-load scenario includes at least one target scenario, and each target scenario has a corresponding first hit rate threshold and a corresponding second hit rate threshold.

7. The data request method according to claim 5, characterized in that, When the first write request is cached in the cache space, after the subsystem executes the first read request to obtain the data corresponding to the first read request, the method further includes: When the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space in order to execute the first write request.

8. The data request method according to claim 7, characterized in that, When the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request, including: When the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space, executes the first write request, and writes the first write request into the main memory.

9. The data request method according to claim 8, characterized in that, When the first write request is cached in the cache space, after the subsystem executes the first read request to obtain the data corresponding to the first read request, the method further includes: When the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space in order to execute the first write request.

10. The data request method according to claim 9, characterized in that, When the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space to execute the first write request, including: When the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space, executes the first write request, and writes the first write request into the main memory.

11. The data request method according to claim 1, characterized in that, After the subsystem caches the first write request to the cache space corresponding to the preset cache path number in the first cache, it also includes: If the second read request in the read request reaches the first cache, and the first write request has not been released in the cache space, and if the memory address corresponding to the second read request is the same as the memory address corresponding to the first write request, then the subsystem obtains the data corresponding to the first write request that the second read request hits in the first cache.

12. The data request method according to claim 10, characterized in that, The subsystem includes a cache controller. When the electronic device is under concurrent heavy load, the subsystem sends at least one read request to the first cache via a first channel in the bus, and the subsystem sends at least one write request to the first cache via a second channel in the bus, including: When the electronic device is under concurrent heavy load, the cache controller sends at least one read request to the first cache based on the first channel, and the cache controller sends at least one write request to the first cache based on the second channel.

13. The data request method according to claim 12, characterized in that, The subsystem executes the first read request to obtain the data corresponding to the first read request, including: The cache controller executes the first read request, and if the first read request hits the first cache, it retrieves the data corresponding to the first read request from the first cache.

14. The data request method according to claim 13, characterized in that, The subsystem further includes the main memory controller, which executes the first read request to obtain data corresponding to the first read request from the main memory, including: The cache controller executes the first read request, and if the first read request does not hit the first cache, it sends the first read request to the main memory controller; The main memory controller executes the first read request to retrieve the data corresponding to the first read request from the main memory.

15. The data request method according to claim 14, characterized in that, The electronic device monitors the first bandwidth and the cache hit rate corresponding to the first cache, including: The subsystem obtains at least one of the following through a built-in performance counter: the amount of data accessed to the main memory, the amount of data accessed to the main memory controller, the number of hits in the first cache, and the number of misses in the first cache. The subsystem obtains the amount of data accessed to the main memory or the amount of data accessed to the main memory controller from the performance counter based on the built-in first monitor to calculate the first bandwidth. The subsystem also obtains the number of cache hits and the number of cache misses from the performance counter based on the built-in second monitor to calculate the cache hit rate. The first monitor includes a cache bandwidth monitor, and the second monitor includes a cache utilization monitor.

16. The data request method according to claim 15, characterized in that, When the electronic device determines that the first bandwidth is greater than or equal to a preset second bandwidth threshold, the subsystem controls the first cache to increase the size of the cache space, including: When the first monitor determines that the first bandwidth is greater than or equal to the second bandwidth threshold, the cache controller controls the first cache to increase the size of the cache space.

17. The data request method according to claim 15, characterized in that, When the electronic device determines that the cache hit rate is less than a first hit rate threshold and greater than or equal to a second hit rate threshold, the subsystem controls the first cache to stop increasing the size of the cache space, including: If the second monitor determines that the cache hit rate is less than the first hit rate threshold and greater than or equal to the second hit rate threshold, the cache controller controls the first cache to stop increasing the size of the cache space.

18. The data request method according to claim 15, characterized in that, When the electronic device determines that the cache hit rate is less than the second hit rate threshold, the subsystem controls the first cache to reduce the cache space size, including: If the second monitor determines that the cache hit rate is less than the second hit rate threshold, the cache controller controls the first cache to reduce the size of the cache space.

19. The data request method according to claim 15, characterized in that, When the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space to execute the first write request, including: When the first monitor determines that the first bandwidth is less than the second bandwidth threshold, the cache controller releases the first write request cached in the cache space to execute the first write request, and if the first write request hits the first cache, writes the data corresponding to the first write request into the first cache.

20. The data request method according to claim 19, characterized in that, When the electronic device determines that the first bandwidth is less than the second bandwidth threshold, the subsystem releases the first write request cached in the cache space, executes the first write request, and writes the first write request into the main memory, including: If the first monitor determines that the first bandwidth is less than the second bandwidth threshold, the cache controller releases the first write request cached in the cache space to execute the first write request, and if the first write request does not hit the first cache, it sends the first write request to the main memory controller. The main memory controller executes the first write request to write the data corresponding to the first write request into the main memory.

21. The data request method according to claim 15, characterized in that, When the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space to execute the first write request, including: When the cache controller determines that the cache space is saturated, it releases the first write request cached in the cache space to execute the first write request, and if the first write request hits the first cache, it writes the data corresponding to the first write request into the first cache.

22. The data request method according to claim 21, characterized in that, When the subsystem determines that the cache space is saturated, the subsystem releases the first write request cached in the cache space, executes the first write request, and writes the first write request into the main memory, including: When the cache controller determines that the cache space is saturated, the cache controller releases the first write request cached in the cache space to execute the first write request, and if the first write request does not hit the first cache, the cache controller sends the first write request to the main memory controller. The main memory controller executes the first write request to write the data corresponding to the first write request into the main memory.

23. The data request method according to claim 1, characterized in that, The cache space is located in the static random access memory (SRAM) on the first cache.

24. The data request method according to claim 1, characterized in that, The bus protocol corresponding to the bus includes at least one of the Advanced Extensible Interface (AXI) protocol and the Consistent Hub Interface (CHI) protocol.

25. A data request device, characterized in that, It includes a subsystem and a first cache, which are connected via a bus; The subsystem is configured to: send at least one read request to the first cache based on a first channel in the bus when the electronic device is under concurrent heavy load, and send at least one write request to the first cache based on a second channel in the bus, wherein the first channel and the second channel are independent of each other; The subsystem is further configured to: when the first read request in the read request and the first write request in the write request arrive at the first cache, cache the first write request to the cache space corresponding to a preset cache path number in the first cache, wherein the size of the cache space is adjustable; The subsystem is also configured to: if the first write request is cached in the cache space, execute the first read request to obtain the data corresponding to the first read request.

26. The data request device according to claim 25, characterized in that, It also includes main memory, and the subsystem, the first cache and the main memory are connected via the bus; The subsystem is also configured to: if the first write request is cached in the cache space, execute the first read request to retrieve the data corresponding to the first read request from the main memory.

27. An electronic device, characterized in that, It includes: a subsystem and a memory, the subsystem and the memory being coupled together, the memory storing program instructions that, when executed by the subsystem, cause the subsystem to perform the data request method as described in any one of claims 1-24.

28. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the data request method as described in any one of claims 1-24.

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