Memory random access verification method and device

Abstract

This application provides a method and apparatus for verifying random access to memory. The method includes: exhaustively enumerating combinations of access addresses, access granularities, and access types corresponding to the target memory to obtain multiple access triples; for each access triple, filling in fields according to a preset data structure to obtain at least one access instance, wherein the fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask, and the access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read / write operation; and randomly rearranging multiple access instances according to test requirements to obtain a target access sequence. This application enables the rapid generation of target access sequences that meet test requirements, balancing access coverage completeness with execution randomness.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a method and apparatus for verifying random access to memory. Background Technology

[0002] As the integration level of System-on-Chip (SoC) chips continues to increase, the interaction between embedded software and hardware is becoming increasingly complex. Among these, memory (such as RAM, ROM, Flash, etc.) is a core component for data storage, and the correctness of its access directly affects the stability of the system. Therefore, during the chip verification phase, it is necessary to thoroughly test the memory access behavior to discover potential functional defects.

[0003] In existing technologies, sequential access, fixed access granularity, or manually writing a small number of targeted read and write test cases are often used to cover conventional read and write scenarios. However, they are insufficient for complex scenarios such as non-aligned access, mixed access with different access granularities, cross-read and write of the same address region, and read data depending on multiple historical write operations under out-of-order execution conditions. It is difficult to simultaneously ensure the completeness of access coverage and the randomness of execution, resulting in complex defects that are not easily exposed. Summary of the Invention

[0004] This application provides a memory random access verification method and apparatus, which can solve the technical problem that existing memory verification methods cannot simultaneously take into account access coverage completeness and execution randomness.

[0005] In a first aspect, embodiments of this application provide a memory random access verification method, the memory random access verification method comprising: By exhaustively listing the combinations of access address, access granularity and access type corresponding to the target memory, multiple access triplets are obtained; For each access triple, at least one access instance is obtained by filling in the fields according to the preset data structure. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read and write operation. Based on the testing requirements, multiple access instances are selected and randomly rearranged to obtain the target access sequence.

[0006] Furthermore, in one embodiment, in the target access sequence, access instances of access type read are denoted as target read access instances, and access instances of access type write are denoted as target write access instances. Following the step of randomly rearranging multiple access instances according to test requirements to obtain the target access sequence, the method further includes: Determine the expected read value for each target read access instance; Perform read and write operations on the target memory based on the target access sequence, and obtain the read return value of each target read access instance; The expected read value and the read return value of each target read access instance are compared to obtain the verification result.

[0007] Further, in one embodiment, the step of determining the read expectation value for each target read access instance includes: For each target read access instance, determine the expected read value of each target data unit in the read access instance, and combine the expected read values ​​of all target data units in address order to obtain the expected read value of the read access instance. The step of determining the expected read value for each target data unit in the read access instance includes: For each target data unit in this read access instance: Check if the data unit has a first write access instance, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit; If a first write access instance exists, the read expectation value of that data unit is determined to be the write expectation value of the target data unit at the same address of the nearest first write access instance; If no first write access instance exists, the expected read value of that data unit is determined as the initial value of the target memory at the same address.

[0008] Furthermore, in one embodiment, a target read access instance where the expected read value is not equal to the read return value is denoted as an erroneous read access instance, and a target data unit where the expected read value is not equal to the read return value is denoted as an erroneous data unit; After the step of comparing the expected read value and the return read value of each target read access instance to obtain the verification result, the method further includes: If any erroneous read access instance satisfies the first and second judgment conditions, then the error type of the erroneous read access instance is determined to be a data concatenation error. If any erroneous read access instance satisfies the first judgment condition but does not satisfy the second judgment condition, then the error type of the erroneous read access instance is determined to be an unaligned access processing error. If any erroneous read access instance does not satisfy the first judgment condition, but satisfies the third, fourth, and fifth judgment conditions, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. If any erroneous read access instance does not satisfy the first and fifth judgment conditions, but satisfies the third and fourth judgment conditions, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and fourth judgment conditions, but meets the third and sixth judgment conditions, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, fourth, and sixth judgment conditions, but satisfies the third judgment condition, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and third judgment conditions, but meets the sixth judgment condition, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, third, and sixth judgment conditions, but satisfies the seventh judgment condition, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. The first condition is: the read access instance is an unaligned access, and any second write access instance of the read access instance is an unaligned access, wherein the second write access instance is a target write access instance located before the read access instance, and has a target data unit with the same address as the read access instance; The second judgment condition is: the address of any erroneous data unit of the read access instance is the target aligned address, and the read return value of the erroneous data unit is equal to the write expectation value of any unrequested data unit of the second write access instance. Here, the target aligned address is within the access range of the read access instance, the target aligned address is divisible by the data bus width, the starting point of the access range is the access address, the length is the access granularity, the unrequested data unit is any target data unit of the second write access instance, and the read access instance does not have a target data unit with the same address as the unrequested data unit. The third condition is: any target data unit of the read access instance is not an erroneous data unit; The fourth condition is: the nearest first write access instance to any erroneous data unit of the read access instance has a non-requested data unit, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit. The fifth condition is: whether the return value of any erroneous data unit of the read access instance is equal to the expected write value of the target data unit at the same address of any non-nearest first write access instance; The sixth condition is: the read access instance has a second write access instance with multiple access granularities; The seventh condition is: the read return value of each erroneous data unit of the read access instance is equal to the write expectation value of the target data unit at the same address of any second write access instance that is not the most recent one.

[0009] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding address segment group. The access instances in the candidate instance set are selected according to the test requirements. Each address segment group is used to summarize different access instances whose access addresses fall within the same address range. In each iteration, an access instance from an address segment group with a high access weight is selected first and added to the end of the target access sequence. The access weight is negatively correlated with the frequency of the address segment group within the sliding window. The sliding window is used to record the address segment groups to which a preset number of access instances recently added to the target access sequence belong.

[0010] Furthermore, in one embodiment, the random rearrangement operation includes: For each access instance in the candidate instance set, an attribute vector is constructed based on the access granularity and access type of that access instance. The access instances in the candidate instance set are selected according to the test requirements. In each iteration, the access instance whose attribute vector is farthest from the attribute vector of the last access instance is selected and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0011] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding co-address access chain. The access instances in the candidate instance set are selected according to the test requirements, and each co-address access chain is used to aggregate different access instances with the same access address. In each iteration, the target spacing range of the co-address access chain to which the last access instance belongs is determined, and an access instance is randomly selected from the co-address access chains within the target spacing range and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0012] Furthermore, in one embodiment, the random rearrangement operation includes: A target access sequence is randomly generated based on the access instances in the candidate instance set, wherein the access instances in the candidate instance set are selected according to the test requirements; In each iteration, two access elements are randomly selected from the target access sequence for position swapping. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is closer to the preset proportion target than before the swap, the position swap is accepted. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is further away from the preset proportion target than before the swap, the position swap is accepted with decreasing probability. Among them, the dependencies include write-after-read, read-after-write, and write-after-write.

[0013] Furthermore, in one embodiment, the fields of the preset data structure also include an alignment identifier, which is used to mark whether the access instance is an aligned access.

[0014] Secondly, embodiments of this application also provide a memory random access verification device, the memory random access verification device comprising: The triplet construction module is used to exhaustively enumerate the combinations of access address, access granularity and access type corresponding to the target memory to obtain multiple access triplets; The instantiation module is used to fill in the fields of a preset data structure for each access triplet to obtain at least one basic access instance. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read and write operation. The sequence building module is used to select multiple basic access instances and randomly rearrange them to obtain the target access sequence according to the test requirements.

[0015] In this application, the combinations of access addresses, access granularities, and access types corresponding to the target memory are exhaustively enumerated to obtain multiple access triples. For each access triple, at least one access instance is obtained by filling in the fields according to a preset data structure. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read / write operation. Multiple access instances are selected and randomly rearranged according to test requirements to obtain the target access sequence. This application can quickly generate target access sequences that meet test requirements, balancing access coverage completeness and execution randomness. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a memory random access verification method in one embodiment of this application; Figure 2 This is a schematic diagram of the functional modules of a memory random access verification device in one embodiment of this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] In a first aspect, embodiments of this application provide a method for verifying random access to a memory.

[0020] Figure 1 A flowchart illustrating a memory random access verification method according to an embodiment of this application is shown.

[0021] Reference Figure 1 In one embodiment, the memory random access verification method includes the following steps: S1. Exhaustively enumerate the combinations of access address, access granularity and access type corresponding to the target memory to obtain multiple access triplets.

[0022] Specifically, the target memory refers to the memory to be verified, the access address corresponding to the target memory includes every access address in the target memory address range, the access granularity corresponding to the target memory includes every access granularity supported by the target memory, and the access type includes read access and write access.

[0023] For example, M access addresses and N access granularities can generate M×N "address-granularity" combinations, which, when combined with read access and write access respectively, can generate 2×M×N access triples.

[0024] In this embodiment, the access triples are obtained by exhaustive search, which theoretically ensures that all possible access scenarios (including regular alignment, non-alignment, mixed granularity, etc.) exist in the basic pool and can be selected as needed.

[0025] S2. For each access triple, fill in the fields according to the preset data structure to obtain at least one access instance. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read / write operation.

[0026] Specifically, the access address, access granularity, and access type of the access triple can be directly filled into the corresponding fields in the preset data structure. For read access, the data to be written is empty; for write access, the data to be written can be randomly generated or calculated according to rules.

[0027] The access range can be determined based on the access address and access granularity. The starting point of the access range is the access address, and the length is the access granularity. However, not every access requires reading or writing all data units within the access range. In this embodiment, a target unit mask is also set to combine the access address and access granularity to determine the address of the target data unit involved in the read / write operation.

[0028] Optionally, the target unit mask is defined at the program level, based on the access address, to identify multiple consecutive data units. When filling the target unit mask, there is no need to concern oneself with how the underlying bus is split. This facilitates the writing of access instances and also allows for verification of the functionality of the underlying bus splitting mechanism.

[0029] Alternatively, depending on the type of memory, the data unit can be a bit, byte, word, word block, etc.

[0030] Optionally, the fields of the preset data structure also include a sequence identifier. The value of the sequence identifier for each access instance is a globally unique sequence number, which facilitates quick retrieval.

[0031] Optionally, the fields of the preset data structure also include an alignment identifier. The alignment identifier is used to mark whether the access instance is an aligned access. In subsequent use cases, the access instance can be quickly determined to be an aligned access or a non-aligned access by directly reading the alignment identifier, without having to calculate based on the access address and access granularity (access whose access address is divisible by the access granularity is an aligned access, and access whose access address is not divisible by the access granularity is a non-aligned access).

[0032] S3. Select multiple access instances according to the test requirements and randomly rearrange them to obtain the target access sequence.

[0033] In this embodiment, an on-demand selection strategy is adopted, which directly selects instances that meet the current test requirements from the pre-built instance pool, thus avoiding the generation of invalid sequences and repeated attempts.

[0034] For example, first select a subset of access instances to form a minimum set of essential accesses to be tested. The goal is to cover all test dimension combinations with fewer access operations, without redundancy or omissions. This mainly includes: Minimal address coverage: For each independent access granularity, ensure that its aligned "starting address block" is represented. For example, for a 4-byte granularity, only one 4-byte aligned address needs to be covered; for a 2-byte granularity, two non-overlapping aligned 2-byte blocks need to be covered; for a 1-byte granularity, any byte address can be chosen. At the same time, an unaligned instance is explicitly included.

[0035] Completeness of access type and access granularity combination: For each selected "address-granularity" combination, both "read" and "write" operations are explicitly generated to ensure that no read-write combinations are omitted.

[0036] Overlap relationship construction: The selected addresses must be able to naturally form "full overlap" and "partial overlap" relationships. For example, choosing a base address such as 0x00, accesses of different granularities will intersect here, naturally forming partial / full coverage.

[0037] After obtaining the minimum set of mandatory tests, we increase the stress and randomness by adding "expanded access elements" while ensuring full coverage of boundary conditions. The expansion strategy is as follows: Boundary extension: Explicitly increases multi-granularity access near the physical beginning and end addresses of memory (such as 0x0C, 0x0F) to verify address decoding boundaries.

[0038] Unaligned traversal: Add multiple unaligned addresses (such as 0x03, 0x05) and combine them with different granularities to form an unaligned access chain that spans multiple levels of boundaries.

[0039] Highly overlapping "pressure" elements: Within an already covered address range (such as 0x00-0x03), write operations of different granularities and different data are added, deliberately creating complex RAW (read after write) and WAW (write after write) dependencies.

[0040] This approach of "first selecting the smallest set, then strategically expanding" avoids combinatorial explosion while ensuring the depth and breadth of validation.

[0041] Therefore, in this embodiment, the combinations of access addresses, access granularities, and access types corresponding to the target memory are exhaustively enumerated to obtain multiple access triples. For each access triple, at least one access instance is obtained by filling in the fields according to a preset data structure. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read / write operation. Multiple access instances are selected and randomly rearranged according to the test requirements to obtain the target access sequence. Through this embodiment, a target access sequence that meets the test requirements can be quickly generated, balancing access coverage completeness and execution randomness.

[0042] Furthermore, in one embodiment, in the target access sequence, access instances of access type read are denoted as target read access instances, and access instances of access type write are denoted as target write access instances. Following the step of randomly rearranging multiple access instances according to test requirements to obtain the target access sequence, the method further includes: Determine the expected read value for each target read access instance; Perform read and write operations on the target memory based on the target access sequence, and obtain the read return value of each target read access instance; The expected read value and the read return value of each target read access instance are compared to obtain the verification result.

[0043] In this embodiment, since each access instance includes fields such as access address, access granularity, access type, data to be written, and target unit mask, the expected read value of each target read access instance can be accurately calculated based on the field information and the order of the access instances in the target access sequence, serving as a verification basis.

[0044] Further, in one embodiment, the step of determining the read expectation value for each target read access instance includes: For each target read access instance, determine the expected read value of each target data unit in the read access instance, and combine the expected read values ​​of all target data units in address order to obtain the expected read value of the read access instance. The step of determining the expected read value for each target data unit in the read access instance includes: For each target data unit in this read access instance: Check if the data unit has a first write access instance, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit; If a first write access instance exists, the read expectation value of that data unit is determined to be the write expectation value of the target data unit at the same address of the nearest first write access instance; If no first write access instance exists, the expected read value of that data unit is determined as the initial value of the target memory at the same address.

[0045] Specifically, the write expectation value for each target data unit in a write access instance needs to be determined based on the endianness of the target memory and the data to be written.

[0046] For ease of explanation, the following description is provided byte-wise. In big-endian mode, the high byte of the data to be written is written to the low address, and the low byte is written to the high address. In little-endian mode, the low byte of the data to be written is written to the low address, and the high byte is written to the high address.

[0047] For example, assuming the 4 bytes of data to be written are 0x11223344, in little-endian mode, the expected write value of the target byte at address 0x00 is 0x44, the expected write value of the target byte at address 0x01 is 0x33, the expected write value of the target byte at address 0x02 is 0x22, and the expected write value of the target byte at address 0x03 is 0x11.

[0048] This embodiment provides a specific method for calculating the expected value of a read, which can quickly and accurately calculate the expected value of a read.

[0049] The following is a specific example to help understand the solution in this embodiment.

[0050] The target memory is a 16-byte RAM with an address range of 0x00 to 0x0F. Supported access granularities include 1-byte, 2-byte, and 4-byte access, and the data bus width is 4 bytes. The memory's initial data state is set to all bytes initialized to 0x00.

[0051] Assume that multiple access instances selected based on testing requirements are shown in Table 1.

[0052] Table 1. Multiple access instances selected based on testing requirements.

[0053] Therefore, E1 is an aligned write access, with the target byte address being 0x00, 0x01, 0x02, 0x03, and the corresponding expected write values ​​being 0x44, 0x33, 0x22, 0x11.

[0054] E2 is an aligned read access, with the target byte address being 0x00, 0x01, 0x02, or 0x03.

[0055] E3 is an aligned write access, with the target byte address being 0x01 and the corresponding write expectation value being 0xAA.

[0056] E4 is an aligned read access, with the target byte address being 0x00 or 0x01.

[0057] E5 is an aligned write access, with the target byte address being 0x02 and 0x03, and the corresponding write expectation values ​​being 0xEF and 0xBE.

[0058] E6 is an unaligned read access, with the target byte address being 0x01, 0x02, 0x03, or 0x04.

[0059] E7 is an aligned write access, with the target byte address being 0x00 or 0x02, and the corresponding write expectation values ​​being 0x88 or 0x66.

[0060] E8 is an aligned read access, with the target byte address being 0x00 or 0x02.

[0061] E9 is an aligned read access, with the target byte address being 0x00, 0x02, or 0x03.

[0062] E10 is an unaligned read access, with the target byte address being 0x01 or 0x03.

[0063] Assume the target access sequence after random rearrangement is as shown in Table 2.

[0064] Table 2 Target access sequence after random rearrangement

[0065] The above sequence is for illustrative purposes only. In practical applications, shuffling algorithms, random permutation algorithms, or index mapping methods can be used to form different target access sequences.

[0066] The memory state evolution after each target write access is as follows: After executing S1, the byte content at address 0x00 in RAM changes from 0x00 to 0x44, the byte content at address 0x01 changes from 0x00 to 0x33, the byte content at address 0x02 changes from 0x00 to 0x22, and the byte content at address 0x03 changes from 0x00 to 0x11. After executing S2, the byte content at address 0x00 in RAM changes from 0x44 to 0x88, and the byte content at address 0x02 changes from 0x22 to 0x66. After executing S3, the byte content at address 0x01 in RAM changes from 0x33 to 0xAA. After executing S6, the byte content at address 0x02 in RAM changes from 0x66 to 0xEF, and the byte content at address 0x03 changes from 0x11 to 0xBE.

[0067] The process of solving the expected read value of S4 is as follows: For the target byte at address 0x00, the expected read value is equal to the expected write value of the most recent first write access instance S2 (E7) at the target byte at address 0x00, which is 0x88. For the target byte at address 0x01, the expected read value is equal to the expected write value of the most recent first write access instance S3 (E3) at the target byte at address 0x01, which is 0xAA. The expected read value of S4 is 0xAA88 when the values ​​are combined according to the address order.

[0068] The process of solving the expected read value of S5 is as follows: For the target byte at address 0x01, the expected read value is equal to the expected write value of the most recent first write access instance S3 (E3) at the target byte at address 0x01, which is 0xAA. For the target byte at address 0x03, the expected read value is equal to the expected write value of the most recent first write access instance S2 (E1) at the target byte at address 0x03, which is 0x11. The expected read value of S5 is 0x11AA when the values ​​are combined according to the address order.

[0069] The process of solving the expected read value of S7 is as follows: For the target byte at address 0x00, the expected read value is equal to the expected write value of the most recent first write access instance S2 (E7) at the target byte at address 0x00, which is 0x88. For the target byte at address 0x02, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x02, which is 0xEF. The expected read value of S7 is 0xEF88 when the values ​​are combined according to the address order.

[0070] The process of calculating the expected read value of S8 is as follows: For the target byte at address 0x01, the expected read value is equal to the expected write value of the most recent first write access instance S3 (E3) at the target byte at address 0x01, which is 0xAA. For the target byte at address 0x02, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x02, which is 0xEF. For the target byte at address 0x03, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x03, which is 0xBE. For the target byte at address 0x04, the expected read value is equal to the initial value of the target memory at address 0x04, which is 0x00. The expected read value of S8 is 0x00BEEFAA, which is obtained by combining the values ​​according to the address order.

[0071] The process of calculating the expected read value of S9 is as follows: For the target byte at address 0x00, the expected read value is equal to the expected write value of the most recent first write access instance S2 (E7) at the target byte at address 0x00, which is 0x88. For the target byte at address 0x02, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x02, which is 0xEF. For the target byte at address 0x03, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x03, which is 0xBE. Combining these values ​​in address order, we obtain the expected read value of S8, which is 0xBEEF88.

[0072] The process of calculating the expected read value of S10 is as follows: For the target byte at address 0x00, the expected read value is equal to the expected write value of the most recent first write access instance S2 (E7) at the target byte at address 0x00, which is 0x88. For the target byte at address 0x01, the expected read value is equal to the expected write value of the most recent first write access instance S3 (E3) at the target byte at address 0x01, which is 0xAA. For the target byte at address 0x02, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x02, which is 0xEF. For the target byte at address 0x03, the expected read value is equal to the expected write value of the most recent first write access instance S6 (E5) at the target byte at address 0x03, which is 0xBE. Combining these values ​​in address order, we obtain the expected read value of S8, which is 0xBEEFAA88.

[0073] A target read access instance where the expected value and the return value are not equal is denoted as an erroneous read access instance, and a target data unit where the expected value and the return value are not equal is denoted as an erroneous data unit; Furthermore, in one embodiment, after the step of comparing the expected read value and the return read value of each target read access instance to obtain the verification result, the method further includes: If any erroneous read access instance satisfies the first and second judgment conditions, then the error type of the erroneous read access instance is determined to be a data concatenation error. If any erroneous read access instance satisfies the first judgment condition but does not satisfy the second judgment condition, then the error type of the erroneous read access instance is determined to be an unaligned access processing error. If any erroneous read access instance does not satisfy the first judgment condition, but satisfies the third, fourth, and fifth judgment conditions, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. If any erroneous read access instance does not satisfy the first and fifth judgment conditions, but satisfies the third and fourth judgment conditions, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and fourth judgment conditions, but meets the third and sixth judgment conditions, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, fourth, and sixth judgment conditions, but satisfies the third judgment condition, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and third judgment conditions, but meets the sixth judgment condition, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, third, and sixth judgment conditions, but satisfies the seventh judgment condition, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. The first condition is: the read access instance is an unaligned access, and any second write access instance of the read access instance is an unaligned access, wherein the second write access instance is a target write access instance located before the read access instance, and has a target data unit with the same address as the read access instance; The second judgment condition is: the address of any erroneous data unit of the read access instance is the target aligned address, and the read return value of the erroneous data unit is equal to the write expectation value of any unrequested data unit of the second write access instance. Here, the target aligned address is within the access range of the read access instance, the target aligned address is divisible by the data bus width, the starting point of the access range is the access address, the length is the access granularity, the unrequested data unit is any target data unit of the second write access instance, and the read access instance does not have a target data unit with the same address as the unrequested data unit. The third condition is: any target data unit of the read access instance is not an erroneous data unit; The fourth condition is: the nearest first write access instance to any erroneous data unit of the read access instance has a non-requested data unit, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit. The fifth condition is: whether the return value of any erroneous data unit of the read access instance is equal to the expected write value of the target data unit at the same address of any non-nearest first write access instance; The sixth condition is: the read access instance has a second write access instance with multiple access granularities; The seventh condition is: the read return value of each erroneous data unit of the read access instance is equal to the write expectation value of the target data unit at the same address of any second write access instance that is not the most recent one.

[0074] For example, the specific explanations of the various error types are as follows: Unaligned access handling error: If the current read or the write operation affecting it is marked as "unaligned" when the verification fails, this is highly likely to be the case. Specialized test cases can be designed consisting entirely of unaligned operations; once an error occurs, the cause is very easy to pinpoint.

[0075] Byte Overwrite Error: This error is characterized by "partial byte errors." Some bytes of the read data are correct, while others are incorrect. During comparison, not only is the overall result output for a match, but also a byte-by-byte comparison is performed. If only a few bytes are inconsistent, and the "most recent valid write" of these bytes was a partial overwrite write operation, then the error can be identified.

[0076] Error involving mixed access granularities: This error occurs when the address and granularity of a read access do not match the address and granularity of the write access it depends on. It can be checked to see if multiple access granularities are mixed within the dependency chain.

[0077] Write-after-read sequence dependency error: This error is characterized by "reading data that was previously written". When dynamically calculating the expected value, the source of each byte can be recorded as a write operation. If the check fails, compare it to the actual value to see which historical write operation wrote the value.

[0078] Data concatenation error: This is a more complex version of the "byte overwrite logic error." The characteristic remains the same: some bytes are correct, while others are incorrect. Locating the error requires considering the data path: if the bus interface processes data byte-by-byte, and the concatenation control malfunctions, it often occurs in unaligned multi-byte access.

[0079] Through this embodiment, after an erroneous read access instance is detected, the error can be quickly attributed based on whether the judgment conditions are met.

[0080] For example, the specific judgment steps are shown in Table 3.

[0081] Table 3 Error Attribution Judgment Steps

[0082] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding address segment group. The access instances in the candidate instance set are selected according to the test requirements. Each address segment group is used to summarize different access instances whose access addresses fall within the same address range. In each iteration, an access instance from an address segment group with a high access weight is selected first and added to the end of the target access sequence. The access weight is negatively correlated with the frequency of the address segment group within the sliding window. The sliding window is used to record the address segment groups to which a preset number of access instances recently added to the target access sequence belong.

[0083] In this embodiment, random rearrangement is combined with address distribution randomization to avoid "clustering" of accesses to the same address segment in the target access sequence, making address jumps sparse and discrete, approximating the characteristics of real applications.

[0084] For example, the formula for calculating access weight is: Access weight = 1 / (1 + frequency of occurrence of the address segment group within the sliding window).

[0085] Optionally, after selecting an address segment group, one of the access instances can be selected sequentially or randomly and added to the end of the target access sequence.

[0086] Furthermore, in one embodiment, the random rearrangement operation includes: For each access instance in the candidate instance set, an attribute vector is constructed based on the access granularity and access type of that access instance. The access instances in the candidate instance set are selected according to the test requirements. In each iteration, the access instance whose attribute vector is farthest from the attribute vector of the last access instance is selected and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0087] In this embodiment, random rearrangement is combined with access interval randomization to control the switching frequency of adjacent access instances in terms of access granularity and access type in the target access sequence, making attribute changes unpredictable.

[0088] For example, the attribute vector distance is calculated as follows: 1 point is awarded for different access granularities and 1 point is awarded for different access types.

[0089] Optionally, before the iteration begins, the attribute vector distance between every two accessed instances in the candidate instance set is pre-calculated for direct use during the iteration process.

[0090] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding co-address access chain. The access instances in the candidate instance set are selected according to the test requirements, and each co-address access chain is used to aggregate different access instances with the same access address. In each iteration, the target spacing range of the co-address access chain to which the last access instance belongs is determined, and an access instance is randomly selected from the co-address access chains within the target spacing range and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0091] In this embodiment, random rearrangement is combined with the randomization of the distance between consecutive accesses to the same address. For multiple accesses to the same address range, their logical distance in the target access sequence (other operands in the intermediate interval) is randomized to verify different data lifetimes.

[0092] It should be noted that when calculating the address spacing, the address range of the target memory is considered as a ring. For example, assuming the address range of the target memory is 0x00 to 0x0F, for address 0x0A, the target spacing range [1,8] corresponds to the address ranges 0x0B~0x0F and 0x00~0x02.

[0093] It should be noted that the number of access instances in different co-address access chains may be different. As the iteration progresses, in a certain round of iteration, there may be no other co-address access chains within the target spacing range of the co-address access chain to which the last access instance belongs. At this time, the iteration can be terminated directly, or the target spacing range can be dynamically adjusted until a co-address access chain that meets the requirements is found.

[0094] Optionally, after selecting a co-address access chain, other co-address access chains within the target spacing range are reselected with a 50% probability to avoid overly uniform spacing and to form a "randomized lifetime".

[0095] Furthermore, in one embodiment, the random rearrangement operation includes: A target access sequence is randomly generated based on the access instances in the candidate instance set, wherein the access instances in the candidate instance set are selected according to the test requirements; In each iteration, two access elements are randomly selected from the target access sequence for position swapping. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is closer to the preset proportion target than before the swap, the position swap is accepted. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is further away from the preset proportion target than before the swap, the position swap is accepted with decreasing probability. Among them, the dependencies include write-after-read, read-after-write, and write-after-write.

[0096] In this embodiment, random rearrangement is combined with dependency randomization factors to actively control and randomize the occurrence ratio and distribution pattern of various dependencies in the target access sequence.

[0097] For example, a maximum number of iterations, an initial acceptance probability, and a step size for decreasing the probability are preset. Each time it is determined that the swapped position will move away from the preset percentage target, the acceptance probability is reduced by the corresponding step size. The iteration stops when the maximum number of iterations is reached.

[0098] Optionally, before the iteration begins, a dependency tag set for each access instance is pre-created. This dependency tag set records other access instances that have potential dependencies on the access instance, allowing for rapid calculation of the actual proportion of various dependencies during the iteration process. That is, during the iteration process, it is not necessary to check the access scope and access type again; instead, the dependency tag set of each access instance within the preset statistical range can be directly viewed to check whether other access instances with potential dependencies are also within the preset statistical range.

[0099] It is understandable that schemes such as address distribution randomization, access interval randomization, randomization of access distance for consecutive identical addresses, and dependency randomization can work together as needed. The first three schemes select the last access instance of the target access sequence one by one from the candidate instance set, and construct the target access sequence after selection. The fourth scheme optimizes the target access sequence by continuously swapping the positions of access elements within the constructed target access sequence. When any number of the first three schemes are combined, the selection of the last access instance needs to consider multiple factors. When the fourth scheme is combined with the schemes from the first three schemes, position optimization can be performed based on the target access sequence constructed by the first three schemes.

[0100] Secondly, embodiments of this application also provide a memory random access verification device.

[0101] Figure 2 A schematic diagram of the functional modules of a memory random access verification device in one embodiment of this application is shown.

[0102] Reference Figure 2 In one embodiment, the memory random access verification device includes: The triplet construction module 10 is used to exhaustively enumerate the combinations of access address, access granularity and access type corresponding to the target memory to obtain multiple access triplets; The instantiation module 20 is used to fill in the fields of a preset data structure for each access triplet to obtain at least one basic access instance. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read and write operation. The sequence construction module 30 is used to select multiple basic access instances and randomly rearrange them to obtain the target access sequence according to the test requirements.

[0103] Furthermore, in one embodiment, in the target access sequence, access instances of access type read are denoted as target read access instances, and access instances of access type write are denoted as target write access instances. The memory random access verification apparatus also includes a verification execution module for: Determine the expected read value for each target read access instance; Perform read and write operations on the target memory based on the target access sequence, and obtain the read return value of each target read access instance; The expected read value and the read return value of each target read access instance are compared to obtain the verification result.

[0104] Furthermore, in one embodiment, the verification execution module is used to: For each target read access instance, determine the expected read value of each target data unit in the read access instance, and combine the expected read values ​​of all target data units in address order to obtain the expected read value of the read access instance. The step of determining the expected read value for each target data unit in the read access instance includes: For each target data unit in this read access instance: Check if the data unit has a first write access instance, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit; If a first write access instance exists, the read expectation value of that data unit is determined to be the write expectation value of the target data unit at the same address of the nearest first write access instance; If no first write access instance exists, the expected read value of that data unit is determined as the initial value of the target memory at the same address.

[0105] Furthermore, in one embodiment, a target read access instance where the expected read value is not equal to the read return value is denoted as an erroneous read access instance, and a target data unit where the expected read value is not equal to the read return value is denoted as an erroneous data unit; The memory random access verification apparatus also includes an error attribution module for: If any erroneous read access instance satisfies the first and second judgment conditions, then the error type of the erroneous read access instance is determined to be a data concatenation error. If any erroneous read access instance satisfies the first judgment condition but does not satisfy the second judgment condition, then the error type of the erroneous read access instance is determined to be an unaligned access processing error. If any erroneous read access instance does not satisfy the first judgment condition, but satisfies the third, fourth, and fifth judgment conditions, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. If any erroneous read access instance does not satisfy the first and fifth judgment conditions, but satisfies the third and fourth judgment conditions, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and fourth judgment conditions, but meets the third and sixth judgment conditions, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, fourth, and sixth judgment conditions, but satisfies the third judgment condition, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and third judgment conditions, but meets the sixth judgment condition, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, third, and sixth judgment conditions, but satisfies the seventh judgment condition, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. The first condition is: the read access instance is an unaligned access, and any second write access instance of the read access instance is an unaligned access, wherein the second write access instance is a target write access instance located before the read access instance, and has a target data unit with the same address as the read access instance; The second judgment condition is: the address of any erroneous data unit of the read access instance is the target aligned address, and the read return value of the erroneous data unit is equal to the write expectation value of any unrequested data unit of the second write access instance. Here, the target aligned address is within the access range of the read access instance, the target aligned address is divisible by the data bus width, the starting point of the access range is the access address, the length is the access granularity, the unrequested data unit is any target data unit of the second write access instance, and the read access instance does not have a target data unit with the same address as the unrequested data unit. The third condition is: any target data unit of the read access instance is not an erroneous data unit; The fourth condition is: the nearest first write access instance to any erroneous data unit of the read access instance has a non-requested data unit, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit. The fifth condition is: whether the return value of any erroneous data unit of the read access instance is equal to the expected write value of the target data unit at the same address of any non-nearest first write access instance; The sixth condition is: the read access instance has a second write access instance with multiple access granularities; The seventh condition is: the read return value of each erroneous data unit of the read access instance is equal to the write expectation value of the target data unit at the same address of any second write access instance that is not the most recent one.

[0106] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding address segment group. The access instances in the candidate instance set are selected according to the test requirements. Each address segment group is used to summarize different access instances whose access addresses fall within the same address range. In each iteration, an access instance from an address segment group with a high access weight is selected first and added to the end of the target access sequence. The access weight is negatively correlated with the frequency of the address segment group within the sliding window. The sliding window is used to record the address segment groups to which a preset number of access instances recently added to the target access sequence belong.

[0107] Furthermore, in one embodiment, the random rearrangement operation includes: For each access instance in the candidate instance set, an attribute vector is constructed based on the access granularity and access type of that access instance. The access instances in the candidate instance set are selected according to the test requirements. In each iteration, the access instance whose attribute vector is farthest from the attribute vector of the last access instance is selected and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0108] Furthermore, in one embodiment, the random rearrangement operation includes: Each access instance in the candidate instance set is assigned to a corresponding co-address access chain. The access instances in the candidate instance set are selected according to the test requirements, and each co-address access chain is used to aggregate different access instances with the same access address. In each iteration, the target spacing range of the co-address access chain to which the last access instance belongs is determined, and an access instance is randomly selected from the co-address access chains within the target spacing range and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

[0109] Furthermore, in one embodiment, the random rearrangement operation includes: A target access sequence is randomly generated based on the access instances in the candidate instance set, wherein the access instances in the candidate instance set are selected according to the test requirements; In each iteration, two access elements are randomly selected from the target access sequence for position swapping. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is closer to the preset proportion target than before the swap, the position swap is accepted. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is further away from the preset proportion target than before the swap, the position swap is accepted with decreasing probability. Among them, the dependencies include write-after-read, read-after-write, and write-after-write.

[0110] Furthermore, in one embodiment, the fields of the preset data structure also include an alignment identifier, which is used to mark whether the access instance is an aligned access.

[0111] The functions of each module in the above-mentioned memory random access verification device correspond to the steps in the above-mentioned memory random access verification method embodiment, and their functions and implementation processes will not be described in detail here.

[0112] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0113] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0114] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0115] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0116] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0117] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0118] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A memory random access verification method, characterized by, The memory random access verification method includes: By exhaustively listing the combinations of access address, access granularity and access type corresponding to the target memory, multiple access triplets are obtained; For each access triple, at least one access instance is obtained by filling in the fields according to the preset data structure. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read and write operation. Based on the testing requirements, multiple access instances are selected and randomly rearranged to obtain the target access sequence.

2. The memory random access verification method of claim 1, wherein, In the target access sequence, access instances of the access type of read are denoted as target read access instances, and access instances of the access type of write are denoted as target write access instances. Following the step of randomly rearranging multiple access instances according to test requirements to obtain the target access sequence, the method further includes: Determine the expected read value for each target read access instance; Perform read and write operations on the target memory based on the target access sequence, and obtain the read return value of each target read access instance; The expected read value and the read return value of each target read access instance are compared to obtain the verification result.

3. The memory random access verification method of claim 2, wherein, The step of determining the read expectation value for each target read access instance includes: For each target read access instance, determine the expected read value of each target data unit in the read access instance, and combine the expected read values ​​of all target data units in address order to obtain the expected read value of the read access instance. The step of determining the expected read value for each target data unit in the read access instance includes: For each target data unit in this read access instance: Check if the data unit has a first write access instance, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit; If a first write access instance exists, the read expectation value of that data unit is determined to be the write expectation value of the target data unit at the same address of the nearest first write access instance; If no first write access instance exists, the expected read value of that data unit is determined as the initial value of the target memory at the same address.

4. The memory random access verification method of claim 2, wherein, A target read access instance where the expected value and the return value are not equal is denoted as an erroneous read access instance, and a target data unit where the expected value and the return value are not equal is denoted as an erroneous data unit; After the step of comparing the expected read value and the return read value of each target read access instance to obtain the verification result, the method further includes: If any erroneous read access instance satisfies the first and second judgment conditions, then the error type of the erroneous read access instance is determined to be a data concatenation error. If any erroneous read access instance satisfies the first judgment condition but does not satisfy the second judgment condition, then the error type of the erroneous read access instance is determined to be an unaligned access processing error. If any erroneous read access instance does not satisfy the first judgment condition, but satisfies the third, fourth, and fifth judgment conditions, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. If any erroneous read access instance does not satisfy the first and fifth judgment conditions, but satisfies the third and fourth judgment conditions, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and fourth judgment conditions, but meets the third and sixth judgment conditions, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, fourth, and sixth judgment conditions, but satisfies the third judgment condition, then the error type of the erroneous read access instance is determined to be a byte overwrite logic error. If any erroneous read access instance does not meet the first and third judgment conditions, but meets the sixth judgment condition, then the error type of the erroneous read access instance is determined to be a mixed error of different width accesses. If any erroneous read access instance does not satisfy the first, third, and sixth judgment conditions, but satisfies the seventh judgment condition, then the error type of the erroneous read access instance is determined to be a write-after-read sequence dependency error. The first condition is: the read access instance is an unaligned access, and any second write access instance of the read access instance is an unaligned access, wherein the second write access instance is a target write access instance located before the read access instance, and has a target data unit with the same address as the read access instance; The second judgment condition is: the address of any erroneous data unit of the read access instance is the target aligned address, and the read return value of the erroneous data unit is equal to the write expectation value of any unrequested data unit of the second write access instance. Here, the target aligned address is within the access range of the read access instance, the target aligned address is divisible by the data bus width, the starting point of the access range is the access address, the length is the access granularity, the unrequested data unit is any target data unit of the second write access instance, and the read access instance does not have a target data unit with the same address as the unrequested data unit. The third condition is: any target data unit of the read access instance is not an erroneous data unit; The fourth condition is: the nearest first write access instance to any erroneous data unit of the read access instance has a non-requested data unit, wherein the first write access instance is the target write access instance located before the read access instance, and there exists a target data unit with the same address as the data unit. The fifth condition is: whether the return value of any erroneous data unit of the read access instance is equal to the expected write value of the target data unit at the same address of any non-nearest first write access instance; The sixth condition is: the read access instance has a second write access instance with multiple access granularities; The seventh condition is: the read return value of each erroneous data unit of the read access instance is equal to the write expectation value of the target data unit at the same address of any second write access instance that is not the most recent one.

5. The memory random access verification method of claim 1, wherein, Random rearrangement operations include: Each access instance in the candidate instance set is assigned to a corresponding address segment group. The access instances in the candidate instance set are selected according to the test requirements. Each address segment group is used to summarize different access instances whose access addresses fall within the same address range. In each iteration, an access instance from an address segment group with a high access weight is selected first and added to the end of the target access sequence. The access weight is negatively correlated with the frequency of the address segment group within the sliding window. The sliding window is used to record the address segment groups to which a preset number of access instances recently added to the target access sequence belong.

6. The memory random access verification method of claim 1, wherein, Random rearrangement operations include: For each access instance in the candidate instance set, an attribute vector is constructed based on the access granularity and access type of that access instance. The access instances in the candidate instance set are selected according to the test requirements. In each iteration, the access instance whose attribute vector is farthest from the attribute vector of the last access instance is selected and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

7. The memory random access verification method as described in claim 1, characterized in that, Random rearrangement operations include: Each access instance in the candidate instance set is assigned to a corresponding co-address access chain. The access instances in the candidate instance set are selected according to the test requirements, and each co-address access chain is used to aggregate different access instances with the same access address. In each iteration, the target spacing range of the co-address access chain to which the last access instance belongs is determined, and an access instance is randomly selected from the co-address access chains within the target spacing range and added to the end of the target access sequence. The last access instance is the access instance that is currently at the end of the target access sequence.

8. The memory random access verification method as described in claim 1, characterized in that, Random rearrangement operations include: A target access sequence is randomly generated based on the access instances in the candidate instance set, wherein the access instances in the candidate instance set are selected according to the test requirements; In each iteration, two access elements are randomly selected from the target access sequence for position swapping. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is closer to the preset proportion target than before the swap, the position swap is accepted. If the actual proportion of various dependencies in the target access sequence within the preset statistical range after the swap is further away from the preset proportion target than before the swap, the position swap is accepted with decreasing probability. Among them, the dependencies include write-after-read, read-after-write, and write-after-write.

9. The memory random access verification method as described in claim 1, characterized in that, The pre-defined data structure also includes fields for alignment flags, which are used to mark whether an access instance is an aligned access.

10. A memory random access verification device, characterized in that, The memory random access verification device includes: The triplet construction module is used to exhaustively enumerate the combinations of access address, access granularity and access type corresponding to the target memory to obtain multiple access triplets; The instantiation module is used to fill in the fields of a preset data structure for each access triplet to obtain at least one basic access instance. The fields of the preset data structure include access address, access granularity, access type, data to be written, and target unit mask. The access address, access granularity, and target unit mask are used to determine the address of the target data unit involved in the read and write operation. The sequence building module is used to select multiple basic access instances and randomly rearrange them to obtain the target access sequence according to the test requirements.

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