Bus data processing method, system and electronic device

Abstract

The application provides a bus data processing method, system and electronic equipment, and relates to the field of chip bus control. The method can perform real-time address monitoring, data monitoring and timeout monitoring on access transaction data signals in the AHB bus by using read-write address data and write data of the access transaction, and can actively intercept abnormal access transactions through synergistic reuse of the multiple monitoring functions, so as to avoid bus hanging and system crashes caused by illegal access. In addition, the method can quickly locate problems in the abnormal debugging process by bypassing register cache access to historical data signals and abnormal data signals of the access transaction, and greatly improves the execution efficiency of abnormal debugging.

Description

Technical Field

[0001] This invention relates to the field of chip bus control, and in particular to a bus data processing method, system and electronic device. Background Technology

[0002] The AHB (Advanced High-performance Bus) bus between the master and slave devices has the following problems in signal data processing: When the slave device is in a hardware failure, clock off, or low-power mode, it cannot respond to the master, causing data transmission on the AHB bus to be blocked, and the master cannot initiate new data transmissions on the AHB bus. Therefore, multiple independent detection modules are required to detect and process AHB bus data. The processing consumes a lot of computing resources, and the detection modules cannot work together.

[0003] Furthermore, for access transactions to certain special addresses (such as security control registers and debug interfaces) or specific data values ​​(such as write data that triggers illegal operations) in the slave device, even if the transaction is detected, it cannot be prevented from reaching the slave device. It can only be reported and cannot be actively intercepted. Moreover, it is difficult to locate the problem during subsequent debugging. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a bus data processing method, system, and electronic device. This method can perform real-time address monitoring, data monitoring, and timeout monitoring of access transaction data signals in the AHB bus using read and write address data and write data of access transactions. Through the coordinated multiplexing of the above-mentioned monitoring functions, abnormal access transactions can be actively intercepted, thereby avoiding system crashes caused by bus hangs and illegal access. In addition, this method caches historical data signals and abnormal data signals of access transactions through bypass registers, which can quickly locate problems during abnormal debugging and greatly improve the execution efficiency of abnormal debugging.

[0005] In a first aspect, embodiments of the present invention provide a bus data processing method, the method comprising: By using the enable type parameter and bus type parameter of the access transaction in the AHB bus, the address monitoring range and data monitoring range of the access transaction are generated, and the address phase signal and write data signal of the access transaction are buffered into the bypass register of the AHB bus according to the clock cycle of the AHB bus. When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the AHB bus is controlled to release the first access transaction. When the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave device of the AHB bus through the bypass register, and the target write data signal of the second access transaction is sent to the slave device in the next clock cycle.

[0006] Optionally, the address monitoring range and data monitoring range of the access transaction can be generated through the enable type parameter and bus type parameter of the access transaction in the AHB bus, including: Obtain the enable type parameter of the access transaction in the AHB bus, and use the address monitoring type and data monitoring type corresponding to the enable type parameter to obtain the address monitoring enable flag value and data monitoring enable flag value of the access transaction respectively. Obtain the bus type parameter of the access transaction in the AHB bus, and use the address monitoring type and data monitoring type corresponding to the bus type parameter to determine the address monitoring bus flag value and data monitoring bus flag value of the access transaction; The target address attribute value of the access transaction is obtained by using the data monitoring enable flag value and the address monitoring bus flag value, and the address monitoring range of the access transaction is generated by the minimum address and the maximum address determined by the target address attribute value. The matching value and mask value of the target data of the access transaction are obtained by using the data monitoring enable flag value and the data monitoring bus flag value, and the data monitoring range of the access transaction is generated by using the data bit matching result of the matching value and the mask value.

[0007] Optionally, the address phase signal and write data signal of the access transaction are buffered in the bypass register of the AHB bus according to the clock cycle of the AHB bus, including: The address phase signal is determined by using the non-idle transfer type signal, slave select signal, address bus signal and read / write control signal of the access transaction in the AHB bus, and the write data signal of the access transaction in the AHB bus is obtained. When the slave select signal is high, the non-idle transfer type signal is high, and the read / write control signal is high, determine whether the address bus signal appears in the AHB bus in the current clock cycle and whether the write data signal appears in the AHB bus in the next clock cycle. If so, the address phase signal and write data signal are buffered into the bypass register of the AHB bus per unit clock cycle.

[0008] Optionally, when the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the steps to control the AHB bus to release the first access transaction include: Real-time monitoring of the first access transaction in the data read / write state on the AHB bus, obtaining the read / write address in the first access transaction, and determining whether the read / write address is within the address monitoring range; If so, the AHB bus is controlled to intercept the first access transaction in order to prevent the first access transaction from being sent to the slave device of the AHB bus; The first access transaction's transmission ready signal and transmission response signal are generated based on the read and write addresses; After the transmission ready signal and transmission response signal are sequentially uploaded to the AHB bus host via the AHB bus, the AHB bus is controlled to release the first access transaction.

[0009] Optionally, after controlling the AHB bus to release the first access transaction, the method further includes: The target address bus signal, target non-idle transfer type signal, target read / write control signal, and target write data signal of the first access transaction are obtained based on the AHB bus. Save the target address bus signal, target non-idle transfer type signal, target read / write control signal, and target write data signal to the bypass register.

[0010] Optionally, when it is detected that the write data of the second access transaction in the AHB bus is outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave device of the AHB bus through the bypass register, and in the next clock cycle, the bypass register is controlled to send the target write data signal of the second access transaction to the slave device, including: Real-time monitoring of the second access transaction in the write data state on the AHB bus, obtaining the write data of the second access transaction, and determining whether the write data is outside the address monitoring range; If so, the target non-idle transfer type signal, target slave select signal, target address bus signal, and target read / write control signal for the second access transaction in the current clock cycle are obtained through the bypass register; The target address phase signal of the second access transaction is obtained based on the target non-idle transmission type signal, the target slave selection signal, the target address bus signal, and the target read / write control signal, and the target address phase signal is sent to the slave of the AHB bus. The target write data signal for the second access transaction in the next clock cycle is obtained through the bypass register, and the target write data signal is sent to the slave device.

[0011] Optionally, when the write data of the second access transaction in the AHB bus is detected to be within the data monitoring range, the method further includes: Control the AHB bus to intercept the second access transaction to prevent it from being sent to the slave device; The second access transaction's transmission ready signal and transmission response signal are generated based on the written data; After the transmission ready signal and transmission response signal are sequentially uploaded to the AHB bus host via the AHB bus, the AHB bus is controlled to release the second access transaction.

[0012] Optionally, the method further includes: Using the first or second access transaction as the target access transaction, obtain the start time of the target access transaction in the AHB bus. When the startup duration exceeds the preset timeout threshold, the current address bus signal, current non-idle transfer type signal, current read / write control signal, and current write data signal of the target access transaction in the AHB bus are saved to the bypass register. After the target access transaction is intercepted by the AHB bus to prevent it from being sent to the slave device, a transmission ready signal and a transmission response signal for the target access transaction are generated based on the write data. After the transmission ready signal and transmission response signal are uploaded to the AHB bus master in sequence through the AHB bus, the AHB bus is controlled to release the target access transaction.

[0013] In a second aspect, the present invention provides a bus data processing system, the system comprising: Parameter caching setting module: Generates the address monitoring range and data monitoring range of the access transaction through the enable type parameter and bus type parameter of the access transaction in the AHB bus, and caches the address phase signal and write data signal of the access transaction into the bypass register of the AHB bus according to the clock cycle of the AHB bus. Address monitoring module: When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, control the AHB bus to release the first access transaction; Data monitoring module: When the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the module sends the target address phase signal of the second access transaction to the slave device of the AHB bus through the bypass register, and controls the bypass register to send the target write data signal of the second access transaction to the slave device in the next clock cycle.

[0014] Thirdly, embodiments of the present invention also provide an electronic device, which includes a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the steps of the bus data processing method provided in the first aspect.

[0015] This invention provides a bus data processing method, system, and electronic device. In the process of monitoring and processing access transaction signal data in the AHB bus, the method first generates the address monitoring range and data monitoring range of the access transaction using the enable type parameter and bus type parameter of the access transaction in the AHB bus. Then, it buffers the address phase signal and write data signal of the access transaction in the bypass register of the AHB bus according to the clock cycle of the AHB bus. When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the method controls the AHB bus to release the first access transaction. When the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the method sends the target address phase signal of the second access transaction to the slave device of the AHB bus through the bypass register, and in the next clock cycle, controls the bypass register to send the target write data signal of the second access transaction to the slave device. This method can perform real-time address monitoring, data monitoring, and timeout monitoring of access transaction data signals in the AHB bus by utilizing the read and write address data and write data of access transactions. Through the coordinated multiplexing of the above-mentioned monitoring functions, abnormal access transactions can be actively intercepted, thereby avoiding system crashes caused by bus hangs and illegal access. In addition, this method caches historical data signals and abnormal data signals of access transactions through bypass registers, which can quickly locate problems during anomaly debugging and greatly improve the execution efficiency of anomaly debugging.

[0016] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A flowchart of a bus data processing method provided in an embodiment of the present invention; Figure 2 A signal timing diagram of a bus data processing method provided in an embodiment of the present invention; Figure 3A flowchart of another bus data processing method provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a bus data processing system provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0020] icon: 100 - Parameter cache setting module; 200 - Address monitoring module; 300 - Data monitoring module; 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] To facilitate understanding of this embodiment, a bus data processing method disclosed in this embodiment of the invention will first be described, as follows: Figure 1 As shown, it includes: Step S101: Generate the address monitoring range and data monitoring range of the access transaction through the enable type parameter and bus type parameter of the access transaction in the AHB bus, and cache the address phase signal and write data signal of the access transaction into the bypass register of the AHB bus according to the clock cycle of the AHB bus.

[0023] Based on the enable type parameters and bus type parameters of access transactions in AHB bus transmission, the configuration and generation of address monitoring range and data monitoring range are completed. The address monitoring range corresponds to the special sensitive address range of the slave device's security control register, debugging interface, etc., and the data monitoring range corresponds to the write data threshold range that prohibits the triggering of illegal operations. At the same time, strictly following the clock cycle timing of the AHB bus, the address phase signal and write data signal of the current transmission access transaction are synchronously sampled and cached in real time to the AHB bus dedicated bypass register. This bypass register can persistently store the historical data signals and abnormal data signals of the access transaction, providing original data support for subsequent abnormal interception, transaction management and fault debugging, realizing the pre-caching and reuse of monitoring data.

[0024] Step S102: When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, control the AHB bus to release the first access transaction.

[0025] The system monitors the first access transaction transmitted on the AHB bus in real time. When it is determined that the read / write address of the access transaction falls within the preset address monitoring range, the active interception control logic is immediately triggered to drive the AHB bus to forcibly release the first access transaction, blocking its transmission path to the slave end. This prevents illegal access to special sensitive addresses from the source and achieves active protection against high-risk access transactions.

[0026] Step S103: When the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave of the AHB bus through the bypass register, and the target write data signal of the second access transaction is sent to the slave in the next clock cycle.

[0027] The system monitors the second access transaction transmitted on the AHB bus in real time. When it is determined that the write data of the access transaction is outside the preset data monitoring range (i.e., the write data is a legal and compliant value and will not trigger an illegal operation), the system first sends the target address phase signal of the second access transaction to the AHB bus slave through the bypass register according to the AHB bus transmission timing. When the next AHB bus clock cycle arrives, the system uses the bypass register to synchronously send the target write data signal of the second access transaction to the slave. While ensuring the normal transmission of legal access transactions, the system uses the cached data of the bypass register to complete the transaction transmission timing calibration and anomaly tracing.

[0028] The signal timing diagram of the above bus data processing method is as follows: Figure 2 As shown in the figure, the typical synchronous pipelined transmission timing of the AHB bus is illustrated. All signals are synchronously sampled based on the system clock HCLK. The transmission process is divided into two overlapping phases: the address phase and the data phase. The core signals and transmission logic are as follows: The system clock HCLK is the bus synchronization clock. All signals are sampled on the clock edge to provide a time base for transmission. The switching of address / data phases is driven by the clock edge. The address bus HADDR[31:0] is the target address for transmitting access transactions, and is a stable output for the address phase phase (e.g., ...). Figure 2 (At addresses A and B), the data phase phase can be overwritten by the address of the next transaction (pipeline overlap). The Control group contains control parameters for transmission transactions (read / write type, transmission size, burst type, etc.), synchronized with the address bus, and used to define transaction attributes during the address phase phase.

[0029] The write data bus HWDATA[31:0] is used to send write data to the slave device during write transmission. It is stably output during the data phase phase (e.g., Figure 2 The write data Data(A) of A is transmitted in the middle. The read data bus HRDATA[31:0] contains the read data returned by the slave device during read transfer, which is stably output during the data phase phase (e.g., Figure 2 Data(A) is read from A during transmission. The HREADY signal is a transmission status signal fed back by the slave device; a high level indicates that the transmission is complete. Figure 2 During the high-level transmission phase (corresponding to the successful operation marker), a low level indicates that the slave device is in a waiting state (e.g., ...). Figure 2 (Multiple waiting periods in the middle).

[0030] Figure 2 The bus data processing method in this paper is based on the above pipeline timing. It introduces parameter configuration, signal buffering, real-time monitoring, and dynamic interception logic in the address and data phases to achieve collaborative multiplexing of address monitoring, data monitoring, and timeout monitoring. The specific implementation is as follows: 1. Address phase: parameter configuration and signal buffering.

[0031] During the address phase of each access transaction (the clock cycle in which HADDR and Control signals are stable), this method performs two core operations: Dynamically generate monitoring range: Based on the enable type parameters (read / write enable, transfer enable) and bus type parameters (transfer size, address space type) in the Control signal, dynamically generate the address monitoring range and data monitoring range corresponding to the current transaction. Address monitoring range: For the restricted access range configured for sensitive addresses (such as security control registers and debug interface addresses), the monitoring boundary is generated by distinguishing between ordinary addresses and sensitive addresses through the address space type and read / write type parameters in Control. Data monitoring range: For illegal write data (such as specific values ​​that trigger abnormal operation of the slave device), the legal data range is configured, and the corresponding bit width data monitoring boundary is generated by the transmission size and write enable parameters in Control.

[0032] Bypass register buffer signals: According to the HCLK clock cycle, the address phase signals (HADDR, Control) of the current transaction and the write data signals (HWDATA) of the subsequent data phase are buffered in real time into the bypass register of the AHB bus (e.g., Figure 2The HADDR[A] and Control signals of the address phase, as well as the HWDATA[Data(A)] of the subsequent data phase, are all cached. This register can store historical signals (address, control, write data) and exception signals of transactions, providing raw data support for subsequent monitoring and debugging, and avoiding resource consumption caused by repeated sampling by multiple modules.

[0033] 2. Address Phase: Address monitoring and transaction release control.

[0034] During the address phase phase, this method compares the read / write addresses transmitted on the HADDR bus with the preset address monitoring range in real time: If the read / write address falls within the address monitoring range (i.e., accessing a sensitive address), this method immediately triggers active interception logic to control the AHB bus to release the access transaction: before the address phase ends, the control logic of the bypass register blocks the transmission of the address information of the transaction to the slave device, and at the same time forces the HREADY signal to go low or returns an error response to prevent the transaction from entering the data phase stage, thus preventing the sensitive address from being illegally accessed from the source and solving the defect of existing technologies that can only report but cannot actively intercept.

[0035] If the read / write address is not within the address monitoring range, the transaction will normally enter the data phase phase and continue subsequent transmission.

[0036] 3. Data Phase: Data monitoring and transaction timing control.

[0037] During the data phase phase, for the write data signal of a write transaction, this method compares the write data transmitted on the HWDATA bus with the preset data monitoring range in real time: If the write data is outside the data monitoring range (i.e., the write data is a valid value and will not trigger abnormal operation of the slave device), this method implements the time-sequential delivery of transactions through a bypass register: First, in the address phase phase, the target address phase signal (HADDR, Control) of the transaction is sent to the slave device to complete the slave device's address resolution; then, in the next HCLK clock cycle (i.e., the data phase phase), the control bypass register sends the target write data signal (HWDATA) to the slave device, cooperating with the slave device's HREADY signal to complete the transmission (e.g., ...). Figure 2 The write data Data(A) of transmission A is sent down in the clock cycle after the address phase, and the slave returns HREADY high level, marking the operation as successful.

[0038] If the written data is within the data monitoring range (i.e., the written data is an illegal value), this method intercepts the transmission of the written data through the bypass register, records the abnormal data signal, and returns an error response through the bus to prevent the illegal written data from reaching the slave device and avoid triggering abnormal operations of the slave device.

[0039] Optionally, the address monitoring range and data monitoring range of the access transaction are generated through the enable type parameter and bus type parameter of the access transaction in the AHB bus, including the following steps: Step S301: Obtain the enable type parameter of the access transaction in the AHB bus, and use the address monitoring type and data monitoring type corresponding to the enable type parameter to obtain the address monitoring enable flag value and data monitoring enable flag value of the access transaction respectively.

[0040] Obtain the enable type parameter of the currently pending access transaction in the AHB bus. This enable type parameter is used to characterize the enabled status of the address monitoring function and the data monitoring function. Based on the address monitoring type and data monitoring type corresponding to the enable type parameter, match and obtain the address monitoring enable flag value and data monitoring enable flag value specific to the current access transaction. The address monitoring enable flag value is used to control the opening or closing of the address monitoring function (e.g., when the address monitoring enable flag value is 1, the address monitoring function is enabled; when the address monitoring enable flag value is 0, the address monitoring function is closed). The data monitoring enable flag value is used to control the opening or closing of the data monitoring function (e.g., when the data monitoring enable flag value is 1, the data monitoring function is enabled; when the data monitoring enable flag value is 0, the data monitoring function is closed).

[0041] Step S302: Obtain the bus type parameter of the access transaction in the AHB bus, and determine the address monitoring bus flag value and data monitoring bus flag value of the access transaction using the address monitoring type and data monitoring type corresponding to the bus type parameter.

[0042] Obtain the bus type parameter of the currently pending access transaction in the AHB bus. This bus type parameter represents the bus control permissions of address monitoring and data monitoring. Based on the address monitoring type and data monitoring type corresponding to the bus type parameter, determine and configure the address monitoring bus control flag value and data monitoring bus control flag value for the current access transaction. The address monitoring bus control flag value is only valid when the address monitoring enable flag value is active, and is used to control whether address monitoring has bus interception and takeover permissions (e.g., when the address monitoring bus control flag value is 1, the address monitoring bus control function is enabled; when the address monitoring bus control flag value is 0, the address monitoring bus control function is disabled). The data monitoring bus control flag value is only valid when the data monitoring enable flag value is active, and is used to control whether data monitoring has bus interception and takeover permissions (e.g., when the data monitoring bus control flag value is 1, the data monitoring bus control function is enabled; when the data monitoring bus control flag value is 0, the data monitoring bus control function is disabled).

[0043] Step S303: Obtain the target address attribute value of the access transaction using the data monitoring enable flag value and the address monitoring bus flag value, and generate the address monitoring range of the access transaction using the minimum address and maximum address determined by the target address attribute value.

[0044] Based on the data monitoring enable flag value obtained in step S301 and the address monitoring bus control flag value obtained in step S302, the target address attribute value of the current access transaction is extracted and determined. The minimum address (0x0000_0000) and maximum address (0x0000_1000) of the address monitoring range are obtained by parsing the target address attribute value. The address monitoring range (0x0000_0000~0x0000_1000) corresponding to the current access transaction is generated with the minimum address as the starting boundary and the maximum address as the ending boundary. This range is the judgment range for the address monitoring module to identify illegal address access.

[0045] Step S304: Use the data monitoring enable flag value and the data monitoring bus flag value to obtain the matching value and mask value of the target data of the access transaction, and use the data bit matching result of the matching value and the mask value to generate the data monitoring range of the access transaction.

[0046] Based on the data monitoring enable flag value obtained in step S301 and the data monitoring bus control flag value obtained in step S302, the target data matching value (DATA, such as 0xFFFF_FFFF) and the target data mask value (MASK, such as 0x0000_FFFF) of the current access transaction are extracted and determined. The write data to be monitored in the AHB bus write transaction is matched bitwise with the matching value and the mask value to obtain an accurate data bit matching result (monitoring all bus write access transactions to which hwdata with the lower 16 bits being 0xFFFF). Based on the data bit matching result, the illegal data characteristics to be monitored are defined, and the data monitoring range corresponding to the current access transaction is generated. This range is the basis for the data monitoring module to identify illegal data writing.

[0047] Optionally, the address phase signal and write data signal of the access transaction are buffered in the bypass register of the AHB bus according to the clock cycle of the AHB bus, including the following steps: Step S401: Determine the address phase signal using the non-idle transfer type signal, slave selection signal, address bus signal, and read / write control signal of the access transaction on the AHB bus, and obtain the write data signal of the access transaction on the AHB bus.

[0048] Based on the AHB bus standard transmission timing, the key bus signals of the current access transaction are collected, including the non-idle transmission type signal htrans[1], the slave selection signal hsel, the address bus signal haddr, and the read / write control signal hwrite. Taking htrans[1], hsel, haddr, and hwrite signals as the core, the address phase signal of the current access transaction is determined by combination, and the write data signal hwdata corresponding to the data phase of the access transaction is obtained synchronously, so as to provide a complete original signal basis for subsequent timing verification and signal buffering.

[0049] Step S402: When the slave select signal is detected to be high, the non-idle transfer type signal is detected to be high, and the read / write control signal is detected to be high, determine whether the address bus signal appears in the AHB bus in the current clock cycle and whether the write data signal appears in the AHB bus in the next clock cycle.

[0050] According to the hardware judgment rules for valid write transactions on the AHB bus, the bus signals are checked in real time: whether the slave selection signal hsel is high, whether the non-idle transfer type signal htrans[1] is high, and whether the read / write control signal hwrite is high; under the premise that all three are high, further verify whether the address bus signal haddr is stably output to the AHB bus in the current clock cycle, and whether the write data signal hwdata will appear on the AHB bus in the next clock cycle, so as to match the inherent pipeline characteristics of the AHB bus write operation address phase and data phase being one clock cycle apart.

[0051] Step S403: If so, buffer the address phase signal and write data signal into the bypass register of the AHB bus every unit clock cycle.

[0052] If step S402 determines that the timing and signal conditions for a valid write transaction are met, a single-cycle synchronous buffering operation is performed: the address phase signal and write data signal of the current access transaction are strictly buffered in accordance with the timing constraints of the AHB bus unit clock cycle into the dedicated bypass register configured on the AHB bus; through this single-clock-cycle pre-buffering operation, a judgment window is reserved for subsequent data monitoring and illegal write interception, ensuring that the data legality check is completed before the write data is transmitted to the slave device.

[0053] Optionally, when the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the step of controlling the AHB bus to release the first access transaction includes the following steps: Step S501: Monitor the first access transaction in the data read / write state on the AHB bus in real time, obtain the read / write address in the first access transaction, and determine whether the read / write address is within the address monitoring range.

[0054] The system monitors the first access transaction on the AHB bus that is in a valid data read / write transmission state in real time, and synchronously collects the read / write address signal HADDR corresponding to the transaction. The collected read / write address is compared with the preset address monitoring range (formed by the minimum address and maximum address configuration) in real time to accurately determine whether the read / write address falls within the sensitive address range defined by the address monitoring range.

[0055] Step S502: If so, control the AHB bus to intercept the first access transaction to prevent the first access transaction from being sent to the slave device of the AHB bus.

[0056] If the determination result is yes, and the address monitoring bus control flag value is in the enabled state, the address monitoring hardware interception logic is immediately triggered to control the AHB bus to perform a blocking operation on the first access transaction, cut off the transmission path of the transaction signal to the target slave, and prevent the first access transaction from being sent to the slave from the hardware level.

[0057] Step S503: Generate the transmission ready signal and transmission response signal for the first access transaction based on the read / write address.

[0058] Following the AHB bus protocol specification, based on the address attributes and transmission status of the first intercepted access transaction, standard bus response signals are generated: the transmission ready signal HREADY is set to high level to terminate the current transmission; the transmission response signal HRESP is set to ERROR to report to the host that the access was illegal and failed.

[0059] Step S504: After sequentially uploading the transmission ready signal and transmission response signal to the host of the AHB bus via the AHB bus, control the AHB bus to release the first access transaction.

[0060] Through the slave response channel of the AHB bus, the generated transmission ready signal and transmission response signal are sequentially transmitted back to the host that initiated the access according to the protocol timing to complete the hardware handshake of abnormal transmission. After the signal transmission is completed, the AHB bus is controlled to release the bus resources occupied by the first access transaction, restore the normal transmission path of the bus, and at the same time, the key transaction information of this abnormal access is latched and the address monitoring interrupt is triggered to report.

[0061] In the above process, when the address monitoring enable flag is 1, the read / write address of the first access transaction on the AHB bus is monitored. When the read / write address is within the address monitoring range, there are two possibilities: 1. When the address monitoring bus control flag value is 1, the first access transaction is intercepted, and the response channel of the slave device is actively taken over. The takeover steps are as follows: Intercept the first access transaction and prevent it from reaching the slave device; Return hready=1 to the host (end the current transfer); It also returns hresp=ERROR (indicating a transmission error); After completing the above transmission, release the AHB bus to allow subsequent transactions to continue.

[0062] 2. When the address monitoring bus control flag value is 0, the AHB bus will not be controlled to perform interception.

[0063] Optionally, after controlling the AHB bus to release the first access transaction, the method further includes the following steps: Step S601: Based on the AHB bus, obtain the target address bus signal, target non-idle transfer type signal, target read / write control signal, and target write data signal of the first access transaction.

[0064] After completing the hardware interception and bus release operation of the first access transaction, based on the AHB bus transmission link, all core bus signals corresponding to the abnormal access transaction are collected in real time, including the target address bus signal HADDR, the target non-idle transmission type signal htrans[1], the target read / write control signal hwrite, and the target write data signal HWDATA, so as to obtain the full transaction feature information of this sensitive address illegal access.

[0065] Step S602: Save the target address bus signal, target non-idle transfer type signal, target read / write control signal, and target write data signal to the bypass register.

[0066] The target address bus signal, target non-idle transmission type signal, target read / write control signal, and target write data signal collected above are used as on-site reserved data for address monitoring anomalies. They are synchronously latched and written into the bypass register of the AHB bus monitoring unit or the dedicated storage unit of the configuration reporting module, providing complete and original transaction data support for subsequent reading of anomaly logs, rapid location of illegal access sources, and fault tracing.

[0067] Optionally, when the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave device of the AHB bus through the bypass register, and the target write data signal of the second access transaction is sent to the slave device in the next clock cycle, including the following steps: Step S701: Monitor the second access transaction in the write data state on the AHB bus in real time, obtain the write data of the second access transaction, and determine whether the write data is outside the address monitoring range.

[0068] The system monitors the second access transaction in the valid write transfer state on the AHB bus in real time and synchronously collects the write data signal HWDATA corresponding to the write transaction. The collected write data is compared in real time with the preset data monitoring range (defined by bit-by-bit matching operation of data matching value DATA and data mask MASK) to accurately determine whether the write data is outside the data monitoring range, that is, to confirm that the write data is legal data that will not trigger illegal operations.

[0069] Step S702: If yes, then obtain the target non-idle transfer type signal, target slave selection signal, target address bus signal and target read / write control signal of the second access transaction in the current clock cycle through the bypass register.

[0070] If the write data of the second access transaction is determined to be valid, the core signals of the transaction that have been cached in the current clock cycle are retrieved from the bypass register of the AHB bus monitoring unit. Specifically, these signals include the target non-idle transmission type signal htrans[1], the target slave selection signal hsel, the target address bus signal haddr, and the target read / write control signal hwrite.

[0071] Step S703: Based on the target non-idle transmission type signal, the target slave selection signal, the target address bus signal, and the target read / write control signal, obtain the target address phase signal of the second access transaction, and send the target address phase signal to the slave of the AHB bus.

[0072] Based on the core signals retrieved above, the complete target address phase signal of the second access transaction is generated. Strictly following the AHB bus protocol timing, the target address phase signal is synchronously sent to the target slave device corresponding to the AHB bus, completing the address resolution and transmission enable pre-interaction on the slave device side.

[0073] Step S704: Obtain the target write data signal of the second access transaction in the next clock cycle through the bypass register, and send the target write data signal to the slave device.

[0074] Waiting for the next system clock cycle of the AHB bus, retrieve the cached target write data signal HWDATA from the bypass register; according to the pipelined characteristic of the AHB bus write transmission address phase and data phase being spaced one clock cycle apart, send the target write data signal to the target slave on time, and complete the full transmission of the legitimate write transaction with the transmission ready signal fed back by the slave.

[0075] Optionally, when the write data of the second access transaction in the AHB bus is detected to be within the data monitoring range, the method further includes the following steps: Step S801: Control the AHB bus to intercept the second access transaction to prevent the second access transaction from being sent to the slave device.

[0076] When it is determined that the write data of the second access transaction in the AHB bus is within the preset data monitoring range and the data monitoring bus control flag value is enabled, the data monitoring hardware interception logic is immediately triggered to clear the non-idle transmission type signal htrans, slave selection signal hsel, address bus signal haddr and read / write control signal hwrite corresponding to the transaction cached in the bypass register, cut off the transmission path, and prevent the address and write data signals of the second access transaction from being sent to the target slave.

[0077] Step S802: Generate a transmission ready signal and a transmission response signal for the second access transaction based on the written data.

[0078] Strictly following the AHB bus protocol specification, based on the transmission attributes of the illegal write data, a standard bus response signal is generated: the transmission ready signal HREADY is set to high level to terminate the current illegal transmission, and the transmission response signal HRESP is set to ERROR to report to the host that the write data is illegal and the transmission execution has failed.

[0079] Step S803: After sequentially uploading the transmission ready signal and transmission response signal to the host of the AHB bus via the AHB bus, control the AHB bus to release the second access transaction.

[0080] Through the slave response channel of the AHB bus, the generated transmission ready signal and transmission response signal are sequentially transmitted back to the host that initiated the access according to the protocol timing, completing the hardware handshake of the abnormal write transaction; after the signal transmission is completed, the AHB bus is controlled to release the bus resources occupied by the second access transaction, restore the normal transmission link of the bus, and at the same time, the key transaction information of this illegal write access is latched and the data monitoring interruption report is triggered.

[0081] During the above process, when the data monitoring enable flag is 1, the hwdata of write transactions on the AHB bus is monitored. When hwdata is within the address monitoring range, there are two possibilities: 1. When the data monitoring bus control flag is set to 1, the second access transaction is intercepted, and the response channel of the slave device is actively taken over. The takeover steps are as follows: Intercept the write access of the second access transaction, clear the htrans (non-IDLE transmission), hsel, haddr, and hwrite cached in the cache unit during the cache phase, and prevent the write access of the second access transaction from being sent to the slave. Return hready=1 to the host (end the current transfer); It also returns hresp=ERROR (indicating a transmission error); After completing the above transmission, release the AHB bus to allow subsequent transactions to continue.

[0082] 2. When the data monitoring bus control flag value is configured to 0, the AHB bus will not be controlled to perform interception. At the same time, htrans (non-IDLE transmission), hsel (slave selection), haddr, and hwrite in the bypass register will be sent to the slave, and the cached hwdata will be sent in the next clock cycle.

[0083] Optionally, the method also includes a timeout monitoring function, specifically comprising the following steps: Step S901: Using the first access transaction or the second access transaction as the target access transaction, obtain the start time of the target access transaction in the AHB bus.

[0084] The first or second access transaction currently in a valid transmission state on the AHB bus is identified as the target access transaction. Based on the valid level of the AHB bus slave select signal hsel and the non-idle transmission type signal htrans[1], the transmission start time of the target access transaction is accurately identified. The bus clock cycle is used as the timing reference, and the transmission start time of the target access transaction on the AHB bus is statistically obtained in real time through a dedicated timeout counter.

[0085] Step S902: When the startup duration exceeds the preset timeout threshold, save the current address bus signal, current non-idle transfer type signal, current read / write control signal, and current write data signal of the target access transaction in the AHB bus to the bypass register.

[0086] When the real-time transmission start-up time exceeds the preset programmable timeout threshold, it is determined that the target access transaction has a bus transmission timeout fault; immediately the core bus signals of the target access transaction at the current moment, including the current address bus signal haddr, the current non-idle transmission type signal htrans[1], the current read / write control signal hwrite, and the current write data signal hwdata, are latched as timeout fault field data and saved to the bypass register of the AHB bus maintenance unit, so as to provide complete original transaction information for fault location and debugging.

[0087] Step S903: Control the AHB bus to intercept the target access transaction to prevent the target access transaction from being sent to the slave device. Generate the transmission ready signal and transmission response signal of the target access transaction based on the write data. Then, upload the transmission ready signal and transmission response signal to the AHB bus master in sequence through the AHB bus. Finally, control the AHB bus to release the target access transaction.

[0088] The timeout monitoring hardware takeover logic is triggered, controlling the AHB bus to intercept the target access transaction, cutting off the transmission path to prevent the target access transaction from being sent to the corresponding slave device; following the AHB bus protocol specification, a transmission ready signal HREADY and a transmission response signal HRESP are generated, setting the transmission ready signal to a high level to terminate the current transmission, and setting the transmission response signal to an ERROR error state to report the transmission failure; the above two signals are sequentially returned to the host that initiated the access through the AHB bus slave response channel according to the protocol timing, completing the hardware handshake of the abnormal transmission; after the signal return is completed, the AHB bus is controlled to release the bus resources occupied by the target access transaction, and normal bus transmission can be restored without system reset.

[0089] Based on all the content in the above embodiments, refer to Figure 3 Another bus data processing method, as shown, achieves secure control, anomaly interception, and timing adaptation of bus access transactions through the collaborative design of address monitoring, data monitoring, and bypass caching. The architecture and workflow are described in detail below in conjunction with module interaction and signal flow: Master: The initiator of bus access transactions, responsible for sending read and write requests to slave devices, and can also configure address monitoring and data monitoring rule parameters.

[0090] AHB bus: The communication carrier between the master and slave devices, carrying the transmission of address signals, control signals, read / write data signals and response signals, following the "address phase - data phase" pipeline timing.

[0091] Slave: The responding end of a bus access transaction, receives signals from the master and performs corresponding operations, and feeds back transmission status signals (such as HREADY, HRESP).

[0092] Address monitoring module: Collects bus addresses and control signals in real time, compares them with the preset address monitoring range, realizes proactive interception of access to sensitive addresses, and provides transaction context for data monitoring module.

[0093] Data monitoring module: Combines the transaction context of the address monitoring module with the write data in the bypass register cache, and compares it with the preset data monitoring range to actively intercept illegal write data.

[0094] Bypass register: Buffers the address phase signal and write data signal of a transaction according to the AHB clock cycle, provides pre-buffered data for data monitoring, and latches the on-site information of abnormal transactions.

[0095] Address / Data Monitoring Range Configuration Module: Based on the enable type parameters and bus type parameters configured on the host, it dynamically generates the address monitoring range (sensitive address range) and the data monitoring range (illegal data feature range), providing a basis for judgment for the monitoring module.

[0096] The signal interaction logic of each module is as follows: Monitoring rule configuration process: The host writes enable type parameters and bus type parameters to the address / data monitoring range configuration module; the configuration module generates the address monitoring range and data monitoring range based on the above parameters, and outputs them to the address monitoring module and data monitoring module to complete the monitoring rule initialization.

[0097] Address monitoring link: The address signals and control signals (htrans, hsel, hwrite) of the AHB bus are input to the address monitoring module; the address monitoring module compares the address signals with the address monitoring range on the one hand, transmits the transaction context signals to the data monitoring module on the other hand, and outputs the bus signals to the bypass register for buffering.

[0098] Data monitoring link: The write data signal of the bypass register cache is input to the data monitoring module. Combined with the transaction context transmitted by the address monitoring module, the data monitoring module compares the write data with the data monitoring range and outputs an intercept or allow control signal.

[0099] Transaction transmission link: The host initiates an access transaction to the slave through the AHB bus. The address phase signal and write data signal are sent to the slave in sequence after being controlled by the address monitoring module and the data monitoring module. The slave's response signal is sent back to the host through the AHB bus.

[0100] The complete workflow of the bus data processing method is as follows: 1. Address phase stage: monitoring rule verification and signal buffering.

[0101] After the host initiates an access transaction, the address signal and control signal are transmitted to the address monitoring module via the AHB bus: The address monitoring module compares the collected address signals with the address monitoring range: If the address falls within the monitoring range (sensitive address access): trigger the interception logic, block the transmission of the transaction to the slave device, generate HREADY (high level) and HRESP (ERROR) signals to send back to the master device, and write the bus signal of the abnormal transaction into the bypass register for latching, and then release the bus resources.

[0102] If the address is not within the monitoring range: the transaction context signal is transmitted to the data monitoring module, and the address signal and control signal are buffered by the bypass register according to the clock cycle to prepare for subsequent data monitoring.

[0103] 2. Data Phase Stage: Data monitoring and transaction timing control.

[0104] The host's write data signal is transmitted to the data monitoring module in the next clock cycle (and is simultaneously buffered by the bypass register): The data monitoring module compares the written data with the data monitoring range: If the data to be written is outside the monitoring range (legitimate data): the control bypass register, according to the AHB bus timing, first sends the address phase signal to the slave to complete the address resolution, and then sends the write data signal in the next clock cycle to realize the normal transmission of legitimate transactions. The slave then sends back the HREADY high-level signal to complete the handshake.

[0105] If the write data is within the monitoring range (illegal data): trigger the interception logic, block the transmission of write data to the slave device, generate an error response signal and send it back to the master device, and simultaneously write the write data signal of the abnormal transaction into the bypass register for latching, and then release the bus resources.

[0106] 3. Timeout monitoring and anomaly tracing.

[0107] The address monitoring module and the data monitoring module simultaneously monitor the transaction transmission start time: when the transaction transmission time exceeds the preset timeout threshold, the timeout interception logic is triggered, the current bus signal is written into the bypass register for latching, the transmission of the transaction to the slave is blocked, an error response signal is generated and sent back to the master and the bus resources are released; the abnormal transaction signals cached in the bypass register can be used for subsequent fault location and debugging.

[0108] As can be seen from the above bus data processing method, this method can use the read and write address data and write data of the access transaction to perform real-time address monitoring, data monitoring and timeout monitoring of the access transaction data signals in the AHB bus, realizing the collaborative multiplexing of multiple monitoring functions. Through the collaborative multiplexing of the above-mentioned multiple monitoring functions, abnormal access transactions can be actively intercepted, thereby avoiding system crashes caused by bus hangs and illegal access. In addition, this method caches the historical data signals and abnormal data signals of access transactions through bypass registers, which can quickly locate problems during abnormal debugging and greatly improve the execution efficiency of abnormal debugging.

[0109] Corresponding to the above-described bus data processing method embodiments, this invention also provides a bus data processing system, such as... Figure 4 As shown, the system includes: Parameter caching setting module 100: generates the address monitoring range and data monitoring range of the access transaction through the enable type parameter and bus type parameter of the access transaction in the AHB bus, and caches the address phase signal and write data signal of the access transaction into the bypass register of the AHB bus according to the clock cycle of the AHB bus. Address monitoring module 200: When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, control the AHB bus to release the first access transaction; Data monitoring module 300: When it is detected that the write data of the second access transaction in the AHB bus is outside the data monitoring range, it sends the target address phase signal of the second access transaction to the slave of the AHB bus through the bypass register, and controls the bypass register to send the target write data signal of the second access transaction to the slave in the next clock cycle.

[0110] As can be seen from the above bus data processing system, the system can use the read and write address data and write data of access transactions to perform real-time address monitoring, data monitoring and timeout monitoring of access transaction data signals in the AHB bus. It realizes the collaborative multiplexing of multiple monitoring functions. Through the collaborative multiplexing of the above monitoring functions, abnormal access transactions can be actively intercepted, thereby avoiding system crashes caused by bus hangs and illegal access. In addition, the system caches historical data signals and abnormal data signals of access transactions through bypass registers, which can quickly locate problems during abnormal debugging and greatly improve the execution efficiency of abnormal debugging.

[0111] The bus data processing system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned bus data processing method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned bus data processing method embodiment.

[0112] This embodiment also provides an electronic device, the structural schematic diagram of which is shown below. Figure 5 As shown, the device includes a processor 101 and a memory 102; wherein, the memory 102 is used to store one or more computer instructions, which are executed by the processor to implement the steps of the bus data processing method described above.

[0113] Figure 5 The electronic device shown also includes a bus 103 and a communication interface 104, with the processor 101, communication interface 104 and memory 102 connected via the bus 103.

[0114] The memory 102 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The bus 103 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0115] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and to send encapsulated IPv4 packets or IPv4 packets to the user terminal through the network interface.

[0116] Processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. The processor 101 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 102. The processor 101 reads the information in memory 102 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0117] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the bus data processing method described in the foregoing embodiments.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, devices, and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0119] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0121] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A bus data processing method, characterized in that, The method includes: The address monitoring range and data monitoring range of the access transaction are generated by using the enable type parameter and bus type parameter of the access transaction in the AHB bus, and the address phase signal and write data signal of the access transaction are cached in the bypass register of the AHB bus according to the clock cycle of the AHB bus. When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the AHB bus is controlled to release the first access transaction. When the write data of the second access transaction in the AHB bus is detected to be outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave of the AHB bus through the bypass register, and in the next clock cycle, the bypass register is controlled to send the target write data signal of the second access transaction to the slave. The address monitoring range and data monitoring range of the access transaction are generated by using the enable type parameter and bus type parameter of the access transaction in the AHB bus, including: Obtain the enable type parameter of the access transaction in the AHB bus, and use the address monitoring type and data monitoring type corresponding to the enable type parameter to obtain the address monitoring enable flag value and data monitoring enable flag value of the access transaction respectively. Obtain the bus type parameter of the access transaction in the AHB bus, and use the address monitoring type and data monitoring type corresponding to the bus type parameter to determine the address monitoring bus flag value and data monitoring bus flag value of the access transaction; The target address attribute value of the access transaction is obtained by using the data monitoring enable flag value and the address monitoring bus flag value, and the address monitoring range of the access transaction is generated by using the minimum address and the maximum address determined by the target address attribute value. The matching value and mask value of the target data of the access transaction are obtained by using the data monitoring enable flag value and the data monitoring bus flag value, and the data monitoring range of the access transaction is generated by using the data bit matching result of the matching value and the mask value.

2. The bus data processing method according to claim 1, characterized in that, The address phase signal and write data signal of the access transaction are buffered into the bypass register of the AHB bus according to the clock cycle of the AHB bus, including: The address phase signal is determined by using the non-idle transfer type signal, slave selection signal, address bus signal and read / write control signal of the access transaction in the AHB bus, and the write data signal of the access transaction in the AHB bus is obtained. When the slave selection signal is detected to be high, the non-idle transfer type signal is detected to be high, and the read / write control signal is detected to be high, it is determined whether the address bus signal appears in the AHB bus in the current clock cycle and whether the write data signal appears in the AHB bus in the next clock cycle. If so, the address phase signal and the write data signal are buffered into the bypass register of the AHB bus per unit clock cycle.

3. The bus data processing method according to claim 1, characterized in that, When the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range, the step of controlling the AHB bus to release the first access transaction includes: The system monitors the first access transaction in the data read / write state on the AHB bus in real time, obtains the read / write address in the first access transaction, and determines whether the read / write address is within the address monitoring range. If so, the AHB bus is controlled to intercept the first access transaction to prevent the first access transaction from being sent to the slave device of the AHB bus; The first access transaction's transmission ready signal and transmission response signal are generated based on the read / write address; After the transmission ready signal and the transmission response signal are sequentially uploaded to the host of the AHB bus via the AHB bus, the host controls the AHB bus to release the first access transaction.

4. The bus data processing method according to claim 3, characterized in that, After controlling the AHB bus to release the first access transaction, the method further includes: Based on the AHB bus, the target address bus signal, target non-idle transfer type signal, target read / write control signal, and target write data signal of the first access transaction are obtained. The target address bus signal, the target non-idle transfer type signal, the target read / write control signal, and the target write data signal are saved to the bypass register.

5. The bus data processing method according to claim 1, characterized in that, When it is detected that the write data of the second access transaction in the AHB bus is outside the data monitoring range, the target address phase signal of the second access transaction is sent to the slave device of the AHB bus through the bypass register, and in the next clock cycle, the bypass register is controlled to send the target write data signal of the second access transaction to the slave device, including: The system monitors the second access transaction in the write data state on the AHB bus in real time, obtains the write data of the second access transaction, and determines whether the write data is outside the address monitoring range. If so, the target non-idle transfer type signal, target slave selection signal, target address bus signal, and target read / write control signal of the second access transaction in the current clock cycle are obtained through the bypass register; The target address phase signal of the second access transaction is obtained based on the target non-idle transmission type signal, the target slave selection signal, the target address bus signal, and the target read / write control signal, and the target address phase signal is sent to the slave of the AHB bus. The target write data signal of the second access transaction in the next clock cycle is obtained through the bypass register, and the target write data signal is sent to the slave device.

6. The bus data processing method according to claim 1, characterized in that, When the write data of the second access transaction in the AHB bus is detected to be within the data monitoring range, the method further includes: The AHB bus is controlled to intercept the second access transaction, thereby preventing the second access transaction from being sent to the slave device; Based on the written data, generate the transmission ready signal and transmission response signal for the second access transaction; After the transmission ready signal and the transmission response signal are sequentially uploaded to the host of the AHB bus via the AHB bus, the host controls the AHB bus to release the second access transaction.

7. The bus data processing method according to claim 1, characterized in that, The method further includes: Using the first access transaction or the second access transaction as the target access transaction, obtain the startup duration of the target access transaction in the AHB bus; When the startup duration exceeds the preset timeout threshold, the current address bus signal, current non-idle transfer type signal, current read / write control signal, and current write data signal of the target access transaction in the AHB bus are saved to the bypass register. After the target access transaction is intercepted by the AHB bus to prevent it from being sent to the slave device, a transmission ready signal and a transmission response signal for the target access transaction are generated based on the write data. The transmission ready signal and the transmission response signal are then uploaded to the host device of the AHB bus via the AHB bus. Finally, the AHB bus is controlled to release the target access transaction.

8. A bus data processing system, characterized in that, The system includes: Parameter caching setting module: Generates the address monitoring range and data monitoring range of the access transaction through the enable type parameter and bus type parameter of the access transaction in the AHB bus, and caches the address phase signal and write data signal of the access transaction into the bypass register of the AHB bus according to the clock cycle of the AHB bus. Address monitoring module: used to control the AHB bus to release the first access transaction when the read / write address of the first access transaction in the AHB bus is detected to be within the address monitoring range; Data monitoring module: When it is detected that the write data of the second access transaction in the AHB bus is outside the data monitoring range, it sends the target address phase signal of the second access transaction to the slave of the AHB bus through the bypass register, and controls the bypass register to send the target write data signal of the second access transaction to the slave in the next clock cycle; In the process of generating the address monitoring range and data monitoring range of the access transaction by accessing the transaction through the AHB bus, the parameter cache setting module is further configured to: obtain the enable type parameter of the access transaction in the AHB bus; obtain the address monitoring enable flag value and data monitoring enable flag value of the access transaction using the address monitoring type and data monitoring type corresponding to the enable type parameter; obtain the bus type parameter of the access transaction in the AHB bus; determine the address monitoring bus flag value and data monitoring bus flag value of the access transaction using the address monitoring type and data monitoring type corresponding to the bus type parameter; obtain the target address attribute value of the access transaction using the data monitoring enable flag value and the address monitoring bus flag value; generate the address monitoring range of the access transaction using the minimum address and the maximum address determined by the target address attribute value; obtain the matching value and mask value of the target data of the access transaction using the data monitoring enable flag value and the data monitoring bus flag value; and generate the data monitoring range of the access transaction using the data bit matching result of the matching value and the mask value.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the steps of the bus data processing method according to any one of claims 1 to 7.

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