Storage controller device, computing system, and method of operating a computing system

Abstract

This disclosure relates to a storage controller device, a computing system, and a method for operating the computing system. A storage controller device is coupled to a host computer, a storage memory, and a computing memory, and configured to directly move data between the storage memory and the computing memory. The storage controller device is configured to perform computational operations on computational data transferred from the host computer and computational data transferred from the computing memory.

Description

[0001] Cross-references to related applications This application claims priority to U.S. Patent Application No. 63 / 756,914, filed February 11, 2025; Korean Application No. 10-2026-0001159, filed January 5, 2026 with the Intellectual Property Office; and U.S. Patent Application No. 19 / 535,430, filed February 10, 2026, which are incorporated herein by reference in their entirety. Technical Field

[0002] The various implementations generally relate to integrated circuit technology, and more specifically, to a memory controller device configured to perform computation, a multi-chip package using the memory controller device, and a computing system using the memory controller device. Background Technology

[0003] Traditional computing systems can include a host, main memory, on-chip memory, and storage memory. Typically, because memory manufacturers manufacture main memory, on-chip memory, and storage memory together, they can be packaged into a single package and offered as a multi-chip package. Since the main memory does not have a separate connection to the on-chip memory, it can be located within the multi-chip package or outside of it. Large volumes of data, such as big data, can be stored in storage memory. To perform computational operations using big data, the host can move data stored in storage memory to main memory and perform computational operations while performing data input / output operations with main memory. However, data stored in storage memory is provided to the host via the on-chip memory, and the serial link connecting the on-chip memory and the host has limited bandwidth. Therefore, moving data from storage memory to main memory can take a significant amount of time, and the performance of the computing system can degrade. Summary of the Invention

[0004] In one embodiment, a memory controller device includes a serial interface, a memory controller, a memory engine, and a memory interface. The serial interface can be coupled to a host and an internal bus. The memory controller can be coupled to the internal bus and can be coupled to storage memory via the memory bus. The memory controller can be coupled to the internal bus. The computing engine can be coupled to the internal bus. The memory interface can be coupled to computing memory via the memory bus and can be configured to selectively couple the computing engine and the memory controller to the data bus of the memory bus based on command address signals of the memory bus.

[0005] In one embodiment, a computing system includes a host and a storage controller device. The host may be coupled to main memory via a first memory bus. The storage controller device may be coupled to the host via a serial bus, coupled to storage memory via a storage bus, and coupled to computing memory via a second memory bus. The storage controller device may be configured to perform computations on first computational data transmitted from the host via the serial bus and second computational data provided from the computing memory via the second memory bus.

[0006] In one embodiment, a method of operating a computing system includes providing first computational data to a storage memory via a storage controller device from a host computer. The method may include directly moving the first computational data stored in the storage memory to the computing memory via the storage controller device. The method may also include: providing second computational data to the storage controller device from the host computer; and providing the first computational data to the storage controller device from the computing memory. The method may further include performing computational operations on the first and second computational data by the storage controller device. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1 The diagram shows the configuration and connection relationships of the memory controller, memory interface, computing memory, and computing engine.

[0009] Figure 3A , Figure 3B and Figure 3C This is a diagram illustrating the operation of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0010] Terms such as "first," "second," etc., are used to distinguish different elements and do not imply the size, order, priority, quantity, or importance of these elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element, it may be directly on, directly connected to, or directly coupled to that other element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intermediate elements.

[0011] Various embodiments of this disclosure relate to a memory controller device that integrates data movement, memory control, and computing capabilities, as well as a multi-chip package and computing system incorporating the memory controller device. In conventional computing systems, computational operations on large amounts of data stored in memory typically require data transfer to the host and main memory via a serial interface, which can become a performance bottleneck due to limited bandwidth. Various embodiments of this disclosure address this limitation by performing computational operations within or near the memory controller device, thereby reducing data movement through bandwidth-constrained interfaces.

[0012] According to various embodiments of this disclosure, the storage controller device may include: a serial interface for communicating with a host, a storage controller coupled to a storage memory, a storage controller coupled to a compute memory, a compute engine configured to perform computations, and a storage interface configured to selectively couple the storage controller or compute engine to a memory bus. With this architecture, data can be moved directly between the storage memory and the compute memory under the control of the storage controller device, and computational operations can be performed using computational data provided from the host and computational data stored in the compute memory without routing such data via the host or main memory.

[0013] Furthermore, various embodiments of this disclosure provide a computing system and a method of operating the computing system, wherein computational operations are performed in coordination with data transfer between the storage controller device and the host, the storage memory, and the compute memory. In one embodiment, overall system performance can be improved by allowing large volumes of computational data to be provided from the compute memory and smaller volumes of computational data to be provided from the host, and by performing computations within the storage controller device. Additionally, in one embodiment, because the disclosed architecture can be implemented in a single package or a multi-chip package, compatibility with existing host systems can be maintained, and computational efficiency improvements can be achieved for applications such as artificial intelligence and high-performance computing.

[0014] Figure 1 This is a diagram illustrating the configuration of a computing system 100 according to an embodiment of the present disclosure. (Refer to...) Figure 1The computing system may include a host 110, main memory 120, a storage controller device 130, storage memory 140, and computing memory 150. The host 110 can perform one or more operations based on user input and can control signal processing within the computing system 100. The host 110 can perform data communication with the main memory 120 and can perform data communication with the storage memory 140 via the storage controller device 130. The host 110 can be coupled to the storage controller device 130 via a serial bus 101 and can communicate with the storage controller device 130 via the serial bus 101. The host 110 can transmit system command address signals and data to the storage controller device 130 via the serial bus 101 and can receive data transmitted from the storage controller device 130 via the serial bus 101. The serial bus 101 may include one of PCIe (PCIe, Universal Component Interconnect), UFS (Universal Flash Memory), and UCIe (Universal Chip Interconnect). The host 110 can be coupled to the main memory 120 via the first memory bus 102 and can communicate with the main memory 120 via the first memory bus 102. The host 110 can transmit memory command address signals and data to the main memory 120 via the first memory bus 102, and can receive data transmitted from the main memory 120 via the first memory bus 102. The host 110 may include at least one processor. The processor may include one or more of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and an application processor (AP).

[0015] Main memory 120 is coupled to host 110 via first memory bus 102 and can store data provided by host 110. Main memory 120 stores data related to operations and programs executed by host 110, and host 110 can quickly access the data stored in main memory 120. Main memory 120 can be volatile memory. For example, main memory 120 can be DRAM (Dynamic Random Access Memory) and may include one of DDR (Double Data Rate) RAM, LPDDR (Low Power Double Data Rate) RAM, and GDDR (Graphics Double Data Rate) RAM. In addition, main memory 120 may include one of three-dimensional stacked memory, HBM (High Bandwidth Memory), and HMC (Hybrid Memory Cube). Main memory 120 can communicate with host 110 via first memory bus 102. Main memory 120 can receive memory command address signals from host 110, and based on the memory command address signals, can store data transferred from host 110, or can output data stored in main memory 120 to host 110.

[0016] Storage controller device 130 may be coupled to host 110 via serial bus 101. Storage controller device 130 may be coupled to storage memory 140 via storage bus 103. Storage controller device 130 may be coupled to compute memory 150 via second memory bus 104. Storage controller device 130 may not have a separate connection to main memory 120. Storage controller device 130 may relay communication between host 110, storage memory 140, and compute memory 150. Storage controller device 130 may control data input / output operations between host 110 and storage memory 140. Storage controller device 130 may receive a first command address signal from host 110 via serial bus 101 and may control data movement between host 110 and storage memory 140 based on the first command address signal. Storage controller device 130 may generate a storage command address signal based on the first command address signal. The storage command address signal may include a storage write command address signal and a storage read command address signal. During a write operation to the storage memory, the storage controller device 130 can generate a storage write command address signal based on a first command address signal, and can send the storage write command address signal and data transferred from the host 110 to the storage memory 140 via the storage bus 103. The storage memory 140 can store the data transferred via the storage bus 103 in the storage memory 140 based on the storage write command address signal. During a read operation to the storage memory, the storage controller device 130 can generate a storage read command address signal based on the first command address signal, and can send the storage read command address signal to the storage memory 140 via the storage bus 103. The storage memory 140 can output the data stored in the storage memory 140 based on the storage read command address signal, and can send the data to the storage controller device 130 via the storage bus 103. The storage controller device 130 can send data received via the storage bus 103 to the host 110 via the serial bus 101. The storage memory 140 may include a non-volatile memory device that can be used as a storage-level memory. For example, the storage memory 140 may include flash memory, PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), and FRAM (ferroelectric RAM).

[0017] The storage controller device 130 can control data input / output operations between the host 110 and the computing memory 150. The storage controller device 130 can receive a second command address signal from the host 110 via a serial bus 101, and can control data movement between the host 110 and the computing memory 150 based on the second command address signal. The storage controller device 130 can generate a memory command address signal based on the second command address signal. The memory command address signal may include a memory write command address signal and a memory read command address signal. During a memory write operation, the storage controller device 130 can generate a memory write command address signal based on the second command address signal, and can send the memory write command address signal and the data transferred from the host 110 to the computing memory 150 via a second memory bus 104. As used herein, the memory bus may include one or more command address buses, data buses, or combinations thereof for communicating with the memory device. The computing memory 150 can store the data transferred via the second memory bus 104 in the computing memory 150 based on the memory write command address signal. During a memory read operation, the memory controller device 130 can generate a memory read command address signal based on the second command address signal, and can send the memory read command address signal to the compute memory 150 via the second memory bus 104. The compute memory 150 can output data stored in the compute memory 150 based on the memory read command address signal, and can send the data to the memory controller device 130 via the second memory bus 104. The memory controller device 130 can send data received via the second memory bus 104 to the host 110 via the serial bus 101. The compute memory 150 may include a volatile memory device. For example, the compute memory 150 may include one of DDR (Double Data Rate) RAM, LPDDR (Low Power Double Data Rate) RAM, and GDDR (Gift DDR) RAM. In one embodiment, the second memory bus 104 may be a wide input / output bus that can provide high bandwidth, and the computing memory 150 may include one of the following: a three-dimensional stacked (3DS) memory including multiple dies coupled by wire bonding, an HBM (high bandwidth memory) including multiple dies coupled by TSV, and an HMC (hybrid memory cube).

[0018] The storage controller device 130 can control the data input / output operations between the storage memory 140 and the computing memory 150. The storage controller device 130 can receive a first command address signal and a second command address signal from the host 110 via the serial bus 101, and can control the data movement between the storage memory 140 and the computing memory 150 based on the first and second command address signals. When data moves from the storage memory 140 to the computing memory 150, the storage controller device 130 can generate a storage read command address signal based on the first command address signal, and can generate a storage write command address signal based on the second command address signal. The storage controller device 130 can send the storage read command address signal to the storage memory 140 via the storage bus 103, and can send the storage write command address signal to the computing memory 150 via the second memory bus 104. The storage memory 140 can output the data stored in the storage memory 140 based on the storage read command address signal, and can send the data to the storage controller device 130 via the storage bus 103. The storage controller device 130 can send data transmitted via the storage bus 103 to the computing memory 150 via the second memory bus 104. The computing memory 150 can store the data transmitted via the second memory bus 104 in the computing memory 150 based on a memory write command address signal. Conversely, when data moves from the computing memory 150 to the memory 140, the storage controller device 130 can generate a storage write command address signal based on a first command address signal and a memory read command address signal based on a second command address signal. The storage controller device 130 can send the storage write command address signal to the storage memory 140 via the storage bus 103 and the memory read command address signal to the computing memory 150 via the second memory bus 104. The computing memory 150 can output the data stored in the computing memory 150 based on the memory read command address signal and can send the data to the storage controller device 130 via the second memory bus 104. The storage controller device 130 can also send data transmitted via the second memory bus 104 to the storage memory 140 via the storage bus 103. The storage memory 140 can store data transmitted via the storage bus 103 in the storage memory 140 based on the storage write command address signal.

[0019] The storage controller device 130 can perform computational operations. The storage controller device 130 can receive first computational data from the host 110 and second computational data from the computational memory 150, and can perform computational operations on the first and second computational data. Computational operations can include linear operations (e.g., GEMV (Generalized Matrix-Vector Multiplication) operations) and nonlinear operations (e.g., activation function operations). For example, the first computational data can be vector data, and the second computational data can be weight data. The storage controller device 130 can receive a computational command address signal from the host 110 via a serial bus 101, and can perform computational operations based on the computational command address signal. The storage controller device 130 can generate a memory read command address signal based on the computational command address signal, and can send the memory read command address signal to the computational memory 150 via a second memory bus 104. The computational memory 150 can output the data stored in the computational memory 150 as the second computational data based on the memory read command address signal. The storage controller device 130 can receive the second computational data via the second memory bus 104. The storage controller device 130 can receive first computation data from the host 110 via a serial bus 101. The storage controller device 130 can perform computation operations on the first and second computation data to generate computation result data. The storage controller device 130 can provide the computation result data to at least one of the host 110, the storage memory 140, and the computing memory 150. For example, the storage controller device 130 can store the computation result data in the computing memory 150, and then move the computation result data from the computing memory 150 to at least one of the host 110 and the storage memory 140.

[0020] The storage controller device 130 may include a serial interface 131, a storage controller 132, a memory controller 133, a computing engine 134, and a memory interface 135. The serial interface 131 may be coupled to the host 110 via a serial bus 101 and may also be coupled to the internal bus 136 of the storage controller device 130. The storage controller device 130 may communicate with the host 110 via the serial interface 131. The serial interface 131 may output a first command address signal, a second command address signal, a computing command address signal, and data transmitted from the host 110 via the serial bus 101 to the internal bus 136, and may also send data transmitted via the internal bus 136 to the host 110 via the serial bus 101.

[0021] The storage controller 132 can be coupled to the internal bus 136 and to the storage memory 140 via the storage bus 103. As used herein, a storage controller refers to a hardware circuit block configured to manage access to the storage memory, including generating storage command address signals and controlling data transfers. The storage controller 132 can communicate with the storage memory 140 via the storage bus 103. The storage controller 132 can receive a first command address signal via the internal bus 136, generate a storage command address signal from the first command address signal, and provide the storage command address signal to the storage memory 140 via the storage bus 103. The storage controller 132 can receive data transmitted from the serial interface 131 via the internal bus 136 and provide the received data to the storage memory 140 via the storage bus 103. The storage controller 132 can receive data transmitted from the storage memory 140 via the storage bus 103 and can send the received data back to the internal bus 136.

[0022] Memory controller 133 can be coupled to compute memory 150 via second memory bus 104. As used herein, a memory controller refers to a hardware circuit block configured to control access to memory devices via a memory bus (including generating memory command address signals and managing data transfers). Memory controller 133 can communicate with compute memory 150 via second memory bus 104. Memory controller 133 can receive a second command address signal and a compute command address signal from serial interface 131 via internal bus 136, generate a memory command address signal from the second command address signal and the compute command address signal, and provide the memory command address signal to compute memory 150 via second memory bus 104. Memory controller 133 can receive data transmitted via internal bus 136 and provide the received data to compute memory 150 via second memory bus 104. Memory controller 133 can receive data transmitted from compute memory 150 via second memory bus 104 and can send the received data to internal bus 136.

[0023] Computation engine 134 may be coupled to internal bus 136 and second memory bus 104. As used herein, the computation engine may perform one or more arithmetic, logical, or data processing operations on data received via one or more buses. Computation engine 134 may receive first computation data via internal bus 136 and second computation data via second memory bus 104. Computation engine 134 may perform computation operations on the first and second computation data to generate computation result data. Computation engine 134 may include multiple processing elements, artificial intelligence accelerators, and data computation engines designed to efficiently perform specific computational tasks. Computation engine 134 may store computation result data and may output the computation result data to second memory bus 104.

[0024] Memory interface 135 can be coupled to memory controller 133 and computing engine 134, and can be coupled to computing memory 150 via second memory bus 104. As used herein, a data bus refers to one or more signal lines configured to transmit data and can form part of a memory bus. Memory interface 135 can receive memory command address signals and data from memory controller 133, and can send data to computing memory 150 via second memory bus 104. Memory interface 135 can receive data from computing memory 150 via second memory bus 104, and can send the data to one of memory controller 133 and computing engine 134. Second memory bus 104 may include a command address bus and a data bus. Memory command address signals can be transmitted from memory interface 135 to computing memory 150 via command address bus. Data can be transmitted between memory interface 135 and computing memory 150 via data bus. Memory interface 135 can selectively couple memory controller 133 and computing engine 134 to computing memory 150. When host 110 performs data input / output operations with compute memory 150, and when data moves between storage memory 140 and compute memory 150, memory interface 135 can couple memory controller 133 to compute memory 150 via the data bus of second memory bus 104. When performing computation operations, memory interface 135 can couple compute engine 134 to compute memory 150 via the data bus of second memory bus 104. Memory interface 135 can selectively couple memory controller 133 and compute engine 134 to the data bus of second memory bus 104 based on memory command address signals. As used herein, command address signals can include memory command address signals, compute command address signals, or signals derived therefrom. For example, memory interface 135 can couple one of memory controller 133 and compute engine 134 to the data bus based on the logic level of at least one bit of a memory command address signal received from memory controller 133. The memory command address signal may contain at least one bit that distinguishes whether the memory command address signal is generated by the second command address signal or by the compute command address signal. When the memory command address signal is generated based on the second command address signal, the memory interface 135 can couple the data bus of the second memory bus 104 to the memory controller 133, allowing data to be transferred between the memory controller 133 and the compute memory 150. When the memory command address signal is generated based on the compute command address signal, the memory interface 135 can couple the data bus of the second memory bus 104 to the compute engine 134, allowing data to be transferred between the compute engine 134 and the compute memory 150.In one implementation, host 110 may provide a select command address signal to memory controller device 130. Memory controller 133 may generate a path selection signal based on the select command address signal. Memory controller 133 may provide the path selection signal to memory interface 135. Memory interface 135 may couple one of memory controller 133 and computing engine 134 to a data bus based on the path selection signal. For example, when the path selection signal is logic high, memory interface 135 may couple the data bus of second memory bus 104 to memory controller 133. When the path selection signal is logic low, memory interface 135 may couple the data bus of second memory bus 104 to computing engine 134.

[0025] The storage controller device 130 may further include a storage processor 137 and a buffer memory 138. The storage processor 137 can control communication between the serial interface 131 and the storage controller 132, and can control communication between the serial interface 131 and the memory controller 133. The storage processor 137 can perform various functions. For example, the storage processor 137 can map logical addresses transmitted from the host 110 to physical addresses of the storage memory 140, can perform wear leveling on the storage memory 140, and can perform error correction on data transmitted via the storage bus 103. Furthermore, in one embodiment, the storage processor 137 can manage bad blocks in the storage memory 140 and can mitigate read interference. Additionally, the storage processor 137 can queue multiple commands transmitted from the host 110 and can schedule multiple commands according to priority to determine the processing order of the multiple commands.

[0026] In embodiments of this disclosure, the terms "computing engine," "memory interface," and "memory processor" refer to one or more hardware circuit blocks. For example, a computing engine may include one or more processing elements configured to perform computational operations, arithmetic circuitry, data paths, registers, and control logic. A memory interface may include one or more routing circuitry, multiplexers, buffers, drivers / receivers, and associated control logic configured to selectively couple data paths and command / address paths of a memory bus. A memory processor may include one or more processors or microcontrollers for controlling memory operations, state machines, address translation circuitry, error correction circuitry, and memory management logic. The foregoing examples are for illustrative purposes only, and the disclosed functionality may be implemented using various combinations of dedicated logic circuitry, programmable logic, or firmware-controlled hardware.

[0027] In one embodiment, buffer memory 138 may store data output from storage memory 140 or data to be stored in storage memory 140, and may be provided to compensate for the relatively slow speed of storage memory write and read operations. Buffer memory 138 may serve as a data cache to reduce the speed difference in operation between storage memory 140 and other components communicating with storage memory 140. Buffer memory 138 may store a mapping table to allow storage processor 137 to map logical addresses to physical addresses, and may provide this mapping table to storage processor 137. In one embodiment, buffer memory 138 may improve the efficiency of storage memory write operations to extend the lifespan of storage memory 140. Buffer memory 138 may include one of a variety of high-speed RAMs, such as SRAM (Static Random Access Memory).

[0028] In one embodiment, the memory controller device 130 and the storage memory 140 can be packaged into a single package and can be provided as a single storage device. The main memory 120 and the compute memory 150 can each be packaged into a separate package. In one embodiment, the memory controller device 130, the storage memory 140, and the compute memory 150 can be packaged into a single package and can be provided as a multi-chip package (MCP) and / or a multi-die package. The main memory 120 can be packaged into a separate package. In one embodiment, the memory controller device 130, the storage memory 140, the compute memory 150, and the main memory 120 can be packaged into a single package. In one embodiment, the memory controller device 130, the storage memory 140, the compute memory 150, and the main memory 120 can all be manufactured as chips and can be coupled to each other via chip interconnects within a multi-chip package or a multi-die package.

[0029] Figure 2 It is shown Figure 1 The diagram shows the configuration and connection relationships of the memory controller 133, memory interface 135, computing memory 150, and computing engine 134. (Refer to...) Figure 2The memory interface 135 may include routing circuitry 210. Routing circuitry 210 may be coupled to memory controller 133 and computing engine 134, and may be coupled to computing memory 150 via a second memory bus 104. Routing circuitry 210 may receive a memory command address signal CA from memory controller 133, and may receive data from or transmit data to memory controller 133. The second memory bus 104 may include a command address bus 201 and a first data bus 202. The first data bus 202 may be a set of signal transmission lines within the second memory bus 104 used for data transmission. Memory interface 135 may provide the memory command address signal CA from memory controller 133 to computing memory 150 via command address bus 201. Routing circuitry 210 may be coupled to computing engine 134 via second data bus 203. Routing circuitry 210 may selectively couple the first data bus 202 to either memory controller 133 or computing engine 134 based on the memory command address signal CA or path selection signal PSS. Routing circuit 210 can couple memory controller 133 to first data bus 202 based on at least one bit of memory command address signal CA, or it can couple computing engine 134 and / or second data bus 203 to first data bus 202. Alternatively, routing circuit 210 can couple memory controller 133 to first data bus 202 based on path selection signal PSS, or it can couple computing engine 134 and / or second data bus 203 to first data bus 202. Computing memory 150 can transmit data stored in computing memory 150 as memory data DQ1, DQ2, ..., DQn to routing circuit 210 via first data bus 202 during memory read operations, and can receive memory data DQ1, DQ2, ..., DQn via routing circuit 210 and first data bus 202 during memory write operations. Here, n can be an integer equal to or greater than 4. When routing circuit 210 connects memory controller 133 to computing memory 150, routing circuit 210 can send data transmitted from memory controller 133 as memory data DQ1, DQ2, ..., DQn to computing memory 150 via first data bus 202. Furthermore, routing circuit 210 can send memory data DQ1, DQ2, ..., DQn transmitted from computing memory 150 via first data bus 202 to memory controller 133. When routing circuit 210 connects computing engine 134 to computing memory 150, routing circuit 210 can provide memory data DQ1, DQ2, ..., DQn transmitted from computing memory 150 via first data bus 202 as second computing data PD2 to computing engine 134 via second data bus 203.

[0030] The computational memory 150 may include a memory cell array 221, a command address control circuit 222, and a data input / output circuit 223. The memory cell array 221 may include multiple memory cells capable of storing data. The memory cell array 221 may include multiple word lines arranged along the column direction and multiple bit lines arranged along the row direction, and the multiple memory cells may be coupled at the intersections of the multiple word lines and multiple bit lines. The command address control circuit 222 may receive a memory command address signal CA via a command address bus 201. The command address control circuit 222 may decode and latch the memory command address signal CA to generate internal command signals and internal address signals for the computational memory 150. The internal command signals may be provided to the memory cell array 221 and the data input / output circuit 223, and the memory cell array 221 and the data input / output circuit 223 may perform memory write operations and memory read operations based on the internal command signals. Internal address signals can be provided to the memory cell array 221, and the memory cell array 221 can select a specific word line from multiple word lines and a specific bit line from multiple bit lines based on the internal address signals, enabling access to the memory cell coupled to the specific word line and the specific bit line. During a memory read operation, the data input / output circuit 223 can generate memory data DQ1, DQ2, ..., DQn based on data read from the memory cell array 221, and can output the memory data DQ1, DQ2, ..., DQn via the first data bus 202. During a memory write operation, the data input / output circuit 223 can receive the memory data DQ1, DQ2, ..., DQn transmitted via the first data bus 202, and can provide the received data to the memory cell array 221.

[0031] The computing engine 134 may include a global buffer 231, multiple processing elements 232, and a register 233. The global buffer 231 may be coupled to an internal bus 136 and may receive first computational data PD1 transmitted via the internal bus 136. The global buffer 231 may store the first computational data PD1 and may provide the first computational data PD1 to the processing elements 232, enabling the computing engine 134 to perform computational operations. The processing elements 232 may receive the first computational data PD1 from the global buffer 231 and may receive second computational data PD2 via a second data bus 203. The processing elements 232 may perform computational operations on the first computational data PD1 and the second computational data PD2 to generate computational result data PRD. The processing elements 232 may output the computational result data PRD to the register 233. The register 233 may store the computational result data PRD and may output the computational result data PRD to the routing circuit 210 via the second data bus 203. The computational result data PRD may be transmitted to the computing memory 150 via the first data bus 202.

[0032] Figures 3A to 3C This is a diagram illustrating the operation of a computing system 100 according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 3C The computational operation of the computing system 100 according to an embodiment of this disclosure is described below. The host 110 can provide a first command address signal and second computational data PD2 to the storage controller device 130 via a serial bus 101. The storage controller 132 can generate a storage write command address signal based on the first command address signal, and can send the storage write command address signal and the second computational data PD2 to the storage memory 140 via the storage bus 103. The storage memory 140 can store the second computational data PD2 in the storage memory 140 based on the storage write command address signal.

[0033] Reference Figure 3ATo perform computational operations, the second computational data PD2 stored in storage memory 140 can be directly moved to computing memory 150. Host 110 can transmit a first command address signal and a second command address signal to storage controller device 130 via serial bus 101. Storage controller 132 can generate a storage read command address signal based on the first command address signal and can send the storage read command address signal to storage memory 140 via storage bus 103. Storage memory 140 can read the second computational data PD2 stored in storage memory 140 based on the storage read command address signal and can transmit the second computational data PD2 to storage controller 132 via storage bus 103. Memory controller 133 can generate a memory write command address signal based on the second command address signal and can provide the memory write command address signal to memory interface 135. Memory interface 135 can determine that the memory write command address signal is generated based on the second command address signal and can couple the first data bus 202 to memory controller 133. The memory interface 135 can send a memory write command address signal to the compute memory 150 via the command address bus 201. The memory controller 132 can output the second computed data PD2 to the internal bus 136, and the memory controller 133 can receive the second computed data PD2 via the internal bus 136. The memory controller 133 can provide the second computed data PD2 to the memory interface 135, and the memory interface 135 can send the second computed data PD2 to the compute memory 150 via the first data bus 202. The compute memory 150 can store the second computed data PD2 in the compute memory 150 based on the memory write command address signal. In one embodiment, the host 110 can transmit a selection command address signal to the memory controller device 130 before providing the first command address signal and the second command address signal. The memory controller 133 can generate a selection command address signal based on the selection command address signal. Figure 2 The path selection signal PSS is shown, and the memory interface 135 can couple the first data bus 202 to the memory controller 133 based on the path selection signal PSS. After the first data bus 202 is coupled to the memory controller 133 based on the path selection signal PSS, the second computed data PD2 can be moved from the storage memory 140 to the compute memory 150.

[0034] After the second computational data PD2 is moved from the storage memory 140 to the computational memory 150, the storage controller device 130 can perform computational operations via the computational engine 134. (Refer to...) Figure 3BThe host 110 can transmit a computation command address signal to the storage controller device 130 via the serial bus 101. Furthermore, the host 110 can transmit first computation data PD1 to the storage controller device 130 via the serial bus 101. The computation engine 134 can receive and store the first computation data PD1 via the internal bus 136. The memory controller 133 can generate a memory read command address signal based on the computation command address signal. The memory interface 135 can determine that the memory read command address signal is generated based on the computation command address signal and can couple the first data bus 202 to the computation engine 134. The memory interface 135 can send the memory read command signal to the computation memory 150. The computation memory 150 can read second computation data PD2 stored in the computation memory 150 based on the memory read command signal and can transmit the second computation data PD2 via the first data bus 202. The memory interface 135 can provide the second computation data PD2 transmitted via the first data bus 202 to the computation engine 134 via the second data bus 203. The computing engine 134 can perform computation operations on the first computation data PD1 and the second computation data PD2. The computing engine 134 can perform computation operations on the first computation data PD1 and the second computation data PD2 to generate computation result data PRD. In one embodiment, the host 110 can transmit a selection command address signal to the memory controller device 130 before providing the computation command address signal. The memory controller 133 can generate computation result data PRD based on this selection command address signal. Figure 2 The path selection signal PSS shown is used, and the memory interface 135 can couple the first data bus 202 to the computing engine 134 based on the path selection signal PSS.

[0035] Reference Figure 3CThe computing engine 134 can output the computation result data PRD to the memory interface 135, and the memory interface 135 can transfer the computation result data PRD to the computing memory 150. The computing memory 150 can store the computation result data PRD in the computing memory 150. The computing memory 150 can store the computation result data PRD in the computing memory 150 based on a memory write command address signal. For example, the memory write command address signal can be generated based on a computation command address signal. After the memory read command address signal is generated based on the computation command address signal and after a sufficient time has elapsed since the computing engine 134 performed the computation operation, the memory controller 133 can generate the memory write command address signal. In one embodiment, when or before the computation operation of the computing engine 134 is completed, the host 110 can provide a second command address signal to the storage controller device 130 so that the computation result data is stored in the computing memory 150, and the storage controller 133 can generate the memory write command address signal based on the second command address signal.

[0036] The host 110 can read the calculation result data PRD stored in the computing memory 150, or it can move the calculation result data PRD from the computing memory 150 to the storage memory 140. When the host 110 reads the calculation result data, it can transmit a second command address signal to the memory controller device 130 via the serial bus 101. The memory controller 133 can generate a memory read command address signal based on the second command address signal and send it to the computing memory 150. The computing memory 150 can read the calculation result data PRD based on the memory read command address signal and can transmit the calculation result data PRD via the second memory bus 104. The calculation result data PRD can be transmitted to the internal bus 136 via the memory interface 135 and the memory controller 133. The serial interface 131 can transmit the calculation result data PRD to the host 110 via the serial bus 101.

[0037] When the computation result data PRD is moved from the compute memory 150 to the storage memory 140, the host 110 can transmit a first command address signal and a second command address signal to the storage controller device 130 via the serial bus 101. The storage controller 133 can generate a memory read command address signal based on the second command address signal and send the memory read command address signal to the compute memory 150. The compute memory 150 can read the computation result data PRD based on the memory read command address signal and can transmit the computation result data PRD via the second memory bus 104. The computation result data PRD can be transmitted to the internal bus 136 via the memory interface 135 and the storage controller 133. The storage controller 132 can generate a storage write command address signal based on the first command address signal. The storage controller 132 can send the storage write command address signal and the computation result data PRD transmitted via the internal bus 136 to the storage memory 140 via the storage bus 103. The storage memory 140 can store the computation result data PRD in the storage memory 140 based on the storage write command address signal.

[0038] In the prior art, when a host performs a computational operation, it must move a large amount of computational data from storage memory to main memory. However, since the bandwidth of the serial bus is less than that of the first memory bus, the serial bus may become a bottleneck for moving computational data. The computing system 100 according to embodiments of this disclosure can perform fast computational operations without involving the host 110 by including a computing engine 134 and a computing memory 150 within the storage controller device 130. Because in one embodiment, a large amount of computational data can be moved from storage memory 140 to computing memory 150 within the storage controller device 130 without using the serial bus 101, the time and / or latency required to move computational data are reduced. In one embodiment, the computing engine 134 can receive relatively small amounts of computational data (e.g., vector data) from the host 110 and relatively large amounts of computational data (e.g., weight data) from the computing memory 150, thus enabling efficient and fast computational operations. In one implementation, the storage controller device 130 can perform computational operations in parallel and / or together with the host 110, thus supporting enhanced AI computing and HPC (high-performance computing) capabilities, and achieving high compatibility because no changes are required to the design of the host 110.

[0039] In one embodiment, the host 110 can store both the first computational data PD1 and the second computational data PD2 in the storage memory 140, and the storage controller device 130 can move the first computational data PD1 to the global buffer 231 of the computing engine 134 via the internal bus 136, and can move the second computational data PD2 from the storage memory 140 to the computing memory 150, and a plurality of processing elements 232 can perform computational operations on the first computational data PD1 provided from the global buffer 231 and the second computational data PD2 provided from the computing memory 150.

[0040] In one embodiment, host 110 may sequentially provide first computational data PD1 and second computational data PD2 to storage controller device 130. The first computational data PD1 may be stored in a global buffer 231 of computation engine 134, while the second computational data PD2 may be stored in computation memory 150. A plurality of processing elements 232 may perform computational operations on the first computational data PD1 provided from global buffer 231 and the second computational data PD2 provided from computation memory 150.

[0041] The concept has been disclosed in conjunction with examples and embodiments. Those skilled in the art will understand that various modifications, additions, combinations, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustrative rather than restrictive. Therefore, the scope of this disclosure is not limited to the description provided. All modifications within the meaning of the claims and their equivalents are included within its scope.

Claims

1. A storage controller device, comprising: A serial interface that couples the host computer to the internal bus; A storage controller, which is coupled to the internal bus and, via the storage bus, to the storage memory; A memory controller, coupled to the internal bus; The computing engine is coupled to the internal bus; as well as A memory interface, which is coupled to the computing memory via a memory bus, and selectively couples the computing engine and the memory controller to the data bus of the memory bus based on command address signals.

2. The storage controller device of claim 1, wherein, The computing engine performs calculations on first computing data provided via the internal bus and second computing data provided from the computing memory via the memory interface to generate computing result data.

3. The storage controller device of claim 2, wherein, The first calculation data is provided by the host.

4. The storage controller device of claim 2, wherein, The computing engine outputs the computing results to the memory interface.

5. The storage controller device of claim 1, wherein, The memory interface: couples the memory controller to the computing memory based on the memory command address signal; And the computing engine is coupled to the computing memory based on the computing command address signal.

6. The storage controller device of claim 1, wherein, The memory interface includes a routing circuit that couples one of the memory controller and the computing engine to the data bus of the memory bus based on the command address signal.

7. The storage controller device of claim 6, wherein, The computing engine includes: A global buffer that stores the first computed data provided via the internal bus; Multiple processing elements, which: receive first computational data from the global buffer; receive second computational data from the memory interface; and perform computations on the first computational data and the second computational data to generate computational result data; and A register that stores the calculation result data.

8. The storage controller apparatus according to claim 7, wherein, The computing memory is coupled to the routing circuit via a first data bus, and the registers and the plurality of processing elements are coupled to the routing circuit via a second data bus.

9. A computing system, comprising: The host is coupled to the main memory via a first memory bus; as well as A storage controller device, coupled to the host via a serial bus, coupled to the storage memory via a storage bus, and coupled to the computing memory via a second memory bus. The storage controller device performs calculations on first computational data transmitted from the host via the serial bus and second computational data provided from the computational memory via the second memory bus.

10. The computing system according to claim 9, wherein, The storage controller device generates calculation result data by performing the calculation on the first calculation data and the second calculation data; And to provide the calculation result data to one of the host, the storage memory, and the computing memory.

11. The computing system according to claim 9, wherein, The storage controller device includes: A serial interface that couples the serial bus and the internal bus; A storage controller, which is coupled to the internal bus and the storage bus; A memory controller, coupled to the internal bus; The computing engine, coupled to the internal bus; and A memory interface, coupled to the memory controller, the second memory bus, and the computing engine. The computing engine: receives the first computing data via the internal bus; receives the second computing data via the second memory bus and the memory interface; and performs the computing on the first computing data and the second computing data.

12. The computing system according to claim 11, wherein, The memory interface selectively couples the data bus of the second memory bus to the memory controller and the computing engine based on the command address signal.

13. The computing system according to claim 11, wherein, The memory interface includes a routing circuit that couples the data bus of the second memory bus to one of the memory controller and the computing engine based on a command address signal.

14. The computing system according to claim 9, wherein, The storage controller device, the storage memory, and the computing memory are packaged into a single package.

15. The computing system according to claim 9, wherein, The main memory, the memory controller device, the storage memory, and the computing memory are packaged into a single package.

16. A method for operating a computing system, comprising: The host computer provides the first computational data to the storage memory via the storage controller device; The storage controller device directly moves the first computational data stored in the storage memory to the computational memory; The host provides the second computational data to the storage controller device, and the computing memory provides the first computational data to the storage controller device. as well as The storage controller device performs calculation operations on the first calculation data and the second calculation data.

17. The method according to claim 16, wherein, The first computational data provided by the host includes: The host computer provides the first computed data to the storage controller device via a serial bus; The storage controller device provides the first computed data to the storage memory via the storage bus; and The first calculated data is stored in the storage memory.

18. The method according to claim 16, wherein, Directly moving the first calculated data includes: The storage memory provides the first computed data to the storage controller device; The storage controller device provides the first computational data to the computing memory; and The first computational data is stored in the computational memory.

19. The method of claim 16, further comprising: The calculation result data is generated by performing the calculation operation on the first calculation data and the second calculation data; as well as The storage controller device provides the calculation result data to the computing memory.

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