AXI-Lite-based multi-channel serial communication and interrupt multiplexing system and its control method

Abstract

This invention discloses a multi-channel serial communication and interrupt multiplexing system and its control method based on AXI-Lite. The system includes an AXI-Lite bus interface module, a multi-channel serial communication module, and a multi-channel interrupt multiplexing module, forming a hardware system with a unified clock domain. The AXI-Lite bus interface module receives access requests from the CPU and maps configuration parameters, status signals, and transmit / receive data to registers. The multi-channel serial communication module contains multiple independent full-duplex serial port channels. Each serial port channel sends an interrupt request to the multi-channel interrupt multiplexing module after receiving a complete frame of data. The multi-channel interrupt multiplexing module is connected to each serial port channel and configured to perform priority arbitration on each interrupt request, merge them into a single interrupt signal, and output it to the CPU. Upon receiving a CPU response, it distributes an interrupt response signal to the corresponding serial port. This invention improves system integration, real-time performance, and reliability, while supporting flexible configuration of serial port parameters.

Description

Technical Field

[0001] This invention relates to the field of intelligent integrated circuit technology, specifically to a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite and its control method. Background Technology

[0002] Serial ports are one of the most widely used communication interfaces in electronic devices. With the development of the Internet of Things (IoT), industrial control, and multi-peripheral systems, a single chip or board often needs to communicate with multiple serial port devices simultaneously, such as connecting to a GPS module, a wireless communication module, or multiple sensors at the same time. Furthermore, the data frame formats and communication rates of different devices vary, posing significant challenges to system integration. Traditional solutions typically employ the following methods:

[0003] Multi-serial port expansion chips are used. Some manufacturers offer multi-channel serial port expansion chips (such as the TL16C554A, which can expand to four UARTs). Although this solution can achieve multi-channel serial port expansion, each serial port channel requires an independent interrupt pin. As the number of serial port channels increases, the interrupt resources of the CPU chip will be quickly exhausted. In addition, the introduction of expansion chips increases the system hardware cost and PCB board layout area, which is not conducive to system miniaturization.

[0004] A multi-serial port IP core based on FPGA is adopted. Existing multi-channel UART IP cores have significant drawbacks: one approach allocates a separate interrupt output to each serial port channel, similar to multi-serial port expansion chips, leading to a shortage of interrupt pin resources and insufficient pin count for the CPU chip; another approach combines the interrupt lines of all serial port channels into a single output using a wired-AND method. While this reduces interrupt pin usage, it fails to distinguish the specific interrupt source, requiring the CPU chip to sequentially query all serial port channels to determine the interrupt source, thus reducing interrupt response efficiency. Furthermore, most existing multi-serial port IP cores require each serial port channel to use an independent clock source, or require external circuitry to provide clock signals corresponding to different baud rates. This not only increases the complexity of system clock design but also makes routing across multiple clock domains within the FPGA difficult, increasing the risk of metastability and affecting data transmission reliability.

[0005] Furthermore, traditional UART modules have relatively limited functionality. When receiving data, they can only convert serial byte streams into parallel data and transmit them to the CPU. Operations such as frame header recognition, frame format parsing, and data verification must all be performed by the CPU in software, which significantly increases the complexity of the CPU's software design and its computational burden. At the same time, receiving a complete frame of data often requires triggering multiple CPU interrupts (such as triggering an interrupt every time one or a few bytes are received). Frequent interrupt responses consume CPU computing resources and affect the system's real-time performance.

[0006] Therefore, there is an urgent need for a highly integrated serial communication implementation scheme that can support parallel communication of multiple independent serial ports, significantly reduce interrupt resource consumption, reduce CPU software burden, and improve system real-time performance and reliability, so as to solve the above-mentioned defects. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention aims to provide a multi-channel serial communication and interrupt multiplexing system and its control method based on AXI-Lite. It overcomes the shortcomings of existing multi-channel serial communication schemes, such as excessive interrupt resource consumption, complex clock resource design, heavy CPU software burden, and difficulties in system integration. This invention achieves parallel communication of multiple independent serial ports, significantly reducing interrupt pin and clock resource consumption, lowering the CPU computation and software design burden, and improving system integration, real-time performance, and reliability. Simultaneously, it supports flexible configuration of serial port parameters to adapt to the communication needs of different serial port devices, thus solving many shortcomings of existing multi-serial port expansion schemes.

[0008] This invention is achieved through the following technical solution:

[0009] Firstly, an AXI-Lite-based multi-channel serial communication and interrupt multiplexing system includes: an AXI-Lite bus interface module, a multi-channel serial communication module, and a multi-channel interrupt multiplexing module, forming a hardware system with a unified clock domain.

[0010] The AXI-Lite bus interface module contains 128 32-bit registers, which are used to receive access requests from the CPU. By mapping configuration parameters, status signals, and transmit / receive data to the registers, the CPU can configure the parameters of each serial port and read / write access the transmit / receive data.

[0011] The multi-channel serial communication module includes multiple independent full-duplex serial channels, each of which includes an independent receiving path and a transmitting path. The receiving path is configured to perform frame header identification and frame reception in hardware, and the transmitting path is configured to perform batch frame transmission in hardware. Each serial channel initiates an interrupt request to the multi-channel interrupt multiplexing module after receiving a complete frame of data.

[0012] The multiplexed interrupt module is connected to each serial port channel and is configured to perform priority arbitration on each interrupt request and merge it into a single interrupt signal for output to the CPU. At the same time, it reports the current interrupt source number and data status through the interrupt status word, and distributes the interrupt response signal to the corresponding serial port after receiving the CPU response.

[0013] An optional solution is that the AXI-Lite bus interface module supports the standard AXI-Lite bus protocol, adopts a 32-bit data and 9-bit address standard, and the 128 32-bit registers include a global control register, an interrupt multiplexing module control register, an interrupt multiplexing module status register, a multiplexed serial port configuration register, a data transceiver register, and a version information register; wherein,

[0014] The global control register is configured to control the system's global reset, the multiplexed interrupt module reset, and each serial port's independent reset; the interrupt multiplexing module control register is a reserved register; the interrupt multiplexing module status register is used to store the interrupt source number, FIFO data count, and single frame byte count; the multiplexed serial port configuration register is used to configure the frame format and communication parameters of each serial port; the data transceiver register includes the receive FIFO read address and transmit FIFO write address for each serial port, used for the CPU to read and write serial port data, the receive FIFO of each serial port is used to buffer received data, and the transmit FIFO is used to buffer data to be sent; the version information register is used to store the version number, release date, and release time.

[0015] An optional scheme is that the receiving path includes a serial-to-parallel conversion module, a frame receiving module, and a receiving FIFO module, with each module working together to complete the reception and buffering of a frame of data; the transmitting path includes a parallel-to-serial conversion module, a frame sending module, and a sending FIFO module, with each module working together to complete data reading, parallel-to-serial conversion, and sending; the receiving and transmitting paths control the operation of the state machine according to the configuration information in their control modules, and the top-level module of each serial port channel includes a configuration interface, a clock reset interface, a serial physical interface, a data interaction interface, and a FIFO read / write interface; the multi-channel serial communication module adopts a parameterized instantiation method to realize the expansion of up to 12 serial port channels, each serial port operates independently and in parallel, shares the same clock domain, and has independent reset signals, configuration signals, and data signals.

[0016] An optional scheme is as follows: the configuration interface includes receive frame header identifier RX_FRAME_HEAD, receive frame control RX_FRAME_CTRL, transmit frame control TX_FRAME_CTRL, baud rate and parity configuration SIO_CONFIG; the clock reset interface includes clock clk and active-high reset rst; the serial physical interface includes serial data input serial_in and serial data output serial_out; the data interaction interface includes frame upload request output upload_data_req, acknowledgment signal input upload_data_ack, and data counter. The output is `upload_data_count`; the receive FIFO interface includes read enable input `rx_fifo_rden`, data output `rx_fifo_dout`, output validity flag `rx_fifo_dvalid`, empty flag `rx_fifo_empty`, and data count `rx_fifo_dcount`; the send FIFO interface includes write enable input `tx_fifo_wren`, data input `tx_fifo_din`, write acknowledgment output `tx_fifo_wrack`, full flag `tx_fifo_full`, and data count `tx_fifo_dcount`.

[0017] An optional scheme is that the serial-to-parallel conversion module is configured to oversample and decide on the serial input data according to the configured parity enable, parity mode, and bit length parameters, identify the start bit, data bits, parity bit, and stop bit, complete the serial-to-parallel conversion, and output parallel byte data, a valid flag, and a reception error flag; the frame receiving module is configured to use the configured frame header identifier as the matching basis, match the frame header in real time according to the configured frame header byte count, frame length mode, and frame length value, parse the frame length, combine the byte data output by the serial-to-parallel conversion module into 32-bit parallel data, write it into the receive FIFO, and complete a full frame of data. After writing, an upload request signal is output, and the receiving state is reset after waiting for an acknowledgment signal. If a frame header error or length overflow occurs, the receiving FIFO is reset and frame header matching is restarted. The receiving FIFO module is configured with a synchronous first-in-first-out structure, with a bit width of 32 bits and a depth of 512, and is implemented by the FPGA on-chip BRAM to buffer a complete frame of received data. The read enable of the receiving FIFO is controlled by the CPU through the read operation of the AXI-Lite bus. When the CPU reads the receiving data address of the corresponding serial port, the receiving FIFO outputs data to the AXI-Lite bus interface module.

[0018] An optional scheme is as follows: the parallel-to-serial conversion module is configured to add start bits, parity bits, and stop bits to the input parallel data according to the configured parity enable, parity mode, and bit length parameters, convert it into a serial data stream output, and output an idle flag to indicate the serial port transmission link status; the frame transmission module is configured to identify the transmission start signal by detecting the falling edge of the transmission start bit of the transmission frame control register, read data from the transmission FIFO according to the configured transmission frame length, and split it into bytes to send to the parallel-to-serial conversion module; the transmission FIFO module is configured to adopt a synchronous first-in-first-out structure, with a bit width of 32 bits and a depth of 512, implemented by the FPGA on-chip BRAM, used to buffer the data to be transmitted written by the CPU at one time, and output a full flag, an empty flag, a data count, and a write acknowledgment signal.

[0019] An optional scheme is that the frame format configuration includes: the frame header identifier supports 1 to 4 bytes of customization, and the frame length supports fixed length mode, 1-byte variable length mode and 2-byte variable length mode; the communication parameter configuration includes: the baud rate is configured through the bit length parameter, and parity check supports three modes: no parity, odd parity and even parity.

[0020] An optional solution is that the multiplexed interrupt module includes an interrupt request encoding unit, an interrupt response unit, an interrupt status register unit, and an interrupt handling state machine, used for unified interrupt management of frame reception completion signals from multiple independent serial ports; wherein,

[0021] The interrupt request encoding unit is configured to receive upload request signals from each serial port and perform fixed priority encoding.

[0022] The interrupt status register unit is configured to latch the highest priority interrupt source number and the corresponding channel data count, and generate a 32-bit interrupt status word. The high 10 bits of the interrupt status word are the interrupt source number, and the low 22 bits are the FIFO data count and the number of bytes per frame.

[0023] The interrupt handling state machine is configured to control the arbitration, initiation, and response processes of interrupt requests;

[0024] The interrupt response unit is configured to output an upload response signal to the corresponding serial port channel based on the interrupt response signal of the CPU.

[0025] An optional approach is that the interrupt handling state machine is a four-stage state machine, including an idle state, a request source encoding state, an interrupt initiation state, and an acknowledgment return state; the workflow of the four-stage state machine includes:

[0026] In the idle state, the interrupt handling state machine controls the interrupt request encoding unit to monitor the upload request signals of each serial port in real time. When any one or more requests are detected to be valid, the process jumps to the request source encoding state.

[0027] In the request source encoding state, the interrupt handling state machine controls the interrupt request encoding unit to encode each request with a fixed priority, and controls the interrupt status register unit to latch the interrupt source number with the highest priority and the data count of the corresponding channel, and then jumps to the interrupt initiation state.

[0028] In the interrupt initiation state, the interrupt handling state machine outputs a valid interrupt request signal to the CPU, and then jumps to the response return state after waiting for the CPU to generate an interrupt response signal.

[0029] In the response return state, the interrupt handling state machine controls the interrupt response unit to generate the corresponding channel upload response signal according to the latched interrupt source number, notifying the corresponding serial port interrupt processing to be completed, and then returns to the idle state to wait for the next request.

[0030] Secondly, a control method for a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, applied to the aforementioned multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, includes the following steps:

[0031] S1: After the CPU configures the parameters of each serial port through the AXI-Lite bus interface module, the global reset is canceled, and the system enters the working state.

[0032] S2: Multiple serial ports work in parallel. The hardware of the receiving channel completes frame reception and stores it in the receiving FIFO. The CPU reads and writes the FIFO to complete data transmission and reception.

[0033] S3: After the serial port completes the reception of a frame, it initiates an upload request. The multiplexer module merges the multiplexed interrupts into a single interrupt output to the CPU after priority arbitration. The CPU reads the interrupt status word to locate the interrupt source and processes it. After receiving the CPU's response, the multiplexer module distributes a response signal to the corresponding serial port.

[0034] The multi-channel serial communication and interrupt multiplexing system and its control method based on AXI-Lite according to the present invention have the following advantages and beneficial effects compared with the prior art: They significantly save processor interrupt resources by merging interrupt requests from up to 12 serial ports into a single interrupt line, allowing the CPU to handle all serial port events with just one interrupt pin. Simultaneously, interrupt source location is achieved through the interrupt multiplexing module's status register, eliminating the need for software polling of all channels and significantly improving interrupt response efficiency. They eliminate the multi-clock domain problem, using the same clock for all modules, avoiding metastability, clock skew, and cross-clock domain synchronization circuit overhead caused by multiple clock domains, thus improving system reliability and timing convergence, and reducing FPGA routing complexity. The baud rate configuration is flexible and precise. The serial-to-parallel and parallel-to-serial modules of each channel count the serial bit length based on the same clock and can be set to any standard or non-standard baud rate, facilitating the simultaneous connection of peripherals with different baud rates. Supports multiple frame formats, with each channel independently configurable for frame header identifier, the number of bytes in the frame header identifier (1, 2, 3, or 4 bytes), the number of bytes in the frame length (0 for fixed length, 1 or 2 for the number of bytes immediately following the frame header), and the frame length (valid for fixed length). It adapts to serial port frames of different formats from multiple devices, accommodating complex multi-device scenarios. Reduces CPU load: This invention completes multi-channel data frame reception and buffering at the hardware level, and reduces the number of interrupts through an interrupt multiplexing mechanism (only one interrupt is triggered for each complete frame), avoiding the inefficient mode of triggering an interrupt every few bytes received in traditional solutions, freeing up CPU resources for other processing tasks. High integration and low cost: Up to 12 full-function UARTs are implemented in a single FPGA chip, eliminating the need for external serial port expansion chips, significantly reducing BOM cost and PCB area. This invention achieves significant technological advancements in interrupt resource consumption, clock design complexity, CPU load, and system integration. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings:

[0036] Figure 1 This is a block diagram of the logical structure of a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite according to an embodiment of the present invention.

[0037] Figure 2 This is an overall structural diagram of a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite according to an embodiment of the present invention;

[0038] Figure 3 This is a block diagram of a multi-channel serial communication module according to an embodiment of the present invention;

[0039] Figure 4 This is a block diagram of a multiplexed interrupt module according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] Definitions:

[0042] AXI-Lite (Advanced eXtensible Interface Lite) is a lightweight, simplified version of the memory-mapped interface protocol in the ARM AMBA bus protocol family. It is mainly used for low-throughput, simple register access scenarios (such as configuration registers and status registers), and is one of the most commonly used protocols for communication between the PS (processor system) and PL (programmable logic) in FPGAs (especially Xilinx Zynq / MPSoC).

[0043] Example 1

[0044] like Figure 1-4 As shown, this embodiment provides a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, suitable for application scenarios of programmable logic devices such as FPGAs and PSOCs that require parallel serial communication between multiple devices and efficient utilization of interrupt resources. A multi-level hardware architecture is built using the AXI-Lite bus as the interaction center. Interrupt multiplexing technology unifies multiple serial port interrupt requests into a single output, solving the problem of interrupt resource scarcity; the bus clock is used as the sole input clock, avoiding complex wiring across multiple clock domains and metastability risks; a complete frame reception function is integrated into the serial port receive channel, transferring some processing tasks originally handled by the CPU to hardware, reducing the CPU load; a batch transmission function is integrated into the serial port transmit channel, allowing the CPU to input the data to be transmitted at once, with the hardware completing the data transmission; and register mapping design enables independent configuration of parameters for multiple serial ports, improving system flexibility and integration.

[0045] The AXI-Lite-based multi-channel serial communication and interrupt multiplexing system of this embodiment may include: an AXI-Lite bus interface module, a multi-channel serial communication module, and a multi-channel interrupt multiplexing module, which constitute a hardware system with a unified clock domain.

[0046] The AXI-Lite bus interface module contains 128 32-bit registers, which are used to receive access requests from the CPU. By mapping configuration parameters, status signals, and transmit / receive data to the registers, the CPU can configure the parameters of each serial port and read / write data.

[0047] The multi-channel serial communication module contains multiple independent full-duplex serial port channels. Each serial port channel includes an independent receiving path and a transmitting path. The receiving path is configured to perform frame header recognition and frame reception in hardware, and the transmitting path is configured to perform batch frame transmission in hardware. After each serial port has completely received a frame of data, it sends an interrupt request to the multiplexed interrupt module.

[0048] The multiplexed interrupt module is connected to each serial port channel and is configured to perform priority arbitration on each interrupt request and merge it into a single interrupt signal for output to the CPU. At the same time, it reports the current interrupt source number and data status through the interrupt status word, and sends an interrupt response signal to the corresponding serial port after receiving the CPU response.

[0049] The system employs a single global clock, with all modules sharing the same clock domain, eliminating the risk of metastability across multiple clock domains by avoiding the use of external independent baud rate clocks. Parameter configuration and data interaction are achieved through unified address mapping. The AXI-Lite bus interface module uses the AXI-Lite protocol, implementing a 32-bit data width and a 9-bit address width; internally, it is configured with 128 32-bit slave registers (slv_reg0~slv_reg127), with an address decoding range of 0~127, enabling global control, parameter configuration, data read / write, and status feedback. The multi-channel serial communication module includes independent receive and transmit paths, achieving full-duplex asynchronous communication. Hardware handles frame header identification, frame reception, and FIFO buffering. Each serial port supports independent configuration of baud rate, frame format, and parity check method. On the receive path, data from the serial link first enters the serial-to-parallel converter module, where it is sampled and converted into parallel data. The converted parallel data is then sent to the frame receive module, which writes a complete data frame into the receive FIFO buffer according to the configured protocol format for the CPU to read. On the transmission path, the CPU first writes the parallel data to be transmitted into the transmission FIFO module; the frame transmission module reads the data from it and outputs the data frame bit by bit to the serial bus through the parallel-to-serial conversion module. The multiplexed interrupt module connects to the receiving channels of all serial ports, collects the frame reception completion requests of all serial ports, performs priority encoding, status latching, and interrupt request merging on the frame reception completion signals of each serial port, and finally outputs a single interrupt signal to the CPU, directly indicating the interrupt source, FIFO data volume, and single frame byte count through the interrupt status word.

[0050] After system initialization, the main controller completes configuration via AXI-Lite, enabling parallel data transmission and reception across multiple serial ports. An interrupt multiplexing module manages interrupt requests uniformly, achieving efficient communication and interrupt resource reuse across multiple serial ports. This embodiment is particularly suitable for FPGA-implemented intelligent integrated circuits, IoT embedded systems, and multi-peripheral industrial control scenarios.

[0051] The AXI-Lite bus interface module supports the standard AXI-Lite bus protocol, using a 32-bit data and 9-bit address standard. The address space is 0x00-0x7F, and it contains 128 32-bit registers, including a global control register, an interrupt multiplexing module control register, an interrupt multiplexing module status register, a multiplexed serial port configuration register, a data transceiver register, and a version information register.

[0052] The global control register is configured to control the system's global reset, the multiplexed interrupt module reset, and the independent reset of each serial port. The interrupt multiplexing module control register is a reserved register. The interrupt multiplexing module status register stores the interrupt source number, FIFO data count, and single-frame byte count. The multiplexed serial port configuration register configures the frame format and communication parameters of each serial port. The data transceiver register includes the receive FIFO read address and transmit FIFO write address for each serial port, used by the CPU to read and write serial port data. The receive FIFO of each serial port is used to buffer received data, and the transmit FIFO is used to buffer data to be sent. The version information register stores the version number, release date, and release time. The address division logic is clear, and the boundaries of each functional area are well-defined. The CPU can quickly complete module configuration, status reading, and data read / write operations through the AXI-Lite bus without additional address decoding logic, reducing the complexity of logic development. It also facilitates subsequent functional expansion according to needs; only the reserved address space needs to be modified to add functional registers, adapting to customized needs in different scenarios.

[0053] Frame format configuration includes: a customizable frame header identifier (1-4 bytes), and frame length support for fixed-length, 1-byte variable-length, and 2-byte variable-length modes. Communication parameter configuration includes: baud rate configured via bit length parameters, and parity checking supports no parity, odd parity, and even parity modes. The serial port receive path supports configurable 1-4 byte frame headers, automatic identification of fixed-length and variable-length frames, and generates an upload request only after receiving a complete frame of data. The serial port supports arbitrary baud rate configuration, implementing standard and non-standard baud rates via bit length parameters, with a maximum support of 6.25Mbps@100MHz clock. Different communication parameters and frame formats are customized for different serial ports to meet the communication needs of various peripherals with different protocols in the system, eliminating the need for additional protocol conversion logic and simplifying the overall hardware architecture design.

[0054] The receiving path includes a serial-to-parallel conversion module, a frame receiving module, and a receiving FIFO module. These modules work together to receive and buffer a single frame of data. The transmitting path includes a parallel-to-serial conversion module, a frame sending module, and a sending FIFO module. These modules work together to read data, convert between parallel and serial, and send it. The receiving and transmitting paths control the operation of the frame receiving state machine and the frame sending state machine according to the configuration information in their respective control modules. The top-level module of each serial port channel includes a configuration interface, a clock reset interface, a serial physical interface, a data interaction interface, and a FIFO read / write interface. The multi-channel serial communication module uses a parameterized instantiation method to expand up to 12 serial port channels. Each serial port operates independently and in parallel, sharing the same clock domain and possessing independent reset, configuration, and data signals.

[0055] The multi-channel full-duplex serial communication module supports up to 12 independent serial ports. Each serial port consists of a serial-to-parallel converter, frame receiver, receive FIFO, parallel-to-serial converter, frame transmitter, transmit FIFO, and control module. Each serial port can be independently configured with baud rate, parity mode, etc., via the AXI-Lite bus, with no interference between parameter configurations. Simultaneously, each port independently transmits and receives data in parallel, enabling simultaneous data transmission of multiple channels compared to single-port multiplexing solutions, significantly improving data throughput efficiency. The parameterized and instantiated design allows adjustment of the number of serial port channels according to actual usage requirements, flexibly adapting to different application scenarios and reducing resource waste.

[0056] The configuration interface includes the receive frame header identifier RX_FRAME_HEAD, receive frame control RX_FRAME_CTRL, transmit frame control TX_FRAME_CTRL, and baud rate and parity configuration SIO_CONFIG; the clock reset interface includes clock clk and active-high reset rst; the serial physical interface includes serial data input serial_in and serial data output serial_out; and the data interaction interface includes frame upload request output upload_data_req, acknowledge signal input upload_data_ack, and data count output uploa. d_data_count; The receive FIFO interface includes read enable input rx_fifo_rden, data output rx_fifo_dout, output validity flag rx_fifo_dvalid, empty flag rx_fifo_empty, and data count rx_fifo_dcount; The send FIFO interface includes write enable input tx_fifo_wren, data input tx_fifo_din, write acknowledgment output tx_fifo_wrack, full flag tx_fifo_full, and data count tx_fifo_dcount.

[0057] The serial-to-parallel conversion module is configured to oversample and decide on the serial input data according to the configured parity enable, parity mode, and bit length parameters. It automatically identifies the start bit, data bits, parity bit, and stop bit, completes the serial-to-parallel conversion, and outputs parallel byte data, a valid flag, and a reception error flag. The frame receiving module is configured to use the configured frame header identifier as the matching basis. Based on the configured frame header byte count, frame length mode, and frame length value, it matches the frame header in real time, parses the frame length, combines the byte data output from the serial-to-parallel conversion module into 32-bit parallel data, writes it to the receive FIFO module, and outputs the data after a complete frame has been written. The system sends a request signal, waits for an acknowledgment signal, and then resets the receiving state. If a frame header error or length overflow occurs, the receiving FIFO module is reset, and frame header matching restarts. The receiving FIFO module is configured with a synchronous first-in-first-out structure, 32 bits wide and 512 bits deep, implemented by the FPGA's on-chip BRAM, and is used to buffer a complete frame of received data. The read enable of the receiving FIFO module is controlled by the CPU through the AXI-Lite bus read operation. When the CPU reads the corresponding serial port's receive data address, the receiving FIFO module outputs data to the AXI-Lite bus interface module. This achieves reliable buffering of received data, adapting to the low-speed reading of the CPU's AXI-Lite bus and the high-speed data reception of the serial port, avoiding data loss, and ensuring the independence and integrity of multi-channel serial port data reception.

[0058] The parallel-to-serial conversion module is configured to automatically add start, parity, and stop bits to the input parallel data based on the configured parity enable, parity mode, and bit length parameters, converting it into a serial data stream output and outputting an idle flag to indicate the serial port transmission link status. The frame transmission module is configured to identify the transmission start signal by detecting the falling edge of the transmission start bit in the transmission frame control register, read data from the transmission FIFO module according to the configured transmission frame length, split it into bytes, and send it to the parallel-to-serial conversion module. The transmission FIFO module is configured with a synchronous first-in-first-out structure, a bit width of 32 bits, and a depth of 512, implemented by the FPGA on-chip BRAM. It is used to buffer the data to be transmitted written by the CPU at one time and outputs a full flag, an empty flag, a data count, and a write acknowledge signal. The serial port transmission path supports batch data transmission. After the master controller writes data into the transmission FIFO, the hardware automatically completes the parallel-to-serial conversion and transmission of one frame of data. The CPU can determine the status of the transmission FIFO module through the full flag, and only write data to be transmitted when the FIFO is not full. Combined with the data count, the length of a single transmission frame can be flexibly controlled to adapt to the serial port data transmission requirements of different protocols. Storage is implemented using on-chip BRAM on the FPGA, which does not require additional logic resources. It can match the writing of the CPU-side AXI-Lite bus and the serial transmission of the serial port, avoiding data loss or blockage during data transmission and ensuring that the transmission processes of each serial port are independent of each other.

[0059] The multiplexed interrupt module includes an interrupt request encoding unit, an interrupt response unit, an interrupt status register unit, and an interrupt handling state machine. It is used for unified interrupt management of frame reception completion signals from multiple independent serial ports. The interrupt request encoding unit is configured to receive upload request signals from each serial port and perform fixed-priority encoding. The interrupt status register unit is configured to latch the highest-priority interrupt source number and the corresponding channel's data count, and generate a 32-bit interrupt status word. The high 10 bits of the interrupt status word represent the interrupt source number, and the low 22 bits represent the FIFO data count and the number of bytes per frame. The main controller can locate the interrupt channel after reading the word without polling. The interrupt handling state machine is configured to control the arbitration, initiation, and response processes for interrupt requests. The interrupt response unit is configured to output an upload response signal to the corresponding serial port channel based on the CPU's interrupt response signal. An interrupt can be initiated to the CPU through a single interrupt request line, eliminating the need to allocate an interrupt pin for each serial port channel. This effectively saves interrupt resources on the chip side and simplifies system wiring and resource allocation. Fixed priority coding ensures that interrupt requests from high-priority channels are processed first, and the latched interrupt status word allows the CPU to quickly identify the interrupt source and read the received data count of the corresponding channel, without having to poll all serial port channels sequentially to determine the interrupt source.

[0060] The interrupt handling state machine is a four-stage state machine, including an idle state, a request source encoding state, an interrupt initiation state, and an acknowledgment return state. The workflow of the four-stage state machine is as follows: In the idle state, the interrupt handling state machine controls the interrupt request encoding unit to monitor the upload request signals of each serial port in real time. When any one or more requests are detected as valid, it jumps to the request source encoding state. In the request source encoding state, the interrupt handling state machine controls the interrupt request encoding unit to encode each request with a fixed priority and controls the interrupt status register unit to latch the highest priority interrupt source number and the corresponding channel's data count, then jumps to the interrupt initiation state. In the interrupt initiation state, the interrupt handling state machine outputs a valid interrupt request signal to the CPU, waits for the CPU to generate an interrupt acknowledgment signal, and then jumps to the acknowledgment return state. In the acknowledgment return state, the interrupt handling state machine controls the interrupt acknowledgment unit to generate the corresponding channel's upload acknowledgment signal based on the latched interrupt source number, notifying the corresponding serial port that the interrupt handling is complete, and then returns to the idle state to wait for the next request. With clear division of the four states and well-defined responsibilities, the system can orderly complete the arbitration, initiation, and response of interrupt requests, avoiding processing conflicts between different interrupt sources and ensuring the reliable operation of the multi-interrupt multiplexing process.

[0061] The technical solution of this embodiment will be described in detail below with specific examples to further clarify the feasibility and completeness of the invention. Using a PSOC device (model: Xilinx Zynq-7000 series XC7Z020 CLG484-2) as a carrier, it is implemented using Verilog HDL programming language, as detailed below:

[0062] The hardware architecture is built on a PSOC device (XC7Z020 CLG484-2). The device integrates an ARM Cortex-A9 processor and a programmable logic unit. The programmable logic unit can implement the three-level hardware architecture of this invention (AXI-Lite bus interface module, multiple serial communication module, and multiple interrupt multiplexing module). The ARM processor acts as the CPU and interacts with the hardware module of the programmable logic unit through the on-chip AXI-Lite bus to complete register configuration, data reading and writing, and interrupt response.

[0063] AXI-Lite Bus Interface Module Implementation Details

[0064] This module adopts the AXI-Lite protocol, with a 32-bit data width and a 9-bit address width, corresponding to AXI-Lite byte addresses 0-508 (step size 4), providing a total of 128 read and write address spaces (address range: 0-127). The write space is configured with 128 32-bit registers (slv_reg0-slv_reg127). The address mapping is implemented as follows:

[0065] Global control register: Address 0, readable and writable, bit

[31] is the system global reset (1 is valid), bit

[30] is the multiplexer module reset (1 is valid), bits [11:0] are the 12-channel serial port reset (1 is valid), and the remaining bits are reserved.

[0066] Interrupt multiplexing module control register: Address 1, readable and writable, reserved.

[0067] Interrupt multiplexing module status register: address 2, read-only, where bits [31:22] are the interrupt source number, with values ​​0-11 (corresponding to 12 serial ports), bits [21:12] indicate the FIFO data count, and bits [11:0] indicate the number of bytes per frame.

[0068] Multi-channel serial port configuration registers and data transceiver registers: 12 serial ports use a total of 60 addresses (range: 10-69), with each serial port occupying 5 addresses. Serial port 0 uses address 10 to configure the receive frame header identifier; address 11 configures frame reception (including the number of header bytes, the number of frame length bytes, and the frame length value); address 12 configures frame transmission, baud rate, and parity check; address 13 is for outputting data to the receive FIFO, and address 14 is for writing data to the transmit FIFO. The remaining serial ports are allocated sequentially.

[0069] Version Information Register: Address 125 stores the version number (e.g., hexadecimal 0x00_01_00_01, representing version V1.0.1); Address 126 stores the release date (e.g., hexadecimal 0x07EA_05_08, representing May 8, 2026); Address 127 stores the release time (e.g., hexadecimal 0x00_0E_1E_00, representing 14:30:00).

[0070] The remaining addresses are reserved addresses.

[0071] Implementation details of multi-channel serial communication module

[0072] like Figure 3 As shown, the single-channel serial port consists of seven parts: serial-to-parallel conversion, frame reception, receive FIFO, parallel-to-serial conversion, frame transmission, transmit FIFO, and a control module. Transmission and reception are independent, enabling full-duplex communication. The hardware handles frame parsing, frame interrupts, and batch transmission, freeing the CPU from heavy serial port data processing. The reception function is implemented collaboratively by the serial-to-parallel conversion module, frame reception module, and receive FIFO module. The transmission function is implemented collaboratively by the parallel-to-serial conversion module, frame transmission module, and transmit FIFO module. The transmit / receive channel controls the operation of the state machines in the frame reception and frame transmission modules based on the configuration information in the control module. The top-level serial port module is named FD_UART, and it has a configuration interface, clock and reset interface, serial physical interface, data interaction interface, receive FIFO interface, and transmit FIFO interface. The functions of each interface are as follows:

[0073] The configuration interface includes receive frame header identifier RX_FRAME_HEAD[31:0], receive frame control RX_FRAME_CTRL[31:0], transmit frame control TX_FRAME_CTRL[15:0], and baud rate and parity configuration SIO_CONFIG[15:0]; the clock and reset interface includes clock clk and active-high reset rst; the serial physical interface includes serial data input serial_in and serial data output serial_out; the data interaction interface includes frame upload request output upload_data_req, acknowledgment signal input upload_data_ack, and data count output upload_ data_count[21:0]; The receive FIFO interface includes read enable input rx_fifo_rden, data output rx_fifo_dout[31:0], output valid flag rx_fifo_dvalid, empty flag rx_fifo_empty, and data count rx_fifo_dcount[9:0]; The send FIFO interface includes write enable input tx_fifo_wren, data input tx_fifo_din[31:0], output write acknowledgment tx_fifo_wrack, full flag tx_fifo_full, and data count tx_fifo_dcount[9:0].

[0074] The serial port receiving channel includes a serial-to-parallel conversion module, a frame receiving module, and a receiving FIFO module. These modules work together to receive and buffer a frame of data.

[0075] The implementation of the serial-to-parallel conversion module SART_RX_S2P: The module oversamples and makes a decision on the serial input data serial_in according to the parity enable configured in bit

[15] of SIO_CONFIG, the parity mode configured in bit

[14] , and the bit length parameters configured in bit [13:0], and recovers the valid bit stream; the module automatically identifies the start bit, data bit, parity bit and stop bit, completes the serial-to-parallel conversion, and outputs 8-bit parallel data rx_data[7:0], valid flag rx_data_valid and receive error flag rx_data_error, so as to realize the reliable serial data reception function.

[0076] The SART_RX_FIFO_WR frame reception module operates as follows: The module uses RX_FRAME_HEAD as the frame header identifier and RX_FRAME_CTRL's header byte count, frame length mode, and frame length value as the parsing criteria. It supports both fixed-length and variable-length frame reception modes. The module matches the frame header in real-time, parses the frame length, and combines the byte data output from the serial-to-parallel converter into 32-bit parallel data, writing it into the receive FIFO. After a frame of data is received and fully stored in the FIFO, it outputs an upload_data_req upload request signal, waits for the upper-layer upload_data_ack response, resets the reception state, and prepares for the next frame reception. If an error occurs, such as a frame header error or length overflow, the module resets the FIFO and returns to the frame header matching state.

[0077] The FIFO_CC_BRAM_32X512 receiver FIFO module adopts a synchronous first-in-first-out (FIFO) structure, with a bit width of 32 bits and a depth of 512, implemented using on-chip BRAM on the FPGA. The module supports write enable, read enable, full / empty flag, data count, and output valid indication. Both receive reset and frame error reset can clear the FIFO, ensuring the safety of the received data buffer. The read enable of the receiver FIFO is controlled by the AXI read operation. When the CPU reads the corresponding receive data address (e.g., address 13 corresponds to the 0th serial port receive data address), it asserts read enable, and the receiver FIFO feeds back the information to the AXI bus.

[0078] The serial port transmission channel includes a parallel-to-serial conversion module, a frame transmission module, and a transmission FIFO module. These modules work together to complete data reading, parallel-to-serial conversion, and transmission.

[0079] Parallel-to-serial module SART_TX_P2S implementation: The module automatically adds start bit, parity bit and stop bit to the input 8-bit parallel data according to the parity enable configured in bit

[15] of SIO_CONFIG, the parity mode configured in bit

[14] , and the bit length parameters configured in bits [13:0], and converts it into a serial data stream and outputs it through serial_out; the module outputs a high active idle flag tx_line_idle to indicate the serial port transmission link status.

[0080] The implementation of the frame transmission module SART_TX_FIFO_RD: The module identifies the transmission start signal tx_frame_launch by detecting the falling edge of TX_FRAME_CTRL

[12] . According to the set transmission frame length TX_FRAME_CTRL[11:0], it reads 32 bits of data from the transmission FIFO, splits it into 8-bit bytes, and sends them to the serial-to-byte converter. The control module automatically completes the complete and reliable transmission of one frame of data and outputs the transmission status.

[0081] The FIFO_CC_BRAM_32X512 transmitting FIFO module has the same structure as the receiving FIFO, with a 32-bit width and a 512-bit depth. It supports upper-layer data writing and transmitting module reading, and provides a full / empty flag, data count, and write acknowledgment signal to prevent data overflow or loss. The CPU initiates an AXI write operation. In this embodiment, address assertion enables the transmit FIFO write operation, writing the data to be transmitted into the corresponding FIFO (e.g., address 14 corresponds to the 0th serial port transmit data address). After all the data is written, the CPU controls the TX_FRAME_CTRL data via write transmission, starting the frame transmission module to read the FIFO data and transmit it.

[0082] The serial port supports flexible frame format and communication parameter configuration: the received frame header supports 1-4 bytes of custom identifier, the frame length supports fixed mode and 1 / 2 byte variable length mode; the baud rate is configured through the bit length parameter (bit length calculation formula: clock frequency / baud rate-1, clock frequency unit is Hz, baud rate unit is bps), parity can be enabled and supports switching between odd and even parity to meet the needs of different serial communication protocols.

[0083] This example supports a maximum baud rate of 6.25Mbps (bit length = 15) at a 100MHz clock. It supports full-duplex parallel operation for receiving and transmitting, and the FIFO capacity of 2048 bytes meets the requirements for buffering large data frames. The frame format is highly configurable and can be used as a single channel or expanded into a multi-channel serial port array. It has the advantages of low resource consumption, high stability, and strong compatibility.

[0084] Module instantiation method: The parameterized generation method (genvar i; generate for loop) is used to instantiate 12 FD_UART modules (i from 0 to 11). Each module shares the bus clock and independently receives reset signals, configuration signals and data signals.

[0085] Configuration parameter mapping: The configuration parameters for each serial port are configured through registers controlled by the AXI bus. The receive frame header (uart_rx_head[i*32+:32]), mapped by registers such as slv_reg10 and slv_reg15, is used to specify the frame header identifier for the received serial data, enabling frame synchronization. The receive control (uart_rx_ctrl[i*32+:32]), mapped by registers such as slv_reg11 and slv_reg16, is used to configure the receive... The frame header byte count, frame length byte count, and frame length value are specified. Transmission control (uart_tx_ctrl[i*16+:16]), mapped by the high 16 bits of registers such as slv_reg12 and slv_reg17, is used to control transmission initiation and the number of data bytes. Serial port configuration (uart_sio_cfg[i*16+:16]), mapped by the low 16 bits of registers such as slv_reg12 and slv_reg17, is used to configure parity enable, parity check mode, and baud rate (bit length).

[0086] Reset control: The reset of each serial port (uart_rst[i]) adopts a dual control method of "global reset + local reset". The global reset is controlled by bit

[31] of slv_reg0, and the local reset is controlled by the corresponding bits [11:0]. During the reset, all modules in the serial port are cleared to ensure that the serial port initialization state is correct.

[0087] Implementation details of the multiplexed interrupt module

[0088] like Figure 4 As shown, the interrupt multiplexing module consists of four parts: interrupt request encoding, interrupt acknowledgement, interrupt status register, and interrupt handling state machine. It provides unified interrupt management for the frame reception completion signals of 12 independent serial ports, enabling multi-channel interrupt sharing, priority determination, and status reporting. This solves the problems of excessive interrupt resource consumption and low CPU response efficiency in multi-channel serial ports. The interrupt multiplexing module is named UART_UPLOAD_IRQ, and its external interfaces are as follows:

[0089] Clock and reset input signals: clock clk, active-high reset signal rst; interrupt acknowledge input signal int_ack, active-high; 12-channel serial port upload request input upload_data_req[11:0], each corresponding to one serial port, the request signal is set to high level after the corresponding serial port has received a frame of data and written it to the FIFO; 12-channel data count input upload_data_count_0[21:0]~upload_data_count_11[21:0], each channel is 22 bits, where bits [11:0] represent a single frame word. The number of segments, bits [21:12] indicate the data count of the corresponding receive FIFO; 12-channel upload response output upload_data_ack[11:0], used to reply to the corresponding serial port module that the interrupt processing is complete, active high level; interrupt request output int_req, active high level; 32-bit interrupt status word output int_state_dword[31:0], where bits [31:22] indicate the current interrupt source number, and bits [21:0] indicate the FIFO data count and the number of bytes per frame, which are the same as the definitions of upload_data_count_0~11.

[0090] The multiplexed interrupt module is implemented using a four-stage state machine, with the following states: IDLE (idle), REG_REQ_SOURCE (request source encoding), LAUNCH_INT_REQ (interrupt initiation), and ACK_REQ_SOURCE (acknowledgment return).

[0091] The state machine workflow is as follows:

[0092] In the IDLE state, the module is in a waiting state, monitoring 12 upload_data_req request signals in real time. When any one or more requests are detected to be valid, the state machine jumps to the REG_REQ_SOURCE state. In the REG_REQ_SOURCE state, the module encodes the 12 requests with fixed priorities, with priorities decreasing sequentially from upload_data_req[0] to upload_data_req

[11] . The highest priority interrupt source number is latched into the req_source register, and the 22-bit data count of the corresponding channel is latched into the data_count register. In the LAUNCH_INT_REQ state, the module outputs a valid interrupt request signal int_req and reports the interrupt to the CPU. After waiting for the CPU to respond and generate an int_ack interrupt acknowledgment signal, the module jumps to the ACK_REQ_SOURCE state. In the ACK_REQ_SOURCE state, the module generates the upload_data_ack acknowledgment signal of the corresponding channel based on the latched interrupt source number, notifying the corresponding serial port that the interrupt processing is complete. Then the state machine automatically returns to the IDLE state and waits for the next interrupt request. The CPU can directly obtain the current interrupt channel number, FIFO buffer depth, and frame length by reading this status word, without the need for additional queries, which greatly improves data reading efficiency.

[0093] This multiplexed interrupt module can simultaneously support interrupt request multiplexing for 12 serial ports, occupying only one CPU interrupt, and realizes unified management of multi-channel serial port data reception. It has the advantages of low resource consumption, fast response speed, clear status and high stability.

[0094] System Workflow

[0095] The workflow mainly includes three stages: initialization, multi-serial port parallel communication, and interrupt response, as detailed below:

[0096] Initialization: The CPU writes a global reset signal to slv_reg0 via the AXI bus, causing all system modules to enter a reset state. The CPU then writes configuration parameters to the corresponding registers via AXI write operations, including the frame header, frame format, baud rate, and parity for the 12 serial ports, completing the communication parameter settings. Removing the global reset signal allows the system to enter the working state.

[0097] Multi-serial port communication: After configuration, the 12-channel serial port module starts working in parallel: receiving serial data from external devices, realizing valid data reception through frame header detection, storing it in the receive FIFO, and after writing a complete frame to the FIFO, outputting an upload request to the multiplexed interrupt module; the CPU reads the data in the receive FIFO through AXI read operation to complete data reception; the CPU writes the data to be sent to the transmit FIFO through AXI write operation, and the serial port module reads the data from the transmit FIFO and sends it to the external device.

[0098] Interrupt response: When the data upload of a certain serial port meets the interrupt triggering condition, a data upload request is sent to the multiplexed interrupt module; the multiplexed interrupt module summarizes the interrupt requests and sends an interrupt request to the CPU; the CPU reads the multiple interrupt status words, identifies the interrupt source and performs corresponding processing. After processing, the interrupt request is cleared by reading the interrupt status words, thus completing one interrupt response.

[0099] In this embodiment, multiple serial ports operate in parallel without interference; simultaneously enabling serial communication for 12 devices, improving data transmission efficiency and meeting the application requirements of multi-device linkage; occupying only one interrupt, with direct interrupt source location, simplifying the CPU's interrupt management logic; single clock domain, no metastability, and simple wiring; serial communication parameters are all configured via the AXI bus, supporting flexible adjustment of parameters such as baud rate and frame format, with strong compatibility; hardware completes the reception of a full frame, reducing the CPU load; implemented on a single chip, eliminating the need for external expansion chips.

[0100] Example 2

[0101] This embodiment provides a control method for a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, applied to the multi-channel serial communication and interrupt multiplexing system based on AXI-Lite described in Embodiment 1, including the following steps:

[0102] S1: After the CPU configures the parameters of each serial port through the AXI-Lite bus interface module, the global reset is canceled, and the system enters the working state.

[0103] The CPU writes a global reset signal to the global control register via the AXI-Lite bus, causing all modules in the system to enter a reset state; then it writes configuration parameters to the multiplex serial port configuration register via the AXI-Lite bus, and finally cancels the global reset signal, allowing the system to enter the working state.

[0104] S2: Multiple serial ports work in parallel. The receiving channel hardware completes frame reception and stores it in the receiving FIFO. The CPU reads and writes the FIFO to complete data transmission and reception.

[0105] Multiple serial port channels operate in parallel. Each serial port channel receives serial data from external devices, and valid data reception is achieved through hardware frame header detection and stored in the receive FIFO. The CPU reads the data in the receive FIFO through the AXI-Lite bus. The CPU writes data to be sent to the transmit FIFO through the AXI-Lite bus, and the serial port channels read data from the transmit FIFO and send it to the external device.

[0106] S3: After the serial port completes the reception of a frame, it initiates an upload request. The multiplexer module merges the multiplexed interrupts into a single interrupt output to the CPU after priority arbitration. The CPU reads the interrupt status word to locate the interrupt source and processes it. After receiving the CPU's response, the multiplexer module distributes a response signal to the corresponding serial port.

[0107] When a serial port channel completes the reception of a frame of data, it sends an upload request to the multiplexed interrupt module. The multiplexed interrupt module aggregates the upload requests from all channels, merges them into a single interrupt request after priority arbitration, and outputs it to the CPU. The CPU reads the interrupt status word, identifies the interrupt source according to the interrupt source number in the interrupt status word, and performs corresponding processing. After processing is completed, the multiplexed interrupt module receives the CPU's response and sends a response signal to the corresponding serial port channel, completing one interrupt response.

[0108] This embodiment describes a working method for a system based on AXI-Lite's configurable multi-channel serial communication and interrupt multiplexing. It is applicable to application scenarios of programmable logic devices such as FPGAs and PSOCs that require parallel serial communication between multiple devices and efficient utilization of interrupt resources.

[0109] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, characterized in that, include: The AXI-Lite bus interface module, multiplexed serial communication module, and multiplexed interrupt module constitute a hardware system with a unified clock domain. The AXI-Lite bus interface module contains 128 32-bit registers, which are used to receive access requests from the CPU. By mapping configuration parameters, status signals, and transmit / receive data to the registers, the CPU can configure the parameters of each serial port and read / write access the transmit / receive data. The multi-channel serial communication module includes multiple independent full-duplex serial channels, each of which includes an independent receiving path and a transmitting path. The receiving path is configured to perform frame header identification and frame reception in hardware, and the transmitting path is configured to perform batch frame transmission in hardware. Each serial channel initiates an interrupt request to the multi-channel interrupt multiplexing module after receiving a complete frame of data. The multiplexed interrupt module is connected to each serial port channel and is configured to perform priority arbitration on each interrupt request and merge it into a single interrupt signal for output to the CPU. At the same time, it reports the current interrupt source number and data status through the interrupt status word, and distributes the interrupt response signal to the corresponding serial port after receiving the CPU response.

2. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 1, characterized in that, The AXI-Lite bus interface module supports the standard AXI-Lite bus protocol, employing a 32-bit data width and a 9-bit address width. The 128 32-bit registers include a global control register, an interrupt multiplexing module control register, an interrupt multiplexing module status register, a multiplexed serial port configuration register, a data transceiver register, and a version information register. The global control register is configured to control the system's global reset, the multiplexed interrupt module reset, and each serial port's independent reset; the interrupt multiplexing module control register is a reserved register; the interrupt multiplexing module status register is used to store the interrupt source number, FIFO data count, and single frame byte count; the multiplexed serial port configuration register is used to configure the frame format and communication parameters of each serial port; the data transceiver register includes the receive FIFO read address and transmit FIFO write address for each serial port, used for the CPU to read and write serial port data, the receive FIFO of each serial port is used to buffer received data, and the transmit FIFO is used to buffer data to be sent; the version information register is used to store the version number, release date, and release time.

3. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 1, characterized in that, The receiving path includes a serial-to-parallel conversion module, a frame receiving module, and a receiving FIFO module. Each module works together to receive and buffer a frame of data. The transmitting path includes a parallel-to-serial conversion module, a frame sending module, and a sending FIFO module. Each module works together to read data, convert between parallel and serial, and send it. The receiving and transmitting paths control the operation of the state machine according to the configuration information in their control modules. The top-level module of each serial port channel includes a configuration interface, a clock reset interface, a serial physical interface, a data interaction interface, and a FIFO read / write interface. The multi-channel serial communication module uses a parameterized instantiation method to expand up to 12 serial port channels. Each serial port operates independently and in parallel, sharing the same clock domain and having independent reset signals, configuration signals, and data signals.

4. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 3, characterized in that, The configuration interface includes the receive frame header identifier RX_FRAME_HEAD, receive frame control RX_FRAME_CTRL, transmit frame control TX_FRAME_CTRL, and baud rate and parity configuration SIO_CONFIG; the clock reset interface includes clock clk and active-high reset rst; the serial physical interface includes serial data input serial_in and serial data output serial_out; the data interaction interface includes frame upload request output upload_data_req, acknowledgment signal input upload_data_ack, and data count output u. The `pload_data_count` function is used for the receive FIFO interface, which includes the read enable input `rx_fifo_rden`, data output `rx_fifo_dout`, output validity flag `rx_fifo_dvalid`, empty flag `rx_fifo_empty`, and data count `rx_fifo_dcount`. The transmit FIFO interface includes the write enable input `tx_fifo_wren`, data input `tx_fifo_din`, write acknowledgment output `tx_fifo_wrack`, full flag `tx_fifo_full`, and data count `tx_fifo_dcount`.

5. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 3, characterized in that, The serial-to-parallel conversion module is configured to oversample and decide on the serial input data according to the configured parity enable, parity mode and bit length parameters, identify the start bit, data bits, parity bit and stop bit, complete the serial-to-parallel conversion, and output parallel byte data, valid flag and receive error flag. The frame receiving module is configured to use the configured frame header identifier as the matching basis, and according to the configured frame header byte count, frame length mode, and frame length value, it matches the frame header and parses the frame length in real time. It combines the byte data output by the serial-to-parallel converter into 32-bit parallel data and writes it into the receiving FIFO. After writing a complete frame of data, it outputs an upload request signal and waits for an acknowledgment signal before resetting the receiving state. If a frame header error or length overflow occurs, the receiving FIFO is reset and frame header matching is restarted. The receiving FIFO module is configured to use a synchronous first-in-first-out structure, with a bit width of 32 bits and a depth of 512, and is implemented by the FPGA on-chip BRAM to buffer a complete frame of received data. The read enable of the receiving FIFO is controlled by the CPU through the read operation of the AXI-Lite bus. When the CPU reads the receive data address of the corresponding serial port, the receiving FIFO outputs data to the AXI-Lite bus interface module.

6. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 3, characterized in that, The parallel-to-serial conversion module is configured to add start bits, parity bits, and stop bits to the input parallel data according to the configured parity enable, parity mode, and bit length parameters, convert it into a serial data stream output, and output an idle flag to indicate the serial port transmission link status; the frame transmission module is configured to identify the transmission start signal by detecting the falling edge of the transmission start bit of the transmission frame control register, read data from the transmission FIFO according to the configured transmission frame length, split it into bytes and send it to the parallel-to-serial conversion module; the transmission FIFO module is configured to adopt a synchronous first-in-first-out structure, with a bit width of 32 bits and a depth of 512, implemented by the FPGA on-chip BRAM, used to buffer the data to be transmitted written by the CPU at one time, and output a full flag, an empty flag, a data count, and a write acknowledgment signal.

7. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 2, characterized in that, The frame format configuration includes: the frame header identifier supports 1 to 4 bytes of customizable format, and the frame length supports fixed length mode, 1-byte variable length mode, and 2-byte variable length mode; the communication parameter configuration includes: the baud rate is configured through the bit length parameter, and parity check supports three modes: no parity, odd parity, and even parity.

8. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 1, characterized in that, The multiplexed interrupt module includes an interrupt request encoding unit, an interrupt response unit, an interrupt status register unit, and an interrupt handling state machine, used for unified interrupt management of frame reception completion signals from multiple independent serial ports; wherein... The interrupt request encoding unit is configured to receive upload request signals from each serial port and perform fixed priority encoding. The interrupt status register unit is configured to latch the highest priority interrupt source number and the corresponding channel data count, and generate a 32-bit interrupt status word. The high 10 bits of the interrupt status word are the interrupt source number, and the low 22 bits are the FIFO data count and the number of bytes per frame. The interrupt handling state machine is configured to control the arbitration, initiation, and response processes of interrupt requests; The interrupt response unit is configured to output an upload response signal to the corresponding serial port channel based on the interrupt response signal of the CPU.

9. The multi-channel serial communication and interrupt multiplexing system based on AXI-Lite as described in claim 8, characterized in that, The interrupt handling state machine is a four-stage state machine, including an idle state, a request source encoding state, an interrupt initiation state, and an acknowledgment return state. The workflow of the four-stage state machine includes: In the idle state, the interrupt handling state machine controls the interrupt request encoding unit to monitor the upload request signals of each serial port in real time. When any one or more requests are detected to be valid, the process jumps to the request source encoding state. In the request source encoding state, the interrupt handling state machine controls the interrupt request encoding unit to encode each request with a fixed priority, and controls the interrupt status register unit to latch the interrupt source number with the highest priority and the data count of the corresponding channel, and then jumps to the interrupt initiation state. In the interrupt initiation state, the interrupt handling state machine outputs a valid interrupt request signal to the CPU, and then jumps to the response return state after waiting for the CPU to generate an interrupt response signal. In the response return state, the interrupt handling state machine controls the interrupt response unit to generate the corresponding channel upload response signal according to the latched interrupt source number, notifying the corresponding serial port interrupt processing to be completed, and then returns to the idle state to wait for the next request.

10. A control method for a multi-channel serial communication and interrupt multiplexing system based on AXI-Lite, characterized in that, Applied to the AXI-Lite-based multi-channel serial communication and interrupt multiplexing system as described in any one of claims 1 to 9, Includes the following steps: S1: After the CPU configures the parameters of each serial port through the AXI-Lite bus interface module, the global reset is canceled, and the system enters the working state. S2: Multiple serial ports work in parallel. The hardware of the receiving channel completes frame reception and stores it in the receiving FIFO. The CPU reads and writes the FIFO to complete data transmission and reception. S3: After the serial port completes the reception of a frame, it initiates an upload request. The multiplexer module merges the multiplexed interrupts into a single interrupt output to the CPU after priority arbitration. The CPU reads the interrupt status word to locate the interrupt source and processes it. After receiving the CPU's response, the multiplexer module distributes a response signal to the corresponding serial port.

Images