Method, device, equipment, medium and program product for timing calibration of SPI interface

Abstract

This application provides a timing calibration method, apparatus, device, medium, and program product for an SPI interface, relating to the field of communication interface technology. The timing calibration method for the SPI interface, after the target device completes SPI driver loading and initialization, acquires the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration. Based on the temperature difference between the current temperature and the last timing calibration temperature, it determines whether to trigger local timing incremental calibration. This allows for targeted timing calibration adjustments to the current sampling delay level when temperature changes cause SPI interface timing drift, achieving continuous tracking and dynamic compensation for sampling point phase shifts caused by temperature drift. Furthermore, by updating the sampling timing configuration at the SPI receiver, it improves the timing adaptability and transmission stability of the high-speed SPI read process, reduces the rate of occasional data errors, and lowers the system overhead caused by invalid calibration operations, thereby improving the long-term operational stability of the device.

Description

Technical Field

[0001] This application relates to the field of communication interface technology, and in particular to a timing calibration method, apparatus, device, medium and program product for an SPI interface. Background Technology

[0002] In high-speed Serial Peripheral Interface (SPI) communication, reflections, crosstalk, and signal jitter generated by printed circuit board (PCB) traces, as well as device delay offsets caused by environmental temperature changes and voltage fluctuations, can all lead to timing drift when the data signals transmitted on the SPI bus reach the SPI controller. Currently, to compensate for this timing drift, the SPI controller integrates a configurable sampling point register (also known as a delay adjustment register). By modifying the sampling point configuration value of this register, the delay phase of the data sampling clock can be adjusted, thereby ensuring the accuracy of data reading.

[0003] In related technologies, high-speed SPI communication typically employs a one-time power-on timing calibration method to complete the timing calibration of the SPI interface. Specifically, firstly, the SPI clock is configured to a low-speed clock (e.g., a clock frequency of 12.5MHz), and a fixed data block (Golden Data) is read from a fixed address in the SPI flash memory. Then, the SPI clock is switched to the target high-speed clock (e.g., a clock frequency of 100MHz). By traversing all sampling delay levels supported by the configurable sampling point register integrated within the SPI controller (e.g., the range can be 0-63 levels), the data corresponding to the fixed address of the reference data block stored in the SPI flash memory is read at each sampling delay level, and the read data is stored in the SPI receive buffer. Subsequently, the data read results at each sampling delay level are compared one by one with the reference data block, and all valid sampling delay levels that are verified correctly are recorded. Finally, within the interval formed by consecutive valid sampling delay levels, the sampling delay level corresponding to the midpoint of the interval is selected as the final sampling delay level configuration of the sampling clock. Each sampling delay level corresponds to a unique set of sampling point configuration values ​​in the sampling point register, and the sampling delay level number corresponds one-to-one with the sampling point.

[0004] However, the aforementioned one-time timing calibration method has poor adaptability to timing drift caused by changes in ambient temperature during long-term operation of the equipment, and is prone to causing occasional data errors. Summary of the Invention

[0005] This application provides a timing calibration method, apparatus, device, medium, and program product for an SPI interface, which solves the problem that the one-time timing calibration method upon power-on in related technologies has poor adaptability to timing drift caused by changes in ambient temperature during long-term operation of the device, and is prone to causing occasional data errors.

[0006] In a first aspect, this application provides a timing calibration method for an SPI interface, comprising: in response to a target device with an SPI interface completing SPI driver loading initialization, acquiring the target device's current temperature, reference data block, current sampling delay level, and last timing calibration temperature, wherein the current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device; calculating the temperature difference between the current temperature and the last timing calibration temperature, and determining whether to trigger local timing incremental calibration based on the temperature difference; if it is determined that local timing incremental calibration is triggered, performing local timing incremental calibration on the current sampling delay level based on the reference data block to obtain a target sampling delay level; updating the sampling timing configuration of the SPI receiver using the target sampling delay level, and updating the last timing calibration temperature to the current temperature.

[0007] In one possible implementation, local timing incremental calibration is performed on the current sampling delay level based on the reference data block to obtain the target sampling delay level. This includes: determining a first scanning window corresponding to the current sampling delay level, centered on the current sampling delay level and based on the half-width of a first preset scanning window, wherein the first scanning window includes multiple consecutive first sampling delay levels; for each first sampling delay level, configuring the sampling point register of the SPI receiver to the first sampling point configuration value corresponding to the first sampling delay level, and reading the current data corresponding to the fixed address of the reference data block stored in the SPI Flash under the first sampling point configuration value; comparing the current data read under each first sampling delay level with the reference data block one by one to obtain a first effective sampling delay level set corresponding to the first scanning window; and determining the target sampling delay level from the first effective sampling delay level set.

[0008] In one possible implementation, the timing calibration method further includes: in response to the absence of a valid sampling delay level in the first scanning window, determining a second scanning window corresponding to the current sampling delay level based on the second preset scanning window half-width, with the current sampling delay level as the center and the second preset scanning window half-width being larger than the first preset scanning window half-width; for each second sampling delay level in the second scanning window, configuring the sampling point register to the second sampling point configuration value corresponding to the second sampling delay level, and reading the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the second sampling point configuration value; comparing the current data corresponding to each second sampling delay level with the reference reference data block one by one to obtain the second valid sampling delay level set corresponding to the second scanning window, and determining the target sampling delay level from the second valid sampling delay level set.

[0009] In one possible implementation, the timing calibration method further includes: triggering global timing calibration in response to the absence of a valid sampling delay level in the second scan window; traversing all configurable sampling delay levels in the sampling point register, configuring the sampling point register to the sampling point configuration value corresponding to each sampling delay level, and reading the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the sampling point configuration value; comparing the current data corresponding to each sampling delay level with the reference reference data block one by one to obtain a global set of valid sampling delay levels, and determining the target sampling delay level from the global set of valid sampling delay levels.

[0010] In one possible implementation, the sampling timing configuration of the SPI receiver is updated using the target sampling delay level, including: using an atomic operation to update the current sampling delay level to the target sampling delay level; or using a double buffering mechanism to update the current sampling delay level to the target sampling delay level.

[0011] In one possible implementation, the timing calibration method further includes: obtaining the previous calibration timestamp and the current timestamp of the target device; calculating the time difference between the current timestamp and the previous calibration timestamp; determining whether to trigger local timing incremental calibration based on the time difference; if it is determined that local timing incremental calibration is triggered, then performing local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0012] In one possible implementation, after obtaining the target sampling delay level, the timing calibration method further includes updating the previous calibration timestamp to the current timestamp.

[0013] In one possible implementation, the timing calibration method further includes: during the operation of the SPI receiver, acquiring the error correction code (ECC) error count and / or cyclic redundancy check (CRC) error count; determining whether to trigger local timing incremental calibration based on the ECC error count or CRC error count; if it is determined that local timing incremental calibration is triggered, performing local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0014] In one possible implementation, after obtaining the target sampling delay level, the timing calibration method further includes: clearing the ECC error correction count and / or CRC error count.

[0015] In one possible implementation, the timing calibration method further includes: configuring the timing calibration parameters corresponding to the SPI receiver using device tree attributes; or configuring the timing calibration parameters corresponding to the SPI receiver using a memory-based virtual file interface.

[0016] Secondly, this application provides a timing calibration device for an SPI interface, comprising:

[0017] The acquisition module is used to respond to the target device with the SPI interface completing the SPI driver loading initialization, and to acquire the target device's current temperature, reference data block, current sampling delay level and last timing calibration temperature. The current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device.

[0018] The processing module is used to calculate the temperature difference between the current temperature and the previous timing calibration temperature, and to determine whether to trigger local timing incremental calibration based on the temperature difference.

[0019] The timing calibration module is used to perform local timing incremental calibration on the current sampling delay level according to the reference data block if it is determined that local timing incremental calibration is triggered, so as to obtain the target sampling delay level.

[0020] The update module is used to update the sampling timing configuration of the SPI receiver using the target sampling delay level, and update the temperature of the last timing calibration to the current temperature.

[0021] In one possible implementation, the timing calibration module is specifically used to: determine a first scanning window corresponding to the current sampling delay level, centered on the current sampling delay level and based on the half-width of a first preset scanning window, wherein the first scanning window includes multiple consecutive first sampling delay levels; for each first sampling delay level, configure the sampling point register of the SPI receiver to the first sampling point configuration value corresponding to the first sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the first sampling point configuration value; compare the current data read under each first sampling delay level with the reference reference data block one by one to obtain the first effective sampling delay level set corresponding to the first scanning window; and determine the target sampling delay level from the first effective sampling delay level set.

[0022] In one possible implementation, the timing calibration module is further configured to: respond to the absence of a valid sampling delay level in the first scanning window, determine a second scanning window corresponding to the current sampling delay level based on the second preset scanning window half-width, with the current sampling delay level as the center and the second preset scanning window half-width being larger than the first preset scanning window half-width; for each second sampling delay level in the second scanning window, configure the sampling point register to the second sampling point configuration value corresponding to the second sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the second sampling point configuration value; compare the current data corresponding to each second sampling delay level with the reference reference data block one by one to obtain the second valid sampling delay level set corresponding to the second scanning window, and determine the target sampling delay level from the second valid sampling delay level set.

[0023] In one possible implementation, the timing calibration module is further configured to: trigger global timing calibration in response to the absence of a valid sampling delay level in the second scan window; traverse all configurable sampling delay levels in the sampling point register, configure the sampling point register to the sampling point configuration value corresponding to each sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the sampling point configuration value; compare the current data corresponding to each sampling delay level with the reference reference data block one by one to obtain a global set of valid sampling delay levels, and determine the target sampling delay level from the global set of valid sampling delay levels.

[0024] In one possible implementation, the update module is specifically used to: update the current sampling delay level to the target sampling delay level using an atomic operation; or, update the current sampling delay level to the target sampling delay level using a double buffering mechanism.

[0025] In one possible implementation, the timing calibration module is also used to: obtain the previous calibration timestamp and the current timestamp of the target device; calculate the time difference between the current timestamp and the previous calibration timestamp; determine whether to trigger local timing incremental calibration based on the time difference; if it is determined that local timing incremental calibration is triggered, perform local timing incremental calibration on the current sampling delay level according to the reference data block to obtain the target sampling delay level.

[0026] In one possible implementation, after obtaining the target sampling delay level, the update module is also used to update the previous calibration timestamp to the current timestamp.

[0027] In one possible implementation, the timing calibration module is also used to: acquire ECC error correction count and / or CRC error count during the operation of the SPI receiver; determine whether to trigger local timing incremental calibration based on the ECC error correction count or CRC error count; if it is determined that local timing incremental calibration is triggered, perform local timing incremental calibration on the current sampling delay level according to the reference data block to obtain the target sampling delay level.

[0028] In one possible implementation, after obtaining the target sampling delay level, the update module is also used to: clear the ECC error correction count and / or CRC error count.

[0029] In one possible implementation, the timing calibration device further includes a parameter configuration module (not shown), which is used to: configure the timing calibration parameters corresponding to the SPI receiver using device tree attributes; or configure the timing calibration parameters corresponding to the SPI receiver using a memory-based virtual file interface.

[0030] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0031] The memory stores the instructions that the computer executes;

[0032] The processor executes computer-executable instructions stored in memory to implement the timing calibration method for the SPI interface as provided in the first aspect above.

[0033] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the timing calibration method for the SPI interface as provided in the first aspect above.

[0034] Fifthly, this application provides a computer program product, comprising: a computer program, which, when executed by a processor, implements the timing calibration method for the SPI interface as provided in the first aspect above.

[0035] The timing calibration method, apparatus, device, medium, and program product for the SPI interface provided in this application, in response to the completion of SPI driver loading and initialization of a target device with an SPI interface, obtains the current temperature of the target device, a reference data block, the previous timing calibration temperature, and the current sampling delay level used to adjust the sampling timing of the SPI receiver in the target device. It calculates the temperature difference between the current temperature and the previous timing calibration temperature, and determines whether to trigger local timing incremental calibration based on the temperature difference. Further, when it is determined that local timing incremental calibration is triggered, it performs local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level. Then, it updates the sampling timing configuration of the SPI receiver using the target sampling delay level and updates the previous timing calibration temperature to the current temperature. This application employs a temperature-monitored local incremental timing calibration mechanism. After the target device completes SPI driver loading and initialization, it acquires the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration. Based on the temperature difference between the current temperature and the last timing calibration temperature, it determines whether to trigger local incremental timing calibration. This allows for targeted timing calibration adjustments to the current sampling delay level when temperature changes cause timing drift in the SPI interface. This enables continuous tracking and dynamic compensation of sampling point phase shifts caused by temperature drift. Furthermore, by updating the sampling timing configuration at the SPI receiver, it improves the timing adaptability and transmission stability of the high-speed SPI reading process, reduces the rate of occasional data errors, and lowers the system overhead caused by invalid calibration operations, thereby enhancing the long-term operational stability of the device. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] Figure 1 This is a schematic diagram illustrating an application scenario provided in the embodiments of this application;

[0038] Figure 2 A flowchart illustrating the timing calibration method for the SPI interface provided in this application embodiment. Figure 1 ;

[0039] Figure 3 A flowchart illustrating the timing calibration method for the SPI interface provided in this application embodiment. Figure 2 ;

[0040] Figure 4 A schematic diagram illustrating the adaptive tracking of sampling delay levels as they drift with temperature, provided in an embodiment of this application.

[0041] Figure 5A schematic diagram of the timing calibration device for the SPI interface provided in the embodiments of this application;

[0042] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0043] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] The following section will first explain the technical terms used in the embodiments of this application.

[0046] 1) SPI: Serial Peripheral Interface, a synchronous serial communication interface standard;

[0047] 2) BMC: Baseboard Management Controller, used for out-of-band management of the server;

[0048] 3) Sampling point register: A configurable register inside the SPI controller used to control the timing of data sampling;

[0049] 4) Incremental calibration: A timing calibration method that rescans and adjusts only within a small range based on the existing configuration;

[0050] 5) Golden Data: Known correct data read from Flash under a low-speed reliable clock, used as a comparison benchmark for high-speed sampling point testing;

[0051] 6) ECC: Error Correction Code, a coding technique used to detect and correct data errors;

[0052] 7) CRC: Cyclic Redundancy Check, a verification algorithm used to detect data transmission errors;

[0053] 8) Device tree: A data structure in the Linux kernel used to describe hardware configuration;

[0054] 9) sysfs: A virtual file system provided by the Linux kernel for exporting kernel object information to user space.

[0055] In related technologies, high-speed SPI communication typically employs a one-time power-on timing calibration method to perform timing calibration on the SPI interface. This means that timing calibration is performed only once when the SPI driver is loaded, and the sampling timing of the SPI interface is not updated during subsequent operation. However, with long-term operation, changes in ambient temperature can cause propagation delay drift in PCB traces (e.g., a timing drift of approximately 0.1%-0.2% per degree Celsius temperature change). For an SPI signal with a 100MHz clock, the clock period is only 10 nanoseconds, and a 30°C temperature change can potentially generate approximately 3%-6% timing drift. When the calibrated sampling point configuration value is no longer in the center of the stable window during driver loading, sporadic CRC check errors or data errors may occur during high-speed SPI data reading.

[0056] On the other hand, high-speed SPI communication uses a static parameter pre-configuration method based on temperature range to complete the timing calibration of the SPI interface. Specifically, during the initial timing calibration, the "maximum successful sampling delay value" and "minimum successful sampling delay value" are measured, and then a set of parameters is statically selected according to the operating temperature range of the device's control chip (SoC chip) (e.g., -40℃-0℃, 0℃-40℃, 40℃-85℃). However, this method has the following shortcomings: 1) The temperature range is divided too coarsely, and it cannot cope with continuous temperature fluctuations within the same range; 2) The parameter selection is statically pre-configured rather than dynamically adjusted at runtime, and the parameter selection is fixed, lacking the ability to dynamically adjust at runtime; 3) Multiple temperature points need to be measured in advance, resulting in high testing costs and poor flexibility.

[0057] Based on the technical problems existing in related technologies, this application's embodiments adopt a local incremental timing calibration mechanism based on temperature monitoring. After the target device completes SPI driver loading and initialization, it acquires the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration. Based on the temperature difference between the current temperature and the last timing calibration temperature, it determines whether to trigger local incremental timing calibration. When temperature changes cause SPI interface timing drift, it can specifically adjust the timing calibration of the current sampling delay level, realizing continuous tracking and dynamic compensation for the sampling point phase offset caused by temperature drift. Thus, based on updating the sampling timing configuration of the SPI receiver, it improves the timing adaptability and transmission stability of the SPI high-speed reading process, reduces the rate of occasional data errors, reduces the system overhead caused by invalid calibration operations, and improves the long-term operational stability of the device.

[0058] The application scenarios of the embodiments of this application will be described below first.

[0059] The timing calibration method for the SPI interface provided in this application is applicable to embedded systems such as server baseboard management controllers (BMCs) with SPI interfaces that need to operate for a long time in a wide temperature range (e.g., -40℃ to 85℃).

[0060] Figure 1 This is a schematic diagram illustrating an application scenario provided in an embodiment of this application. For example... Figure 1 As shown, the BMC control chip integrates an SPI controller, which in turn integrates a configurable sampling point register.

[0061] The BMC control chip is connected to an external SPI flash memory via an SPI bus, and the system firmware is stored in the SPI Flash.

[0062] The BMC (Browser Controller) integrates firmware loading, hardware status monitoring, and remote device management functions. In a server BMC system, during the system power-on startup phase, the BMC control chip (such as an Advanced RISC Machine (ARM) Cortex-A series processor) needs to read the startup code from the SPI Flash and load it into the BMC control chip's internal Static Random Access Memory (SRAM) or Double Data Rate (DDR) memory for execution. Specifically, during system power-on startup, data must be read into the BMC control chip's internal memory using a 100MHz high-frequency clock for execution.

[0063] To shorten startup time and improve system response speed, the SPI clock frequency is typically configured to 50MHz to 100MHz or even higher.

[0064] Specifically, the core driver layer of the BMC control chip deploys a temperature monitoring unit, a trigger judgment unit, a local timing incremental calibration unit, and a sampling timing configuration update unit. Each software unit can interact with the sampling point register within the hardware SPI controller to read and configure the sampling delay level.

[0065] The temperature monitoring unit is used to periodically read the temperature measurement values ​​of the onboard temperature sensor of the BMC board or the internal temperature sensor of the control chip, and record the real-time operating temperature of the control chip.

[0066] The trigger judgment unit is used to combine multiple judgment conditions such as temperature change difference, timed polling cycle, and read / write error feedback to output the judgment result of whether to start triggering local time-series incremental calibration.

[0067] The local timing incremental calibration unit is used to quickly select the optimal sampling delay level that is suitable for the current temperature conditions by traversing only the local scanning window around the current sampling delay level, using the fixed reference data block in the SPI Flash as the calibration benchmark.

[0068] The sampling timing configuration update unit supports both atomic operation and double buffering update mechanisms, and is used to complete the switching and updating of the SPI receiver sampling timing configuration without interfering with the ongoing SPI read and write operations.

[0069] Optionally, the core driver layer of the BMC control chip can also be deployed with an error statistics feedback unit, which is used to count the CRC error count and the number of ECC error corrections during the SPI data reading process, and use such error statistics as a passive triggering condition for local timing incremental calibration.

[0070] The timing calibration method for the SPI interface provided in this application will be described in detail below with reference to specific embodiments.

[0071] Figure 2 A flowchart illustrating the timing calibration method for the SPI interface provided in this application embodiment. Figure 1 .like Figure 2 As shown, a specific implementation of the timing calibration method for this SPI interface may include the following steps:

[0072] S201, in response to the target device with the SPI interface completing the SPI driver loading initialization, obtain the target device's current temperature, reference data block, current sampling delay level and last timing calibration temperature. The current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device.

[0073] For example, the target device can be a server BMC, board management unit, or other types of embedded systems that have an SPI interface and require an external SPI Flash to be connected via the SPI bus for high-speed reading of boot code, firmware, and configuration data.

[0074] For example, the SPI interface is a hardware communication interface for performing serial data transmission between the target device and an external SPI Flash, and the calibration object is the sampling phase timing on the receiving path of the SPI interface.

[0075] For example, completing the SPI driver loading initialization means that the target device's built-in control chip has completed the basic configuration of the SPI controller clock, chip select, transmit / receive mode, receive buffer, and sampling point register.

[0076] For example, the SPI receiver is the data receiving path of the target device's built-in SPI controller, used to receive serial data transmitted from an external SPI Flash. The sampling point register integrated within the SPI controller is located inside this SPI receiver and is used to configure the delay phase of the data sampling clock.

[0077] Understandably, after the SPI driver loading and initialization are completed, the SPI receiver has entered a readable and configurable state. Starting the timing calibration process at this time can ensure that subsequent data reading and register configuration operations have a stable and deterministic execution basis.

[0078] For example, the current temperature is the real-time temperature value of the target device at the calibration time, output by the temperature sensor inside the target device's built-in control chip, an onboard thermistor, or a temperature acquisition unit that communicates with the control chip. The current temperature can be read periodically.

[0079] In one possible implementation, a kernel timer is registered in the target device kernel to periodically collect temperature data. The temperature collection period can be triggered every 10 seconds. This application does not limit the temperature collection period; it can be determined based on actual application requirements.

[0080] For example, the last timing calibration temperature is the temperature record value stored in the non-volatile memory area, holding register, or runtime management data area of ​​the target device after the previous calibration was completed adjacent to the current time.

[0081] For example, the reference data block is a standard data block used to verify the correctness of data reading. It can be known data pre-programmed into a fixed address in the external SPI Flash, or it can be reference content cached and retained after verification during the target device's power-on startup phase. The fixed address of the SPI Flash can be selected from the Joint Electron Device Engineering Council (JEDEC) ID area. Areas such as the signature area and the read-only checksum section within the firmware image. For example, the reference data block can be stored in... The signature area is located at offset address 0x1000, and its length can be set to 256 bytes. This reference data block is preset during the SPI Flash programming stage, and its contents are used as a criterion for data correctness during subsequent calibration.

[0082] For example, the length of the reference data block can be set to a number of consecutive bytes or words, as long as the length is sufficient to distinguish between correct and incorrect sampling results. This application does not limit the specific length of the reference data block; it can be determined based on actual application requirements.

[0083] For example, the current sampling delay level is the currently active sampling configuration logic level, corresponding to the sampling point configuration value in the sampling point register. The configuration value mapped to this level directly determines the data sampling time of the SPI receiver relative to the clock edge.

[0084] For example, in this step, the response action can be triggered by the SPI driver in the initialization completion callback function; or it can be triggered by the system startup task detecting that the SPI controller status bit flag has been initialized.

[0085] For example, one possible implementation of this step is as follows: Read the temperature sensor register or access the temperature acquisition device via the bus to obtain a temperature value reflecting the current thermal state of the target device, i.e., the current temperature; read the reference reference data block from the predefined SPI Flash physical address range, or directly obtain the standard content and its corresponding address information from the reference image pre-stored in the target device to obtain the reference reference data block; read the current value of the sampling point register at the SPI receiver and map the register value to the corresponding range number to obtain the current sampling delay range; read the most recently written temperature data from the calibration record area to obtain the previous timing calibration temperature. If the system is powered on for the first time and there are no historical calibration temperature records, the current temperature at the time of SPI driver loading and initialization can be written as the initial reference temperature, and the current sampling delay range at that time can be used as the initial range for subsequent processes.

[0086] S202, calculate the temperature difference between the current temperature and the previous timing calibration temperature, and determine whether to trigger local timing incremental calibration based on the temperature difference.

[0087] The temperature difference is the difference between the current temperature and the temperature of the last time-series calibration, which is used to characterize the magnitude of the change in the thermal state of the target device since the last calibration.

[0088] It is understandable that the setup and hold timing window for high-speed data reading via the SPI interface is affected by the internal circuit delay of the control chip, the transmission characteristics of the PCB traces, and the timing drift of the external SPI Flash device itself. When the temperature change reaches a certain threshold, the currently active sampling delay level will deviate from the stable sampling range. Therefore, by calculating the temperature difference between the current temperature and the previous timing calibration temperature, and determining whether to perform local timing incremental calibration based on the temperature difference, the calibration trigger logic can be matched and linked with the temperature drift amplitude.

[0089] For example, local time-series incremental calibration refers to the process of adjusting the sampling delay level and verifying the data only near the currently effective sampling delay level without having to traverse all the sampling delay levels that the sampling point register supports. This corrects the data sampling position while controlling the calibration time and computing power.

[0090] For example, in one possible implementation, the temperature difference between the current temperature and the previous timing calibration temperature is calculated, and it is determined whether the absolute value of the temperature difference is greater than a preset temperature threshold. If the absolute value of the temperature difference is greater than or equal to the preset temperature threshold, then it is determined that local timing incremental calibration is triggered; if the absolute value of the temperature difference is less than the preset temperature threshold, then it is determined that local timing incremental calibration is not triggered. The preset temperature threshold can be a value such as 5℃.

[0091] For example, the preset temperature threshold value can be set based on the board design, SPI clock frequency, and sampling delay level resolution. For instance, a temperature rise or fall amplitude that reflects a perceptible timing drift can be used as the criterion. This application does not specifically limit the value of the preset temperature threshold; it can be determined according to actual application requirements.

[0092] For example, the temperature difference can be expressed by the following formula:

[0093]

[0094] in, Indicates temperature difference. Indicates the current temperature. This indicates the temperature of the last timing calibration.

[0095] Understandably, in this step, by using the temperature change between the current temperature and the previous time-series calibration temperature as the criterion for triggering local time-series incremental calibration, the calibration behavior no longer relies on the static threshold configuration of a fixed temperature zone, but is driven by the real-time thermal state of the target device. This establishes a direct correspondence between whether calibration is performed and the actual time-series drift amplitude, linking the calibration behavior with the real-time thermal state of the target device. This avoids invalid calibration operations, reduces unnecessary full-range traversal scanning, lowers system overhead, and provides reasonable triggering timing for local range search constraints. It also ensures that the sampling time sequence always adapts to the current temperature conditions, reducing occasional data errors.

[0096] S203, if it is determined that local timing incremental calibration is triggered, then local timing incremental calibration is performed on the current sampling delay level according to the reference data block to obtain the target sampling delay level.

[0097] In this step, the reference data block serves as a criterion for the correctness of data reading, used to compare whether the data actually read by the SPI receiver at the candidate sampling delay level is consistent with the standard content.

[0098] The current sampling delay level is the reference position for local time-series incremental calibration. Calibration around this level can concentrate the search range within the range where there is a high probability of a stable sampling interval. The core logic of local time-series incremental calibration is as follows: register configuration, reference data reading and verification comparison are performed sequentially on several candidate sampling delay levels around the current sampling delay level. The level with consistent verification results is selected as the effective sampling delay level, and the target sampling delay level is selected from all effective sampling delay levels.

[0099] For example, the target sampling delay level is a new sampling configuration level that officially takes effect on the target device after the completion of this round of local timing incremental calibration, used to replace the original current sampling delay level.

[0100] For example, in one possible implementation, for multiple candidate sampling delay levels surrounding the current sampling delay level, their corresponding sampling point configuration values ​​are sequentially written to the sampling point register. After the configuration takes effect, the SPI interface is controlled to read real-time data of equal length from a fixed address in the storage reference data block, and the read real-time data is compared with the reference data block. If the read data corresponding to the candidate sampling delay level is consistent with the reference data block, the candidate sampling delay level is determined to be a valid sampling delay level and included in the selection range of the target sampling delay level. After verifying all candidate sampling delay levels within the local timing increment calibration interval, the target sampling delay level is selected from all valid sampling delay levels that have passed the verification. The target sampling delay level is preferentially selected based on its superior stability compared to the current sampling delay level, ensuring that the updated sampling timing adapts to the data sampling requirements of the SPI receiver under the current hot state.

[0101] Understandably, this step, by performing local timing incremental calibration centered on the current sampling delay level, avoids the time overhead of traversing all levels. By relying on a reference data block for real data reading and verification, the target sampling delay level is determined based on actual link transmission data, rather than simply relying on theoretical timing estimation. In summary, this step transforms the timing offset caused by temperature changes into a quantifiable level search and data verification process, realigning the SPI receiver's sampling point with the stable data sampling range of the external SPI Flash.

[0102] S204 uses the target sampling delay level to update the sampling timing configuration of the SPI receiver and updates the temperature of the last timing calibration to the current temperature.

[0103] In this step, updating the sampling timing configuration of the SPI receiver means writing the register configuration value corresponding to the target sampling delay level determined in step S203 into the sampling point register or equivalent timing control unit inside the SPI receiver, so that subsequent SPI data reception is performed according to the new sampling time.

[0104] In this process, after updating the previous time-series calibration temperature to the current temperature, the calibration result is written into the calibration record and used as the reference value for the next temperature difference calculation, thus forming a continuous closed loop.

[0105] For example, in one possible implementation, after obtaining the target sampling delay level, it is first determined whether the SPI interface of the target device is in a transmission idle state. When it is detected that the chip select signal is not activated, the transmit / receive first-in, first-out (FIFO) buffer is empty, or the current transmission transaction end flag is set, the register configuration value corresponding to the target sampling delay level is written to the sampling point register, and the sampling point register is read back for verification to confirm that the sampling point register configuration is updated correctly. After the sampling point register is updated, the reference data block can be read again, or a short data verification read operation can be performed to verify that the data read under the target sampling delay level is consistent with the reference data block. Then, the current temperature value is written to the record area used to store the temperature of the last timing calibration, and the currently effective target sampling delay level can be saved simultaneously as the status basis for subsequent timing calibration and fault tracing.

[0106] Understandably, in this step, by serializing temperature change detection, local timing increment calibration, target sampling delay level determination, and register configuration update into a continuous execution process, the SPI interface can correct the receiving sampling time according to the real-time thermal state during long-term operation and temperature fluctuations of the target device. This maintains the stability and configuration adaptability of high-speed reading of external SPI Flash without relying on static compensation in a fixed temperature zone or frequently performing full timing calibration.

[0107] This application embodiment employs a local incremental timing calibration mechanism based on temperature monitoring. After the target device completes SPI driver loading and initialization, it acquires the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration. Based on the temperature difference between the current temperature and the last timing calibration temperature, it determines whether to trigger local incremental timing calibration. When temperature changes cause SPI interface timing drift, it can specifically adjust the timing calibration of the current sampling delay level, achieving continuous tracking and dynamic compensation for the sampling point phase shift caused by temperature drift. Furthermore, based on updating the sampling timing configuration of the SPI receiver, it improves the timing adaptability and transmission stability of the SPI high-speed reading process, reduces the rate of occasional data errors, and reduces the system overhead caused by invalid calibration operations, thereby improving the long-term operational stability of the device.

[0108] Alternatively, in one possible implementation, if it is determined that no local timing increment calibration needs to be triggered, the sampling timing configuration of the sampling point register is kept unchanged, and the SPI controller of the target device continues to operate using the stored current sampling delay level.

[0109] The following is combined Figure 3 A detailed explanation is provided of a specific implementation method in step S203, which involves performing local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0110] Figure 3 A flowchart illustrating the timing calibration method for the SPI interface provided in this application embodiment. Figure 2 .like Figure 3 As shown, a specific implementation of the timing calibration method for this SPI interface, which performs local timing incremental calibration on the current sampling delay level based on a reference data block to obtain the target sampling delay level, may include the following steps:

[0111] S301, taking the current sampling delay level as the center, and based on the first preset scanning window half-width, determine the first scanning window corresponding to the current sampling delay level. The first scanning window includes multiple consecutive first sampling delay levels.

[0112] For example, the half-width of the first preset scanning window can be 5. This application embodiment does not limit the specific value of the half-width of the first preset scanning window; it can be determined according to actual application requirements.

[0113] For example, the current sampling delay level can be any of the sampling delay levels supported by the sampling point register.

[0114] Taking a current sampling delay level of 36 and a first preset scan window half-width of 5 as an example, the lower limit of the first scan window corresponding to the current sampling delay level can be 31, and the upper limit of the first scan window can be 41. The determination method for the first scan window corresponding to other levels can be deduced in the same way.

[0115] Understandably, when the sampling delay range supported by the sampling point register is 0-63, let any current sampling delay level be denoted as P, and set the preset scan window half-width to N. Then, the lower limit of the scan window corresponding to any current sampling delay level P is P. min = max(0, P- N), where the upper limit of the scanning window is P. max = min(63, P + N).

[0116] S302, for each first sampling delay level, configure the sampling point register of the SPI receiver to the first sampling point configuration value corresponding to the first sampling delay level, and read the current data corresponding to the fixed address of the reference data block stored in the SPI flash memory under the first sampling point configuration value.

[0117] Specifically, the length of the current data corresponding to the fixed address of the reference data block stored in the SPI receive buffer read under the first sampling point configuration value is the same as the length of the reference data block, so as to ensure that the data granularity is the same when comparing data one by one.

[0118] For example, the reference data block can be pre-stored at a specified logical address in the SPI Flash, while the current data is the content read from the SPI Flash at the same address under the corresponding first sampling delay level. When comparing the two, byte-by-byte consistency verification can be used.

[0119] For example, in one possible implementation, all first sampling delay levels are traversed, and the first sampling point configuration value corresponding to each first sampling delay level is configured in the sampling point register in the traversal order. After the first sampling point configuration value takes effect, the current data corresponding to the fixed address of the reference data block stored in the SPI Flash is read, and the current data corresponding to each first sampling delay level is stored in the SPI receive buffer for subsequent comparison and verification with the reference data block.

[0120] S303, compare the current data read under each first sampling delay level with the reference data block one by one to obtain the first effective sampling delay level set corresponding to the first scanning window.

[0121] For example, the current data read under each first sampling delay level is compared with the reference data block byte by byte or word by word. If the current data is completely consistent with the reference data block, the first sampling delay level is marked as a valid sampling delay level; if the current data is inconsistent with the reference data block in any byte or word, the first sampling delay level is marked as an invalid sampling delay level; the set of all valid sampling delay levels is determined as the first valid sampling delay level set.

[0122] S304, determine the target sampling delay level from the first set of effective sampling delay levels.

[0123] For example, in one possible implementation, a continuous effective sampling delay interval is selected from the first effective sampling delay interval set, and the midpoint of this interval is determined as the target sampling delay interval. For instance, if the effective sampling delay interval included in the first effective sampling delay interval set is 33-39, the midpoint 36 of the interval is determined as the target sampling delay interval. In another possible implementation, if a continuous effective sampling delay interval cannot be formed in the first effective sampling delay interval set, and only discrete effective sampling delay intervals that are not adjacent to each other exist, the effective sampling delay interval with the best sampling stability is selected as the target sampling delay interval.

[0124] In this embodiment, by limiting the first scanning window to only perform level detection within the neighborhood of the current sampling delay level, and using a reference data block to perform consistency verification on the current data read under different first sampling delay levels, a first effective sampling delay level set is obtained. Furthermore, based on this first effective sampling delay level set, target sampling delay levels are selected. This method can complete SPI receiver timing calibration without fully traversing all sampling delay levels. The updated sampling point configuration values ​​are used for subsequent SPI Flash data reading, ensuring read / write timing adapts to the current temperature conditions of the device, thus improving data reading stability and timing calibration efficiency.

[0125] It is understandable that in this embodiment, the calibration range is narrowed by using a local scanning window to reduce the overhead of traversing all ranges. At the same time, effective sampling delay ranges are selected based on the actual data comparison results to ensure that the calibration results meet the current signal integrity requirements and improve calibration efficiency and stability.

[0126] Optionally, in one possible implementation, the timing calibration method for the SPI interface provided in this application embodiment further includes: in response to the absence of a valid sampling delay level in the first scanning window, determining a second scanning window corresponding to the current sampling delay level based on the second preset scanning window half-width, with the current sampling delay level as the center and the second preset scanning window half-width being larger than the first preset scanning window half-width; for each second sampling delay level in the second scanning window, configuring the sampling point register to the second sampling point configuration value corresponding to the second sampling delay level, and reading the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the second sampling point configuration value; comparing the current data corresponding to each second sampling delay level with the reference reference data block one by one to obtain the second valid sampling delay level set corresponding to the second scanning window, and determining the target sampling delay level from the second valid sampling delay level set.

[0127] For example, the half-width of the second preset scanning window can be 8. This application embodiment does not limit the specific value of the half-width of the second preset scanning window; it can be greater than the half-width of the first preset scanning window, and the value can be determined based on actual application requirements.

[0128] The specific implementation of this embodiment is similar to that described above, and will not be repeated here.

[0129] In this embodiment, when no valid sampling delay level is found in the first scanning window, the search range for sampling delay levels is automatically expanded to search for valid sampling working points again in a wider sampling delay interval. For each second sampling delay level in the extended sampling delay interval, i.e., the second scanning window, the current data at the fixed address is read and compared byte by byte with the reference data block. The second valid sampling delay level set is obtained by filtering based on data consistency. Then, the target sampling delay level is selected from the second valid sampling delay level set to complete the SPI receiver sampling configuration update.

[0130] Understandably, in this embodiment, if there is no valid sampling delay level within the first scanning window, the half-width of the scanning window is expanded and the scan is repeated. By traversing a wider range of candidate sampling delay levels, the probability of finding a valid sampling point is increased. Expanding the scanning window can cover a wider range of timing offsets caused by temperature drift, reducing the risk of calibration failure due to an excessively narrow local window and improving the calibration success rate.

[0131] In this embodiment, when the timing margin around the current sampling delay level is insufficient to support stable data reading, a second scanning window with a larger range is opened to search for a valid sampling delay level again. This reduces the risk of calibration failure caused by the lack of a qualified sampling delay level during local narrow window scanning, and allows the selected target sampling delay level to better adapt to the SPI interface timing after temperature drift, thereby improving the stability of high-speed SPI reading and the environmental adaptability of timing calibration.

[0132] Optionally, in one possible implementation, the timing calibration method for the SPI interface provided in this application embodiment further includes: triggering global timing calibration in response to the absence of a valid sampling delay level in the second scanning window; traversing all configurable sampling delay levels in the sampling point register, configuring the sampling point register to the sampling point configuration value corresponding to each sampling delay level, and reading the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the sampling point configuration value; comparing the current data corresponding to each sampling delay level with the reference reference data block one by one to obtain a global set of valid sampling delay levels, and determining the target sampling delay level from the global set of valid sampling delay levels.

[0133] For example, in one possible implementation, after determining that no valid sampling delay level satisfying the comparison conditions is found within the second scanning window, a global timing calibration command is sent to the SPI receiver. The sampling point configuration values ​​(register codes) corresponding to all sampling delay levels supported by the sampling point register are written sequentially to the sampling point register. After each writing and activation of the sampling point configuration value, the current data, with a length consistent with the reference reference data block, is read from a fixed address in the SPI Flash under the current sampling point configuration value. This current data is then compared byte-by-byte or word-by-word with the pre-stored reference reference data block. If the comparison results are consistent, the corresponding sampling delay level is recorded in the global valid sampling delay level set. The sampling point configuration value can use a predefined phase code or delay code in the control register. Different SPI controller models can support different encoding bit widths and the number of levels.

[0134] For example, one possible implementation of determining the target sampling delay level from the set of globally valid sampling delay levels is to filter out a continuous range of valid sampling delay levels from the set of globally valid sampling delay levels and determine the midpoint of the range as the target sampling delay level; another possible implementation is to determine the level that is closest to the current sampling delay level and satisfies the stability constraint as the target sampling delay level, so as to use it as the sampling timing configuration for subsequent SPI data reading operations.

[0135] It is understandable that the target sampling delay level participates in subsequent reception sampling after being written back, so that the SPI interface can still recover usable timing through the global scope when both scans fail.

[0136] Understandably, in this embodiment, if the expanded second scanning window still lacks a valid sampling delay level, a global calibration is triggered. All sampling delay levels are iterated through and compared one by one to select the globally valid sampling delay level. Global calibration serves as a fallback mechanism to ensure that sampling timing can still be restored in the event of a local search failure, thus improving the system's reliability under extreme environments.

[0137] In this embodiment, after the second scanning window fails, all sampling delay levels are further traversed, and one-by-one comparisons are performed based on the reference data block at a fixed address. This enables the discovery of valid sampling positions over a wider range, and the sampling delay level most suitable for the current SPI bus environment is written back to the SPI receiver. Timing recovery can continue even when local searches fail to meet the conditions, thereby improving the determinism and operational stability of the SPI high-speed read configuration.

[0138] It is understood that the embodiments of this application do not limit the number of window scans corresponding to different window sizes during the local time-series incremental calibration process, and the specific number of window scans can be flexibly set according to actual application requirements.

[0139] Optionally, one possible implementation of updating the sampling timing configuration of the SPI receiver by using the target sampling delay level in step S204 is: using atomic operations to update the current sampling delay level to the target sampling delay level; or using a double buffering mechanism to update the current sampling delay level to the target sampling delay level.

[0140] For example, one possible implementation of updating the current sampling delay level to the target sampling delay level using atomic operations is to write the target sampling delay level during the idle interval between two SPI transmissions. Specifically, interrupts are disabled or the SPI receive state machine is frozen, and the target sampling delay level is written and submitted in one go; after the configuration submission is completed, the protection mechanism is immediately removed, and the receive sampling function is restored.

[0141] For example, one possible implementation of updating the current sampling delay level to the target sampling delay level using a double-buffering mechanism is as follows: Two sets of configuration buffers are maintained in the SPI driver layer. The background pre-prepares the new sampling configuration and completes the switching effect through a single register write operation. Specifically, the target sampling delay level is first written to the buffer to be activated. After entering the sampling idle window, the effective buffer is switched to ensure that the delay control value used by the SPI receiver is stable at the target sampling delay level.

[0142] It is understandable that the update process of the sampling timing configuration of the SPI receiver can be performed by the internal firmware of the target device (such as BMC), the SPI controller microarchitecture, or both.

[0143] Understandably, in this embodiment, the atomic operation updates the sampling point register once during the SPI transmission idle interval, avoiding data sampling conflicts during configuration; the double-buffering mechanism maintains two sets of configuration buffers to achieve a seamless transition during configuration switching. Both mechanisms ensure that the sampling point configuration value update process does not interrupt SPI read / write operations, avoiding data loss due to configuration switching and improving system stability.

[0144] In this embodiment, by employing atomic operations or a double-buffering mechanism, the target sampling delay level can replace the current sampling delay level in a controlled manner, avoiding intermediate states in the sampling timing configuration during the update process. This allows the SPI receiver to stably switch to the new sampling position after calibration, ensuring a more continuous process for the sampling timing configuration to take effect. The calibration result after reading the reference data block can be directly converted into a valid configuration, thereby improving the stability and consistency of subsequent high-speed SPI readings.

[0145] Optionally, in one possible implementation, the timing calibration method for the SPI interface provided in this application embodiment further includes: obtaining the previous calibration timestamp and the current timestamp of the target device; calculating the time difference between the current timestamp and the previous calibration timestamp; determining whether to trigger local timing incremental calibration based on the time difference; if it is determined that local timing incremental calibration is triggered, then performing local timing incremental calibration on the current sampling delay level based on the reference reference data block to obtain the target sampling delay level.

[0146] The last calibration timestamp is used to characterize the system time when the most recent sampling timing calibration was completed. The last calibration timestamp can be written to a non-volatile memory area or stored in a control register and refreshed synchronously after each timing update so that it can be read directly in subsequent calls.

[0147] For example, the current timestamp can be obtained by the real-time clock unit or system timing unit inside the target device's built-in control chip.

[0148] For example, in one possible implementation, the time difference between the current timestamp and the previous calibration timestamp is calculated, and it is determined whether the time difference is greater than a preset time interval. If the time difference is greater than the preset time interval, it is determined that the current sampling timing may have deviated from the stable sampling range, and a local timing incremental calibration is triggered. If the time difference is less than or equal to the preset time interval, it is determined that no local timing incremental calibration needs to be triggered, and the current sampling delay level remains unchanged. The preset time interval can be 1 hour. This preset time interval can be preset based on the SPI Flash read rate, board-level trace delay, device temperature drift characteristics, and the field operating cycle. This application embodiment does not limit the size of the preset time interval; it can be determined according to actual application requirements.

[0149] In this embodiment, the specific implementation of performing local timing increment calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level is similar to that described above, and will not be repeated here.

[0150] Understandably, in this embodiment, the last calibration timestamp is recorded and compared with the current timestamp. If the time difference between the current timestamp and the last calibration timestamp exceeds a preset time interval (e.g., 1 hour), local time-series incremental calibration is triggered. The timestamp triggering mechanism ensures that the system is calibrated periodically during long-term operation, avoiding sampling point drift caused by cumulative environmental changes and improving long-term stability.

[0151] In this embodiment of the application, by adopting a local timing incremental calibration method based on time difference triggering, the system can correct only the effective sampling delay interval near the current sampling delay level after a long running interval or cumulative environmental changes, reducing unnecessary full scan overhead and keeping the updated sampling timing matched with the current working state, thereby improving the stability and continuous adaptability of SPI high-speed reading.

[0152] Optionally, based on the above embodiments, in one possible implementation, after obtaining the target sampling delay level, the method further includes: updating the previous calibration timestamp to the current timestamp.

[0153] For example, after obtaining the target sampling delay level, the current timestamp is written to the storage location corresponding to the previous calibration timestamp, so that the subsequent time difference calculation used to determine whether to trigger local timing incremental calibration is performed based on the latest calibration time. This writing process can be performed immediately after the sampling timing configuration is updated, or it can be submitted atomically with the target sampling delay level activation action to maintain the consistency between the calibration record and the actual activation time.

[0154] For example, if the previous calibration timestamp is stored in a register, the register is directly assigned a value; if the previous calibration timestamp is stored in SPI Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM), or other non-volatile media, the timestamp is updated through the firmware write interface, and the verification status flag is refreshed after successful writing to ensure that the latest valid time information is read during the next calibration judgment.

[0155] Understandably, in this embodiment, after updating the target sampling delay level, the current timestamp is written to the storage area of ​​the previous calibration timestamp to provide a time reference for subsequent calibrations. Timestamp updates ensure that the calibration triggering logic is based on the latest calibration time, reducing the risk of duplicate or missed calibrations and improving the accuracy of calibration history records.

[0156] In this embodiment, the previous calibration timestamp is updated promptly after the target sampling delay level is obtained, ensuring that subsequent temperature difference or time difference determinations are always based on the latest calibration time. This maintains consistency between the local calibration triggering conditions and the actual calibration history, reducing duplicate or missed calibrations. Furthermore, since the calibration record is updated synchronously with each valid calibration, the timing management of the SPI receiver is more continuous during long-term operation, thereby improving timing adaptability and configuration reliability in high-speed reading scenarios.

[0157] Optionally, in one possible implementation, the timing calibration method for the SPI interface provided in this application embodiment further includes: during the operation of the SPI receiver, acquiring the ECC error correction count and / or the CRC error count; determining whether to trigger local timing incremental calibration based on the ECC error correction count or the CRC error count; if it is determined that local timing incremental calibration is triggered, then performing local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0158] Among them, the ECC error correction count is used to characterize the cumulative number of anomalies that still occur after error correction during continuous reading at the SPI receiver; the CRC error count is used to characterize the number of mismatches of data frames in the SPI receive buffer during the verification phase.

[0159] For example, both the ECC error correction count and the ECC error correction counter can be obtained in real time from the status register, error statistics register, or firmware-maintained counting unit within the SPI controller.

[0160] It is understandable that both the ECC error correction count and the ECC error correction counter are cumulative counts.

[0161] For example, in one possible implementation, during the operation of the SPI receiver, the system continuously polls or reads the ECC error correction count and / or CRC error count in an event-triggered manner, and combines the preset absolute error threshold, unit time error increment threshold, and count change rate threshold to determine whether the current sampling timing of the SPI has drifted; when the ECC error correction count or CRC error count reaches the trigger condition, it determines to trigger local timing increment calibration.

[0162] For example, one possible implementation for determining whether to trigger local timing incremental calibration based on ECC error correction counts is as follows: determine whether the ECC error correction count exceeds the ECC error correction trigger threshold; if the number of ECC error corrections exceeds the ECC error correction trigger threshold, then determine to trigger local timing incremental calibration; if the number of ECC error corrections does not exceed the ECC error correction trigger threshold, then determine that local timing incremental calibration does not need to be triggered, and maintain the current sampling delay level unchanged. The ECC error correction trigger threshold can be 10 times per hour. This application embodiment does not limit the ECC error correction trigger threshold; it can be determined according to actual application requirements.

[0163] For example, one possible implementation for determining whether to trigger local time-series incremental calibration based on CRC error count is as follows: determine whether the CRC error count exceeds a CRC error triggering threshold; if the CRC error count exceeds the CRC error triggering threshold, then determine to trigger local time-series incremental calibration; if the CRC error count does not exceed the CRC error triggering threshold, then determine that local time-series incremental calibration is not required, and maintain the current sampling delay level unchanged. The CRC error triggering threshold can be 3 times per minute. This application does not limit the CRC error triggering threshold; it can be determined according to actual application requirements.

[0164] In this embodiment, the specific implementation of performing local timing increment calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level is similar to that described above, and will not be repeated here.

[0165] Understandably, in this embodiment, the ECC error correction count and CRC error count are counted during the operation of the SPI receiver. When the error count exceeds a preset threshold, local timing incremental calibration is triggered. The error count triggering mechanism uses the service operation status to provide feedback on calibration requirements, thereby improving the system's response capability to sudden timing degradation and reducing the data error rate.

[0166] In this embodiment, by using ECC error correction count and / or CRC error count as the calibration trigger basis, the SPI receiver can promptly enter the local timing incremental calibration process when data errors accumulate to a certain extent, and redetermine the target sampling delay level based on the reference data block, thereby keeping the sampling timing matched with the current operating state, reducing the probability of verification anomalies in high-speed reading, and reducing the dependence on global recalibration.

[0167] Optionally, based on the above embodiments, after obtaining the target sampling delay level, in one possible implementation, it further includes: clearing the ECC error correction count and / or CRC error count.

[0168] For example, after obtaining the target sampling delay level and completing the sampling timing update, the error statistics related to this calibration are reset, clearing the ECC error correction count and / or CRC error count to zero, so that new error correction events or verification error events can be accumulated from zero again during subsequent operation. For cases where registers are used to store the count values, the firmware can write a preset clear value to the corresponding register, or write a valid level to the clear control bit in the register to trigger hardware to clear the count. For cases where software maintains the count values, the firmware can directly assign the corresponding variable to zero and synchronously refresh it to the running status table. If the system is configured with both ECC error correction statistics and CRC verification statistics, after completing the target sampling delay level update, both types of counts can be cleared synchronously, or only one type of error count corresponding to the current calibration criterion can be cleared, depending on the verification architecture of the target device.

[0169] Understandably, in this embodiment, after updating the target sampling delay level, the ECC error correction count and CRC error count are cleared to zero, resetting the error statistics starting point. Clearing the error count ensures that subsequent error statistics reflect the actual operating status of the current sampling configuration, avoiding interference from historical error data in calibration triggering judgments.

[0170] In this embodiment, the clearing process is coordinated with the update of the target sampling delay level, so that the new sampling timing corresponds to a new error statistics starting point. If the error count subsequently increases again, it can directly reflect the actual operating status of the current sampling configuration under the new conditions, thereby providing an accurate basis for the next local timing incremental calibration. By resetting the error count after calibration, the ECC error correction count and CRC error count no longer retain historical values, reducing interference with subsequent calibration trigger judgments and forming a consistent closed-loop relationship between timing adjustment and error feedback.

[0171] Optionally, in one possible implementation, the timing calibration method for the SPI interface provided in this application embodiment further includes: configuring the timing calibration parameters corresponding to the SPI receiver using device tree attributes; or configuring the timing calibration parameters corresponding to the SPI receiver using a memory-based virtual file interface.

[0172] For example, a memory-based virtual file interface could be a memory-based sysfs virtual file interface.

[0173] For example, timing calibration parameters include, but are not limited to, a preset temperature threshold (°C) for triggering local timing incremental calibration, a preset time interval (e.g., 3600 seconds) for triggering local timing incremental calibration, half-width of the scan window, CRC error trigger threshold, ECC error correction trigger threshold, size of the reference data block (bytes), and the fixed address (i.e., offset address) of the reference data block in SPIFlash.

[0174] For example, the device tree attribute configuration method is suitable for scenarios where parameters are fixed or predetermined with the board version. After detecting the SPI controller, the driver reads the corresponding attribute node, parses out the calibration field related to the SPI receiver based on the attribute name, and takes effect after clock and bus initialization is completed.

[0175] For example, the timing calibration parameter node corresponding to the SPI receiver in the Linux device tree can be represented as:

[0176] spi_calib {

[0177] temp-threshold = <5> ;

[0178] scan-window = <5> ;

[0179] ref-data-offset = <0x1000>;

[0180] ref-data-size = <256> ;

[0181] };

[0182] For example, the memory-based virtual file interface configuration method is suitable for scenarios that are dynamically adjusted during operation. The interface file can be mounted in the system's virtual file system, and the written content can be expressed in the form of hexadecimal values ​​or text key-value pairs. The driver updates the current valid parameters after parsing according to the preset format, and triggers the subsequent timing calibration logic after the parameter update is completed, so that the SPI receiver performs sampling control under the new parameter constraints.

[0183] For example, the virtual file interface configuration is as follows: The configuration interface is exported through the sysfs virtual file system. For instance, file nodes such as temp_threshold and scan_window are created under / sys / class / spi_calib / . User space can dynamically adjust the parameters by writing values ​​(e.g., echo 5 > temp_threshold). After the driver layer parses the configuration, it triggers subsequent timing calibration logic.

[0184] Understandably, in this embodiment, calibration parameters (such as temperature threshold and scan window width) are configured through device tree attributes or the sysfs virtual file interface. The parameter configuration method supports both static loading and dynamic distribution, allowing calibration parameters to adapt to different hardware designs and operational requirements, thus improving system flexibility and deployment efficiency.

[0185] In this embodiment, the above configuration method performs the functions of static loading and dynamic distribution during operation, enabling the timing calibration parameters corresponding to the SPI receiver to be reliably transmitted to the driver layer through system description information or runtime interface, and further participate in the selection and updating of sampling delay levels. This configuration method clarifies the parameter source and application path, facilitating unified management of SPI receiver timing across different board configurations and operational stages. This results in better controllability and consistency in the setting, modification, and activation of calibration parameters.

[0186] The following describes in detail a specific implementation of the timing calibration method for the SPI interface provided in this application embodiment, taking an SPI clock frequency of 100MHz as an example and combining specific embodiments.

[0187] For example, a specific implementation of the timing calibration method for the SPI interface may include the following steps:

[0188] S1, SPI driver loading and initialization:

[0189] During SPI driver loading, a one-time complete timing calibration is performed, resulting in an initial sampling delay level P0=36 and an initial temperature T0=25℃; a Flash offset address of 0x1000 and a length of 256 bytes are selected. The signature area serves as a baseline reference data block, which is read and cached in memory.

[0190] S2, periodically monitor the real-time temperature of the target equipment:

[0191] Register a kernel timer in the target device kernel to read the temperature sensor value every 10 seconds;

[0192] When the current temperature is detected to rise from 25℃ to 30℃, the temperature difference ΔT=5℃ reaches the preset temperature threshold, triggering local time-series incremental calibration.

[0193] S3, Perform local timing increment calibration:

[0194] The current sampling delay level, i.e. the initial sampling delay level, is 36. When the preset half-width of the scanning window N=5, the corresponding scanning range of the scanning window is 31-41.

[0195] Configure the sampling point register of the SPI receiver to the sampling point configuration values ​​corresponding to each sampling delay level, namely 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, and 41. Under each sampling point configuration value, read the current data corresponding to the fixed address of the reference data block stored in the SPI Flash. Compare the current data read under each sampling delay level with the reference data block one by one to obtain the set of valid sampling delay levels corresponding to the scanning window.

[0196] Specifically, when the effective sampling delay range within the effective sampling delay range set is 33-39, the midpoint 36 of the range is determined as the target sampling delay range. If this target sampling delay range is the same as the current sampling delay range, then there is no need to update the sampling timing configuration of the SPI receiver.

[0197] The calibration temperature was recorded as 30℃.

[0198] S4, continuously and periodically monitors the real-time temperature of the target equipment:

[0199] When the current temperature is detected to rise to 55℃, the temperature difference meets the trigger condition again, triggering the local time-series incremental calibration again.

[0200] S5, perform local timing increment calibration again:

[0201] The corresponding scanning window has a scanning range of 31-41.

[0202] The sampling point register of the SPI receiver is sequentially configured to the sampling point configuration values ​​corresponding to each sampling delay level: 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, and 41. Under each sampling point configuration value, the current data corresponding to the fixed address of the reference data block stored in the SPI Flash is read. The current data read under each sampling delay level is compared with the reference data block one by one to obtain the set of valid sampling delay levels corresponding to the scanning window.

[0203] Among them, when the effective sampling delay range included in the effective sampling delay range set is 35-41, the midpoint 38 of the range is determined as the target sampling delay range.

[0204] Update the sampling timing configuration in the sampling point register from 36 to 38.

[0205] The timing calibration temperature was recorded as 55℃.

[0206] S6, continuously and periodically monitors the real-time temperature of the target equipment:

[0207] When the current temperature is detected to rise to 85°C, local time-series incremental calibration is triggered again.

[0208] S7, perform local timing increment calibration again:

[0209] The current sampling delay level is 38. When the preset half-width of the scanning window is N=5, the corresponding scanning range of the scanning window is 33-43.

[0210] The sampling point register of the SPI receiver is sequentially configured to the sampling point configuration values ​​corresponding to each sampling delay level: 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, and 43. Under each sampling point configuration value, the current data corresponding to the fixed address of the reference data block stored in the SPI Flash is read. The current data read under each sampling delay level is compared with the reference data block one by one to obtain the set of valid sampling delay levels corresponding to the scanning window.

[0211] Among them, when the effective sampling delay range included in the effective sampling delay range set is 39-43, the midpoint 41 of the range is determined as the target sampling delay range.

[0212] Update the sampling timing configuration in the sampling point register from 38 to 41.

[0213] The timing calibration temperature was recorded as 85℃.

[0214] Figure 4 This is a schematic diagram illustrating the adaptive tracking of sampling delay levels with temperature drift, provided in an embodiment of this application. Figure 4 In the figure, the vertical axis represents the sampling delay level, the horizontal axis represents the temperature (°C), the black dot represents the sampling delay level that remains unchanged after the driver is loaded and initialized in the related technology, and the black pentagram represents the adaptive sampling delay level obtained by dynamic calibration through the timing calibration method of the SPI interface provided in the embodiment of this application.

[0215] like Figure 4 As shown, within the temperature range of 25℃-45℃, the sampling delay level of this scheme remains unchanged at 36, coinciding with the sampling delay level of related technologies. As the temperature continues to rise, at 55℃, the corresponding dynamically calibrated sampling delay level is updated to 38; at 65℃, the corresponding dynamically calibrated sampling delay level is updated to 40; at 75℃, the corresponding dynamically calibrated sampling delay level is updated to 42; and at 85℃, the corresponding dynamically calibrated sampling delay level is updated to 43, achieving continuous adaptive tracking of temperature time-series drift.

[0216] In summary, compared to the following shortcomings of related technologies: One-time power-on calibration solutions can only adapt to the initial environmental signal integrity during device initialization. During long-term device operation, when environmental temperature changes cause timing drift, they lack adaptive adjustment capabilities and cannot dynamically compensate for timing offsets during operation. Static parameter pre-configuration solutions based on temperature range division rely on segmented fixed parameters for compensation, which cannot finely track continuous temperature changes, resulting in coarse temperature compensation adjustment granularity and poor timing adaptation accuracy. While hardware-fixed temperature compensation solutions can automatically adapt to temperature drift, the compensation logic is integrated into the hardware, preventing firmware developers from adjusting key parameters according to different product requirements or flexibly switching calibration functions on and off, resulting in poor overall configurability and versatility. Traditional solutions no longer continuously monitor the read / write quality of sampling points after the calibration process is completed, lacking a feedback trigger mechanism based on actual business read / write status, and cannot detect real-time timing degradation scenarios during operation.

[0217] The timing calibration method for the SPI interface provided in this application has the following beneficial effects:

[0218] 1) Adaptive temperature adjustment during operation, balancing timing compensation accuracy and long-term operational stability: Utilizing periodic temperature acquisition and a local timing incremental calibration mechanism, continuous tracking and dynamic compensation of sampling delay levels as temperature drifts are achieved. Experimental data shows that within the full temperature range of 25℃-85℃, the number of SPI high-speed read errors decreased from 7 times / 5 minutes to 0 times / 5 minutes after adopting the method provided in this application embodiment, significantly improving the long-term read / write reliability of the device over a wide temperature range.

[0219] 2) Lightweight incremental window calibration with extremely low overhead and no interruption to upper-layer business read / write: The calibration strategy adopts a local neighborhood scanning window and a pre-stored reference data block in memory. A single calibration only traverses about 11 sampling delay levels, which is reduced to 1 / 6 to 1 / 10 of the global full calibration time compared to traversing 64 sampling delay levels. At the same time, the sampling point register is updated only during the idle interval of SPI transmission, without the need to reset the SPI controller, so that the upper-layer business read / write is transparent.

[0220] 3) Multi-dimensional calibration triggering mechanism with both active prediction and passive fallback protection: Temperature change threshold and periodic timed monitoring are used as active prediction triggering conditions, while CRC error count and ECC error correction count are introduced as passive fault fallback triggering conditions. The dual protection mechanism covers various temperature drift and timing deterioration conditions to ensure stable operation of the SPI interface.

[0221] 4) Pure software driver implementation, flexible configuration, and low deployment threshold: This solution is implemented entirely at the SPI driver layer without modifying the chip hardware circuit; all key parameters such as temperature trigger threshold, scan window half-width, and temperature polling cycle can be configured through the device tree, which can adapt to products with different specifications and stability requirements. Firmware developers do not need a professional signal integrity analysis background to deploy and use it.

[0222] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0223] Figure 5 This is a schematic diagram of the timing calibration device for the SPI interface provided in an embodiment of this application. Figure 5 As shown, the timing calibration device 50 of the SPI interface includes an acquisition module 510, a processing module 520, a timing calibration module 530, and an update module 540.

[0224] The acquisition module 510 is used to acquire the target device's current temperature, reference data block, current sampling delay level and last timing calibration temperature in response to the target device completing the SPI driver loading initialization. The current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device.

[0225] The processing module 520 is used to calculate the temperature difference between the current temperature and the previous timing calibration temperature, and to determine whether to trigger local timing incremental calibration based on the temperature difference.

[0226] The timing calibration module 530 is used to perform local timing incremental calibration on the current sampling delay level according to the reference data block if it is determined that local timing incremental calibration is triggered, so as to obtain the target sampling delay level.

[0227] The update module 540 is used to update the sampling timing configuration of the SPI receiver by adopting the target sampling delay level, and to update the previous timing calibration temperature to the current temperature.

[0228] In one possible implementation, the timing calibration module 530 is specifically used to: determine a first scanning window corresponding to the current sampling delay level, centered on the current sampling delay level and based on the half-width of a first preset scanning window, wherein the first scanning window includes multiple consecutive first sampling delay levels; for each first sampling delay level, configure the sampling point register of the SPI receiver to the first sampling point configuration value corresponding to the first sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPI Flash under the first sampling point configuration value; compare the current data read under each first sampling delay level with the reference reference data block one by one to obtain a first effective sampling delay level set corresponding to the first scanning window; and determine the target sampling delay level from the first effective sampling delay level set.

[0229] In one possible implementation, the timing calibration module 530 is further configured to: respond to the absence of a valid sampling delay level in the first scanning window, determine a second scanning window corresponding to the current sampling delay level based on the second preset scanning window half-width, with the current sampling delay level as the center and the second preset scanning window half-width being larger than the first preset scanning window half-width; for each second sampling delay level in the second scanning window, configure the sampling point register to the second sampling point configuration value corresponding to the second sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPIFlash under the second sampling point configuration value; compare the current data corresponding to each second sampling delay level with the reference reference data block one by one to obtain the second valid sampling delay level set corresponding to the second scanning window, and determine the target sampling delay level from the second valid sampling delay level set.

[0230] In one possible implementation, the timing calibration module 530 is further configured to: trigger global timing calibration in response to the absence of a valid sampling delay level in the second scan window; traverse all configurable sampling delay levels in the sampling point register, configure the sampling point register to the sampling point configuration value corresponding to each sampling delay level, and read the current data corresponding to the fixed address of the reference reference data block stored in the SPIFlash under the sampling point configuration value; compare the current data corresponding to each sampling delay level with the reference reference data block one by one to obtain a global set of valid sampling delay levels, and determine the target sampling delay level from the global set of valid sampling delay levels.

[0231] In one possible implementation, the update module 540 is specifically used to: update the current sampling delay level to the target sampling delay level using an atomic operation; or, update the current sampling delay level to the target sampling delay level using a double buffering mechanism.

[0232] In one possible implementation, the timing calibration module 530 is further configured to: obtain the previous calibration timestamp and the current timestamp of the target device; calculate the time difference between the current timestamp and the previous calibration timestamp; determine whether to trigger local timing incremental calibration based on the time difference; if it is determined that local timing incremental calibration is triggered, perform local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0233] In one possible implementation, after obtaining the target sampling delay level, the update module 540 is also used to update the previous calibration timestamp to the current timestamp.

[0234] In one possible implementation, the timing calibration module 530 is further configured to: acquire ECC error correction count and / or CRC error count during the operation of the SPI receiver; determine whether to trigger local timing incremental calibration based on the ECC error correction count or CRC error count; if it is determined that local timing incremental calibration is triggered, perform local timing incremental calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level.

[0235] In one possible implementation, after obtaining the target sampling delay level, the update module 540 is also used to: clear the ECC error correction count and / or CRC error count.

[0236] In one possible implementation, the timing calibration device further includes a parameter configuration module (not shown), which is used to: configure the timing calibration parameters corresponding to the SPI receiver using device tree attributes; or configure the timing calibration parameters corresponding to the SPI receiver using a memory-based virtual file interface.

[0237] The timing calibration device for the SPI interface provided in this application embodiment can be used to execute the method steps of the above method embodiment. The specific implementation and technical effects are similar, and will not be described again here.

[0238] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 6 As shown, the electronic device 60 includes at least one processor 601 and a memory 602.

[0239] Optionally, the electronic device 60 also includes a communication component 603. The processor 601, memory 602, and communication component 603 are connected via a bus 604.

[0240] In a specific implementation, at least one processor 601 executes computer execution instructions stored in memory 602, causing at least one processor 601 to perform the above-described method.

[0241] The specific implementation process of processor 601 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0242] For example, the electronic device can be an embedded device such as a server BMC. After the SPI driver is loaded and initialized, the processor calls the instructions in the memory to obtain the current temperature, the reference data block, the current sampling delay level, and the temperature of the last timing calibration. Based on the temperature difference, it determines whether to trigger local timing incremental calibration, thereby avoiding full calibration every time. Furthermore, when calibration is required, the processor makes a local adjustment to the current sampling delay level based on the reference data block to obtain the target sampling delay level and updates the sampling timing configuration of the SPI receiver. This enables the device to dynamically correct the high-speed reading sampling position as the temperature changes, thereby improving the stability and adaptability of reading external SPI Flash firmware, startup code, or configuration data. Therefore, it can reduce the risk of verification anomalies and access failures in wide temperature variation and long-term operation scenarios.

[0243] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.

[0244] The memory may include Random Access Memory (RAM) and Non-volatile Memory (NVM), such as at least one disk storage device. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0245] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0246] For example, after the computer program product is deployed on target devices such as server BMC, the processor can execute the corresponding calibration process after the SPI driver is loaded and initialized. Based on the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration, it determines whether to trigger local timing incremental calibration, thereby avoiding frequent full adjustments when the temperature change is not significant. Furthermore, when the temperature difference condition is met, the program controls the processor to perform local calibration on the current sampling delay level based on the reference data block and update the target sampling delay level, so that the sampling timing of the SPI receiver can be specifically corrected according to the change of the operating environment, thereby improving the data sampling margin and stability when the external SPI Flash is read at high speed. Therefore, it can balance calibration efficiency, resource overhead, and firmware reading reliability under wide temperature conditions.

[0247] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0248] For example, by storing the timing calibration method of the SPI interface as computer-executable instructions in a computer-readable storage medium, the processor can call and execute it after the SPI driver is loaded and initialized. This allows calibration judgment and parameter updates to be completed based on the current temperature, reference data block, current sampling delay level, and the temperature of the last timing calibration. This eliminates the need for fixed temperature zones or one-time static settings, enabling local incremental timing calibration to be triggered when the temperature changes. This ensures that the sampling timing of the SPI receiver continuously matches the actual working state, thereby reducing the time and resource overhead of full recalibration. Therefore, it improves the stability of high-speed reading from the external SPI Flash, environmental adaptability, and system startup and operational reliability.

[0249] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0250] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0251] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through interfaces, devices, or units, and may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate; components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0252] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0253] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0254] Finally, it should be noted that other embodiments of this application will readily conceive of by those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and alterations may be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A timing calibration method for an SPI interface, characterized in that, include: In response to the target device with the SPI interface completing the SPI driver loading initialization, the current temperature, reference data block, current sampling delay level, and last timing calibration temperature of the target device are obtained. The current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device. Calculate the temperature difference between the current temperature and the previous timing calibration temperature, and determine whether to trigger local timing incremental calibration based on the temperature difference; If it is determined that the local timing incremental calibration is triggered, then the local timing incremental calibration is performed on the current sampling delay level according to the reference data block to obtain the target sampling delay level; Using the target sampling delay level, update the sampling timing configuration of the SPI receiver, and update the previous timing calibration temperature to the current temperature.

2. The timing calibration method according to claim 1, characterized in that, The step of performing local timing increment calibration on the current sampling delay level based on the reference data block to obtain the target sampling delay level includes: Centered on the current sampling delay level, and based on the half-width of the first preset scanning window, a first scanning window corresponding to the current sampling delay level is determined, and the first scanning window includes multiple consecutive first sampling delay levels. For each first sampling delay level, the sampling point register of the SPI receiver is configured to the first sampling point configuration value corresponding to the first sampling delay level, and the current data corresponding to the fixed address of the reference reference data block stored in the SPI flash memory is read under the first sampling point configuration value; The current data read at each first sampling delay level is compared with the reference data block one by one to obtain the first effective sampling delay level set corresponding to the first scanning window; The target sampling delay level is determined from the first set of effective sampling delay levels.

3. The timing calibration method according to claim 2, characterized in that, Also includes: In response to the absence of a valid sampling delay level in the first scanning window, a second scanning window corresponding to the current sampling delay level is determined based on the second preset scanning window half-width, with the current sampling delay level as the center. The second preset scanning window half-width is greater than the first preset scanning window half-width. For each second sampling delay level in the second scanning window, the sampling point register is configured to the second sampling point configuration value corresponding to the second sampling delay level, and the current data corresponding to the fixed address of the reference reference data block stored in the SPI flash memory is read under the second sampling point configuration value; The current data corresponding to each second sampling delay level is compared one by one with the reference data block to obtain the second effective sampling delay level set corresponding to the second scanning window, and the target sampling delay level is determined from the second effective sampling delay level set.

4. The timing calibration method according to claim 3, characterized in that, Also includes: In response to the absence of a valid sampling delay level in the second scanning window, a global timing calibration is triggered; Iterate through all the configurable sampling delay levels of the sampling point register, configure the sampling point register to the sampling point configuration value corresponding to each sampling delay level, and read the current data corresponding to the fixed address of the reference data block stored in the SPI flash memory under the sampling point configuration value; The current data corresponding to each sampling delay level is compared one by one with the reference data block to obtain a global effective sampling delay level set, and the target sampling delay level is determined from the global effective sampling delay level set.

5. The timing calibration method according to any one of claims 1 to 4, characterized in that, The step of updating the sampling timing configuration of the SPI receiver using the target sampling delay level includes: Atomic operations are used to update the current sampling delay level to the target sampling delay level; Alternatively, a double buffering mechanism can be used to update the current sampling delay level to the target sampling delay level.

6. The timing calibration method according to any one of claims 1 to 4, characterized in that, Also includes: Obtain the last calibration timestamp and the current timestamp of the target device; Calculate the time difference between the current timestamp and the last calibration timestamp; Based on the time difference, determine whether to trigger the local timing increment calibration; If the local timing incremental calibration is determined to be triggered, the local timing incremental calibration is performed on the current sampling delay level according to the reference data block to obtain the target sampling delay level.

7. The timing calibration method according to claim 6, characterized in that, After obtaining the target sampling delay level, the method further includes: Update the previous calibration timestamp to the current timestamp.

8. The timing calibration method according to any one of claims 1 to 4, characterized in that, Also includes: During the operation of the SPI receiver, ECC error correction count and / or CRC error count are acquired; Based on the ECC error correction count or the CRC error count, determine whether to trigger the local timing incremental calibration; If the local timing incremental calibration is determined to be triggered, the local timing incremental calibration is performed on the current sampling delay level according to the reference data block to obtain the target sampling delay level.

9. The timing calibration method according to claim 8, characterized in that, After obtaining the target sampling delay level, the method further includes: Clear the ECC error correction count and / or the CRC error count.

10. The timing calibration method according to any one of claims 1 to 4, characterized in that, Also includes: The timing calibration parameters corresponding to the SPI receiver are configured using device tree attributes. Alternatively, a memory-based virtual file interface can be used to configure the timing calibration parameters corresponding to the SPI receiver.

11. A timing calibration device for an SPI interface, characterized in that, include: The acquisition module is used to acquire the current temperature, reference data block, current sampling delay level and last timing calibration temperature of the target device in response to the completion of SPI driver loading and initialization of the target device with SPI interface. The current sampling delay level is used to adjust the sampling timing of the SPI receiver in the target device. The processing module is used to calculate the temperature difference between the current temperature and the previous timing calibration temperature, and determine whether to trigger local timing incremental calibration based on the temperature difference; The timing calibration module is used to perform the local timing incremental calibration on the current sampling delay level according to the reference data block if it is determined that the local timing incremental calibration is triggered, so as to obtain the target sampling delay level. The update module is used to update the sampling timing configuration of the SPI receiver using the target sampling delay level, and update the previous timing calibration temperature to the current temperature.

12. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the timing calibration method for the SPI interface as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the timing calibration method for the SPI interface as described in any one of claims 1 to 10.

14. A computer program product, characterized in that, include: A computer program, which, when executed by a processor, implements the timing calibration method for the SPI interface as described in any one of claims 1 to 10.

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