A wireless communication chip supporting multiplexed PDMA with multiple host interfaces

Abstract

This application provides a wireless communication chip supporting multiple host interface reusable PDMA. The interface selection module is configured to select the currently operating host interface from multiple host interfaces, convert data from the selected host interface into standard data, and output it to the reusable packet direct memory access (PDMA) module. Alternatively, it can output standard data from the reusable PDMA module to the selected host interface. The reusable PDMA module is configured to receive standard data from the interface selection module, de-aggregate the received standard data to obtain data packets, and write them to memory. Alternatively, it can aggregate data packets read from memory to obtain standard data and output it to the interface selection module. This method reduces chip area and power consumption.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a wireless communication chip that supports multiplexed PDMA with multiple host interfaces. Background Technology

[0002] Wireless communication chips (such as 802.11 WiFi chips) typically need to support multiple host communication interfaces (i.e., host interfaces), such as SDIO, USB, and PCIe, to adapt to different application scenarios. A host communication interface is the physical interface through which the chip connects to an external host, responsible for transmitting data between the chip and the host.

[0003] Internally, data transfer is typically handled by DMA (Direct Memory Access) modules. The role of DMA modules is to move data between the host interface and the chip's internal memory. Each DMA module also includes a small internal data storage buffer, used to temporarily store the transferred data.

[0004] In existing technologies, separate DMA modules are typically used for different host interfaces. For example, a chip that simultaneously supports SDIO, USB, and PCIe integrates three independent DMA modules and their corresponding data storage memory. While this design allows for modular data transfer across different interfaces, it suffers from the following significant drawbacks: First, it results in significant hardware footprint overhead. Because each interface requires a separate DMA module, and each DMA module needs its own data storage memory, multiple sets of redundant hardware resources exist within the chip. This redundancy is particularly pronounced in highly integrated ASIC chips, severely increasing chip area and power consumption.

[0005] Second, the general-purpose DMA does not have the ability to process WiFi MAC layer data packets and cannot complete the aggregation and deaggregation of MAC layer data packets. This part of the work still needs to be completed by other modules or software. On the other hand, different host interfaces use independent DMA modules, which means that multiple DMAs with similar functions and their supporting circuits need to be integrated inside the chip, increasing the complexity of system design and making it difficult to efficiently integrate multiple host interfaces and their corresponding independent DMAs into the same chip. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a wireless communication chip that supports multiple host interfaces and reusable PDMA, so as to reduce chip area and power consumption, solve the problem that general DMA cannot complete MAC layer data packet aggregation and deaggregation operations, reduce the complexity of system design, and facilitate the efficient integration of multiple host interfaces and their corresponding DMA functions into the same chip.

[0007] In a first aspect, embodiments of this application provide a wireless communication chip that supports multiple host interface reusable PDMA, including: multiple host interfaces, an interface selection module, a reusable packet direct memory access PDMA module, and a memory; Multiple host interfaces are used to connect to external hosts; the interface selection module is connected to each of the host interfaces and the reusable packet direct memory access (PDMA) module respectively; the reusable packet direct memory access (PDMA) module is connected to the memory; wherein, the multiple host interfaces share the reusable packet direct memory access (PDMA) module and the memory. The interface selection module is configured to select the currently working host interface from multiple host interfaces, convert the data from the selected host interface into standard data and output it to the reusable packet direct memory access (PDMA) module, and / or output the standard data from the reusable packet direct memory access (PDMA) module to the selected host interface. The reusable Packet Direct Memory Access (PDMA) module is configured to receive standard data from the interface selection module, perform de-aggregation processing on the received standard data to obtain data packets, write the obtained data packets into the memory, and / or read data packets from the memory, perform aggregation processing on the read data packets to obtain standard data, and output the obtained standard data to the interface selection module.

[0008] In conjunction with the first aspect, this application provides a first possible implementation of the first aspect, which further includes a MAC controller; the MAC controller is connected to the reusable packet direct memory access (PDMA) module and the memory respectively; In the MAC transmission direction, the MAC controller is configured to allocate free space in the memory and issue a first descriptor to the reusable packet direct memory access (PDMA) module; the first descriptor contains the address information and size of the free space; The reusable packet direct memory access (PDMA) module is configured to write the de-aggregated data packets into the corresponding free space according to the first descriptor.

[0009] In conjunction with the first possible implementation of the first aspect, this application provides a second possible implementation of the first aspect, wherein, in the MAC receiving direction, the MAC controller is configured to, after storing the data packet to be sent into the memory, issue a second descriptor to the reusable packet direct memory access (PDMA) module; the second descriptor contains the storage address and data packet length of the data packet to be sent; The reusable packet direct memory access (PDMA) module is configured to read the corresponding data packets based on the second descriptor and perform aggregation processing.

[0010] In conjunction with the second possible implementation of the first aspect, this application provides a third possible implementation of the first aspect, wherein the reusable packet direct memory access (PDMA) module internally includes a descriptor queue, which is used to cache the first descriptor and / or the second descriptor; In the MAC transmission direction, the reusable packet direct memory access PDMA module is configured to sequentially retrieve the first descriptor from the descriptor queue; In the MAC receiving direction, the reusable packet direct memory access (PDMA) module is configured to sequentially retrieve the second descriptor from the descriptor queue.

[0011] In conjunction with the first aspect, this application provides a fourth possible implementation of the first aspect, wherein the reusable Packet Direct Memory Access (PDMA) module, when aggregating read data packets to obtain standard data and outputting the obtained standard data to the interface selection module, is specifically configured as follows: Based on the receiving capacity of the currently operating host interface, configure aggregation parameters, and aggregate multiple data packets into one data packet according to the aggregation parameters. Then, output the aggregated data packet as standard data to the interface selection module. The aggregation parameters include the number of aggregated packets and / or the maximum aggregation length. The number of aggregated packets is used to limit the number of data packets in a single aggregation, and the maximum aggregation length is used to limit the total length of the data packet after a single aggregation.

[0012] In conjunction with the first aspect, this application provides a fifth possible implementation of the first aspect, wherein the reusable Packet Direct Memory Access (PDMA) module, when performing de-aggregation processing on the received tag data to obtain data packets, is specifically configured as follows: Based on the header information carried in the received standard data, the standard data is split into multiple data packets.

[0013] In conjunction with the first aspect, this application provides a sixth possible implementation of the first aspect, wherein the reusable Packet Direct Memory Access (PDMA) module includes a flow control interface; The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module receives standard data from the interface selection module, arbitrate among multiple pending functional data corresponding to the currently working host interface based on the control state of the reusable packet direct memory access (PDMA) module and the transmission state of the currently working host interface, and select the currently received functional data from the multiple pending functional data. The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: receive standard data output by the interface selection module that corresponds to the selected functional data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module reads data packets from the memory, arbitrate among multiple functional data to be transmitted corresponding to the currently working host interface based on the control state of the reusable packet direct memory access (PDMA) module and the reception state of the currently working host interface, and select the functional data to be sent. The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: read data packets corresponding to selected functional data from the memory, and perform aggregation processing on the read data packets.

[0014] In conjunction with the first aspect, this application provides a seventh possible implementation of the first aspect, wherein the reusable Packet Direct Memory Access (PDMA) module includes a flow control interface; The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module receives standard data from the interface selection module, arbitrate according to the priority of each functional data to be received, and select the functional data to be received with the highest priority as the currently received functional data; The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: receive standard data output by the interface selection module that corresponds to the selected functional data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module reads data packets from the memory, arbitrate according to the priority of each functional data to be sent, and select the functional data to be sent with the highest priority as the functional data to be sent currently; The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: read data packets corresponding to selected functional data from the memory, and perform aggregation processing on the read data packets.

[0015] In conjunction with the first possible implementation of the first aspect, this application provides an eighth possible implementation of the first aspect, wherein the reusable Packet Direct Memory Access (PDMA) module includes a flow control interface; The flow control interface is also configured to: after selecting the currently received functional data, send a receive ready signal to the interface selection module so that the reusable packet direct memory access PDMA module can start receiving standard data. During the process of the reusable packet direct memory access (PDMA) module receiving standard data, when the storage space in the MAC transmission direction of the memory is insufficient, or when the number of first descriptors in the descriptor queue used to cache the first descriptors in the reusable packet direct memory access (PDMA) module is insufficient, the receive ready signal is pulled low, and other functional data is selected as the currently received functional data. The receive ready signal is sent to the interface selection module so that the reusable packet direct memory access (PDMA) module can start receiving the standard data corresponding to the other functional data.

[0016] In conjunction with the eighth possible implementation of the first aspect, this application provides a ninth possible implementation of the first aspect, wherein the flow control interface is further configured as follows: During the process of the reusable packet direct memory access (PDMA) module receiving the standard data, when the end data identifier signal is received from the interface selection module, it is determined that the reusable packet direct memory access (PDMA) module has completed receiving the standard data corresponding to the currently received functional data, and the receiving of the standard data corresponding to the currently received functional data is stopped.

[0017] This application provides a wireless communication chip supporting reusable PDMA for multiple host interfaces. By configuring multiple host interfaces to share the same reusable Packet Direct Memory Access (PDMA) module and the same memory, the independent DMA modules and their associated data storage memory that were originally required for different host interfaces such as SDIO, USB, and PCIe are replaced by a single reusable PDMA module and a single reusable memory. This eliminates the need for multiple redundant DMA hardware resources within the wireless communication chip, effectively reducing chip area and power consumption. Simultaneously, the reusable PDMA module is configured to both receive standard data from the interface selection module, de-aggregate the received standard data to obtain data packets, and write the obtained data packets to the memory, and also read data packets from the memory, aggregate the read data packets to obtain standard data, and output the obtained standard data to the interface selection module. Thus, the packet de-aggregation and aggregation capabilities are integrated into a single reusable PDMA module, solving the problem that general-purpose DMA cannot perform MAC layer packet aggregation and de-aggregation operations, and eliminating the need for other modules or software to perform these operations. Furthermore, since multiple host interfaces share the same reusable Packet Direct Memory Access (PDMA) module, there is no need to integrate multiple DMA modules with similar functions and their supporting circuits inside the chip, thereby reducing the complexity of system design and facilitating the efficient integration of multiple host interfaces and their corresponding DMA functions into the same chip.

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This illustration shows a schematic diagram of the structure of a wireless communication chip supporting multiplexed PDMA with multiple host interfaces, provided in an embodiment of this application. Figure 2 This illustration shows a schematic diagram of another wireless communication chip supporting multiplexed PDMA with multiple host interfaces, provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] In existing technologies, separate DMA modules are typically used for different host interfaces. For example, a chip that simultaneously supports SDIO, USB, and PCIe integrates three independent DMA modules and their corresponding data storage memory. While this design allows for modular data transfer across different interfaces, it suffers from the following significant drawbacks: First, it results in significant hardware footprint overhead. Because each interface requires a separate DMA module, and each DMA module needs its own data storage memory, multiple sets of redundant hardware resources exist within the chip. This redundancy is particularly pronounced in highly integrated ASIC chips, severely increasing chip area and power consumption.

[0023] Second, the general-purpose DMA does not have the ability to process WiFi MAC layer data packets and cannot complete the aggregation and deaggregation of MAC layer data packets. This part of the work still needs to be completed by other modules or software. On the other hand, different host interfaces use independent DMA modules, which means that multiple DMAs with similar functions and their supporting circuits need to be integrated inside the chip, increasing the complexity of system design and making it difficult to efficiently integrate multiple host interfaces and their corresponding independent DMAs into the same chip.

[0024] Based on this, this application provides a wireless communication chip that supports multiple host interface reusable PDMA, which will be described in detail below through embodiments.

[0025] like Figure 1 As shown, the wireless communication chip supporting multiple host interface reusable PDMA includes: multiple host interfaces, an interface selection module, a reusable packet direct memory access PDMA module, and a memory. Multiple host interfaces are used to connect to external hosts; the interface selection module is connected to each host interface and the reusable packet direct memory access (PDMA) module respectively; the reusable packet direct memory access (PDMA) module is connected to the memory; wherein, multiple host interfaces share the reusable packet direct memory access (PDMA) module and the memory. The interface selection module is configured to select the currently working host interface from multiple host interfaces, convert the data from the selected host interface into standard data and output it to the reusable packet direct memory access (PDMA) module, and / or output the standard data from the reusable packet direct memory access (PDMA) module to the selected host interface. The reusable Packet Direct Memory Access (PDMA) module is configured to receive standard data from the interface selection module, de-aggregate the received standard data to obtain data packets, write the obtained data packets to memory, and / or read data packets from memory, aggregate the read data packets to obtain standard data, and output the obtained standard data to the interface selection module.

[0026] In this embodiment, the host interface includes, for example, an SDIO interface, a USB interface, and a PCIe interface. Multiple host interfaces are used to connect to an external host and are responsible for transmitting data between the wireless communication chip and the external host.

[0027] The interface selection module can select the currently operating host interface from multiple host interfaces and adjust the operating mode of the reusable packet direct memory access (PDMA) module according to the selected host interface. In the direction of data transmission from the external host to the internal wireless communication chip, the interface selection module converts the data from the selected host interface into standard data (AXI Stream data) and outputs it to the reusable PDMA module. In the direction of data transmission from the internal wireless communication chip to the external host, the interface selection module outputs standard data from the reusable PDMA module to the selected host interface. Through the data format conversion of the interface selection module, different protocol data from different host interfaces are uniformly converted into a standard data format, enabling subsequent reusable PDMA modules to process data from different host interfaces in a unified manner, thus allowing multiple host interfaces to share the same PDMA hardware.

[0028] Memory is a reusable storage area inside the chip used to store data packets. The reusable Packet Direct Memory Access (PDMA) module integrates packet de-aggregation and aggregation capabilities and can be shared by multiple host interfaces.

[0029] Specifically, the reusable Packet Direct Memory Access (PDMA) module is configured to: receive standard data from the interface selection module in the direction of data transmission from an external host to the internal wireless communication chip; de-aggregate the received standard data to obtain data packets; and write the obtained data packets to memory. De-aggregation refers to splitting the aggregated standard data into multiple independent data packets based on the packet header information carried in the standard data. In the direction of data transmission from the internal chip to the external host, the reusable PDMA module reads data packets from memory; aggregates the read data packets to obtain standard data; and outputs the obtained standard data to the interface selection module. Aggregation refers to concatenating multiple independent data packets into a single standard data packet for transmission to the external host in one go, thereby reducing the number of data transmissions and improving interface bandwidth utilization.

[0030] It should be noted that the order in the descriptions of the two directions above—"receiving standard data, de-aggregating, and writing to memory" followed by "reading data packets, aggregating, and outputting standard data"—is merely for clarity and does not imply that the two directions must coexist or have a fixed execution order in actual operation. In actual chip operation, these two directions can be executed independently according to data transmission requirements; that is, only one direction of data transmission can be performed, or the two directions can be executed alternately.

[0031] In the above technical solution, multiple host interfaces share the same reusable Packet Direct Memory Access (PDMA) module and the same memory. Compared to the prior art where each host interface is equipped with a separate DMA module and its associated data storage memory, this embodiment only requires one reusable PDMA module and one reusable memory to serve all host interfaces, thereby eliminating multiple redundant DMA hardware resources within the chip and effectively reducing chip area and power consumption. Simultaneously, since the reusable PDMA module itself integrates packet aggregation and deaggregation capabilities, it eliminates the need for other modules or software to perform MAC layer packet aggregation and deaggregation operations, solving the problem that general-purpose DMA cannot complete MAC layer packet aggregation and deaggregation. Furthermore, since multiple host interfaces share the same reusable PDMA module, the chip does not need to integrate multiple functionally similar DMA modules and their associated circuits, thereby reducing system design complexity and facilitating the efficient integration of multiple host interfaces and their corresponding DMA functions into a single chip.

[0032] In one possible implementation, such as Figure 2As shown, the wireless communication chip also includes a MAC controller; the MAC controller is connected to the reusable packet direct memory access (PDMA) module and the memory, respectively. In the MAC transmission direction, the MAC controller is configured to allocate free space in memory and issue a first descriptor to the reusable packet direct memory access (PDMA) module; the first descriptor contains the address information and size of the free space; The reusable packet direct memory access (PDMA) module is configured to write the de-aggregated data packets into the corresponding free space based on the first descriptor.

[0033] In this embodiment, the MAC (Media Access Control) controller is a hardware module inside the wireless communication chip responsible for media access control layer processing. It is connected to the reusable packet direct memory access (PDMA) module and the memory, and can instruct the reusable packet direct memory access (PDMA) module to complete the data packet transfer by issuing descriptors.

[0034] In the MAC transmission direction—that is, the direction in which data is transmitted from the external host through the host interface to the internal wireless communication chip and finally written to memory—the MAC controller is configured to allocate free space in memory. Free space refers to an unoccupied storage area in memory that can be used to store new data packets. After allocating free space, the MAC controller issues a first descriptor to the reusable Packet Direct Memory Access (PDMA) module. The first descriptor is a task indication information containing the address information and size of the free space. The address information indicates the specific location of the free space in memory, and the size indicates its capacity. After receiving standard data from the interface selection module, the reusable PDMA module de-aggregates the standard data, splitting the aggregated standard data into multiple independent data packets. Subsequently, the reusable PDMA module writes the de-aggregated data packets one by one into the corresponding free space according to the address information and space size recorded in the first descriptor.

[0035] In this way, the MAC controller pre-defines the storage space in memory for the upcoming data packets by issuing the first descriptor. After completing the de-aggregation process, the reusable Packet Direct Memory Access (PDMA) module directly stores the data packets into the corresponding locations according to the instructions of the first descriptor, thereby achieving efficient and orderly storage of data packets in the MAC transmission direction and avoiding address conflicts or insufficient space problems when writing data packets to memory.

[0036] In one possible implementation, in the MAC receiving direction, the MAC controller is configured to, after storing the data packet to be sent into memory, issue a second descriptor to the reusable packet direct memory access (PDMA) module; the second descriptor contains the storage address and data packet length of the data packet to be sent. The reusable packet direct memory access (PDMA) module is configured to read the corresponding data packets based on the second descriptor and perform aggregation processing.

[0037] In this embodiment, the MAC receiving direction refers to the direction in which data enters the wireless communication chip from the WiFi air interface, is processed, and then sent to an external host through the host interface. Specifically, in the MAC receiving direction, after the WiFi air interface receives wireless data packets, it hands them over to the MAC controller. The MAC controller stores these data packets as data packets to be sent in the memory, generates a second descriptor, and sends it to the reusable Packet Direct Memory Access (PDMA) module. The second descriptor is a task indication information, containing the storage address of the data packet to be sent in the memory and the data packet length. The storage address indicates the specific location of the data packet to be sent in the memory, and the data packet length indicates the size of the data packet. After receiving the second descriptor, the reusable PDMA module reads the corresponding data packet from the memory according to the storage address and data packet length recorded in the second descriptor, and performs aggregation processing on the read data packet. Aggregation processing refers to concatenating multiple independent data packets into a standard data packet for transmission to the external host through the interface selection module, thereby reducing the number of data transmissions and improving interface bandwidth utilization.

[0038] In one possible implementation, the reusable packet direct memory access (PDMA) module internally includes a descriptor queue for caching a first descriptor and / or a second descriptor. In the MAC transmission direction, the reusable packet direct memory access PDMA module is configured to sequentially retrieve the first descriptor from the descriptor queue; In the MAC receive direction, the reusable packet direct memory access PDMA module is configured to sequentially retrieve the second descriptor from the descriptor queue.

[0039] In this embodiment, the reusable Packet Direct Memory Access (PDMA) module includes a descriptor queue. The descriptor queue is a first-in, first-out (FIFO) cache structure located within the reusable PDMA module, used to cache the first and / or second descriptors issued by the MAC controller. Specifically, the descriptor queue can cache both the first and second descriptors simultaneously; that is, descriptors for MAC transmission and MAC reception can be mixed and stored in the same descriptor queue, arranged sequentially according to the order in which they are issued by the MAC controller.

[0040] In the MAC transmission direction, the reusable packet direct memory access (PDMA) module is configured to sequentially retrieve the first descriptor from the descriptor queue. For each first descriptor retrieved, a data packet obtained by de-aggregation is written into the corresponding free space of the memory according to the address information and space size in the first descriptor.

[0041] In the MAC receiving direction, the reusable packet direct memory access (PDMA) module is configured to sequentially retrieve second descriptors from the descriptor queue. For each second descriptor retrieved, the corresponding data packet is read from the memory based on the storage address and data packet length in the second descriptor, and the read data packets are aggregated.

[0042] By setting up a descriptor queue, the first and second descriptors issued by the MAC controller can be cached and scheduled in an orderly manner. The reusable packet direct memory access (PDMA) module processes the tasks corresponding to each descriptor in a first-in-first-out order, thereby achieving orderly management of data transmission tasks in both the MAC sending and receiving directions and avoiding the problems of descriptor loss or disordered processing order.

[0043] In one possible implementation, the reusable Packet Direct Memory Access (PDMA) module, when aggregating read data packets to obtain standard data and outputting the obtained standard data to the interface selection module, is specifically configured as follows: Based on the receiving capacity of the currently operating host interface, configure the aggregation parameters, and aggregate multiple data packets into one data packet according to the aggregation parameters. Then, output the aggregated data packet as standard data to the interface selection module. The aggregation parameters include the number of aggregated packets and / or the maximum aggregation length. The number of aggregated packets is used to limit the number of data packets in a single aggregation, and the maximum aggregation length is used to limit the total length of the data packet after a single aggregation.

[0044] In this embodiment, the receiving capability of the currently working host interface refers to the processing capability and buffer space size of the host interface selected by the interface selection module when receiving data. The receiving capabilities of different host interfaces may be different.

[0045] Aggregation parameters include the number of aggregation packets and / or the maximum aggregation length. The number of aggregation packets limits the maximum number of data packets that can be aggregated in a single aggregation operation, while the maximum aggregation length limits the maximum total length of the data packets obtained after a single aggregation operation. Configuring the number of aggregation packets controls the number of data packets transmitted to the host interface in a single operation, preventing the host interface from being overwhelmed by sending too many data packets at once. Configuring the maximum aggregation length controls the total amount of data transmitted to the host interface in a single operation, preventing data loss or transmission failure due to overload.

[0046] After configuration, the reusable Packet Direct Memory Access (PDMA) module aggregates multiple data packets into a single data packet (standard data) based on the aggregation parameters, and outputs the aggregated data packet as standard data to the interface selection module, which then outputs it to the currently working host interface.

[0047] In one possible implementation, the reusable Packet Direct Memory Access (PDMA) module, when de-aggregating received tag data to obtain data packets, is specifically configured as follows: Based on the header information carried in the received standard data, the standard data is split into multiple data packets.

[0048] In this embodiment, the standard data is obtained by the interface selection module after converting the format of data from the host interface, and it encapsulates the aggregated data packet sent by the external host. The packet header information is the control information in the standard data used to describe the data packet structure and boundary identification, and contains key information such as the length and boundary position of each sub-data packet in the aggregated data packet.

[0049] During the reception of standard data, the reusable Packet Direct Memory Access (PDMA) module parses the header information carried in the standard data, identifies the boundary positions of each sub-data packet in the aggregated data packet based on the header information, and then splits the standard data into multiple independent data packets. Each of the split data packets is the original WiFi data packet, which the reusable PDMA module subsequently writes into the corresponding free space in memory. By performing de-aggregation processing using the header information, the reusable PDMA module can accurately restore the aggregated data packets sent by the external host into the original data packets, providing a correct data foundation for subsequent processing and transmission.

[0050] In one possible implementation, the reusable Packet Direct Memory Access (PDMA) module includes a flow control interface. The flow control interface is configured to: before the reusable packet direct memory access PDMA module receives standard data from the interface selection module, arbitrate among multiple pending function data corresponding to the currently working host interface based on the control state of the reusable packet direct memory access PDMA module and the transmission state of the currently working host interface, and select the function data to be received from the multiple pending function data. The reusable packet direct memory access (PDMA) module is specifically configured to: receive standard data output from the interface selection module corresponding to the selected function data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module reads data packets from the memory, arbitrate among multiple functional data to be transmitted corresponding to the currently working host interface based on the control state of the reusable packet direct memory access (PDMA) module and the reception state of the currently working host interface, and select the functional data to be sent. The reusable packet direct memory access (PDMA) module is specifically configured to read data packets corresponding to selected function data from memory and perform aggregation processing on the read data packets.

[0051] In this embodiment, the flow control interface is a hardware interface within the reusable packet direct memory access (PDMA) module that is responsible for data flow control and arbitration, and is used to perform data flow control and arbitration between the reusable packet direct memory access (PDMA) module and the interface selection module.

[0052] The control state of the reusable packet direct memory access (PDMA) module refers to the module's own operating state, including whether it is busy and whether its internal buffer space is sufficient. The transmission state of the currently operating host interface refers to the state of the host interface selected by the interface selection module when transmitting data, including whether the host interface has data waiting to be transmitted and whether the transmission buffer is ready.

[0053] The data to be received refers to the data types corresponding to different functional endpoints in the currently operating host interface, awaiting reception and processing by the reusable Packet Direct Memory Access (PDMA) module. A host interface can be divided into multiple functional endpoints, each corresponding to a type of data. The transmission priority or processing requirements of different data types may differ. The flow control interface arbitrates among the various data types to be received based on the aforementioned status information, selecting the data to be received. After arbitration, the reusable PDMA module's receive interface selects the standard data output by the module corresponding to the selected data type and performs de-aggregation processing on the received standard data.

[0054] In this embodiment, the receiving state of the currently operating host interface refers to the state of the selected host interface when receiving data, including whether the host interface's receive buffer is ready and whether there is enough space to receive data. The flow control interface arbitrates based on the control state of the reusable packet direct memory access (PDMA) module and the receiving state of the host interface, selecting the currently transmitted functional data from a variety of functional data to be transmitted. After arbitration, the reusable packet direct memory access (PDMA) module reads the data packet corresponding to the selected functional data from the memory and performs aggregation processing on the read data packet.

[0055] The two implementation methods described above can exist independently or in combination, meaning that the reusable Packet Direct Memory Access (PDMA) module arbitrates both before receiving standard data and before reading data packets from memory.

[0056] In another possible implementation, the flow control interface can also arbitrate based on the priority of each function data to be received. Specifically, the reusable packet direct memory access (PDMA) module includes a flow control interface; The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module receives standard data from the interface selection module, arbitrate according to the priority of each functional data to be received, and select the functional data to be received with the highest priority as the currently received functional data. The reusable packet direct memory access (PDMA) module is specifically configured to: receive standard data output from the interface selection module corresponding to the selected function data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: arbitrate based on the priority of each functional data to be sent before the reusable packet direct memory access (PDMA) module reads data packets from memory, and select the functional data to be sent with the highest priority as the functional data to be sent currently. The reusable packet direct memory access (PDMA) module is specifically configured to read data packets corresponding to selected function data from memory and perform aggregation processing on the read data packets.

[0057] In this embodiment, before the reusable Packet Direct Memory Access (PDMA) module receives standard data from the interface selection module, the flow control interface obtains the priority of each functional data to be received corresponding to the currently operating host interface, compares the priorities of each functional data to be received, and selects the functional data with the highest priority as the currently received functional data. The reusable Packet Direct Memory Access (PDMA) module receives the standard data output by the interface selection module corresponding to the selected functional data, and performs de-aggregation processing on the received standard data. Through priority arbitration, high-priority functional data to be received can be selected and processed first, ensuring that important data is transmitted in a timely manner.

[0058] Accordingly, in the direction of data reading from memory and transmission, the flow control interface is configured to: arbitrate based on the priority of each pending functional data before the reusable Packet Direct Memory Access (PDMA) module reads data packets from memory, selecting the highest-priority pending functional data as the currently transmitted functional data. The reusable Packet Direct Memory Access (PDMA) module reads the data packets corresponding to the selected functional data from memory and performs aggregation processing on the read data packets. Through priority arbitration, high-priority pending functional data can be selected and transmitted first, ensuring that important data is transmitted to the external host first.

[0059] The two arbitration methods based on priority mentioned above can also exist alone or in combination.

[0060] In one possible implementation, the reusable Packet Direct Memory Access (PDMA) module includes a flow control interface. The flow control interface is also configured to send a receive ready signal to the interface selection module after selecting the currently received functional data, so that the reusable packet direct memory access PDMA module can start receiving standard data. During the process of receiving standard data by the reusable packet direct memory access (PDMA) module, when the storage space in the MAC transmission direction of the memory is insufficient, or when the number of first descriptors in the descriptor queue used to buffer the first descriptors in the reusable packet direct memory access (PDMA) module is insufficient, the receive ready signal is pulled low, and other functional data is selected as the currently received functional data. The receive ready signal is sent to the interface selection module so that the reusable packet direct memory access (PDMA) module can start receiving the standard data corresponding to other functional data.

[0061] In this embodiment, the receive ready signal is a handshake signal sent by the flow control interface to the interface selection module, indicating that the reusable packet direct memory access (PDMA) module is ready to receive standard data. Upon receiving the receive ready signal, the interface selection module begins sending standard data to the reusable packet direct memory access (PDMA) module, thereby enabling the reusable packet direct memory access (PDMA) module to begin receiving standard data.

[0062] During the process of receiving standard data by the reusable packet direct memory access (PDMA) module, the flow control interface continuously monitors the storage space status in the MAC transmission direction in the memory, as well as the cache count of the first descriptor in the internal descriptor queue of the reusable packet direct memory access (PDMA) module.

[0063] The storage space in the MAC transmission direction of the memory refers to the storage area allocated for the MAC transmission direction, used to store the de-aggregated data packets. The first descriptor is a task indication message issued by the MAC controller to the reusable Packet Direct Memory Access (PDMA) module, indicating the address and size of free space in the memory available for writing data packets. When the storage space in the MAC transmission direction of the memory is insufficient—that is, the storage area is full or the remaining space is insufficient to accommodate newly de-aggregated data packets—or when the number of first descriptors buffered in the descriptor queue is insufficient to indicate the location of free space, the flow control interface pulls the receive ready signal low. Pulling the receive ready signal low means that the flow control interface suspends the handshake with the interface selection module, informing the interface selection module that it can no longer continue sending standard data. Simultaneously, the flow control interface selects other functional data as the currently received functional data and then resends the receive ready signal to the interface selection module, so that the reusable Packet Direct Memory Access (PDMA) module can begin receiving the standard data corresponding to the newly selected functional data.

[0064] Through this reverse pressure switching mechanism, when the storage space or first descriptor in the MAC transmission direction is insufficient, the flow control interface promptly suspends the reception of the current function data and switches to receiving other function data, avoiding data loss or transmission blockage due to insufficient resources, and ensuring the reliability of data transmission and efficient utilization of interface bandwidth.

[0065] In one possible implementation, the flow control interface is further configured as follows: During the process of receiving standard data by the reusable packet direct memory access (PDMA) module, when the end data identifier signal is received from the interface selection module, it is determined that the reusable packet direct memory access (PDMA) module has completed receiving the standard data corresponding to the currently received functional data, and the receiving of the standard data corresponding to the currently received functional data is stopped.

[0066] In this embodiment, during the reception of standard data by the reusable Packet Direct Memory Access (PDMA) module, the received end-of-data identifier signal is monitored. The end-of-data identifier signal is a boundary identifier signal sent by the interface selection module to the flow control interface when sending the last standard data corresponding to the current functional data. It indicates that all standard data corresponding to the current functional data has been transmitted. When the flow control interface receives the end-of-data identifier signal from the interface selection module, it determines that the reusable PDMA module has completed receiving the standard data corresponding to the currently received functional data and stops receiving the standard data corresponding to the currently received functional data. Subsequently, the reusable PDMA module performs de-aggregation processing on the received standard data. Through the end-of-data identifier signal, the flow control interface can accurately identify the end position of the transmission of standard data corresponding to each functional data, thereby correctly dividing the data packet boundaries of the continuous standard data stream, ensuring that the de-aggregation processing is performed on the basis of complete data packets, and avoiding problems such as data packet truncation or splicing errors.

[0067] In the embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0068] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0070] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims.

Claims

1. A wireless communication chip supporting multi-host interface multiplexable PDMA, characterized in that, include: Multiple host interfaces, interface selection module, reusable packet direct memory access PDMA module, memory; Multiple host interfaces are used to connect to external hosts; the interface selection module is connected to each of the host interfaces and the reusable packet direct memory access (PDMA) module respectively; the reusable packet direct memory access (PDMA) module is connected to the memory; wherein, the multiple host interfaces share the reusable packet direct memory access (PDMA) module and the memory. The interface selection module is configured to select the currently working host interface from multiple host interfaces, convert the data from the selected host interface into standard data and output it to the reusable packet direct memory access (PDMA) module, and / or output the standard data from the reusable packet direct memory access (PDMA) module to the selected host interface. The reusable Packet Direct Memory Access (PDMA) module is configured to receive standard data from the interface selection module, perform de-aggregation processing on the received standard data to obtain data packets, write the obtained data packets into the memory, and / or read data packets from the memory, perform aggregation processing on the read data packets to obtain standard data, and output the obtained standard data to the interface selection module.

2. The wireless communication chip of claim 1, wherein, It also includes a MAC controller; the MAC controller is connected to the reusable packet direct memory access (PDMA) module and the memory, respectively. In the MAC transmission direction, the MAC controller is configured to allocate free space in the memory and issue a first descriptor to the reusable packet direct memory access (PDMA) module. The first descriptor contains the address information and size of the free space; The reusable packet direct memory access (PDMA) module is configured to write the de-aggregated data packets into the corresponding free space according to the first descriptor.

3. The wireless communication chip of claim 2, wherein, In the MAC receiving direction, the MAC controller is configured to store the data packet to be sent into the memory, and then issue a second descriptor to the reusable packet direct memory access (PDMA) module; the second descriptor contains the storage address and data packet length of the data packet to be sent. The reusable packet direct memory access (PDMA) module is configured to read the corresponding data packets based on the second descriptor and perform aggregation processing.

4. The wireless communication chip of claim 3, wherein, The reusable packet direct memory access (PDMA) module includes a descriptor queue, which is used to cache the first descriptor and / or the second descriptor. In the MAC transmission direction, the reusable packet direct memory access PDMA module is configured to sequentially retrieve the first descriptor from the descriptor queue; In the MAC receiving direction, the reusable packet direct memory access (PDMA) module is configured to sequentially retrieve the second descriptor from the descriptor queue.

5. The wireless communication chip according to claim 1, characterized in that, When the reusable Packet Direct Memory Access (PDMA) module aggregates the read data packets to obtain standard data and outputs the obtained standard data to the interface selection module, it is specifically configured as follows: Based on the receiving capacity of the currently operating host interface, configure aggregation parameters, and aggregate multiple data packets into one data packet according to the aggregation parameters. Then, output the aggregated data packet as standard data to the interface selection module. The aggregation parameters include the number of aggregated packets and / or the maximum aggregation length. The number of aggregated packets is used to limit the number of data packets in a single aggregation, and the maximum aggregation length is used to limit the total length of the data packet after a single aggregation.

6. The wireless communication chip according to claim 1, characterized in that, The reusable Packet Direct Memory Access (PDMA) module is specifically configured to, when de-aggregating received tag data to obtain data packets: Based on the header information carried in the received standard data, the standard data is split into multiple data packets.

7. The wireless communication chip according to claim 1, characterized in that, The reusable packet direct memory access (PDMA) module includes a flow control interface. The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module receives standard data from the interface selection module, arbitrate among multiple pending functional data corresponding to the currently working host interface based on the control state of the reusable packet direct memory access (PDMA) module and the transmission state of the currently working host interface, and select the currently received functional data from the multiple pending functional data. The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: receive standard data output by the interface selection module that corresponds to the selected functional data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module reads data packets from the memory, arbitrate among multiple functional data to be transmitted corresponding to the currently working host interface based on the control state of the reusable packet direct memory access (PDMA) module and the reception state of the currently working host interface, and select the functional data to be sent. The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: read data packets corresponding to selected functional data from the memory, and perform aggregation processing on the read data packets.

8. The wireless communication chip according to claim 1, characterized in that, The reusable packet direct memory access (PDMA) module includes a flow control interface. The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module receives standard data from the interface selection module, arbitrate according to the priority of each functional data to be received, and select the functional data to be received with the highest priority as the currently received functional data; The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: receive standard data output by the interface selection module that corresponds to the selected functional data, and perform de-aggregation processing on the received standard data; And / or, The flow control interface is configured to: before the reusable packet direct memory access (PDMA) module reads data packets from the memory, arbitrate according to the priority of each functional data to be sent, and select the functional data to be sent with the highest priority as the functional data to be sent currently; The reusable Packet Direct Memory Access (PDMA) module is specifically configured to: read data packets corresponding to selected functional data from the memory, and perform aggregation processing on the read data packets.

9. The wireless communication chip according to claim 2, characterized in that, The reusable packet direct memory access (PDMA) module includes a flow control interface. The flow control interface is also configured to: after selecting the currently received functional data, send a receive ready signal to the interface selection module so that the reusable packet direct memory access PDMA module can start receiving standard data. During the process of the reusable packet direct memory access (PDMA) module receiving standard data, when the storage space in the MAC transmission direction of the memory is insufficient, or when the number of first descriptors in the descriptor queue used to cache the first descriptors in the reusable packet direct memory access (PDMA) module is insufficient, the receive ready signal is pulled low, and other functional data is selected as the currently received functional data. The receive ready signal is sent to the interface selection module so that the reusable packet direct memory access (PDMA) module can start receiving the standard data corresponding to the other functional data.

10. The wireless communication chip according to claim 9, characterized in that, The flow control interface is also configured as follows: During the process of the reusable packet direct memory access (PDMA) module receiving the standard data, when the end data identifier signal is received from the interface selection module, it is determined that the reusable packet direct memory access (PDMA) module has completed receiving the standard data corresponding to the currently received functional data, and the receiving of the standard data corresponding to the currently received functional data is stopped.

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