A data transmission circuit and chip

Abstract

The application discloses a data transmission circuit and chip, relates to the technical field of integrated circuit design, and aims to solve the technical problem that the whole data transmission circuit cannot work normally when independent asynchronous reset occurs at one end of a read / write end of an existing data transmission circuit. The data transmission circuit comprises a reset fusion module, a write-side gray code pointer management module and a read-side gray code pointer management module. The reset fusion module is configured to output a reset signal in response to any one of a write-side asynchronous reset end and a read-side asynchronous reset end, and output a quasi-logic reset signal. The write-side gray code pointer management module is configured to make a write-side gray code pointer of an asynchronous FIFO zero when the quasi-logic reset signal is received. The read-side gray code pointer management module is configured to make a read-side gray code pointer zero when the quasi-logic reset signal is received. The application can ensure that the whole data transmission circuit still has normal working capability when independent asynchronous reset occurs at any one of the read / write end.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a data transmission circuit and chip. Background Technology

[0002] In modern large-scale system-on-chip (SoC) and complex application-specific integrated circuit (ASIC) designs, data transmission across clock domains (CDC) is extremely common. Asynchronous first-in-first-out (FIFO) has become the core data transfer mechanism for solving cross-clock domain data transmission due to its advantage of enabling asynchronous data stream buffering and interaction.

[0003] Transmitting multi-bit binary pointers directly across clock domains can easily lead to metastability, resulting in misjudgment of state and data errors. Standard asynchronous FIFOs, by converting read / write pointers to Gray code and synchronizing them to the peer clock domain, utilize the characteristic that adjacent values ​​of Gray code only flip by a single bit, effectively avoiding the metastability problem caused by multi-bit signals crossing domains and ensuring the reliability of data transmission.

[0004] However, the inventors recognized that existing data transmission circuits use asynchronous FIFOs, which can solve the metastability problem caused by data transmission across clock domains to a certain extent. However, since asynchronous FIFOs usually share a global reset signal or have a strictly coordinated reset and release sequence, if one of the read or write ends experiences an independent asynchronous reset due to system strategy or abnormality during normal operation, it often leads to a complete imbalance in the relative position of the read and write pointers and the data state inside the FIFO. The pointer verification logic and the empty / full state judgment mechanism all fail, causing the entire data transmission circuit to be unable to work normally. Summary of the Invention

[0005] The present invention mainly addresses the technical problem that if an independent asynchronous reset occurs at either the read or write end of an existing data transmission circuit, the entire data transmission circuit will fail to function properly.

[0006] According to a first aspect, one embodiment provides a data transmission circuit configured with an asynchronous FIFO, the data transmission circuit comprising:

[0007] A reset fusion module includes a first reset signal input terminal, a second reset signal input terminal, and a reset signal output terminal. The first reset signal input terminal of the reset fusion module is connected to a write-side asynchronous reset terminal, and the second reset signal input terminal of the reset fusion module is connected to a read-side asynchronous reset terminal. The reset fusion module is configured to output a reset signal in response to either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal, and to output a quasi-logic reset signal through the reset signal output terminal of the reset fusion module.

[0008] A write-side Gray code pointer management module is provided, wherein the signal input terminal of the write-side Gray code pointer management module is connected to the reset signal output terminal of the reset fusion module; the write-side Gray code pointer management module is configured to set the write-side Gray code pointer of the asynchronous FIFO to zero when the quasi-logic reset signal is received.

[0009] A read-side Gray code pointer management module is provided, wherein the signal input terminal of the read-side Gray code pointer management module is connected to the reset signal output terminal of the reset fusion module; the read-side Gray code pointer management module is configured to set the read-side Gray code pointer of the asynchronous FIFO to zero when the quasi-logic reset signal is received.

[0010] In one embodiment, the reset fusion module includes a first metastable state elimination synchronization module, a second metastable state elimination synchronization module, a first logic module, a third metastable state elimination synchronization module, and a fourth metastable state elimination synchronization module, and the reset signal output terminal of the reset fusion module includes a first reset signal output terminal and a second reset signal output terminal;

[0011] The signal input terminal of the first metastability elimination synchronization module is connected to the write-side asynchronous reset terminal as the first reset signal input terminal of the reset fusion module, and the signal output terminal of the first metastability elimination synchronization module is connected to the first signal input terminal of the first logic module through the first signal extension module.

[0012] The signal input terminal of the second metastability elimination synchronization module is connected to the read-side asynchronous reset terminal as the second reset signal input terminal of the reset fusion module, and the signal output terminal of the second metastability elimination synchronization module is connected to the second signal input terminal of the first logic module through the second signal extension module.

[0013] The first logic module is configured to output a reset signal in response to either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal, and to output a quasi-logic reset signal through the signal output terminal of the first logic module;

[0014] The signal input terminal of the third metastability elimination synchronization module is connected to the signal output terminal of the first logic module, and the signal output terminal of the third metastability elimination synchronization module is connected to the signal input terminal of the write-side Gray code pointer management module as the first reset signal output terminal of the reset fusion module.

[0015] The signal input terminal of the fourth metastability elimination synchronization module is connected to the signal output terminal of the first logic module, and the signal output terminal of the fourth metastability elimination synchronization module is connected to the signal input terminal of the read-side Gray code pointer management module as the second reset signal output terminal of the reset fusion module.

[0016] In one embodiment, the write-side Gray code pointer management module includes a first signal selection module. The selection control terminal of the first signal selection module is connected to the reset signal output terminal of the reset fusion module as the signal input terminal of the write-side Gray code pointer management module. One signal input terminal of the first signal selection module is connected to the write-side Gray code counter of the asynchronous FIFO. The output terminal of the first signal selection module is connected to the data input terminal of the write-side Gray code pointer register of the asynchronous FIFO. The first signal selection module is configured to output a first logic level through its output terminal when the quasi-logic reset signal is received, and to output the pointer generated by the write-side Gray code counter through its output terminal when the quasi-logic reset signal is not received.

[0017] When the first logic level is input to the data input terminal of the write-side Gray code pointer register, the write-side Gray code pointer of the asynchronous FIFO is set to zero; when the pointer generated by the write-side Gray code counter is input to the data input terminal of the write-side Gray code pointer register, the write-side Gray code pointer of the asynchronous FIFO takes the pointer generated by the write-side Gray code counter.

[0018] The read-side Gray code pointer management module includes a second signal selection module. The selection control terminal of the second signal selection module serves as the signal input terminal of the read-side Gray code pointer management module and is connected to the reset signal output terminal of the reset fusion module. One signal input terminal of the second signal selection module is connected to the read-side Gray code counter of the asynchronous FIFO, and the output terminal of the second signal selection module is connected to the data input terminal of the read-side Gray code pointer register of the asynchronous FIFO. The second signal selection module is configured to output a second logic level through its output terminal when the quasi-logic reset signal is received, and to output the pointer generated by the read-side Gray code counter through its output terminal when the quasi-logic reset signal is not received.

[0019] When the second logic level is input to the data input terminal of the read-side Gray code pointer register, the read-side Gray code pointer of the asynchronous FIFO is set to zero; when the pointer generated by the read-side Gray code counter is input to the data input terminal of the read-side Gray code pointer register, the read-side Gray code pointer of the asynchronous FIFO takes the pointer generated by the read-side Gray code counter.

[0020] In one embodiment, the data transmission circuit further includes:

[0021] A write-side forced takeover module is provided, wherein the signal input terminal of the write-side forced takeover module is connected to the reset signal output terminal of the reset fusion module, and the write-side forced takeover module is connected to the full state indicator terminal of the asynchronous FIFO. The write-side forced takeover module is configured to enable the full state indicator terminal when the quasi-logic reset signal is received.

[0022] A read-side forced takeover module is provided, wherein the signal input terminal of the read-side forced takeover module is connected to the reset signal output terminal of the reset fusion module, and the read-side forced takeover module is connected to the empty signal indicator terminal of the asynchronous FIFO. The read-side forced takeover module is configured to enable the empty signal indicator terminal when the quasi-logic reset signal is received.

[0023] In one embodiment, the write-side forced takeover module includes a third signal extension module and a second logic module. The signal input terminal of the third signal extension module is connected to the reset signal output terminal of the reset fusion module, serving as the signal input terminal of the write-side forced takeover module. The signal output terminal of the third signal extension module is connected to the first signal input terminal of the second logic module. The second signal input terminal of the second logic module is connected to the signal output terminal of the write-side state judgment module, and the output terminal of the second logic module is connected to the full state indicator terminal of the asynchronous FIFO. The write-side state judgment module is connected to the write-side Gray code pointer management module.

[0024] The write-side state determination module is used to determine whether the write side of the asynchronous FIFO is full. When it is determined that the write side of the asynchronous FIFO is full, the write-side state determination module outputs a full flag signal through the signal output terminal of the write-side state determination module. The second logic module is configured to enable the full state indicator terminal when it receives the quasi-logic reset signal or the full flag signal.

[0025] The read-side forced takeover module includes a fourth signal extension module and a third logic module. The signal input terminal of the fourth signal extension module is connected to the reset signal output terminal of the reset fusion module, serving as the signal input terminal of the read-side forced takeover module. The signal output terminal of the fourth signal extension module is connected to the first signal input terminal of the third logic module. The second signal input terminal of the third logic module is connected to the signal output terminal of the read-side state judgment module. The output terminal of the third logic module is connected to the empty signal indicator terminal of the asynchronous FIFO. The read-side state judgment module is connected to the read-side Gray code pointer management module.

[0026] The read-side state determination module is used to determine whether the read side of the asynchronous FIFO is empty. When it is determined that the read side of the asynchronous FIFO is empty, the read-side state determination module outputs an empty flag signal through the signal output terminal of the read-side state determination module. The third logic module is configured to enable the empty signal indicator terminal when it receives the quasi-logic reset signal or the empty flag signal.

[0027] In one embodiment, the input terminal of the write-side state determination module is connected to the reset signal output terminal of the reset fusion module, and the write-side state determination module is configured to output a full flag signal through the signal output terminal of the write-side state determination module when the quasi-logic reset signal is received.

[0028] The input terminal of the read-side state determination module is connected to the reset signal output terminal of the reset fusion module. The read-side state determination module is configured to output an empty flag signal through its signal output terminal when it receives the quasi-logic reset signal; and / or,

[0029] The third signal extension module can extend the input signal by 3b / a cycles, and the fourth signal extension module can extend the input signal by 3a / b cycles, where a is the read-side frequency of the asynchronous FIFO, b is the write-side frequency of the asynchronous FIFO; and / or,

[0030] Both the second and third logic modules are OR gates.

[0031] In one embodiment, the data transmission circuit further includes:

[0032] A data access module is provided, wherein the address input terminal of the data access module is connected to the address output terminal of the write-side Gray code pointer management module, and the selection control terminal of the data access module is connected to the address output terminal of the read-side Gray code pointer management module. The data access module is configured to store the write data of the asynchronous FIFO according to the write address output by the address output terminal of the write-side Gray code pointer management module, and to output the read data of the asynchronous FIFO according to the read address output by the address output terminal of the read-side Gray code pointer management module.

[0033] In one embodiment, the data access module includes:

[0034] The data storage array has its address input terminal connected to the address output terminal of the write-side Gray code pointer management module, which serves as the address input terminal of the data access module. The write data input terminal of the data storage array is connected to the write data terminal of the asynchronous FIFO, and the write enable input terminal of the data storage array is connected to the write enable terminal of the asynchronous FIFO.

[0035] An address selector, wherein the data input terminal of the address selector is connected to the data output terminal of the data storage array, and the selection control terminal of the address selector is connected to the address output terminal of the read-side Gray code pointer management module as the selection control terminal of the data access module;

[0036] A fifth metastability elimination and synchronization module, wherein the data input terminal of the fifth metastability elimination and synchronization module is connected to the data output terminal of the address selector;

[0037] A read-side synchronous clock domain FIFO module is provided, wherein the write data input terminal of the read-side synchronous clock domain FIFO module is connected to the data output terminal of the fifth metastability elimination synchronization module, the data output terminal of the read-side synchronous clock domain FIFO module is connected to the read data terminal of the asynchronous FIFO, and the read enable input terminal of the read-side synchronous clock domain FIFO module is connected to the read enable terminal of the asynchronous FIFO.

[0038] In one embodiment, the data transmission circuit further includes:

[0039] A synchronous FIFO write status management module is provided, wherein the data input terminal of the synchronous FIFO write status management module is connected to the pointer output terminal of the read-side synchronous clock domain FIFO module; the synchronous FIFO write status management module is used to determine whether the read-side synchronous clock domain FIFO module is in a full state; when it is determined that the read-side synchronous clock domain FIFO module is not in a full state, the synchronous FIFO write status management module outputs a non-full signal.

[0040] An internal read request generation module is connected to the synchronous FIFO write state management module. One signal input terminal of the internal read request generation module is connected to the signal output terminal of the read-side state judgment module. The read-side state judgment module is connected to the read-side Gray code pointer management module. The read-side state judgment module is used to determine whether the read side of the asynchronous FIFO is empty. When the read side is determined to be non-empty, the read-side state judgment module outputs a non-empty signal through its signal output terminal. The signal output terminal of the internal read request generation module is connected to the write enable input terminal of the read-side synchronous clock domain FIFO module through a signal delay module. The signal output terminal of the internal read request generation module is also connected to the read-side Gray code pointer management module.

[0041] The internal read request generation module is configured to send internal read request signals to the read-side synchronous clock domain FIFO module and the read-side Gray code pointer management module respectively when it receives the non-full signal and the non-empty signal, thereby enabling the write enable input of the read-side synchronous clock domain FIFO module and using the internal read request signal as the increment condition of the read-side Gray code pointer in the read-side Gray code pointer management module, thereby incrementing the read-side Gray code pointer.

[0042] According to the second aspect, one embodiment provides a chip, the chip being provided with the data transmission circuit of any embodiment of the first aspect.

[0043] According to the data transmission circuit and chip of the above embodiment, this embodiment of the invention, based on the existing asynchronous FIFO, sets up a reset fusion module, a write-side Gray code pointer management module, and a read-side Gray code pointer management module. Since the reset fusion module is configured to respond to a reset signal output from either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal, and outputs a quasi-logic reset signal through the reset signal output terminal of the reset fusion module, the reset fusion module can generate a quasi-logic reset signal when either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal is reset and outputs a reset signal. This, in turn, enables the write-side Gray code pointer management module and the read-side Gray code pointer management module to... The pointer management module can simultaneously drive the Gray code pointer of its domain to zero on both the write and read sides. This ensures that when either the read or write end of the data transmission circuit experiences an independent asynchronous reset, the pointers in both clock domains will be cleared simultaneously. This prevents serious errors in the relative positions of the read and write pointers and the internal data state of the FIFO, eliminates the failure of the pointer verification logic and the empty / full discrimination mechanism, and ensures that even if a single end of the data transmission circuit experiences an independent asynchronous reset, the entire data transmission circuit can still operate normally. The data transmission circuit and chip provided in this embodiment of the invention are data transmission circuits and chips that can be independently and asynchronously reset on either the read or write end. Attached Figure Description

[0044] Figure 1 A block diagram of the first module architecture of a data transmission circuit according to one embodiment;

[0045] Figure 2 This is a block diagram of the internal components of a reset fusion module according to one embodiment;

[0046] Figure 3 This is a block diagram showing the internal components of a write-side Gray code pointer management module and a read-side Gray code pointer management module according to one embodiment;

[0047] Figure 4 A first internal structural block diagram of a data transmission circuit according to one embodiment;

[0048] Figure 5 This is a block diagram of the second module architecture of a data transmission circuit according to one embodiment;

[0049] Figure 6 This is a first internal block diagram of a write-side forced takeover module and a read-side forced takeover module according to one embodiment;

[0050] Figure 7 A second internal block diagram of a write-side forced takeover module and a read-side forced takeover module according to one embodiment;

[0051] Figure 8 This is a block diagram of the second internal structure of a data transmission circuit according to one embodiment;

[0052] Figure 9 This is a block diagram of the third module architecture of a data transmission circuit according to one embodiment;

[0053] Figure 10 A first internal component block diagram of a data access module according to one embodiment;

[0054] Figure 11 This is a second internal component block diagram of a data access module according to one embodiment;

[0055] Figure 12 This is a third internal structural block diagram of a data transmission circuit according to one embodiment;

[0056] Figure 13 This is a fourth internal structural block diagram of a data transmission circuit according to one embodiment.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100. Data transmission circuit; 10. Reset fusion module; 11. First metastability elimination synchronization module; 12. Second metastability elimination synchronization module; 13. First logic module; 14. Third metastability elimination synchronization module; 15. Fourth metastability elimination synchronization module; 16. First signal extension module; 17. Second signal extension module; 20. Write-side Gray code pointer management module; 21. First signal selection module; 22. Write-side Gray code counter; 23. Write-side Gray code pointer register; 30. Read-side Gray code pointer management module; 31. Second signal selection module; 32. Read-side Gray code counter; 33. Read-side Gray code pointer register; 40. Write-side forced takeover module; 41. Third signal extension module; 42. Second logic module; 43. Write-side status judgment module; 50. Read-side forced takeover module; 51. Fourth signal extension module; 52. Third logic module; 53. Read-side status judgment module; 60. Data access module; 61. Data storage array; 62. Address selector; 63. Fifth metastability elimination synchronization module; 64. Read-side synchronous clock domain FIFO module; 65. Synchronous FIFO write status management module; 66. Internal read request generation module; 67. Signal delay module; 200. Write-side asynchronous reset terminal; 300. Read-side asynchronous reset terminal; 400. Full status indicator terminal; 500. Empty signal indicator terminal; 600. Write data terminal; 700. Write enable terminal; 800. Read data terminal; 900. Read enable terminal. Detailed Implementation

[0059] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0060] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0061] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0062] Existing asynchronous FIFOs have the following problems when handling reset signals:

[0063] 1. The destructive nature of a single-sided independent reset: If, during normal operation, a clock domain on one side (e.g., the read end) experiences an independent asynchronous reset due to system policy or an anomaly, only the pointer of that clock domain (e.g., the read pointer) will be cleared, causing the asynchronous FIFO to malfunction.

[0064] 2. Metastability Propagation: Current timing path analysis often struggles to examine the timing of the reset signal reaching the register reset terminal during asynchronous reset pull-up, easily inducing severe metastability. Asynchronous reset pull-up occurs when a signal change occurs at a reset terminal, from 0 to 1, or from 1 to 0, triggering the reset action.

[0065] 3. Limitations of existing solutions: Traditionally, to avoid this problem, extremely complex reset trees and reset handshake protocols are designed at the SoC level, or a heavy state machine is added around the FIFO for data isolation. This not only consumes a lot of hardware logic area, but also increases the transmission latency of the link, making it difficult to balance high performance and high reliability.

[0066] The purpose of this invention is to break away from the reliance on strong coupling between read and write reset signals in traditional CDC designs and provide a highly robust digital circuit for data transmission. This circuit utilizes a FIFO architecture with peripheral modules, allowing both read and write ends to accept arbitrary independent asynchronous resets at any time, without ever generating metastable propagation at non-reset ends.

[0067] In one embodiment of the present invention, such as Figure 1 As shown, a data transmission circuit 100 is provided, which is configured with an asynchronous FIFO and can be used for data transmission between different clock domains; the data transmission circuit 100 includes:

[0068] The reset fusion module 10 includes a first reset signal input terminal, a second reset signal input terminal, and a reset signal output terminal. The first reset signal input terminal of the reset fusion module 10 is connected to the write-side asynchronous reset terminal 200, and the second reset signal input terminal of the reset fusion module 10 is connected to the read-side asynchronous reset terminal 300. The reset fusion module 10 is configured to output a reset signal in response to either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300, and to output a quasi-logic reset signal through the reset signal output terminal of the reset fusion module 10.

[0069] The write-side Gray code pointer management module 20 has its signal input terminal connected to the reset signal output terminal of the reset fusion module 10. The write-side Gray code pointer management module 20 is configured to set the write-side Gray code pointer of the asynchronous FIFO to zero when it receives a quasi-logic reset signal.

[0070] The read-side Gray code pointer management module 30 has its signal input terminal connected to the reset signal output terminal of the reset fusion module 10. The read-side Gray code pointer management module 30 is configured to set the read-side Gray code pointer of the asynchronous FIFO to zero when it receives a quasi-logic reset signal.

[0071] In the above embodiments, the reset signal can be a low-level signal (0) or a high-level signal (1). The choice between a low-level signal and a high-level signal can be arbitrarily specified as needed. For example, a low-level signal can be set as the reset signal. When either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300 outputs a low-level signal, it indicates that the terminal outputs a reset signal, which can also be referred to as the terminal being reset and pulled up.

[0072] The data transmission circuit 100 provided in this embodiment of the invention is an improvement on existing data transmission circuits implemented through asynchronous FIFOs. When a reset signal is generated at any end of the data transmission circuit 100, the reset fusion module 10 generates a quasi-logic reset signal and synchronizes it to the write-side clock domain and the read-side clock domain respectively. Then, it simultaneously drives the Gray code pointers on both the write and read sides to zero, thereby ensuring that when an independent asynchronous reset occurs at one end, the pointers in both clock domains will be cleared simultaneously. This prevents serious errors in the relative positions of the read and write pointers and the internal data state of the FIFO, eliminates the failure of the pointer verification logic and the empty / full discrimination mechanism, and ensures that even if an independent asynchronous reset occurs at one end, the entire data transmission circuit 100 can still operate normally. Therefore, the data transmission circuit 100 provided by this invention is a data transmission circuit in which either the read or write end can be independently and asynchronously reset.

[0073] As an optional implementation method, such as Figure 2 As shown, the reset fusion module 10 may specifically include a first metastability elimination synchronization module 11, a second metastability elimination synchronization module 12, a first logic module 13, a third metastability elimination synchronization module 14, and a fourth metastability elimination synchronization module 15. The reset signal output terminal of the reset fusion module 10 includes a first reset signal output terminal and a second reset signal output terminal.

[0074] The signal input terminal of the first metastability elimination synchronization module 11 is connected to the write-side asynchronous reset terminal 200 as the first reset signal input terminal of the reset fusion module 10. The signal output terminal of the first metastability elimination synchronization module 11 is connected to the first signal input terminal of the first logic module 13 through the first signal extension module 16. The first metastability elimination synchronization module 11 uses the write-side clock of the asynchronous FIFO.

[0075] The signal input terminal of the second metastability elimination synchronization module 12 is connected to the read-side asynchronous reset terminal 300 as the second reset signal input terminal of the reset fusion module 10. The signal output terminal of the second metastability elimination synchronization module 12 is connected to the second signal input terminal of the first logic module 13 through the second signal extension module 17. The second metastability elimination synchronization module 12 uses the read-side clock of the asynchronous FIFO.

[0076] The first logic module 13 is configured to output a reset signal in response to either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300, and to output a quasi-logic reset signal through the signal output terminal of the first logic module 13.

[0077] The signal input terminal of the third metastability elimination synchronization module 14 is connected to the signal output terminal of the first logic module 13. The signal output terminal of the third metastability elimination synchronization module 14 is connected to the signal input terminal of the write-side Gray code pointer management module 20 as the first reset signal output terminal of the reset fusion module 10. The third metastability elimination synchronization module 14 adopts the write-side clock of the asynchronous FIFO.

[0078] The signal input terminal of the fourth metastability elimination synchronization module 15 is connected to the signal output terminal of the first logic module 13. The signal output terminal of the fourth metastability elimination synchronization module 15 is connected to the signal input terminal of the read-side Gray code pointer management module 30 as the second reset signal output terminal of the reset fusion module 10. The fourth metastability elimination synchronization module 15 adopts the read-side clock of the asynchronous FIFO.

[0079] In the above embodiments, the first metastability elimination synchronization module 11, the second metastability elimination synchronization module 12, the third metastability elimination synchronization module 14, and the fourth metastability elimination synchronization module 15 can each include two stages of flip-flops. The first stage flip-flop samples the input signal at the clock edge to absorb metastabilities that may be introduced during transmission; the second stage flip-flop resamples the output of the previous stage to completely eliminate metastabilities and output a stable synchronization signal, preventing indeterminate states and logic errors in subsequent digital logic stages. For those skilled in the art, how to implement a synchronization module using flip-flops is common knowledge.

[0080] The first signal extension module 16 can extend the input signal by 3a / b cycles, and the second signal extension module 17 can extend the input signal by 3b / a cycles, where a is the read-side frequency of the asynchronous FIFO and b is the write-side frequency of the asynchronous FIFO.

[0081] As an optional implementation, when the reset signal output from either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300 is a low-level signal, the first logic module 13 can be an AND gate, and the corresponding quasi-logic reset signal is also a low-level signal; that is, when either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300 is reset and pulls up to generate a low-level signal, the first logic module 13 will also generate a low-level signal as a quasi-logic reset signal.

[0082] When the reset signal output from either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300 is a high-level signal, the first logic module 13 can be an OR gate, and the corresponding quasi-logic reset signal is a high-level signal; that is, when either the write-side asynchronous reset terminal 200 or the read-side asynchronous reset terminal 300 is reset and a high-level signal is generated, the first logic module 13 will also generate a high-level signal as a quasi-logic reset signal.

[0083] In other words, in this embodiment of the invention, the two-way two-stage synchronization modules (to avoid metastability) + two-way reset signal extension modules + one logic gate circuit (AND gate / OR gate) + two synchronization modules together constitute the reset fusion module 10 (also known as the two-stage synchronization fusion signal processing circuit) in this embodiment of the invention. Further details can be provided below:

[0084] (1) First metastability elimination synchronization module 11: Write-side asynchronous reset → Write-side clock domain two-stage flip-flops (D-FF1→D-FF2, rst terminal connected to the asynchronous reset terminal itself) → Output a stable level in the write-side clock domain;

[0085] (2) Second metastability elimination synchronization module 12: read-side asynchronous reset → read-side clock domain two-stage flip-flops → output at a stable level in the read-side clock domain;

[0086] (3) First signal extension module 16: The output of the first metastability elimination synchronization module 11 is then passed through a 3-level shift register in the write-side clock domain to widen the level pulse width to 3a / b cycles (a is the read-side frequency, b is the write-side frequency, and the ratio is rounded up to ≥3 beats to ensure that at least one complete level can be stably sampled under the read-side clock).

[0087] (4) Second signal extension module 17: The output of the second metastability elimination synchronization module 12 is then passed through a 3-level shift register in the clock domain on the read side to widen the level pulse width to 3b / a cycles;

[0088] (5) First logic module 13: Perform AND operation (reset low active) and OR operation (reset high active) on the outputs of the first signal extension module 16 and the second signal extension module 17 to synthesize a quasi-logic reset signal;

[0089] (6) Third metastability elimination synchronization module 14 / Fourth metastability elimination synchronization module 15: The quasi-logic reset signal is synchronized in two stages using the write-side clock and the read-side clock respectively to obtain the "logic reset" in the clock domains at both ends.

[0090] The reason why the reset fusion module 10 in this embodiment of the invention is not a simple two-stage trigger is as follows:

[0091] Simple two-stage synchronization can only solve the metastable sampling problem of asynchronous signals within their own clock domain, but cannot solve the problem of how to reliably notify the other end's clock domain when either end is reset alone. If the narrow pulse is not first widened into a wide pulse of more than one other end's clock cycle within the local clock domain, the other end's clock may directly miss the sample, and thus the two-stage synchronization of the third metastable elimination synchronization module 14 / fourth metastable elimination synchronization module 15 at the back end cannot capture the reset event.

[0092] The 3a / b period widening performed by the first signal extension module 16 and the 3b / a period widening performed by the second signal extension module 17 provide the third metastability elimination synchronization module 14 and the fourth metastability elimination synchronization module 15 with inputs that can be sampled by the counterpart clock. This is the physical prerequisite for subsequent two-end linked resets. The AND / OR gates of the first logic module 13 treat the reset of either end as a logical fusion of the resets of both ends, serving as the unified source for all downstream logic resets.

[0093] As an optional implementation method, such as Figure 3 As shown, the write-side Gray code pointer management module 20 includes a first signal selection module 21. The selection control terminal of the first signal selection module 21 is connected to the reset signal output terminal of the reset fusion module 10 as the signal input terminal of the write-side Gray code pointer management module 20. One signal input terminal of the first signal selection module 21 is connected to the write-side Gray code counter 22 of the asynchronous FIFO. The output terminal of the first signal selection module 21 is connected to the data input terminal (D terminal) of the write-side Gray code pointer register 23 of the asynchronous FIFO. The first signal selection module 21 is configured to output a first logic level through its output terminal when a quasi-logic reset signal is received, and to output the pointer generated by the write-side Gray code counter 22 through its output terminal when no quasi-logic reset signal is received.

[0094] When the first logic level is input to the data input terminal of the write-side Gray code pointer register 23, the write-side Gray code pointer of the asynchronous FIFO is set to zero; when the pointer generated by the write-side Gray code counter 22 is input to the data input terminal of the write-side Gray code pointer register 23, the write-side Gray code pointer of the asynchronous FIFO is taken from the pointer generated by the write-side Gray code counter 22.

[0095] The read-side Gray code pointer management module 30 includes a second signal selection module 31. The selection control terminal of the second signal selection module 31 is connected to the reset signal output terminal of the reset fusion module 10 as the signal input terminal of the read-side Gray code pointer management module 30. One signal input terminal of the second signal selection module 31 is connected to the read-side Gray code counter 32 of the asynchronous FIFO. The output terminal of the second signal selection module 31 is connected to the data input terminal (D terminal) of the read-side Gray code pointer register 33 of the asynchronous FIFO. The second signal selection module 31 is configured to output a second logic level through its output terminal when a quasi-logic reset signal is received, and to output the pointer generated by the read-side Gray code counter 32 through its output terminal when no quasi-logic reset signal is received.

[0096] When the second logic level is input to the data input terminal of the read-side Gray code pointer register 33, the read-side Gray code pointer of the asynchronous FIFO is set to zero; when the pointer generated by the read-side Gray code counter 32 is input to the data input terminal of the read-side Gray code pointer register 33, the read-side Gray code pointer of the asynchronous FIFO is taken from the pointer generated by the read-side Gray code counter 32.

[0097] Based on the specific structure of the reset fusion module 10, the specific connection relationship between the write-side Gray code pointer management module 20 and the read-side Gray code pointer management module 30 can also be found in [reference needed]. Figure 4 Based on the specific structure of the reset fusion module 10, the selection control terminal of the first signal selection module 21 is connected to the signal output terminal of the third metastability elimination synchronization module 14 as the signal input terminal of the write-side Gray code pointer management module 20, and the selection control terminal of the second signal selection module 31 is connected to the signal output terminal of the fourth metastability elimination synchronization module 15 as the signal input terminal of the read-side Gray code pointer management module 30.

[0098] In the above embodiments, the first signal selection module 21 / second signal selection module 31 can specifically be a 2-to-1 selector, or it can be implemented equivalently using an AND gate shield. That is to say, the specific circuit structure of the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30 can be that a 2-to-1 selector is inserted before the D terminal of the write-side Gray code pointer register 23 / read-side Gray code pointer register 33. Taking the high-level signal (1) as the reset signal as an example, an optional connection relationship of each port of the 2-to-1 selector is as follows:

[0099] The sel terminal is a logic reset applied to the D terminal (connected to the output of the third metastability elimination synchronization module 14 or the fourth metastability elimination synchronization module 15).

[0100] in0 = next_gray_pointer (the next Gray code value calculated based on the current pointer and the increment / decrement rule);

[0101] in1=0;

[0102] The selector output is fed into the D terminal of the register; the register's own rst terminal still retains the connection to the chip's top-level hardware asynchronous reset pin and remains unchanged.

[0103] The effect achieved by applying the output of the selector to the D terminal of register in this embodiment of the invention is as follows:

[0104] (1) When the logic reset of the present invention is valid, the Q terminal (main output terminal) of the register at the next clock edge is forced to 0; when the logic reset is invalid, the register is updated to next_gray_pointer (next Gray code pointer) according to the normal clock cycle, and the circuit behavior is completely consistent with the traditional asynchronous FIFO;

[0105] (2) Since the path is a synchronous path within the local clock domain (the input is a stable level that has been synchronized by the third metastability elimination synchronization module 14 / the fourth metastability elimination synchronization module 15), timing convergence can be achieved using ordinary setup / hold (setup time / hold time) synchronization constraints, without needing to write a special false_path / max_delay (pseudo path / maximum delay constraint) for the reset signal.

[0106] (3) The register’s own rst terminal is still reserved for the top-level asynchronous reset of the chip, which has a higher priority than the logic reset of the present invention and does not destroy the original reset tree structure;

[0107] (4) The three-level priority is clear: top-level hard asynchronous reset > logic reset in the embodiment of the present invention > normal data update, which facilitates the identification of synthesis tools and the constraints of back-end timing engineers. This is the fundamental reason why the present invention can simplify the structure of timing constraint files (SynopsysDesign Constraints, SDC).

[0108] In some embodiments, such as Figure 5 As shown, the data transmission circuit 100 also includes:

[0109] The write-side forced takeover module 40 has its signal input terminal connected to the reset signal output terminal of the reset fusion module 10. The write-side forced takeover module 40 is also connected to the full state indicator terminal 400 of the asynchronous FIFO. The write-side forced takeover module 40 is configured to enable the full state indicator terminal 400 when it receives a quasi-logic reset signal, so that the full state indicator terminal 400 presents a full state to the outside world.

[0110] The read-side forced takeover module 50 has its signal input terminal connected to the reset signal output terminal of the reset fusion module 10. The read-side forced takeover module 50 is also connected to the empty signal indicator terminal 500 of the asynchronous FIFO. The read-side forced takeover module 50 is configured to enable the empty signal indicator terminal 500 when a quasi-logic reset signal is received, so that the empty signal indicator terminal 500 presents an empty signal to the outside world.

[0111] As an optional implementation method, such as Figure 6 As shown, the write-side forced takeover module 40 includes a third signal extension module 41 and a second logic module 42. The signal input terminal of the third signal extension module 41 is connected to the reset signal output terminal of the reset fusion module 10 as the signal input terminal of the write-side forced takeover module 40. The signal output terminal of the third signal extension module 41 is connected to the first signal input terminal of the second logic module 42. The second signal input terminal of the second logic module 42 is connected to the signal output terminal of the write-side state judgment module 43. The output terminal of the second logic module 42 is connected to the full state indicator terminal 400 of the asynchronous FIFO. The write-side state judgment module 43 is connected to the write-side Gray code pointer management module 20.

[0112] The write-side status judgment module 43 is used to determine whether the write side of the asynchronous FIFO is full. When it is determined that the write side of the asynchronous FIFO is full, the write-side status judgment module 43 outputs a full flag signal through the signal output terminal of the write-side status judgment module 43. The second logic module 42 is configured to enable the full status indicator terminal 400 when it receives a quasi-logic reset signal or a full flag signal.

[0113] The read-side forced takeover module 50 includes a fourth signal extension module 51 and a third logic module 52. The signal input terminal of the fourth signal extension module 51 is connected to the reset signal output terminal of the reset fusion module 10 as the signal input terminal of the read-side forced takeover module 50. The signal output terminal of the fourth signal extension module 51 is connected to the first signal input terminal of the third logic module 52. The second signal input terminal of the third logic module 52 is connected to the signal output terminal of the read-side status judgment module 53. The output terminal of the third logic module 52 is connected to the empty signal indicator terminal 500 of the asynchronous FIFO. The read-side status judgment module 53 is connected to the read-side Gray code pointer management module 30.

[0114] The read-side status judgment module 53 is used to determine whether the read side of the asynchronous FIFO is empty. When it is determined that the read side of the asynchronous FIFO is empty, the read-side status judgment module 53 outputs an empty flag signal through the signal output terminal of the read-side status judgment module 53. The third logic module 52 is configured to enable the empty signal indicator terminal 500 when it receives a quasi-logic reset signal or an empty flag signal.

[0115] In the above embodiments, the third signal extension module 41 can extend the input signal by 3b / a cycles, and the fourth signal extension module 51 can extend the input signal by 3a / b cycles, where a is the read-side frequency of the asynchronous FIFO and b is the write-side frequency of the asynchronous FIFO; the second logic module 42 and the third logic module 52 can both be OR gates.

[0116] In other words, in this embodiment of the invention, by setting up the write-side forced takeover module 40 and the read-side forced takeover module 50, a circuit logic is provided to prevent external circuits from reading and writing to the system. This circuit logic corresponds to the following modules in the accompanying drawings:

[0117] (1) Write side: Third signal extension module 41 (extends the quasi-logic reset signal by 3b / a cycles as the write side takeover signal) + second logic module 42 (the write side takeover signal forces the write side to be full), output to the external full state port;

[0118] (2) Read side: The fourth signal extension module 51 (extends the quasi-logic reset signal by 3a / b cycles as the read side takeover signal) + the third logic module 52 (forces the read side to be empty with the read side takeover signal), output to the external empty signal port.

[0119] Function: During the effective period of the logic reset signal and for several cycles after its release, the write-side forced takeover module 40 and the read-side forced takeover module 50 can force the external full / empty signal to be full / empty, so that the external host sees the interface as busy and stops reading and writing. This avoids data loss or reading of incorrect data when the full / empty judgment and pointer are still in the transition state window when the FIFO body at both ends of the read and write are reset.

[0120] The design basis for the extended time is as follows: the additional extended time of the third signal extension module 41 / fourth signal extension module 51 = the max (the expansion period provided by the first signal extension module 16 in the write-side clock domain and the expansion period provided by the second signal extension module 17 in the read-side clock domain) after being converted according to the ratio of the peer clock + a certain margin, to ensure that the full / empty shield is only released after the Gray code pointer, credit management and empty / full determination of the FIFO main body at both ends have been completely restored to stability.

[0121] As an optional implementation method, such as Figure 7As shown, the input terminal of the write-side state judgment module 43 (specifically, the D terminal of the register in the write-side state judgment module 43) can also be connected to the reset signal output terminal of the reset fusion module 10. The write-side state judgment module 43 is configured to output a full flag signal through the signal output terminal of the write-side state judgment module 43 when a quasi-logic reset signal is received.

[0122] The input terminal of the read-side status judgment module 53 (specifically, the D terminal of the register in the read-side status judgment module 53) can also be connected to the reset signal output terminal of the reset fusion module 10. The read-side status judgment module 53 is configured to output an empty flag signal through the signal output terminal of the read-side status judgment module 53 when a quasi-logic reset signal is received.

[0123] By connecting the reset signal output terminal of the reset fusion module 10 to the input terminals of the write-side state judgment module 43 and the read-side state judgment module 53, during single-ended asynchronous reset, the write-side state output by the write-side state judgment module 43 can be forced to full, and the read-side state output by the read-side state judgment module 53 can be forced to empty. This allows the second logic module 42 to simultaneously receive the quasi-logic reset signal and the full flag signal, and the third logic module 52 to simultaneously receive the quasi-logic reset signal and the empty flag signal. This ensures that the second logic module 42 can definitely set the full state indicator terminal 400 to valid, and the third logic module 52 can definitely set the empty signal indicator terminal 500 to valid.

[0124] Based on the specific structure of the reset fusion module 10, the specific connection relationship between the write-side forced takeover module 40 and the read-side forced takeover module 50 can also be found in [reference needed]. Figure 8 Based on the specific structure of the reset fusion module 10, the signal input terminal of the third signal extension module 41 is connected to the signal output terminal of the third metastability elimination synchronization module 14 as the signal input terminal of the write-side forced takeover module 40, and the input terminal of the write-side state judgment module 43 is connected to the signal output terminal of the third metastability elimination synchronization module 14; the signal input terminal of the fourth signal extension module 51 is connected to the signal output terminal of the fourth metastability elimination synchronization module 15 as the signal input terminal of the read-side forced takeover module 50, and the input terminal of the read-side state judgment module 53 is connected to the signal output terminal of the fourth metastability elimination synchronization module 15.

[0125] In the above embodiments, the write-side forced takeover module 40 and the read-side forced takeover module 50, for each externally visible empty / full signal, connect a two-input OR gate in series at the output of the original empty / full determination (e.g., assign empty=(rd_gray==wr_gray_sync)). The original empty / full determination is the empty / full determination logic of a traditional asynchronous FIFO, which corresponds to the write-side state determination module 43 and the read-side state determination module 53 in the embodiments of the present invention.

[0126] Write side: The judgment logic in the second logic module 42 is full_out = full_logic OR reset_logic_wr, where full_logic is the full flag signal output by the write side state judgment module 43, and reset_logic_wr is the logic reset output in the write side clock domain by the third metastability elimination synchronization module 14.

[0127] On the read side: the judgment logic in the third logic module 52 is empty_out=empty_logic OR reset_logic_rd, where empty_logic is the empty flag signal output by the read side state judgment module 53, and reset_logic_rd is the logic reset output in the read side clock domain by the fourth metastability elimination synchronization module 15.

[0128] The logic reset signal output by the reset fusion module 10 is forced to set the full signal to 1 and the empty signal to 1 during the reset period by passing through the other input of the OR gate.

[0129] The working timing steps involved in the write-side forced takeover module 40 and the read-side forced takeover module 50 are as follows:

[0130] t=0: The quasi-logic reset signal of the first logic module 13 is valid;

[0131] t=1~2: After two stages of synchronization, the third metastability elimination synchronization module 14 and the fourth metastability elimination synchronization module 15 output reset_logic_wr / reset_logic_rd in the clock domains at both ends respectively;

[0132] t=3: The third signal extension module 41 / fourth signal extension module 51 extends reset_logic_wr / reset_logic_rd through 3b / a and 3a / b cycles and then sends it to the second logic module 42 / third logic module 52;

[0133] Starting at t=4: The OR gate combinational logic in the second logic module 42 / third logic module 52 immediately sets the corresponding full_out / empty_out to 1, and stably outputs full and empty values ​​to the outside.

[0134] This invention provides a mechanism for transmitting the empty signal on the read side and the full signal on the write side when a reset is valid, through the write-side forced takeover module 40 and the read-side forced takeover module 50: the logic reset output by the third metastability elimination synchronization module 14 / fourth metastability elimination synchronization module 15 acts on the forced terminal of the above-mentioned OR gate, so that the empty and full signals no longer depend on the intermediate states of the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30 / write-side state judgment module 43 / read-side state judgment module 53 during the reset validity period (these intermediate states may be erroneous or in a transitional state during the reset process), but are directly determined by the logic reset signal in this invention embodiment, thereby ensuring the reliability of external shielding read and write.

[0135] In some embodiments, such as Figure 9 As shown, the data transmission circuit 100 also includes:

[0136] The data access module 60 has its address input terminal connected to the address output terminal of the write-side Gray code pointer management module 20, and its selection control terminal connected to the address output terminal of the read-side Gray code pointer management module 30. The data access module 60 is configured to store the write data of the asynchronous FIFO according to the write address output by the address output terminal of the write-side Gray code pointer management module 20, and to output the read data of the asynchronous FIFO according to the read address output by the address output terminal of the read-side Gray code pointer management module 30.

[0137] As an optional implementation method, such as Figure 10 As shown, the data access module 60 includes:

[0138] The data storage array 61 has its address input terminal connected to the address output terminal of the write-side Gray code pointer management module 20, which serves as the address input terminal of the data access module 60. The write data input terminal of the data storage array 61 is connected to the write data terminal 600 of the asynchronous FIFO, and the write enable input terminal of the data storage array 61 is connected to the write enable terminal 700 of the asynchronous FIFO. That is, the write data of the asynchronous FIFO is sent to the write data input terminal of the data storage array 61, and the write enable signal generated by the write-side control logic is connected to the write enable input terminal of the data storage array 61.

[0139] Address selector 62, the data input terminal of address selector 62 is connected to the data output terminal of data storage array 61, and the selection control terminal of address selector 62 is connected to the address output terminal of read-side Gray code pointer management module 30 as the selection control terminal of data access module 60.

[0140] The fifth metastability elimination and synchronization module 63 has its data input terminal connected to the data output terminal of the address selector 62; the fifth metastability elimination and synchronization module 63 uses the read-side clock of the asynchronous FIFO;

[0141] The read-side synchronous clock domain FIFO module 64 (also referred to as synchronous FIFO) has its write data input terminal connected to the data output terminal of the fifth metastability elimination synchronization module 63, its data output terminal connected to the read data terminal 800 of the asynchronous FIFO, and its read enable input terminal connected to the read enable terminal 900 of the asynchronous FIFO. That is, the data output terminal of the read-side synchronous clock domain FIFO module 64 is used to output the read data of the asynchronous FIFO, and the read enable signal generated by the read-side control logic is connected to the read enable input terminal of the read-side synchronous clock domain FIFO module 64.

[0142] As an optional implementation method, such as Figure 11 As shown, the data access module 60 also includes:

[0143] The synchronous FIFO write status management module 65 is connected to the pointer output terminal of the read-side synchronous clock domain FIFO module 64. The synchronous FIFO write status management module 65 is used to determine whether the read-side synchronous clock domain FIFO module 64 is in a full state. When it is determined that the read-side synchronous clock domain FIFO module 64 is not in a full state, the synchronous FIFO write status management module 65 outputs a non-full signal.

[0144] An internal read request generation module 66 is connected to a synchronous FIFO write status management module 65. One signal input terminal of the internal read request generation module 66 is connected to the signal output terminal of the read-side status judgment module 53. The read-side status judgment module 53 is connected to a read-side Gray code pointer management module 30. The read-side status judgment module 53 is used to determine whether the read side of the asynchronous FIFO is empty. When the read side is determined to be non-empty, the read-side status judgment module 53 outputs a non-empty signal through its signal output terminal. The signal output terminal of the internal read request generation module 66 is connected to the write enable input terminal of the read-side synchronous clock domain FIFO module 64 through a signal delay module 67. The signal output terminal of the internal read request generation module 66 is also connected to the read-side Gray code pointer management module 30.

[0145] The internal read request generation module 66 is configured to send internal read request signals to the read-side synchronous clock domain FIFO module 64 and the read-side Gray code pointer management module 30 respectively when it receives a non-full signal and a non-empty signal. This enables the write enable input of the read-side synchronous clock domain FIFO module 64, allowing the read data output by the fifth metastability elimination synchronization module 63 to be written and then output to the user. The internal read request signal is also used as the increment condition for the read-side Gray code pointer in the read-side Gray code pointer management module 30, causing the read-side Gray code pointer to increment.

[0146] In the above embodiments, similar to other metastability elimination synchronization modules, the fifth metastability elimination synchronization module 63 may also include two-stage flip-flops; the signal delay module 67 can delay the input signal by three read-side cycles; the depth of the read-side synchronization clock domain FIFO module 64 is greater than or equal to 4; and the internal read request generation module 66 may include an AND gate.

[0147] A complete circuit block diagram of the data transmission circuit 100 provided in this embodiment of the invention can also be found in [the following text is missing from the original] Figure 12 and Figure 13 .exist Figure 13 The document fully illustrates the connections between the internal structures of each module. Figure 13 It can be seen that the output of the write-side Gray code pointer register 23 is connected to the address input of the data storage array 61 as the address output of the write-side Gray code pointer management module 20; the output of the read-side Gray code pointer register 33 is connected to the selection control terminal of the address selector 62 as the address output of the read-side Gray code pointer management module 30; the signal output of the internal read request generation module 66 is specifically connected to the read-side Gray code counter 32 to control the increment of the count in the read-side Gray code counter 32.

[0148] In the above embodiment, the fifth metastability elimination synchronization module 63, as a two-stage synchronous metastability elimination circuit in the data path, is located between the output of the address selector 62 and the write data input of the read-side synchronous clock domain FIFO module 64 (synchronous FIFO). Specifically, the fifth metastability elimination synchronization module 63 employs two stages of flip-flops (D-FF1→D-FF2), each operating under the read-side clock. The D terminal of D-FF1 is connected to the output of the address selector 62, the Q terminal of D-FF1 is connected to the D terminal of D-FF2, and the Q terminal of D-FF2 is sent to the write data port of the read-side synchronous clock domain FIFO module 64. The reset of both stages of flip-flops is connected to the logic reset output of the fourth metastability elimination synchronization module 15 (maintaining consistency with the system reset).

[0149] The data storage array 61 is written by the write clock and write address, and outputs all address data in parallel. The address selector 62 selects the current data by the read address within the read clock domain. When an independent asynchronous reset occurs on the write side, the write-side Gray code pointer management module 20 is set to zero by the logic reset of the third metastability elimination synchronization module 14. The write address changes abruptly at a certain clock cycle, and all address data columns of the data storage array 61 also change abruptly. The output of the address selector 62 may happen to be at the edge of the setup / hold window of the read-side clock at that clock cycle, thus entering a metastable state. After adding the two-stage flip-flops of the fifth metastability elimination synchronization module 63, the metastability of D-FF1 has sufficient time to converge within a complete read-side clock cycle, and the output of D-FF2 is stable externally, achieving hardware-level metastability avoidance.

[0150] The read-side synchronous clock domain FIFO module 64 serves as a data valid signal alignment and synchronization FIFO. It operates entirely under the read-side clock, without any cross-clock domain issues. Structurally, it is identical to a traditional single-clock domain FIFO, including common write pointers / read pointers / memory, etc. Its internal working principle is as follows:

[0151] (a) The read-side status judgment module 53 outputs a non-empty value when the asynchronous FIFO is not empty;

[0152] (b) The synchronous FIFO write status management module 65 tracks the number of writes sent to the read-side synchronous clock domain FIFO module 64 and the number of writes that have been released, and outputs a full signal;

[0153] (c) Internal read request generation module 66 (AND gate): Internal read request = NOT (read-side status judgment module 53 outputs empty signal) AND NOT (synchronous FIFO write status management module 65 outputs full signal);

[0154] (d) The internal read request serves as the actual increment condition for the read-side Gray code pointer management module 30 (read-side Gray code pointer). Each time it goes high, the read address increases by 1, and the address selector 62 selects the current data.

[0155] (e) Data path: The output of address selector 62 is sent to the write data port of FIFO module 64 of read-side synchronous clock domain after two-stage synchronization by fifth metastability elimination and synchronization module 63. The total delay is 3 clock cycles (1 clock cycle trigger of address selector 62 back end + 2 clock cycle trigger of fifth metastability elimination and synchronization module 63).

[0156] (f) Write enable path: The internal read request is delayed by 3 read-side cycles by the signal delay module 67 and then sent to the write enable input port of the read-side synchronous clock domain FIFO module 64, which is strictly aligned with (e).

[0157] Data retrieval specifically refers to the process where the internal read request generation module 66 raises an internal read request for one cycle (generating an internal read request); its triggering condition is that the read-side status judgment module 53 is not empty, and the synchronous FIFO write status management module 65 is not full; the specific data retrieved is the data corresponding to the current read address of the traditional asynchronous FIFO (composed of write-side Gray code counter 22 + write-side Gray code pointer register 23 + read-side Gray code counter 32 + read-side Gray code pointer register 33 + data storage array 61 + address selector 62). In other words, it is not that the asynchronous FIFO's "empty flag is 1" that a request is made (on the contrary, the empty flag is 0, i.e., not empty), but rather that a request is issued only when the asynchronous FIFO is not empty and the downstream synchronous FIFO still has empty slots.

[0158] The "request signal" refers to the internal read request at the input of the signal delay module 67, and the "data" refers to the output data of the address selector 62 at the input of the fifth metastability elimination synchronization module 63. Their synchronization cycle delays are as follows:

[0159] The write enable delay is 3 cycles (provided by signal delay module 67), and the data delay is 3 cycles (1 cycle at the back end of address selector 62 + 2 cycles from fifth metastability elimination synchronization module 63). Equivalent cycles mean that the total delay of these two paths is the same, thus ensuring strict alignment at the entry of FIFO module 64 in the read-side synchronous clock domain.

[0160] The derivation process of the synchronous FIFO depth is as follows:

[0161] Assuming all system clocks are read-side clocks, the following sub-cycles are defined:

[0162] t1: From the time the internal read request generation module 66 pulls up the internal read request, to the time the synchronous FIFO write enable / write data corresponding to the request is completed and written to the read-side synchronous clock domain FIFO module 64, and is counted as sent by the synchronous FIFO write status management module 65, that is, internal read request → three-step delay by the signal delay module 67 → completion of writing by the read-side synchronous clock domain FIFO module 64, t1=3+1=4 steps;

[0163] t2: When the user sends the read enable signal to the FIFO module 64 in the synchronous clock domain on the read side when it is not empty, it reads one clock cycle of data and generates a "synchronous FIFO release signal" which is sent back to the synchronous FIFO write status management module 65. t2 = 1 clock cycle (ideal pipeline, no delay for the user).

[0164] t3: After receiving the release signal, the synchronous FIFO write status management module 65 clears one credit, causing the internal read request generation module 66 to re-release the next internal read request. t3 = 1 cycle.

[0165] The round-trip cycle T = t1 + t2 + t3 = 4 + 1 + 1 = 6 cycles (worst-case; in ideal full pipeline mode, t2 and t3 can be combined into a single cycle at the hardware level). To ensure that users do not experience bandwidth drops due to "read-side synchronous clock domain FIFO module 64 being empty but still having data not yet sent" under the highest bandwidth of continuous reading per cycle, the depth of read-side synchronous clock domain FIFO module 64 must be greater than or equal to the maximum number of unreleased data that can be accommodated between the first time the internal read request generation module 66 raises the internal read request and the first readable data appearing in read-side synchronous clock domain FIFO module 64.

[0166] Specifically Figure 12 and Figure 13 The typical scenario shown assumes that the read-side frequency is close to the write-side frequency, and the external read interface can respond within one clock cycle at the fastest:

[0167] From internal read request to completion of synchronous FIFO write = 3 cycles (signal delay module 67 delay) + 1 cycle (read-side synchronous clock domain FIFO module 64 write cycle) = 4 cycles;

[0168] The synchronous FIFO release signal returns to the synchronous FIFO write status management module. 65 release slots = 1 beat.

[0169] Add a 1-step margin (to cover cases where the external read enable does not respond immediately in the first step).

[0170] Total = 4 + 1 + 1 = 6 beats → raise to the power of 2, which is 8;

[0171] When the external interface is in its simplest pipeline (the user reads the data as soon as it is not empty on the first cycle and there is no handshake delay), it can be compressed to 4+1-1=4 cycles.

[0172] Therefore, the depth of the read-side synchronous clock domain FIFO module 64 is 4, which corresponds to the typical pipeline scenario where "the user interface can give read enable as soon as it is not empty on the first clock cycle and return a release signal on the next clock cycle". When there is more handshake delay in the back-end user interface, the depth of the read-side synchronous clock domain FIFO module 64 should be increased proportionally according to the above formula.

[0173] During normal operation (without reset), the overall signal flow of the data transmission circuit 100 provided in this embodiment of the invention is as follows:

[0174] (1) Write side: The user sends write enable and write data from the outside. The write side status judgment module 43 determines whether it is writable based on the difference between the current write pointer in the write side Gray code pointer management module 20 and the read pointer synchronized across the clock. When it is writable, the write pointer of the write side Gray code pointer management module 20 is incremented and the write address is output in Gray code form. At the same time, the write data is written to the corresponding position of the data storage array 61.

[0175] (2) Read side: The data storage array 61 continuously outputs all address data (i.e., the current content at each depth position is output in parallel). The address selector 62 selects the data corresponding to the current read address from the current read address using the current read address of the read side Gray code pointer management module 30 as the selection control terminal, and sends it to the fifth metastability elimination synchronization module 63 (two-stage synchronization to eliminate metastability). After the fifth metastability elimination synchronization module 63 stabilizes the data after two read side clock cycles, it is presented in the write data port of the read side synchronization clock domain FIFO module 64 (synchronization FIFO).

[0176] (3) Data valid signal path: When the asynchronous FIFO is not empty, the read-side state judgment module 53 outputs a non-empty value, which is ANDed with the non-full value of the synchronous FIFO write state management module 65 to obtain the internal read request output by the internal read request generation module 66. The internal read request is sent back to the read-side Gray code pointer management module 30 as the actual increment condition of the read-side Gray code pointer, and is also sent back to the synchronous FIFO write state management module 65 to record the sent request. At the same time, the internal read request is processed by the signal delay module 67 (delayed by three read-side cycles) to form the synchronous FIFO write enable.

[0177] Since the total delay of the data path is "1 clock cycle of address selector 62 + 2 clock cycles of two-stage synchronization by the fifth metastability elimination synchronization module 63 = 3 clock cycles", which is exactly equal to the 3-clock delay provided by the signal delay module 67, the synchronous FIFO write enable and the synchronous FIFO write data are aligned on the same read-side clock edge at the entry of the read-side synchronous clock domain FIFO module 64, ensuring that the valid signal of the data written to the read-side synchronous clock domain FIFO module 64 is strictly synchronized with the data.

[0178] (4) External read path: The user sends the read enable to the read-side synchronous clock domain FIFO module 64, and the read-side synchronous clock domain FIFO module 64 outputs read data to the outside. At the same time, the read enable also drives the release path corresponding to the read-side synchronous clock domain FIFO module 64, forming a synchronous FIFO release signal sent back to the synchronous FIFO write status management module 65, so that the synchronous FIFO write status management module 65 releases a slot, and the internal read request generation module 66 releases the next internal read request accordingly, thereby maintaining the continuous operation of the pipeline.

[0179] When an independent asynchronous reset occurs at either end, the overall signal flow of the data transmission circuit 100 provided in this embodiment of the invention is as follows (taking write-side asynchronous reset as an example):

[0180] Suppose that at time t=0, the write-side asynchronous reset is asynchronously pulled up externally:

[0181] (i) t=0~t1: The first metastability elimination synchronization module 11 performs two-stage pacing under the write-side clock to convert the asynchronous reset level into a stable level within the write-side clock domain; the first signal extension module 16 further widens this level by 3a / b cycles within the write-side clock domain (i.e., calculated according to the ratio of read-side frequency a to write-side frequency b, at least 3 pulse width cycles that can be stably sampled by the read-side clock). At the same time, the read-side asynchronous reset (assuming it has not occurred here) outputs a normal effective level via the second metastability elimination synchronization module 12 and the second signal extension module 17.

[0182] (ii) The first logic module 13 ANDs the two broadened levels (changing to an OR gate for active high reset) and outputs a quasi-logic reset signal. One path of the quasi-logic reset signal is synchronized to the write-side clock domain via the third metastability elimination synchronization module 14, acting as a logic reset at the D terminal, affecting the D terminals of registers such as the write-side Gray code pointer management module 20 and the write-side state judgment module 43. The other path is synchronized to the read-side clock domain via the fourth metastability elimination synchronization module 15, acting on the D terminals of registers such as the read-side Gray code pointer management module 30. In this way, a single-ended reset event is equivalently transformed into a synchronized and ordered logic reset within the read and write clock domains, and the Gray code pointers at both ends are simultaneously set to zero, avoiding pointer misalignment and FIFO deadlock caused by only one end being cleared.

[0183] (iii) Simultaneously, the quasi-logic reset signal output by the third metastability elimination synchronization module 14 is further extended by 3b / a cycles in the write-side clock domain by the third signal extension module 41, and then enters the second logic module 42 as the write-side takeover signal, forcibly pulling the external full state to full. The quasi-logic reset signal output by the fourth metastability elimination synchronization module 15 is further extended by 3a / b cycles in the read-side clock domain by the fourth signal extension module 51, and then enters the third logic module 52 as the read-side takeover signal, forcibly pulling the external empty signal to empty. This mechanism ensures that during the effective period of the quasi-logic reset and for several cycles after its release, the external interface seen by the external host is always empty on the read side and full on the write side, thus naturally blocking read and write operations, preventing data loss and the reading of erroneous data.

[0184] (iv) t=t1~t2: External write-side asynchronous reset release, but the extension provided by the first signal extension module 16 still keeps the quasi-logic reset valid; at the same time, the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30 completes the synchronous zeroing of the registers under the clock domains at both ends; at this time, the empty / full determination of the write-side status judgment module 43 and the read-side status judgment module 53 is also forced to be full on the write side and empty on the read side, further ensuring that the downstream second logic module 42 and the third logic module 52 shield the external read and write.

[0185] (v) After t=t2: The quasi-logic reset signal output by the first logic module 13 is released, and the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30 resumes normal counting; the additional extension provided by the third signal extension module 41 / fourth signal extension module 51 ensures that the second logic module 42 / third logic module 52 remains shielded from external read / write for several cycles, ensuring that the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30 / write-side state judgment module 43 / read-side state judgment module 53 is completely stable before allowing access; after the shielding of the second logic module 42 / third logic module 52 is released, the entire system smoothly resumes operation from a consistent state where both pointers are 0, and only exhibits a brief full / empty state externally throughout the process, without any metastable state propagation externally.

[0186] The process of asynchronous reset on the read side occurring independently is completely symmetrical to the above, except that the roles of the first metastability elimination synchronization module 11 / first signal extension module 16 and the second metastability elimination synchronization module 12 / second signal extension module 17 are interchanged. The conclusion is the same, so it will not be repeated here: the asynchronous reset at either end can achieve synchronous zeroing at both ends, forced shielding from the outside, and smooth recovery through this circuit structure.

[0187] In summary, the data transmission circuit 100 provided in this embodiment of the invention has the following external interface:

[0188] Inputs: Write-side asynchronous reset pin 200, Read-side asynchronous reset pin 300, Write data pin 600, Write enable pin 700, Read enable pin 900;

[0189] Outputs: Full status indicator 400, empty signal indicator 500, read data terminal 800.

[0190] From another perspective, the system can be divided into the following four module groups according to its functions:

[0191] 1. Reset Fusion Circuit Group (Reset Fusion Module 10):

[0192] First metastability elimination synchronization module 11: Write-side two-stage synchronization avoids metastability;

[0193] Second metastability elimination synchronization module 12: Read-side two-stage synchronization avoids metastability;

[0194] First signal extension module 16: Extends the write-side reset signal by 3a / b cycles;

[0195] Second signal extension module 17: Extends the read-side reset signal by 3b / a cycles;

[0196] First logic module 13: AND gate (replaced with OR gate if reset is active high) – synthesizes a quasi-logic reset signal;

[0197] Third metastability elimination synchronization module 14: Two-stage synchronization is applied to the write-side clock to eliminate metastability;

[0198] Fourth metastability elimination synchronization module 15: Two-stage synchronization is applied to the read-side clock to eliminate metastability.

[0199] 2. Modified traditional asynchronous FIFO main body:

[0200] Write-side Gray code pointer management module 20: Its D terminal is connected to the logic reset output of the third metastability elimination synchronization module 14;

[0201] The Gray code pointer management module 30 is connected to the logic reset output of the fourth metastability elimination synchronization module 15 at its D terminal;

[0202] Data storage array 61;

[0203] Address selector 62: Selects the current data from all address data of data storage array 61 using the read address output by read-side Gray code pointer management module 30;

[0204] Write-side state judgment module 43;

[0205] Read-side status judgment module 53 (combinatorial logic).

[0206] 3. Output isolation group to prevent external circuit read / write operations:

[0207] Third signal extension module 41: Extends the write-side control signal by 3b / a cycles;

[0208] Second logic module 42: Forces the full signal to be full (combinational logic) and outputs the full state;

[0209] Fourth signal extension module 51: Read-side control signal extension module for 3a / b cycles;

[0210] Third logic module 52: Force takeover of full signal is empty (combinational logic), output empty signal.

[0211] 4. Metastability elimination and synchronization FIFO group in the read-side data path:

[0212] Fifth metastability elimination synchronization module 63: Two-stage synchronization to eliminate metastability, located between the output of address selector 62 and the read-side synchronous clock domain FIFO module 64 for writing data;

[0213] Signal delay module 67: Delays three read-side cycles, located between the output of the read-side status judgment module 53 / internal read request generation module 66 and the write enable of the read-side synchronous clock domain FIFO module 64;

[0214] Synchronous FIFO write status management module 65;

[0215] Internal read request generation module 66: AND gate, internal read request = NOT (read-side status judgment module 53 empty signal) AND NOT (synchronous FIFO write status management module 65 full signal);

[0216] Read-side synchronous clock domain FIFO module 64 (depth 4).

[0217] To clearly illustrate the function of each module in the data transmission circuit 100 provided in this embodiment of the invention, some modules will be described in turn below:

[0218] (1) Write-side state judgment module 43: Essentially, it is a modified traditional asynchronous FIFO write controller. It determines the remaining writable space based on the difference between the write Gray code pointer of the write-side Gray code pointer management module 20 and the read Gray code pointer synchronized across clock cycles. When the external write enable is valid and the write side is not full, it controls the Gray code pointer in the write-side Gray code pointer management module 20 to increment and generate a new write address, while simultaneously causing the data storage array 61 to sample write data at that address. When the logic reset output by the third metastability elimination synchronization module 14 is valid, the D terminal of the counter register inside the write-side state judgment module 43 is forcibly cleared to zero by the logic reset output by the third metastability elimination synchronization module 14, thus synchronizing with the write-side Gray code pointer management module 20 to zero.

[0219] (2) Write-side Gray code pointer management module 20 / Read-side Gray code pointer management module 30: Use Gray code counter and register, each increment only flips one bit to avoid intermediate state errors when synchronizing multiple bits across clocks; its register D terminal inserts a two-to-one selector for logic reset as described above, and the rst terminal is reserved for asynchronous reset of the chip top layer.

[0220] (3) Data storage array 61: Dual-port SRAM / flip-flop array. The write port is driven by write clock + write address + write data. The read port outputs all address data in parallel (i.e., the current content of all depth positions is output in parallel). Together with the address selector 62, it completes the combination selection within the clock domain and realizes zero-wait readout.

[0221] (4) Address selector 62: Using the read address output by the read-side Gray code pointer management module 30 as the selection control terminal, it selects the one-time data corresponding to the current read address from all the address data of the data storage array 61 and outputs it to the fifth metastability elimination synchronization module 63.

[0222] (5) Read-side state judgment module 53: Combinational logic module, compares the difference between the read Gray code pointer of the read-side Gray code pointer management module 30 and the write Gray code pointer synchronized across domains to obtain an indication of whether the read side is empty; the combined output is connected in series with an OR gate, and when the logic reset output by the fourth metastability elimination synchronization module 15 is valid, the D terminal of the counter register inside the read-side state judgment module 53 is forcibly cleared to zero by the logic reset output by the fourth metastability elimination synchronization module 15, thereby synchronizing with the write-side Gray code pointer management module 20 to zero.

[0223] (6) Synchronous FIFO write status management module 65: Internally maintains a counter cnt. Each time an internal read request is issued (the output of the internal read request generation module 66 is pulled high), cnt is incremented by 1; each time a synchronous FIFO release signal is received, cnt is decremented by 1; when cnt equals the depth of the read-side synchronous clock domain FIFO module 64 (designed as 4 in this embodiment), a full signal is output to the internal read request generation module 66, and the internal read request is turned off. This module ensures that the total number of internal read requests that have been issued but not yet read and released by the outside will not exceed the depth of the read-side synchronous clock domain FIFO module 64, thereby avoiding overflow of the read-side synchronous clock domain FIFO module 64.

[0224] (7) Read-side synchronous clock domain FIFO module 64: pure single clock domain FIFO, with the same structure as ordinary synchronous FIFO; the input is synchronous FIFO write enable / write data, and the output is read data; the user read enable drives its read-side logic, and at the same time generates a synchronous FIFO release signal to be sent back to the synchronous FIFO write status management module 65.

[0225] (8) Summary of the overall workflow:

[0226] During normal operation: The user continuously writes data from the write side → the write-side Gray code pointer management module 20 / read-side status judgment module 53 / data storage array 61 completes the asynchronous FIFO write storage; the read side initiates an internal read request when it is not empty and there is an empty slot downstream → the read-side Gray code pointer management module 30 advances the read address → the address selector 62 selects the current data → the fifth metastability elimination synchronization module 63 eliminates metastability through two-stage synchronization → the read-side synchronous clock domain FIFO module 64 completes the final alignment and buffering within the read clock domain → the read data is output externally.

[0227] When an asynchronous reset occurs: a single-ended asynchronous reset is synthesized into a quasi-logical reset by the first metastability elimination synchronization module 11, the second metastability elimination synchronization module 12, the first signal extension module 16, the second signal extension module 17, and the first logic module 13 → synchronization at both ends by the third metastability elimination synchronization module 14 / the fourth metastability elimination synchronization module 15 → the write-side Gray code pointer management module 20 / the read-side Gray code pointer management module 30 / the write-side state judgment module 43 / the read-side state judgment module 53 synchronously set to zero in the clock domains at both ends → the third signal extension module 41, the second logic module 42, the fourth signal extension module 51, and the third logic module 52 externally force full / empty and shield external read / write → after extending for a sufficient period, gradually release → the system smoothly recovers from a consistent state where both pointers are 0.

[0228] Throughout the entire process, all external signals (read data, empty signal, full state) are generated through two levels of synchronous flip-flops or pure clock domain logic. Physically, there is no metastable external propagation path, thus achieving all the objectives of this invention.

[0229] This invention provides a fully decoupled independent reset mechanism—the read and write clock domains can perform asynchronous reset and synchronous release completely independently: the signals output from the write-side asynchronous reset terminal 200 and the read-side asynchronous reset terminal 300 are respectively connected to an independent two-stage metastability elimination synchronization module (two-stage synchronization avoids metastability), and then each is widened by a signal extension module. If the signal output from a certain reset terminal is a reset signal, the signals output from the write-side asynchronous reset terminal 200 and the read-side asynchronous reset terminal 300 are combined into a quasi-logical reset signal through an AND gate (or an OR gate if the reset is active high). The quasi-logical reset signal is then passed through two independent two-stage metastability elimination synchronization modules, which synchronize the quasi-logical reset signal across the write-side clock and the read-side clock, respectively generating a logical reset acting on the D terminal of register in the write-side clock domain and the read-side clock domain.

[0230] The logic reset signal is ultimately connected to all registers affected by the reset in the write-side Gray code pointer management module 20, the read-side Gray code pointer management module 30, the write-side forced takeover module 40, and the read-side forced takeover module 50, thus equivalently transforming "reset at any one end" into "synchronized and ordered logic reset at both ends of the clock domain".

[0231] In this process, the signal transmission timing is as follows: single-ended asynchronous reset pull-up → the signals output by the write-side asynchronous reset terminal 200 and the read-side asynchronous reset terminal 300 are each synchronized to a stable level in their respective clock domains at two levels → the 3a / b or 3b / a period is extended to ensure that the other end's clock can be sampled → a quasi-logic reset signal is synthesized through an AND gate → the two-level synchronization is applied to both end clocks → the D terminals of each register are simultaneously driven to zero in both end clock domains. There are no cross-clock signals in the entire link that have not undergone two-level synchronization; therefore, the read and write clock domains can independently accept asynchronous resets at any time and release synchronously and safely according to their respective clock cycles, without requiring any reset handshakes or sequence constraints from the upper layer.

[0232] This invention also provides a hardware-level metastability avoidance mechanism—fundamentally cutting off the physical path of metastability caused by unilateral pointer mutation: Figure 10-13 After all the address data of the data storage array 61 is output by the address selector 62, it does not directly enter the downstream user interface. Instead, it first passes through the fifth metastability elimination synchronization module 63 (two-stage synchronization elimination metastability) located at the output of the address selector 62, then is written into the read-side synchronous clock domain FIFO module 64 (depth of 4), and finally outputs as read data.

[0233] The timing-level argument is as follows: For example, when an independent asynchronous reset occurs on the write side, the write-side Gray code pointer is set to zero by the logic reset mechanism of this invention. The write address changes at a certain time, and all address data output by the data storage array 61 also changes accordingly. Therefore, the output of the address selector 62 may fall precisely at the edge of the read-side clock sampling window. The first-stage flip-flop in the fifth metastability elimination synchronization module 63 has a probability of entering a metastable state. However, because the fifth metastability elimination synchronization module 63 adds a second-stage flip-flop, the metastable state of the first stage has sufficient time to converge to a stable value within a complete read-side clock cycle. The second-stage flip-flop outputs a stable logic level. In other words, any disturbance on the write side caused by a reset or pointer mutation is absorbed by these two stages of flip-flops within the read clock domain. Physically, it cannot bypass these two stages of flip-flops to enter the user interface, thus cutting off the physical path of metastability caused by a single-side pointer mutation.

[0234] Even in severe scenarios, such as a partial power outage on the read end, the reset fusion module 10 synchronizes the read end reset event to the write end, and the write end Gray code pointer is also cleared synchronously. The empty / full determination of the asynchronous FIFO body and the external full / empty status signals are forcibly shielded by the write-side forced takeover module 40 and the read-side forced takeover module 50. The write end bus will not be deadlocked due to back pressure. After the read end is powered on, the system can continue to resume operation from a consistent state, so that even if one end is abnormal, the other end can still maintain state convergence.

[0235] The data transmission circuit 100 provided in this embodiment of the invention also features low invasiveness and low latency. In addition to the aforementioned reset fusion module 10, various synchronization modules, and read-side synchronous clock domain FIFO module 64, the traditional asynchronous FIFO's write pointer, read pointer, and empty / full determination structures are completely retained without introducing any complex handshake protocols. The user interface remains the standard write enable / write data / full state and read enable / read data / empty signal, thus being completely transparent to the upper-layer RTL and maintaining the original high throughput and low latency characteristics of the FIFO.

[0236] In summary, the complete structure of the data transmission circuit 100 provided in this embodiment of the invention is a data transmission circuit based on an asynchronous FIFO structure and peripheral auxiliary modules. It is a highly reliable digital circuit system that can effectively prevent metastability propagation caused by unilateral partial asynchronous reset when completely independent asynchronous reset signals are used in the read clock domain and write clock domain. It is a data interaction transmission circuit that solves the problem of metastability generated in different asynchronous reset domains. The technical effects achieved are as follows:

[0237] 1. Significantly improves system-level stability – capable of resolving the issue of the entire chip bus deadlock caused by abnormal resets of local modules:

[0238] Derivation: In a traditional asynchronous FIFO, if the read chip is partially powered on or off, causing the read end to be independently reset while the write end continues to write, a misalignment will occur where the write pointer increments normally while the read pointer is cleared to zero. Soon the FIFO will be determined to be full, the write end will be blocked, and then the upstream module and even the entire chip bus will be blocked through the bus back pressure signal.

[0239] In this embodiment of the invention, the reset fusion module 10 (first metastability elimination synchronization module 11, second metastability elimination synchronization module 12, first signal extension module 16, second signal extension module 17, first logic module 13, third metastability elimination synchronization module 14, and fourth metastability elimination synchronization module 15) generates a logic reset at the D end of the write-side Gray code pointer management module 20 / read-side Gray code pointer management module 30. When an asynchronous reset occurs at either end (e.g., the read end), the reset event at that end (read end) can be reliably synchronized to the clock domain of the other end (write end), so that the Gray code pointer at the other end (write end) is also synchronously cleared to zero, and the FIFO body re-enters a consistent state where both pointers are 0. At the same time, the third signal extension module 41, the second logic module 42, the fourth signal extension module 51, and the third logic module 52 force full / empty signals externally within this window, so that the external bus is naturally blocked rather than deadlocked during this period—the external host sees that the FIFO is temporarily busy and naturally waits. Reading and writing can be resumed after the reset is released and the shielding is removed. Even in the worst-case scenario where the read end is powered off for an extended period, the write operation on the write end will only be politely blocked by a full signal, rather than freezing the bus due to pointer misalignment or state deadlock. This architecture is particularly suitable for modern chips with dynamic power management (partial power-on / off) and heterogeneous multi-core architectures.

[0240] 2. Reduced physical implementation risks – simplified SDC constraints:

[0241] Derivation: Reset processing of traditional cross-clock domain FIFOs typically faces two types of constraint challenges:

[0242] (a) The path from the cross-clock reset signal generated by asynchronous set and synchronous release reset (asynchronous assert, synchronous de-assert) to the target register rst must be declared in SDC for each pseudo path (set_false_path) or maximum delay constraint (set_max_delay). The number of paths increases linearly with the number of FIFOs and is easy to miss.

[0243] (b) The reset tree itself requires the design of complex handshake protocols and hierarchical reset trees for cross-clock domains, which increases the difficulty of back-end synthesis and timing convergence.

[0244] The logic reset generated by this invention is applied to the D terminal of the register instead of the rst terminal. The cross-clock synchronization link is uniformly converged into a standard two-stage synchronous flip-flop structure of the third metastability elimination synchronization module 14 / fourth metastability elimination synchronization module 15, which is exactly the same as the constraint writing of ordinary CDC data synchronization on SDC. At the same time, the rst terminal of the register itself is reserved for the chip top-level hard asynchronous reset, without introducing any new cross-clock domain rst terminal path.

[0245] The resulting simplification is as follows:

[0246] (i) No cross-clock domain rst terminal path needs to be constrained separately. All cross-clock resets are essentially degenerated into standard CDC synchronization paths at the third metastability elimination synchronization module 14 / fourth metastability elimination synchronization module 15. The constraint writing is the same as that of ordinary CDC.

[0247] (ii) Back-end physical engineers no longer need to design a special reset tree or handshake protocol for the reset logic introduced in this invention; they only need to retain the original top-level reset tree of the chip.

[0248] (iii) The static timing tool can automatically identify the two-level synchronization structure at the third metastability elimination synchronization module 14 / fourth metastability elimination synchronization module 15, and complete the unified constraint of false path (false_path) / maximum delay (max_delay), making the overall SDC file structure simpler and easier to maintain.

[0249] 3. Excellent module reusability:

[0250] The circuit still presents itself externally as a standard write enable / write data / full state and read enable / read data / empty signal interface. It can be used as a general IP module that can be seamlessly replaced and in-situ compatible (i.e., a standardized hardware logic unit that is pre-designed, fully simulated and verified, has complete independent functions, and can be reused repeatedly) to directly replace the traditional asynchronous FIFO in various types of designs that have reset risks, without modifying the upper-level logic.

[0251] In one embodiment of the present invention, a chip is provided, on which a data transmission circuit as provided in the above embodiment is disposed.

[0252] The structure, working principle, and technical effects of the data transmission circuit on this chip are the same as those in the above embodiments, and therefore will not be repeated here.

[0253] In some embodiments, the chip may be, but is not limited to, one of a PCIe switch chip, an Ethernet switch chip, and a UALink chip.

[0254] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0255] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A data transfer circuit configured with an asynchronous FIFO, characterized in that, The data transmission circuit includes: A reset fusion module includes a first reset signal input terminal, a second reset signal input terminal, and a reset signal output terminal. The first reset signal input terminal of the reset fusion module is connected to a write-side asynchronous reset terminal, and the second reset signal input terminal of the reset fusion module is connected to a read-side asynchronous reset terminal. The reset fusion module is configured to output a reset signal in response to either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal, and to output a quasi-logic reset signal through the reset signal output terminal of the reset fusion module. A write-side Gray code pointer management module is provided, wherein the signal input terminal of the write-side Gray code pointer management module is connected to the reset signal output terminal of the reset fusion module; the write-side Gray code pointer management module is configured to set the write-side Gray code pointer of the asynchronous FIFO to zero when the quasi-logic reset signal is received. A read-side Gray code pointer management module is provided, wherein the signal input terminal of the read-side Gray code pointer management module is connected to the reset signal output terminal of the reset fusion module; the read-side Gray code pointer management module is configured to set the read-side Gray code pointer of the asynchronous FIFO to zero when the quasi-logic reset signal is received.

2. The data transmission circuit of claim 1, wherein, The reset fusion module includes a first metastable state elimination synchronization module, a second metastable state elimination synchronization module, a first logic module, a third metastable state elimination synchronization module, and a fourth metastable state elimination synchronization module. The reset signal output terminal of the reset fusion module includes a first reset signal output terminal and a second reset signal output terminal. The signal input terminal of the first metastability elimination synchronization module is connected to the write-side asynchronous reset terminal as the first reset signal input terminal of the reset fusion module, and the signal output terminal of the first metastability elimination synchronization module is connected to the first signal input terminal of the first logic module through the first signal extension module. The signal input terminal of the second metastability elimination synchronization module is connected to the read-side asynchronous reset terminal as the second reset signal input terminal of the reset fusion module, and the signal output terminal of the second metastability elimination synchronization module is connected to the second signal input terminal of the first logic module through the second signal extension module. The first logic module is configured to output a reset signal in response to either the write-side asynchronous reset terminal or the read-side asynchronous reset terminal, and to output a quasi-logic reset signal through the signal output terminal of the first logic module; The signal input terminal of the third metastability elimination synchronization module is connected to the signal output terminal of the first logic module, and the signal output terminal of the third metastability elimination synchronization module is connected to the signal input terminal of the write-side Gray code pointer management module as the first reset signal output terminal of the reset fusion module. The signal input terminal of the fourth metastability elimination synchronization module is connected to the signal output terminal of the first logic module, and the signal output terminal of the fourth metastability elimination synchronization module is connected to the signal input terminal of the read-side Gray code pointer management module as the second reset signal output terminal of the reset fusion module.

3. The data transmission circuit of claim 1, wherein, The write-side Gray code pointer management module includes a first signal selection module. The selection control terminal of the first signal selection module serves as the signal input terminal of the write-side Gray code pointer management module and is connected to the reset signal output terminal of the reset fusion module. One signal input terminal of the first signal selection module is connected to the write-side Gray code counter of the asynchronous FIFO, and the output terminal of the first signal selection module is connected to the data input terminal of the write-side Gray code pointer register of the asynchronous FIFO. The first signal selection module is configured to output a first logic level through its output terminal when the quasi-logic reset signal is received, and to output the pointer generated by the write-side Gray code counter through its output terminal when the quasi-logic reset signal is not received. When the first logic level is input to the data input terminal of the write-side Gray code pointer register, the write-side Gray code pointer of the asynchronous FIFO is set to zero; when the pointer generated by the write-side Gray code counter is input to the data input terminal of the write-side Gray code pointer register, the write-side Gray code pointer of the asynchronous FIFO takes the pointer generated by the write-side Gray code counter. The read-side Gray code pointer management module includes a second signal selection module. The selection control terminal of the second signal selection module serves as the signal input terminal of the read-side Gray code pointer management module and is connected to the reset signal output terminal of the reset fusion module. One signal input terminal of the second signal selection module is connected to the read-side Gray code counter of the asynchronous FIFO, and the output terminal of the second signal selection module is connected to the data input terminal of the read-side Gray code pointer register of the asynchronous FIFO. The second signal selection module is configured to output a second logic level through its output terminal when the quasi-logic reset signal is received, and to output the pointer generated by the read-side Gray code counter through its output terminal when the quasi-logic reset signal is not received. When the second logic level is input to the data input terminal of the read-side Gray code pointer register, the read-side Gray code pointer of the asynchronous FIFO is set to zero; When the data input terminal of the read-side Gray code pointer register is input with the pointer generated by the read-side Gray code counter, the read-side Gray code pointer of the asynchronous FIFO takes the pointer generated by the read-side Gray code counter.

4. The data transmission circuit of claim 1, wherein, The data transmission circuit further includes: A write-side forced takeover module is provided, wherein the signal input terminal of the write-side forced takeover module is connected to the reset signal output terminal of the reset fusion module, and the write-side forced takeover module is connected to the full state indicator terminal of the asynchronous FIFO. The write-side forced takeover module is configured to enable the full state indicator terminal when the quasi-logic reset signal is received. A read-side forced takeover module is provided, wherein the signal input terminal of the read-side forced takeover module is connected to the reset signal output terminal of the reset fusion module, and the read-side forced takeover module is connected to the empty signal indicator terminal of the asynchronous FIFO. The read-side forced takeover module is configured to enable the empty signal indicator terminal when the quasi-logic reset signal is received.

5. The data transmission circuit of claim 4, wherein, The write-side forced takeover module includes a third signal extension module and a second logic module. The signal input terminal of the third signal extension module is connected to the reset signal output terminal of the reset fusion module, and the signal output terminal of the third signal extension module is connected to the first signal input terminal of the second logic module. The second signal input terminal of the second logic module is connected to the signal output terminal of the write-side state judgment module, and the output terminal of the second logic module is connected to the full state indicator terminal of the asynchronous FIFO. The write-side state judgment module is connected to the write-side Gray code pointer management module. The write-side state determination module is used to determine whether the write side of the asynchronous FIFO is full. When it is determined that the write side of the asynchronous FIFO is full, the write-side state determination module outputs a full flag signal through the signal output terminal of the write-side state determination module. The second logic module is configured to enable the full state indicator terminal when it receives the quasi-logic reset signal or the full flag signal. The read-side forced takeover module includes a fourth signal extension module and a third logic module. The signal input terminal of the fourth signal extension module is connected to the reset signal output terminal of the reset fusion module, serving as the signal input terminal of the read-side forced takeover module. The signal output terminal of the fourth signal extension module is connected to the first signal input terminal of the third logic module. The second signal input terminal of the third logic module is connected to the signal output terminal of the read-side state judgment module. The output terminal of the third logic module is connected to the empty signal indicator terminal of the asynchronous FIFO. The read-side state judgment module is connected to the read-side Gray code pointer management module. The read-side state determination module is used to determine whether the read side of the asynchronous FIFO is empty. When it is determined that the read side of the asynchronous FIFO is empty, the read-side state determination module outputs an empty flag signal through the signal output terminal of the read-side state determination module. The third logic module is configured to enable the empty signal indicator terminal when it receives the quasi-logic reset signal or the empty flag signal.

6. The data transmission circuit of claim 5, wherein, The input terminal of the write-side state determination module is connected to the reset signal output terminal of the reset fusion module. The write-side state determination module is configured to output a full flag signal through the signal output terminal of the write-side state determination module when it receives the quasi-logic reset signal. The input terminal of the read-side state determination module is connected to the reset signal output terminal of the reset fusion module. The read-side state determination module is configured to output an empty flag signal through the signal output terminal of the read-side state determination module when it receives the quasi-logic reset signal. And / or, The third signal extension module can extend the input signal by 3b / a cycles, and the fourth signal extension module can extend the input signal by 3a / b cycles, where a is the read-side frequency of the asynchronous FIFO, b is the write-side frequency of the asynchronous FIFO; and / or, Both the second and third logic modules are OR gates.

7. The data transmission circuit of claim 1, wherein, The data transmission circuit further includes: A data access module is provided, wherein the address input terminal of the data access module is connected to the address output terminal of the write-side Gray code pointer management module, and the selection control terminal of the data access module is connected to the address output terminal of the read-side Gray code pointer management module. The data access module is configured to store the write data of the asynchronous FIFO according to the write address output by the address output terminal of the write-side Gray code pointer management module, and to output the read data of the asynchronous FIFO according to the read address output by the address output terminal of the read-side Gray code pointer management module.

8. The data transmission circuit of claim 7, wherein, The data access module includes: The data storage array has its address input terminal connected to the address output terminal of the write-side Gray code pointer management module, which serves as the address input terminal of the data access module. The write data input terminal of the data storage array is connected to the write data terminal of the asynchronous FIFO, and the write enable input terminal of the data storage array is connected to the write enable terminal of the asynchronous FIFO. An address selector, wherein the data input terminal of the address selector is connected to the data output terminal of the data storage array, and the selection control terminal of the address selector is connected to the address output terminal of the read-side Gray code pointer management module as the selection control terminal of the data access module; A fifth metastability elimination and synchronization module, wherein the data input terminal of the fifth metastability elimination and synchronization module is connected to the data output terminal of the address selector; A read-side synchronous clock domain FIFO module is provided, wherein the write data input terminal of the read-side synchronous clock domain FIFO module is connected to the data output terminal of the fifth metastability elimination synchronization module, the data output terminal of the read-side synchronous clock domain FIFO module is connected to the read data terminal of the asynchronous FIFO, and the read enable input terminal of the read-side synchronous clock domain FIFO module is connected to the read enable terminal of the asynchronous FIFO.

9. The data transmission circuit of claim 8, wherein, The data transmission circuit further includes: A synchronous FIFO write status management module is provided, wherein the data input terminal of the synchronous FIFO write status management module is connected to the pointer output terminal of the read-side synchronous clock domain FIFO module; the synchronous FIFO write status management module is used to determine whether the read-side synchronous clock domain FIFO module is in a full state; when it is determined that the read-side synchronous clock domain FIFO module is not in a full state, the synchronous FIFO write status management module outputs a non-full signal. An internal read request generation module is connected to the synchronous FIFO write state management module. One signal input terminal of the internal read request generation module is connected to the signal output terminal of the read-side state judgment module. The read-side state judgment module is connected to the read-side Gray code pointer management module. The read-side state judgment module is used to determine whether the read side of the asynchronous FIFO is empty. When the read side is determined to be non-empty, the read-side state judgment module outputs a non-empty signal through its signal output terminal. The signal output terminal of the internal read request generation module is connected to the write enable input terminal of the read-side synchronous clock domain FIFO module through a signal delay module. The signal output terminal of the internal read request generation module is also connected to the read-side Gray code pointer management module. The internal read request generation module is configured to send internal read request signals to the read-side synchronous clock domain FIFO module and the read-side Gray code pointer management module respectively when it receives the non-full signal and the non-empty signal, thereby enabling the write enable input of the read-side synchronous clock domain FIFO module and using the internal read request signal as the increment condition of the read-side Gray code pointer in the read-side Gray code pointer management module, thereby incrementing the read-side Gray code pointer.

10. A chip, characterized in that, The chip is provided with a data transmission circuit as described in any one of claims 1 to 9.

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