A wafer-level chip, board, and electronic device

Abstract

This invention provides a wafer-level chip, board, and electronic device. The wafer-level chip includes: a first computing wafer and a first switching interconnect wafer, which are stacked together. The first computing wafer includes multiple first region blocks, each first region block including K groups of first computing units, and each group of first computing units including M×N first computing cores. The M×N first computing cores in each group of first computing units are connected via a 2D mesh network. The first computing cores of adjacent groups of first computing units correspond one-to-one. The corresponding first computing cores in adjacent groups of first computing units are connected via the first switching interconnect wafer. The first switching interconnect wafer is used to realize the communication connection between the various first region blocks. The wafer-level chip, board, and electronic device provided by this invention improve communication efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a wafer-level chip, circuit board, and electronic device. Background Technology

[0002] As AI models continue to grow in scale and computational complexity increases dramatically, traditional chip architectures are approaching their physical limits in terms of performance and energy efficiency.

[0003] To overcome this bottleneck, the industry has begun exploring a new computing paradigm with larger scale and tighter integration—Wafer-Scale AI Compute. This technology integrates millions of computing cores and massive on-chip storage onto a single silicon wafer, enabling efficient data flow within the wafer and significantly reducing the overhead of cross-chip communication. In existing technologies, wafer-scale AI chips mostly employ a 2D mesh interconnect topology. Due to significant differences in the physical distance between different computing cores, the communication latency between distant computing cores is several orders of magnitude higher than that between adjacent cores, resulting in unsatisfactory performance in typical communication modes such as All-Reduce and All-to-All. Therefore, optimizing the structure of wafer-scale chips to improve communication efficiency has become a crucial issue that urgently needs to be addressed in this field. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of the present invention provide a wafer-level chip, board, and electronic device that can at least partially solve the problems existing in the prior art.

[0005] In a first aspect, the present invention provides a wafer-level chip, comprising a first computing wafer and a first switching interconnect wafer, wherein: The first computing wafer and the first switching interconnect wafer are stacked together; The first computing wafer includes multiple first region blocks, each first region block includes K groups of first computing units, and each group of first computing units includes M×N first computing cores; K is an integer greater than or equal to 2, M and N are both positive integers, and at least one of M and N is greater than or equal to 2; Each group of first computing units includes M×N first computing cores that are connected by a 2D Mesh network; the first computing cores of two adjacent groups of first computing units in the K groups of first computing units correspond one-to-one; the corresponding first computing cores of two adjacent groups of first computing units are connected by the first switching interconnect wafer communication. The first switching interconnect wafer is used to realize communication connections between the various first region blocks.

[0006] Furthermore, the first switching interconnect wafer includes three switch groups: the first switch group includes K×N first switches, the second switch group includes K×M second switches, and the third switch group includes M×N third switches. Each first region block has three interconnection interfaces in three different directions. There are two interconnection interfaces in the first direction, each including K×N first communication interfaces. There are two interconnection interfaces in the second direction, each including K×M second communication interfaces. There are two interconnection interfaces in the third direction, each including M×N third communication interfaces. The first switch group corresponds to the first direction interconnection interface of each first area block, and each first switch is communicatively connected to the corresponding first communication interface; the second switch group corresponds to the second direction interconnection interface of each first area block, and each second switch is communicatively connected to the corresponding second communication interface; the third switch group corresponds to the third direction interconnection interface of each first area block, and each third switch is communicatively connected to the corresponding third communication interface; the switches within each switch group are communicatively connected.

[0007] Furthermore, M, N, and K are equal, and the switches in the three switch groups are arranged in M×N switching interconnection areas, with three switches in each switching interconnection area, and the three switches belong to different switch groups.

[0008] Furthermore, each of the first computing cores in the first computing unit has three interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, and two interconnect interfaces in the third direction. The first computing unit includes M×N first computing cores that are connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core is connected to its respective first computing unit via two third-party interconnect interfaces.

[0009] Furthermore, the wafer-level chip provided in this embodiment of the invention further includes a second switching interconnect wafer, wherein the second switching interconnect wafer, the first computing wafer, and the first switching interconnect wafer are stacked together, and the first computing wafer is disposed between the first switching interconnect wafer and the second switching interconnect wafer; Accordingly, the first computing cores of two adjacent groups of first computing units in each first region block are connected via the second switching interconnect wafer communication.

[0010] Furthermore, the wafer-level chip provided in this embodiment of the invention also includes a second computing wafer, wherein the second computing wafer, the first switching interconnect wafer, and the first computing wafer are stacked together, and the first switching interconnect wafer is disposed between the first computing wafer and the second computing wafer; The second computing wafer includes multiple second region blocks, each second region block includes K groups of second computing units, and each group of second computing units includes M×N second computing cores; Each group of second computing units includes M×N second computing cores connected by a 2D Mesh network; the second computing cores of two adjacent groups of second computing units in U groups correspond one-to-one; each corresponding second computing core in two adjacent groups of second computing units is connected by the first switching interconnect wafer communication. The first switching interconnect wafer is also used to realize communication connections between the various second region blocks.

[0011] Furthermore, the wafer-level chip provided in this embodiment of the invention also includes a third switching interconnect wafer, wherein the third switching interconnect wafer, the first computing wafer, and the first switching interconnect wafer are stacked together, and the first computing wafer is disposed between the first switching interconnect wafer and the third switching interconnect wafer; Accordingly, the first computing wafer includes multiple four-dimensional modules, each four-dimensional module including multiple first region blocks; the first computing cores of two adjacent first region blocks in the multiple four-dimensional modules correspond one-to-one; the corresponding first computing cores of two adjacent first region blocks are connected through the three-dimensional communication of the third switching interconnect wafer. The third switching interconnect wafer is also used to realize four-dimensional communication connections between various four-dimensional modules.

[0012] Furthermore, the third switching interconnect wafer includes a fourth switch group, which includes K×M×N fourth switches; Each four-dimensional module has a fourth-direction interconnection interface, and there are K×M×N fourth communication interfaces in the fourth direction. The fourth switch group corresponds to the interconnection interface in the fourth direction and includes K×M×N fourth switches. Each fourth switch is communicatively connected to the corresponding fourth communication interface, and all fourth switches in the fourth switch group are communicatively connected.

[0013] Furthermore, each of the first computing cores in the first computing unit has four interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, two interconnect interfaces in the third direction, and two interconnect interfaces in the fourth direction. The first computing unit includes M×N first computing cores that are connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core is connected to the two third-party interconnect interfaces of its respective first computing unit through two third-party interconnect interfaces; Each first computing core is connected to its respective first computing unit via two interconnect interfaces in the fourth direction.

[0014] Furthermore, each first region block corresponds to one exposure field, or multiple first region blocks correspond to one exposure field.

[0015] In a second aspect, the present invention provides a board including at least one wafer-level chip as described in any of the above embodiments.

[0016] Thirdly, the present invention provides an electronic device including at least one board as described in the above embodiments.

[0017] The wafer-level chip, board, and electronic device provided in this embodiment of the invention include a first computing wafer and a first switching interconnect wafer, wherein the first computing wafer and the first switching interconnect wafer are stacked together; the first computing wafer includes a plurality of first region blocks, each first region block includes K groups of first computing units, each group of first computing units includes M×N first computing cores; K is an integer greater than or equal to 2, M and N are both positive integers, and at least M and N are greater than or equal to 2; the M×N first computing cores included in each group of first computing units are connected by a 2D Mesh network; the first computing cores of two adjacent groups of first computing units in the K groups of first computing units correspond one-to-one; each first computing core of two adjacent groups of first computing units is connected by communication through the first switching interconnect wafer; the first switching interconnect wafer is used to realize the communication connection between each first region block, and the wafer-level chip adopts a 3D Torus interconnect topology, which can effectively alleviate the communication bottleneck caused by the physical distance difference of 2D Mesh and improve communication efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a wafer-level chip provided in an embodiment of the present invention.

[0019] Figure 2This is a schematic diagram of the planar structure of the first computing wafer provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the planar structure of the first region block provided in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the interconnects of the first computing core provided in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of third-party interconnection within a first region block provided in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure of a switch group provided in an embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of the interconnection interface of the first region block provided in an embodiment of the present invention.

[0025] Figure 8 This is a schematic diagram of the structure of a switch group provided in another embodiment of the present invention.

[0026] Figure 9 This is a schematic diagram of the connection relationship between a switch and a communication interface provided in an embodiment of the present invention.

[0027] Figure 10 This is a schematic diagram of the interconnection interface of the first computing unit provided in an embodiment of the present invention.

[0028] Figure 11 This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention.

[0029] Figure 12 This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention.

[0030] Figure 13 This is a schematic diagram of the planar structure of a second computing wafer provided in an embodiment of the present invention.

[0031] Figure 14 This is a schematic diagram of the planar structure of the second region block provided in an embodiment of the present invention.

[0032] Figure 15 This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention.

[0033] Figure 16 This is a schematic diagram of the planar structure of a four-dimensional module provided in an embodiment of the present invention.

[0034] Figure 17 This is a schematic diagram of the interconnects of the first computing core provided in another embodiment of the present invention.

[0035] Figure 18A This is a schematic diagram of the planar structure of a four-dimensional module provided in another embodiment of the present invention.

[0036] Figure 18B This is a schematic diagram of the fourth direction interconnection within a four-dimensional module provided in an embodiment of the present invention.

[0037] Figure 19 This is a schematic diagram of the structure of a third switching interconnect wafer provided in an embodiment of the present invention.

[0038] Figure 20 This is a schematic diagram of the interconnection interface of the first computing unit provided in another embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been agreed upon by the customer.

[0040] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0041] This application breaks through the limitations of traditional 2D Mesh planar interconnection and explores new solutions such as 3D interconnection topology and dynamic reconfigurable interconnection to achieve deep synergy between topology and communication mode. It not only ensures low-latency direct connection between cores, but also achieves wafer-level communication load balancing. Ultimately, it enables the massive computing resources of wafer-level chips to form efficient synergy and fully release their performance potential in large-scale AI training and inference scenarios.

[0042] This application integrates the computing wafer and the interconnect wafer by 3D stacking dedicated communication interconnect wafers on a computing wafer and utilizing hybrid bonding technology. This allows the planar computing cores on the computing wafer to be reconstructed into nodes with 3D Torus interconnect characteristics. The mesh interconnects of each computing core in the first direction (X-axis) and the second direction (Y-axis) are implemented inside the computing wafer, while the mesh interconnects in the third direction (Z-axis) and the Torus ring connections in the X, Y, and Z dimensions are all completed on the interconnect wafer.

[0043] To further enhance the modularity and scalability of the wafer-level chip proposed in this application, the entire computing wafer is divided into multiple regional blocks. The computing core within each regional block is logically reconstructed into a cube unit using the aforementioned 3D Torus interconnect method. All cube units on the entire computing wafer are then interconnected via switching interconnect wafers, thereby constructing a larger-scale 3D Torus cube array. All switches used for communication between regional blocks are integrated into the switching interconnect wafer, achieving an efficient, compact, and scalable wafer-level 3D Torus interconnect architecture.

[0044] The technical solution of this application ingeniously combines wafer-level 3D integration, 3D Torus network topology and modular architecture design, providing a promising technical path for breaking through the bottleneck of traditional 2D Mesh interconnection and realizing wafer-level high-performance computing.

[0045] Figure 1 This is a schematic diagram of the structure of a wafer-level chip provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the planar structure of a first computing wafer provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the planar structure of the first region block provided in an embodiment of the present invention, as shown below. Figure 1 , Figure 2 and Figure 3 As shown, the wafer-level chip provided in this embodiment of the invention includes a first computing wafer 1 and a first switching interconnect wafer 2, wherein: The first computing wafer 1 and the first switching interconnect wafer 2 are stacked together; The first computing wafer 1 includes multiple first region blocks 101, each first region block 101 includes K groups of first computing units 101-1, and each group of first computing units 101-1 includes M×N first computing cores (Processing Elements, abbreviated as PE) 101-1-1; K is an integer greater than or equal to 2, M and N are both positive integers, and at least one of M and N is greater than or equal to 2; Each group of first computing units 101-1 includes M×N first computing cores 101-1-1 connected by a 2D Mesh network; the first computing cores 101-1-1 of two adjacent groups of first computing units 101-1 correspond one-to-one; the corresponding first computing cores 101-1-1 of two adjacent groups of first computing units 101-1 are connected by a first switching interconnect wafer 2. The first switching interconnect wafer 2 is used to realize the communication connection between each first region block 101.

[0046] Specifically, the first computing wafer 1 and the first switching interconnect wafer 2 are stacked, and the stacking of the first computing wafer 1 and the first switching interconnect wafer 2 can be achieved using hybrid bonding technology. The first computing wafer 1 is the carrier of computing cores 101-1-1, which can integrate a large number of computing cores and enable communication between each computing core 101-1-1 in the first and second directions. The first switching interconnect wafer 2 enables communication between each computing core 101-1-1 in the third direction and communication between each first region block 101. The communication between computing core 101-1-1 and its two directly adjacent left and right computing cores in the 2D Mesh network is the first direction communication; the communication between computing core 101-1-1 and its two directly adjacent upper and lower computing cores in the 2D Mesh network is the second direction communication; the communication between corresponding first computing cores 101-1-1 in two adjacent groups of first computing units 101-1 is the third direction communication.

[0047] The dimensions of the first computing wafer 1 and the first switching interconnect wafer 2 can be the same or different, depending on actual needs, and this embodiment of the invention does not impose any limitation. The first computing wafer 1 can be 12 inches, 8 inches, or 6 inches, etc., selected according to actual needs, and this embodiment of the invention does not impose any limitation. The dimensions of the first switching interconnect wafer 2 can be 12 inches, 8 inches, or 6 inches, etc., and this embodiment of the invention does not impose any limitation.

[0048] In one embodiment, such as Figure 1 As shown, the first computing wafer 1 and the first switching interconnect wafer 2 are stacked together through multiple bonding points 0. The first switching interconnect wafer 2 is located on top of the first computing wafer 1. The number of bonding points is set according to actual needs, and is not limited in this embodiment of the invention. The spacing between the first computing wafer 1 and the first switching interconnect wafer 2 is at the nanometer level to reduce the communication delay between the first computing wafer 1 and the first switching interconnect wafer 2.

[0049] The first computing wafer 1 includes multiple first region blocks 101. Each first region block 101 includes K groups of first computing units 101-1. Each group of first computing units 101-1 includes M×N first computing cores 101-1-1. The M×N first computing cores 101-1-1 are arrayed on the first computing wafer 1 and connected by a 2D mesh network. Adjacent groups of first computing units 101-1 within the K groups of first computing units 101-1 need to be connected via a first switching interconnect wafer 2. The first computing cores 101-1-1 of adjacent groups of first computing units correspond one-to-one and are connected via communication. The interconnect lines of corresponding first computing cores 101-1-1 in adjacent groups of first computing units can be routed through through-silicon vias (TSVs) to the first switching interconnect wafer 2, and are connected via a redistribution layer on the first switching interconnect wafer 2. Communication connections between the various first region blocks 101 can be achieved through the first switching interconnect wafer 2. The number of first region blocks 101 is set according to actual needs, and is not limited in this embodiment of the invention. The values ​​of K, M, and N are set according to actual needs, and are not limited in this embodiment of the invention.

[0050] In one embodiment, such as Figure 3 As shown, the first region block 101 includes four groups of first computing units 101-1, which are arranged sequentially in a clockwise direction and are adjacent to each other in a clockwise direction. If we consider... Figure 3 The first calculation unit 101-1 in the upper left corner is the first group of first calculation units 101-1. Each group of first calculation units 101-1 is numbered sequentially in a clockwise direction, resulting in four groups of first calculation units 101-1: group 1, group 2, group 3, and group 4. The first calculation unit 101-1 in group 1 is adjacent to the first calculation units 101-1 in group 2 and group 4, respectively. Similarly, the first calculation unit 101-1 in group 3 is adjacent to the first calculation units 101-1 in group 2 and group 4, respectively.

[0051] In one embodiment, K=M=N=4, the first region block 101 includes 4 groups of first computing units 101-1, and each group of first computing units 101-1 includes 16 first computing cores 101-1-1.

[0052] In one embodiment, each first region block 101 may be provided with external interconnect interfaces, having two interconnect interfaces in a first direction, two interconnect interfaces in a second direction, and two interconnect interfaces in a third direction. A switch group for realizing interconnect communication between the various first region blocks 101 is provided on the first switching interconnect wafer 2, and the interconnect interface of each first region block 101 is connected to the corresponding switch group to realize communication between the various first region blocks 101.

[0053] In one embodiment, such as Figure 4 As shown, the first computing core 101-1-1 (i.e., PE) has interconnects in three different directions. Each group of first computing units 101-1 includes M×N first computing cores 101-1-1 connected via interconnects in the first direction (i.e., X-axis interconnects) and interconnects in the second direction (i.e., Y-axis interconnects) using a 2D mesh network. The corresponding first computing cores 101-1-1 of two adjacent groups of first computing units 101-1 in K groups of first computing units 101-1 are connected via their respective third-direction interconnects (i.e., Z-axis interconnects). Each third-direction interconnect may include a first interconnect segment on the first computing wafer, a second interconnect segment disposed in the hybrid bonding structure between the first computing wafer and the first exchange interconnect wafer, and a third interconnect segment disposed on the first exchange interconnect wafer (not shown in the figure). The first interconnect segment, the second interconnect segment, and the third interconnect segment are connected sequentially.

[0054] In one embodiment, the first region block 101 includes four groups of first computing units 101-1, and each group of first computing units 101-1 includes 16 first computing cores 101-1-1. For example... Figure 5 As shown, the four groups of 4×4 first computing units 101-1 of the first region block 101 are logically stacked into a 4×4×4 cube unit based on 3D Torus topology. For easy distinction, the four groups of first computing units are numbered as Group 0, Group 1, Group 2, and Group 3, respectively. Group 0, Group 1, Group 2, and Group 3 are grouped sequentially in a clockwise direction, and the four groups of first computing units are arranged in an array.

[0055] The communication connection of the corresponding PE in the first computing unit of the adjacent group can be abstracted as follows: Figure 5The Z-axis connection of the cube on the right side of the middle. By connecting the downward direction of the 4×4 first computing cores in the first computing unit of group 0 to the upward direction of the 4×4 first computing cores in the first computing unit of group 1, the downward direction of the 4×4 first computing cores in the first computing unit of group 1 to the upward direction of the 4×4 first computing cores in the first computing unit of group 2, and the downward direction of the 4×4 first computing cores in the first computing unit of group 2 to the upward direction of the 4×4 first computing cores in the first computing unit of group 3, the logical stacking of the first computing units of group 0, group 1, group 2, and group 3 is achieved, thus constructing a 4×4×4 cube unit. From top to bottom, the cube unit consists of the first computing units of group 0, group 1, group 2, and group 3.

[0056] The wafer-level chip provided in this embodiment of the invention includes a first computing wafer and a first switching interconnect wafer, wherein the first computing wafer and the first switching interconnect wafer are stacked together; the first computing wafer includes a plurality of first region blocks, each first region block includes K groups of first computing units, each group of first computing units includes M×N first computing cores; K is an integer greater than or equal to 2, M and N are both positive integers, and at least M and N are greater than or equal to 2; the M×N first computing cores included in each group of first computing units are connected by a 2D Mesh network; the first computing cores of two adjacent groups of first computing units in the K groups of first computing units correspond one-to-one; each first computing core of two adjacent groups of first computing units is connected by communication through the first switching interconnect wafer; the first switching interconnect wafer is used to realize the communication connection between each first region block, and the wafer-level chip adopts a 3D Torus interconnect topology, which can effectively alleviate the communication bottleneck caused by the physical distance difference of 2D Mesh and improve communication efficiency.

[0057] Figure 6 This is a schematic diagram of the structure of a switch group provided in an embodiment of the present invention, as shown below. Figure 6 As shown, three switch groups are arranged on the first switching interconnect wafer 2. The first switch group 201 includes K×N first switches 201-1, the second switch group 202 includes K×M second switches 202-1, and the third switch group 203 includes M×N third switches 203-1. Each first region block 101 has three interconnection interfaces in three different directions. There are two interconnection interfaces in the first direction, each including K×N first communication interfaces. There are two interconnection interfaces in the second direction, each including K×M second communication interfaces. There are two interconnection interfaces in the third direction, each including M×N third communication interfaces. The first switch group 201 corresponds to the first direction interconnection interface of each first area block 101, and each first switch 201-1 is communicatively connected to the corresponding first communication channel; the second switch group 202 corresponds to the second direction interconnection interface of each first area block 101, and each second switch 202-1 is communicatively connected to the corresponding second communication channel; the third switch group 203 corresponds to the third direction interconnection interface of each first area block 101, and each third switch 203-1 is communicatively connected to the corresponding third communication channel; the switches within each switch group are communicatively connected.

[0058] Specifically, three switch groups are disposed on the first interconnect wafer 2 to realize interconnection communication between the first area blocks 101. The first switch group 201 of the three switch groups is used to realize communication between the first area blocks 101 in a first direction; the second switch group 202 of the three switch groups is used to realize communication between the first area blocks 101 in a second direction; and the third switch group 203 of the three switch groups is used to realize communication between the first area blocks 101 in a third direction.

[0059] The first switch group 201 includes K×N first switches 201-1. The second switch group 202 includes K×M second switches 202-1. The third switch group 203 includes M×N third switches 203-1. The specific locations of each first switch 201-1, each second switch 202-1, and each third switch 203-1 on the first switching interconnect wafer 2 are configured according to actual needs, and are not limited in this embodiment of the invention.

[0060] Communication connections between switches within each switch group can be achieved by setting a redistribution layer on the first switching interconnect wafer 2. Communication connections are established between the first switches 201-1 within the first switch group 201, the second switches 202-1 within the second switch group 202, and the third switches 203-1 within the third switch group 203.

[0061] Each first region block 101 has three interconnection interfaces in three different directions. There are two interconnection interfaces in the first direction, each including K×N first communication interfaces. There are two interconnection interfaces in the second direction, each including K×M second communication interfaces. There are two interconnection interfaces in the third direction, each including M×N third communication interfaces.

[0062] In one embodiment, such as Figure 7As shown, for a first computing unit comprising K groups, each group of first computing units includes a first region block 101 with M×N first computing cores. The first region block 101 can be abstracted as a three-dimensional cuboid composed of K×M×N computing cores. The three-dimensional cuboid has 6 surfaces, each corresponding to an interconnect interface. The interconnect interfaces corresponding to the left and right surfaces are X-axis interconnect interfaces, i.e., interconnect interfaces in the first direction. The interconnect interface corresponding to the left surface is denoted as X-left, and the interconnect interface corresponding to the right surface is denoted as X-right. X-left includes K×N communication interfaces, and X-right includes K×N communication interfaces. The interconnect interfaces corresponding to the front and rear surfaces are Y-axis interconnect interfaces, i.e., interconnect interfaces in the second direction. The interconnect interface corresponding to the front surface is denoted as Y-front, and the interconnect interface corresponding to the rear surface is denoted as Y-rear. Y-front includes K×M communication interfaces, and Y-rear includes K×M communication interfaces. The interconnection interfaces corresponding to the upper and lower surfaces are Z-axis interconnection interfaces, i.e., third-direction interconnection interfaces. The interconnection interface corresponding to the upper surface is denoted as Z-upper, and the interconnection interface corresponding to the lower surface is denoted as Z-lower. Z-upper includes M×N communication interfaces, and Z-lower includes M×N communication interfaces.

[0063] The first switch group 201 corresponds to the first-direction interconnect interface of each first region block 101, and each first switch 201-1 is communicatively connected to the corresponding first communication interface; the second switch group 202 corresponds to the second-direction interconnect interface of each first region block 101, and each second switch 202-1 is communicatively connected to the corresponding second communication interface; the third switch group 203 corresponds to the third-direction interconnect interface of each first region block 101, and each third switch 203-1 is communicatively connected to the corresponding third communication interface. The communication connection between the switch and the corresponding communication interface can be achieved through wafer-level interconnection, such as hybrid bonding technology, redistribution layers, and through-silicon vias (TSVs). The specific connection structure is set according to actual needs, and this embodiment of the invention does not limit it.

[0064] This application realizes three-dimensional interconnection communication between the first area blocks through three switch groups, which can realize three-dimensional Torus loopback function, thereby connecting the various first area blocks on the entire first computing wafer into a complete 3D Torus topology network, and realizing the 3D Torus topology interconnection of the entire wafer-level chip on the first switching interconnect wafer.

[0065] Based on the above embodiments, M, N and K are equal, and the switches in the three switch groups are arranged in M×N switching interconnection areas, with three switches in each switching interconnection area, and the three switches belong to different switch groups.

[0066] In one embodiment, such as Figure 8As shown, M=N=K=4, and 16 switching interconnect regions 200 are set on the first switching interconnect wafer 2. The first switch group 201 includes 16 first switches 201-1, labeled X-SWITCH0, X-SWITCH1, X-SWITCH2...X-SWITCH15 respectively; the second switch group 202 includes 16 second switches 202-1, labeled Y-SWITCH0, Y-SWITCH1, Y-SWITCH2...Y-SWITCH15 respectively; the third switch group 203 includes 16 third switches 203-1, labeled Z-SWITCH0, Z-SWITCH1, Z-SWITCH2...Z-SWITCH15 respectively. Sixteen switching interconnect regions 200 are disposed on the first switching interconnect wafer 2. Each switching interconnect region 200 contains a first switch 201-1, a second switch 202-1, and a third switch 203-1. The 16 switching interconnect regions 200 are arranged in a 4×4 array on the first switching interconnect wafer 2. To distinguish the 16 switching interconnect regions 200, they can be designated as the 0th switching interconnect region 200-0, the 1st switching interconnect region 200-1, the 2nd switching interconnect region 200-2, ..., the 15th switching interconnect region 200-15.

[0067] The 0th switching interconnection zone 200-0 is equipped with a first switch X-SWITCH0, a second switch Y-SWITCH0, and a third switch Y-SWITCH0; the 1st switching interconnection zone 200-1 is equipped with a first switch X-SWITCH1, a second switch Y-SWITCH1, and a third switch Y-SWITCH1; the 2nd switching interconnection zone 200-2 is equipped with a first switch X-SWITCH2, a second switch Y-SWITCH2, and a third switch Y-SWITCH2; the 3rd switching interconnection zone 200-3 is equipped with a first switch X-SWITCH3, a second switch Y-SWITCH3, and a third switch Y-SWITCH3; and so on, with the 15th switching interconnection zone 200-15 equipped with a first switch X-SWITCH15, a second switch Y-SWITCH15, and a third switch Y-SWITCH15.

[0068] In one embodiment, the first computing wafer includes 16 first region blocks, denoted as Cube-0, Cube-1, ..., Cube-15, where the i-th first region block can be represented as Cube-i, and i is an integer greater than or equal to 0 and less than or equal to 15. The two interconnect interfaces in the first direction of the i-th first region block are denoted as X-left and X-right, respectively; the j-th first communication interface of the X-left interconnect interface can be denoted as X-left-j, and the j-th first communication interface of the X-right interconnect interface can be denoted as X-right-j. The two interconnect interfaces in the second direction of the i-th first region block are denoted as Y-front and Y-back, respectively; the j-th second communication interface of the Y-front interconnect interface can be denoted as Y-front-j, and the j-th second communication interface of the Y-back interconnect interface can be denoted as Y-back-j. The two third-direction interconnections of the i-th first region block are denoted as Z-up and Z-down, respectively; the j-th third communication interface of the Z-up interconnection interface can be denoted as Z-up-j, and the j-th third communication interface of the Z-down interconnection interface can be denoted as Z-down-j. j is an integer, greater than or equal to 0 and less than or equal to 15.

[0069] like Figure 9As shown, the communication interfaces of the three interconnection interfaces in different directions of each first area block are respectively connected to the switches in the corresponding switch group. The first switch X-SWITCH0 in the first switch group is connected to the first communication interface X-left-0 and the first communication interface X-right-0 of the first direction interconnection interface X-left of the 0th first area block Cube-0, the first communication interface X-left-0 and the first communication interface X-right-0 of the first direction interconnection interface X-right of the 1st first area block Cube-1, ..., and the first communication interface X-left-0 and the first communication interface X-right-0 of the first direction interconnection interface X-right of the 15th first area block Cube-15. The first switch group includes a first switch X-SWITCH1 which is communicatively connected to the first communication interface X-left-1 of the first direction interconnection interface X-left and the first communication interface X-right-1 of the first direction interconnection interface X-right of the 0th first area block Cube-0, the first communication interface X-left-1 of the first direction interconnection interface X-left and the first communication interface X-right-1 of the first direction interconnection interface X-right of the 1st first area block Cube-1, ..., and the first communication interface X-left-1 of the first direction interconnection interface X-right of the 15th first area block Cube-15. Similarly, the first switch X-SWITCH15 in the first switch group is connected to the first communication interface X-left-15 and the first communication interface X-right-15 of the first direction interconnection interface X-left of the 0th first area block Cube-0, the first communication interface X-left-15 and the first communication interface X-right-15 of the first direction interconnection interface X-right of the 1st first area block Cube-1, ..., and the first communication interface X-left-15 and the first communication interface X-right-15 of the first direction interconnection interface X-right of the 15th first area block Cube-15.

[0070] The second switch group includes a second switch Y-SWITCH0 which is communicatively connected to the second communication interface Y-front-0 before the second direction interconnection interface Y- and the second communication interface Y-back-0 after the second direction interconnection interface Y- of the 0th first area block Cube-0, the second communication interface Y-front-0 before the second direction interconnection interface Y- and the second communication interface Y-back-0 after the second direction interconnection interface Y- of the 1st first area block Cube-1, ..., and the second communication interface Y-front-0 before the second direction interconnection interface Y- and the second communication interface Y-back-0 after the second direction interconnection interface Y- of the 15th first area block Cube-15. The second switch group includes a second switch Y-SWITCH1 that is connected to the second communication interface Y-front-1 before the second direction interconnection interface Y- and the second communication interface Y-rear-1 after the second direction interconnection interface Y- of the 0th first area block Cube-0, respectively; the second communication interface Y-front-1 before the second direction interconnection interface Y- and the second communication interface Y-rear-1 after the second direction interconnection interface Y- of the 1st first area block Cube-1, ..., and the second communication interface Y-front-1 before the second direction interconnection interface Y- and the second communication interface Y-rear-1 after the second direction interconnection interface Y- of the 15th first area block Cube-15. Similarly, the second switch Y-SWITCH15 in the second switch group is connected to the second communication interface Y-front-15 before the second direction interconnection interface Y- and the second communication interface Y-rear-15 after the second direction interconnection interface Y- of the 0th first area block Cube-0, and to the second communication interface Y-front-15 before the second direction interconnection interface Y- and the second communication interface Y-rear-15 after the second direction interconnection interface Y- of the 1st first area block Cube-1, ..., and to the second communication interface Y-front-15 before the second direction interconnection interface Y- and the second communication interface Y-rear-15 after the second direction interconnection interface Y- of the 15th first area block Cube-15.

[0071] The third switch group includes a third switch Z-SWITCH0 which is communicatively connected to the third communication interface Z-up-0 on the third-direction interconnection interface Z- of the 0th first area block Cube-0 and the third communication interface Z-down-0 below the interconnection interface Z-. The third communication interface Z-up-0 on the third-direction interconnection interface Z- of the 1st first area block Cube-1 and the third communication interface Z-down-0 below the interconnection interface Z- are also communicatively connected, ..., and the third communication interface Z-up-0 on the third-direction interconnection interface Z- of the 15th first area block Cube-15 is also communicatively connected to the third communication interface Z-up-0 on the third-direction interconnection interface Z- and the third communication interface Z-down-0 below the interconnection interface Z-. The third switch group includes a third switch Z-SWITCH1 which is communicatively connected to the third communication interface Z-up-1 on the third-direction interconnection interface Z- of the 0th first area block Cube-0 and the third communication interface Z-down-1 below the interconnection interface Z-. The third communication interface Z-up-1 on the third-direction interconnection interface Z- of the 1st first area block Cube-1 is communicatively connected to the third communication interface Z-down-1 below the interconnection interface Z-. ..., the third communication interface Z-up-1 on the third-direction interconnection interface Z- of the 15th first area block Cube-15 is communicatively connected to the third communication interface Z-down-1 below the interconnection interface Z-. Similarly, the third switch group includes the third switch Z-SWITCH15, which is connected to the third communication interface Z-up-15 on the third-direction interconnection interface Z- of the 0th first area block Cube-0 and the third communication interface Z-down-15 on the third-direction interconnection interface Z- of the first area block Cube-1, and the third communication interface Z-up-15 on the third-direction interconnection interface Z- of the first area block Cube-1, and the third communication interface Z-down-15 on the third-direction interconnection interface Z- of the 15th first area block Cube-15.

[0072] Based on the above embodiments, each first computing core 101-1-1 of the first computing unit 101-1 has three interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, and two interconnect interfaces in the third direction. The first computing unit 101-1 includes M×N first computing cores 101-1-1 connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core 101-1-1 is connected to its respective first computing unit 101-1 via two third-party interconnect interfaces.

[0073] Specifically, the first computing core has interconnect interfaces in three different directions, with two sets of interconnect interfaces in each direction, for a total of 6 interconnect interfaces.

[0074] In one embodiment, such as Figure 10 The first computing unit 100-1 shown includes PEs arranged in a 4×4 array. Each PE has interconnect interfaces in four directions, the first direction being the X-axis direction, i.e. Figure 10 The two interconnection interfaces (indicated by the arrow lines on the left and right sides of the PE) are represented as X-left and X-right, respectively. X-left and X-right each include four communication interfaces; the second direction (the Y-axis direction, i.e....) Figure 10 The two interconnecting interfaces (indicated by the arrows on the PE) are represented as Y-front and Y-back, respectively. Y-front and Y-back each include four communication interfaces; the third direction (Z-axis direction, i.e....) Figure 10 The two interconnection interfaces (indicated by the arrow lines at the top left and bottom right of the PE) are represented as Z-up and Z-down, respectively. Z-up and Z-down each include 16 communication interfaces.

[0075] In a 4×4 array of PEs, two adjacent PEs in the first direction are connected through an interconnection interface in the first direction. That is, one of the two adjacent PEs in the first direction is connected to the other PE through the first interconnection interface X-left in the first direction and the second interconnection interface X-right in the first direction. In a 4×4 array of PEs, two adjacent PEs in the second direction are connected through an interconnection interface in the second direction. That is, one of the two adjacent PEs in the second direction is connected to the other PE through the first interconnection interface Y-front in the second direction and the second interconnection interface Y-back in the second direction. Figure 10 In the 4×4 array of PEs, the four PEs located on the left edge are connected in a first direction via a first interconnection interface X-left to the first computing unit 101-1 via a first interconnection interface X-left. Similarly, the four PEs located on the right edge are connected in a first direction via a second interconnection interface X-right to the first computing unit 101-1 via a second interconnection interface X-right. The four PEs located on the top edge are connected in a second direction via a second interconnection interface Y-front to the first computing unit 101-1 via a second interconnection interface Y-front. Finally, the four PEs located on the bottom edge are connected in a second direction via a second interconnection interface Y-rear to the first computing unit 101-1 via a second interconnection interface Y-rear.

[0076] In the 4×4 PEs, each PE is connected to the two third-direction interconnection interfaces of its respective first computing unit 100-1 through two third-direction interconnection interfaces. The first third-direction interconnection interface Z-upper of each PE is communicatively connected to the first third-direction interconnection interface Z-upper of the first computing unit 101-1; the second third-direction interconnection interface Z-lower of each PE is communicatively connected to the second third-direction interconnection interface Z-lower of the first computing unit 101-1.

[0077] Figure 11 This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention, as shown below. Figure 11 As shown, based on the above embodiments, the wafer-level chip provided in this embodiment of the invention further includes a second switching interconnect wafer 3, wherein the second switching interconnect wafer 3, the first computing wafer 1 and the first switching interconnect wafer 2 are stacked, and the first computing wafer 1 is disposed between the first switching interconnect wafer 2 and the second switching interconnect wafer 3. Accordingly, the first computing cores 101-1-1 of two adjacent sets of first computing units 101-1 in each first region block 101 are connected by communication through the second switching interconnect wafer 3.

[0078] Specifically, a hybrid bonding technique can be used to stack the first computing wafer 1 and the second switching interconnect wafer 3. The second switching interconnect wafer 3 enables communication between the various computing cores 101-1-1 in a third-party direction. The dimensions of the second switching interconnect wafer 3 and the first computing wafer 1 can be the same or different, depending on actual needs; this embodiment of the invention does not impose any limitations. The size of the second switching interconnect wafer 3 can be 12 inches, 8 inches, or 6 inches, etc., and this embodiment of the invention does not impose any limitations.

[0079] The second switching interconnect wafer 3 replaces the first switching interconnect wafer 2 to realize communication between the corresponding first computing cores 101-1-1 in two adjacent groups of first computing units 101-1. The structure of the second switching interconnect wafer 3 realizing communication between the corresponding first computing cores 101-1-1 in two adjacent groups of first computing units 101-1 is similar to the structure of the first switching interconnect wafer 2 realizing communication between the corresponding first computing cores 101-1-1 in two adjacent groups of first computing units 101-1, and will not be described again here.

[0080] Replacing the first switching interconnect wafer 2 with the second switching interconnect wafer 3 to achieve communication for the first computing core can reduce the wiring density of the first switching interconnect wafer 2. Alternatively, when there are many first computing cores and the first switching interconnect wafer 2 cannot complete the communication wiring, the second switching interconnect wafer 3 can be used to complete the communication wiring.

[0081] Figure 12This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention. Figure 13 This is a schematic diagram of the planar structure of the second region block provided in an embodiment of the present invention, as shown below. Figure 12 and Figure 13 As shown, based on the above embodiments, the wafer-level chip provided in this embodiment of the invention further includes a second computing wafer 4, wherein the second computing wafer 4, the first switching interconnect wafer 2 and the first computing wafer 1 are stacked, and the first switching interconnect wafer 2 is disposed between the first computing wafer 1 and the second computing wafer 4. The second computing wafer 4 includes a plurality of second region blocks 401, each second region block 401 includes K groups of second computing units 401-1, and each group of second computing units 401-1 includes M×N second computing cores 401-1-1; Each group of second computing units 401-1 includes M×N second computing cores 401-1-1 connected by a 2D Mesh network; the second computing cores 401-1-1 of two adjacent groups of second computing units 401-1 correspond one-to-one; the corresponding second computing cores 401-1-1 of two adjacent groups of second computing units 401-1 are connected by a first switching interconnect wafer 2. The first switching interconnect wafer 2 is also used to realize communication connections between the various second area blocks 401.

[0082] Specifically, a hybrid bonding technique can be used to stack the second computing wafer 4 and the first interconnect wafer 2. The second computing wafer 4 can have the same structure as the first computing wafer 1, and the dimensions of the second computing wafer 4 and the first computing wafer 1 can be the same. The size of the second computing wafer 4 can be 12 inches, 8 inches, or 6 inches, etc., and this embodiment of the invention is not limited thereto.

[0083] The second computing wafer 4 shares the three switch groups included in the first switching interconnect wafer 2 with the first computing wafer 1 to realize the communication connection between each second region block 401. Each second region block 401 has three interconnect interfaces in three different directions: two interconnect interfaces in the first direction, each including K×N fourth communication interfaces; two interconnect interfaces in the second direction, each including K×M fifth communication interfaces; and two interconnect interfaces in the third direction, each including M×N sixth communication interfaces. The first switch group 201 corresponds to the first direction interconnect interface of each second region block 401, and each first switch 201-1 is connected to the corresponding fourth communication interface. The second switch group 202 corresponds to the second direction interconnect interface of each second region block 401, and each second switch 202-1 is connected to the corresponding fifth communication interface. The third switch group 203 corresponds to the third direction interconnect interface of each second region block, and each third switch 203-1 is connected to the corresponding third communication interface.

[0084] Figure 15 This is a schematic diagram of the structure of a wafer-level chip provided in another embodiment of the present invention. Figure 16 This is a schematic diagram of the planar structure of a four-dimensional module provided in an embodiment of the present invention, as shown below. Figure 15 and Figure 16 As shown, based on the above embodiments, the wafer-level chip provided in this embodiment of the invention further includes a third switching interconnect wafer 5, the third switching interconnect wafer 5, the first computing wafer 1 and the first switching interconnect wafer 2 are stacked, and the first computing wafer 1 is disposed between the first switching interconnect wafer 2 and the third switching interconnect wafer 5. Accordingly, the first computing wafer 1 includes a plurality of four-dimensional modules 10, each four-dimensional module 10 including a plurality of first region blocks 101; the first computing cores 101-1-1 of two adjacent first region blocks 101 in the plurality of four-dimensional modules 10 correspond one-to-one; the corresponding first computing cores 101-1-1 of two adjacent first region blocks 101 are connected by four-dimensional communication through the third switching interconnect wafer 5. The third switching interconnect wafer 5 is also used to realize four-dimensional communication connections between the various four-dimensional modules 10.

[0085] Specifically, a hybrid bonding technique can be used to stack the first computing wafer 1 and the third interconnect wafer 5. The third interconnect wafer 5 enables communication between the various computing cores 101-1-1 in the fourth direction. It also enables communication between the various four-dimensional modules 10. The third interconnect wafer 5 can be 12 inches, 8 inches, or 6 inches, etc., selected according to actual needs; this embodiment of the invention does not impose any limitations.

[0086] The first computing wafer 1 includes multiple four-dimensional modules 10, and each four-dimensional module 10 includes multiple first region blocks 101. The specific number of four-dimensional modules 10 included in the first computing wafer 1 is set according to actual needs, and is not limited in this embodiment of the invention. The specific structure of the first region block 101 is detailed above and will not be repeated here.

[0087] The first computing cores 101-1-1 of two adjacent first region blocks 101 in the plurality of four-dimensional modules 10 correspond one-to-one; the corresponding first computing cores 101-1-1 of two adjacent first region blocks 101 are connected by four-dimensional communication through the third switching interconnect wafer 5, that is, the communication of the corresponding first computing cores 101-1-1 of two adjacent first region blocks 101 in the fourth direction is realized through the third switching interconnect wafer 5.

[0088] In one embodiment, such as Figure 14 As shown, four four-dimensional modules 10 are set on the first computing wafer 1. Each four-dimensional module 10 includes four first region blocks, and the four first region blocks are arranged in an array on the first computing wafer.

[0089] In one embodiment, such as Figure 17 As shown, the first computing core 101-1-1 (i.e., PE) has interconnects in four different directions. Each group of first computing units 101-1 includes M×N first computing cores 101-1-1 connected via interconnects in the first direction (i.e., X-axis interconnects) and the second direction (i.e., Y-axis interconnects) using a 2D mesh network. The corresponding first computing cores 101-1-1 of two adjacent groups of first computing units 101-1 are connected via their respective third-direction interconnects (i.e., Z-axis interconnects). The corresponding first computing cores 101-1-1 of two adjacent first region blocks 101 are connected via their respective fourth-direction interconnects (i.e., W-axis interconnects). Each fourth-direction interconnect may include a fourth interconnect on the first computing wafer 1, a fifth interconnect within the hybrid bonding structure between the first computing wafer 1 and the third exchange interconnect 5, and a sixth interconnect (not shown in the figure) on the third exchange interconnect 5, with the fourth, fifth, and sixth interconnects connected sequentially.

[0090] In one embodiment, each four-dimensional module 10 may be provided with a fourth-direction interconnection interface, having two interconnection interfaces in the fourth direction. A fourth switch group is provided on the third switching interconnect wafer 5 to enable fourth-direction interconnection communication between the various four-dimensional modules 10. The fourth-direction interconnection interface of each four-dimensional module is connected to the fourth switch group, enabling communication between the various four-dimensional modules 10 in the fourth direction.

[0091] In one embodiment, such as Figure 18A As shown, each four-dimensional module 10 includes two first region blocks 101, each first region block 101 includes four groups of first computing units 101-1, and each group of first computing units 101-1 includes 16 first computing cores 101-1-1. The four four-dimensional modules are arrayed on the first computing wafer. Figure 18B As shown, the two first region blocks 101 included in the four-dimensional module 10 are logically stacked into a 4×4×4 cube unit based on 3D Torus topology. That is, the four sets of 4×4 first computing units 101-1 of each first region block 101 are logically stacked into a 4×4×4 cube unit based on 3D Torus topology. The corresponding PEs in the two first region blocks 101 are communicatively connected in the fourth direction. Figure 18B The line connecting two cube elements in the middle represents the communication connection between the corresponding two PEs in the fourth direction.

[0092] Figure 19 This is a schematic diagram of the structure of a third switching interconnect wafer provided in an embodiment of the present invention, as shown below. Figure 19 As shown, based on the above embodiments, the third switching interconnect wafer 5 further includes a fourth switch group 501, and the fourth switch group 501 includes K×M×N fourth switches 501-1. Each four-dimensional module 10 has a fourth-direction interconnection interface, and there are K×M×N fourth communication interfaces in the fourth direction. The fourth switch group 501 corresponds to the fourth direction interconnection interface of each four-dimensional module 10, and each fourth switch 501-1 is connected to the corresponding fourth communication interface. The fourth switches 501-1 within the fourth switch group 501 are connected to each other.

[0093] Based on the above embodiments, each first region block 101 corresponds to one exposure field or multiple first region blocks 101 correspond to one exposure field.

[0094] Based on the above embodiments, each first computing core 101-1-1 of the first computing unit 101-1 has four interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, two interconnect interfaces in the third direction, and two interconnect interfaces in the fourth direction. The first computing unit 101-1 includes M×N first computing cores 101-1-1 connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core 101-1-1 is connected to the two third-party interconnection interfaces of its respective first computing unit 101-1 through two third-party interconnection interfaces; Each first computing core 101-1-1 is connected to its respective first computing unit 101-1 via two interconnect interfaces in the fourth direction.

[0095] In one embodiment, such as Figure 20 The first computing unit 100-1 shown includes PEs arranged in a 4×4 array. Each PE has interconnect interfaces in four directions, the first direction being the X-axis direction, i.e. Figure 20 The two interconnection interfaces (indicated by the arrow lines on the left and right sides of the PE) are represented as X-left and X-right, respectively. X-left and X-right each include four communication interfaces; the second direction (the Y-axis direction, i.e....) Figure 20 The two interconnecting interfaces (indicated by the arrows on the PE) are represented as Y-front and Y-back, respectively. Y-front and Y-back each include four communication interfaces; the third direction (Z-axis direction, i.e....) Figure 20 The two interconnecting interfaces (indicated by the arrow lines at the top left and bottom right of the PE) are represented as Z-up and Z-down, respectively. Z-up and Z-down each include 16 communication interfaces. The fourth direction (W-axis direction, i.e....) Figure 20 The two interconnection interfaces (indicated by the arrow lines at the top right and bottom left of the PE) are represented as W-in and W-out respectively, with each of W-in and W-out including 16 communication interfaces.

[0096] In a 4×4 array of PEs, two adjacent PEs in the first direction are connected through an interconnection interface in the first direction. That is, one of the two adjacent PEs in the first direction is connected to the other PE through the first interconnection interface X-left in the first direction and the second interconnection interface X-right in the first direction. In a 4×4 array of PEs, two adjacent PEs in the second direction are connected through an interconnection interface in the second direction. That is, one of the two adjacent PEs in the second direction is connected to the other PE through the first interconnection interface Y-front in the second direction and the second interconnection interface Y-back in the second direction. Figure 20In the 4×4 array of PEs, the four PEs located on the left edge are connected in a first direction via a first interconnection interface X-left to the first computing unit 101-1 via a first interconnection interface X-left. Similarly, the four PEs located on the right edge are connected in a first direction via a second interconnection interface X-right to the first computing unit 101-1 via a second interconnection interface X-right. The four PEs located on the top edge are connected in a second direction via a second interconnection interface Y-front to the first computing unit 101-1 via a second interconnection interface Y-front. Finally, the four PEs located on the bottom edge are connected in a second direction via a second interconnection interface Y-rear to the first computing unit 101-1 via a second interconnection interface Y-rear.

[0097] In the 4×4 PEs, each PE is connected to the two third-direction interconnection interfaces of its respective first computing unit 100-1 through two third-direction interconnection interfaces. The first third-direction interconnection interface Z-upper of each PE is communicatively connected to the first third-direction interconnection interface Z-upper of the first computing unit 101-1; the second third-direction interconnection interface Z-lower of each PE is communicatively connected to the second third-direction interconnection interface Z-lower of the first computing unit 101-1.

[0098] In the 4×4 PEs, each PE is connected to the two interconnecting interfaces in the fourth direction of its respective first computing unit 100-1 via two interconnecting interfaces in the fourth direction. The first interconnecting interface W-in of each PE in the fourth direction is communicatively connected to the first interconnecting interface W-in of the fourth direction of the first computing unit 101-1; the second interconnecting interface W-out of each PE in the fourth direction is communicatively connected to the second interconnecting interface W-out of the fourth direction of the first computing unit 101-1.

[0099] In the process of fabricating wafer-level chips, the wafer needs to be divided into multiple exposure fields, and fabrication is carried out using the exposure field as the basic unit. The first region block 101 is set up using the exposure field to facilitate the fabrication of the first region block.

[0100] An embodiment of the present invention provides a board card comprising at least one wafer-level chip as described in any of the above embodiments.

[0101] An electronic device provided by an embodiment of the present invention includes at least one board as described in any of the above embodiments.

[0102] In one embodiment, the electronic device may be a server or a server cluster.

[0103] The wafer-level chip provided in this application has the following significant advantages over existing wafer-level chips using 2D Mesh interconnect topology due to the use of 3D Torus interconnect topology: (1) Shorter communication path and lower average number of hops. The computing cores of wafer-level chips are arranged in a plane on the whole wafer. In 2D Mesh, the communication latency of long-distance computing cores will increase sharply due to the accumulation of physical distance and number of hops. However, 3DTorus shortens the physical path through vertical interconnection along the Z-axis and reduces the number of hops. It is perfectly adapted to the high-frequency communication modes such as All-Reduce and All-to-All in large-scale AI model inference / training, avoiding the problems of "overkill computing power and communication bottleneck".

[0104] (2) Better scalability and bandwidth utilization. As the number of computing cores increases, the computing core array can be expanded infinitely along the X / Y / Z axes, allowing millions of cores to form a high-efficiency parallel computing cluster. The communication performance of the 3D Torus degrades more gradually, giving full play to the computing power density advantage of wafer-level chips. At the same time, multi-path routing strategies are easier to implement in the 3D Torus interconnect topology, further improving the link bandwidth utilization.

[0105] (3) Higher network symmetry and load balancing capabilities. 3D Torus has a highly symmetrical topology, and all computing cores are essentially equivalent in status within the network, avoiding the communication bottleneck caused by the performance differences between edge and center nodes in 2D Mesh. This uniformity helps to achieve a more balanced data flow distribution in large-scale parallel training, reducing congestion and improving overall throughput efficiency.

[0106] In summary, adopting a 3D Torus interconnect topology in wafer-level chips can effectively alleviate the communication bottleneck caused by the physical distance difference in 2D Mesh, significantly improve the performance, energy efficiency and scalability of communication-intensive AI tasks, and is an important interconnect architecture choice for future ultra-large-scale AI accelerators.

[0107] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0108] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A wafer-level chip, characterized in that, It includes a first computing wafer and a first switching interconnect wafer, wherein: The first computing wafer and the first switching interconnect wafer are stacked together; The first computing wafer includes multiple first region blocks, each first region block includes K groups of first computing units, and each group of first computing units includes M×N first computing cores; K is an integer greater than or equal to 2, M and N are both positive integers, and at least one of M and N is greater than or equal to 2; Each group of first computing units includes M×N first computing cores that are connected by a 2D Mesh network; the first computing cores of two adjacent groups of first computing units in the K groups of first computing units correspond one-to-one; the corresponding first computing cores of two adjacent groups of first computing units are connected by the first switching interconnect wafer communication. The first switching interconnect wafer is used to realize communication connections between the various first region blocks.

2. The wafer-level chip according to claim 1, characterized in that, The first switching interconnect wafer includes three switch groups: the first switch group includes K×N first switches, the second switch group includes K×M second switches, and the third switch group includes M×N third switches. Each first region block has three interconnection interfaces in three different directions. There are two interconnection interfaces in the first direction, each including K×N first communication interfaces. There are two interconnection interfaces in the second direction, each including K×M second communication interfaces. There are two interconnection interfaces in the third direction, each including M×N third communication interfaces. The first switch group corresponds to the first direction interconnection interface of each first area block, and each first switch is communicatively connected to the corresponding first communication interface; the second switch group corresponds to the second direction interconnection interface of each first area block, and each second switch is communicatively connected to the corresponding second communication interface; the third switch group corresponds to the third direction interconnection interface of each first area block, and each third switch is communicatively connected to the corresponding third communication interface; the switches within each switch group are communicatively connected.

3. The wafer-level chip according to claim 2, characterized in that, M, N, and K are equal. The switches in the three switch groups are arranged in M×N switching interconnection areas, and each switching interconnection area is equipped with three switches. The three switches belong to different switch groups.

4. The wafer-level chip according to claim 1, characterized in that, Each of the first computing cores in the first computing unit has three interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, and two interconnect interfaces in the third direction. The first computing unit includes M×N first computing cores that are connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core is connected to its respective first computing unit via two third-party interconnect interfaces.

5. The wafer-level chip according to claim 1, characterized in that, It also includes a second switching interconnect wafer, wherein the second switching interconnect wafer, the first computing wafer and the first switching interconnect wafer are stacked, and the first computing wafer is disposed between the first switching interconnect wafer and the second switching interconnect wafer; Accordingly, the first computing cores of two adjacent groups of first computing units in each first region block are connected via the second switching interconnect wafer communication.

6. The wafer-level chip according to claim 1, characterized in that, It also includes a second computing wafer, wherein the second computing wafer, the first switching interconnect wafer and the first computing wafer are stacked, and the first switching interconnect wafer is disposed between the first computing wafer and the second computing wafer; The second computing wafer includes multiple second region blocks, each second region block includes K groups of second computing units, and each group of second computing units includes M×N second computing cores; Each group of second computing units includes M×N second computing cores connected by a 2D Mesh network; The second computing cores of two adjacent groups of second computing units in the U-group correspond one-to-one; each corresponding second computing core of two adjacent groups of second computing units is connected through the first switching interconnect wafer communication. The first switching interconnect wafer is also used to realize communication connections between the various second region blocks.

7. The wafer-level chip according to claim 1, characterized in that, It also includes a third switching interconnect wafer, wherein the third switching interconnect wafer, the first computing wafer, and the first switching interconnect wafer are stacked together, and the first computing wafer is disposed between the first switching interconnect wafer and the third switching interconnect wafer; Accordingly, the first computing wafer includes multiple four-dimensional modules, each four-dimensional module including multiple first region blocks; the first computing cores of two adjacent first region blocks in the multiple four-dimensional modules correspond one-to-one; the corresponding first computing cores of two adjacent first region blocks are connected through the three-dimensional communication of the third switching interconnect wafer. The third switching interconnect wafer is also used to realize four-dimensional communication connections between various four-dimensional modules.

8. The wafer-level chip according to claim 7, characterized in that, The third switching interconnect wafer includes a fourth switch group, which includes K×M×N fourth switches; Each four-dimensional module has a fourth-direction interconnection interface, and there are K×M×N fourth communication interfaces in the fourth direction. The fourth switch group corresponds to the interconnection interface in the fourth direction and includes K×M×N fourth switches. Each fourth switch is communicatively connected to the corresponding fourth communication interface, and all fourth switches in the fourth switch group are communicatively connected.

9. The wafer-level chip according to claim 7, characterized in that, Each of the first computing cores in the first computing unit has four interconnect interfaces in different directions: two interconnect interfaces in the first direction, two interconnect channels in the second direction, two interconnect interfaces in the third direction, and two interconnect interfaces in the fourth direction. The first computing unit includes M×N first computing cores that are connected via a 2D Mesh network through a first-direction interconnection interface and a second-direction interconnection interface. Each first computing core is connected to the two third-party interconnect interfaces of its respective first computing unit through two third-party interconnect interfaces; Each first computing core is connected to its respective first computing unit via two interconnect interfaces in the fourth direction.

10. The wafer-level chip according to any one of claims 1 to 9, characterized in that, Each first region block corresponds to one exposure field, or multiple first region blocks correspond to one exposure field.

11. A circuit board, characterized in that, It includes at least one wafer-level chip as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, It includes at least one board as described in claim 11.

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