A multi-core chip and a common resource access method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-11
- Publication Date
- 2026-08-11
AI Technical Summary
[0002]现有的多核芯片架构中，由于芯片中包括多个核心处理器，各个核心处理器运行的速度等参数是有差异的，因此，所述多个核心处理器分别通过仲裁总线，与各个公共资源模块相连，所述仲裁总线为异步总线，异步总线传输时序宽松，容易设计，故而多核芯片架构中通常采用异步总线架构，然而，异步总线通过应答信号实现信息传输，因此信息传输效率较低
[0008]可见，本申请实施例提供的多核芯片内，处理器不仅可以通过异步总线访问公共资源模块；并且，新增了与至少一个处理器相应设置的公共资源模块的控制单元的映射端，以及同步走线，使得至少一个处理器还可以通过同步总线对公共资源模块进行读写访问，即本申请实施例提供的多核芯片内部至少一个处理器，还可以通过设置的同步总线，与公共资源模块的控制单元的映射端相连，从而实现该处理器对该公共资源模块的控制单元的映射端的读写访问，也就是说，将实时性要求高、频繁操作、响应速度快的公共资源模块，通过控制单元的映射端，映射到不同处理器的同步总线，从而实现了公共资源模块在不同处理器之间的分时共享，使得公共资源模块得到更高的性能利用，提升了芯片整体性能。并且，在多核联动的场景中，虽然公共资源模块被切换到一个处理器的同步总线，其他处理器依旧可以通过异步总线读取该公共资源模块的相关信息，从而实现公共资源模块的信息在不同处理器之间的共享，方便了多核系统的统一资源调度。
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Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a method for accessing public resources for multi-core chips. Background Technology
[0002] In existing multi-core chip architectures, since the chip includes multiple core processors, and the speed and other parameters of each core processor are different, the multiple core processors are connected to each common resource module through an arbitration bus. The arbitration bus is an asynchronous bus. Asynchronous bus transmission timing is loose and easy to design, so asynchronous bus architecture is usually used in multi-core chip architectures. However, asynchronous bus realizes information transmission through acknowledgment signals, so the information transmission efficiency is low. Summary of the Invention
[0003] This application provides a method for accessing common resources in a multi-core chip, which improves the efficiency of the processor inside the multi-core chip in accessing common resource modules, thereby meeting higher real-time requirements and improving the overall performance of the chip.
[0004] This application provides a multi-core chip, including: multiple processors, and the multi-core chip further includes: a mapping terminal of at least one control unit of a common resource module;
[0005] At least one of the processors is connected to the mapping terminal of the control unit of the common resource module via a synchronization bus, and enables read and write access to the mapping terminal of the control unit of the common resource module.
[0006] Each of the processors is connected to the common resource module via an asynchronous bus and enables read-only access to the control unit of the common resource module;
[0007] The mapping terminal of the control unit of the public resource module is the same as the control unit in the public resource module.
[0008] As can be seen, in the multi-core chip provided in this application embodiment, the processor can not only access the common resource module through the asynchronous bus; but also, a mapping terminal for the control unit of the common resource module corresponding to at least one processor, as well as synchronous wiring, are added, enabling at least one processor to also read and write to the common resource module through the synchronous bus. That is, at least one processor inside the multi-core chip provided in this application embodiment can also be connected to the mapping terminal of the control unit of the common resource module through the set synchronous bus, thereby realizing the processor's read and write access to the mapping terminal of the control unit of the common resource module. In other words, the common resource module with high real-time requirements, frequent operation, and fast response speed is mapped to the synchronous bus of different processors through the mapping terminal of the control unit, thereby realizing the time-sharing of the common resource module among different processors, so that the common resource module can be utilized more effectively and the overall performance of the chip can be improved. Furthermore, in the multi-core linkage scenario, although the common resource module is switched to the synchronous bus of one processor, other processors can still read the relevant information of the common resource module through the asynchronous bus, thereby realizing the sharing of the information of the common resource module among different processors and facilitating the unified resource scheduling of the multi-core system.
[0009] In some embodiments, the multi-core chip includes mapping terminals of control units of multiple common resource modules; wherein, the mapping terminal of each control unit of the common resource module is configured corresponding to a processor, and different processors are connected to the mapping terminals of control units of different common resource modules through different synchronization buses.
[0010] In some embodiments, at least one of the processors is connected to the mapping terminal of the control unit of the public resource module via an asynchronous bus, and enables read-only access to the mapping terminal of the control unit of the public resource module.
[0011] In some embodiments, the multi-core chip further includes:
[0012] At least one of the aforementioned public resource modules.
[0013] In some embodiments, the public resource module further includes:
[0014] The control selection terminal is used to select a processor based on parameters in the control unit of the local public resource module, such that the selected processor can access the local public resource module for read and write operations via the bus.
[0015] In some embodiments, if the selected processor is a processor that reads and writes to the local public resource module via a synchronization bus, then the selected processor's read and write access to the local public resource module via the synchronization bus includes: synchronizing the mapping terminal of the control unit of the local public resource module connected to the selected processor with the control unit of the local public resource module.
[0016] This application provides a public resource access method, applied to the multi-core chip provided in the above-described embodiment of this application. The method includes:
[0017] Determine if the local processor obtains time-sharing exclusive read / write access to the public resource module;
[0018] The synchronous bus enables read and write access to the mapping terminal of the control unit of the common resource module, and synchronizes the data in the mapping terminal of the control unit of the common resource module to the control unit of the common resource module.
[0019] In some embodiments, the method further includes:
[0020] When the local processor does not have time-sharing exclusive access to the public resource module, read-only access to the public resource module is achieved through the asynchronous bus.
[0021] Another embodiment of this application provides a public resource access method, applied to the multi-core chip provided in the above-described embodiment of this application, the method comprising:
[0022] When multiple processors are connected to the local public resource module through different synchronization buses, the first target processor with read and write access permissions to the control unit of the local public resource module is determined based on the parameters in the control unit of the local public resource module.
[0023] Through a synchronization bus, the mapping terminal of the control unit of the local public resource module accessed by the first target processor for reading and writing is synchronized with the data of the control unit of the local public resource module.
[0024] In some embodiments, the method further includes:
[0025] When multiple processors are connected to the local public resource module via an asynchronous bus, a second target processor with read-only access rights to the control unit of the local public resource module is determined.
[0026] The system receives a read-only access request from the second target processor with read-only access rights to the control unit of the local public resource module via an asynchronous bus, and provides the read data. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 A schematic diagram of a multi-core chip architecture provided for an embodiment of this application;
[0029] Figure 2 A schematic diagram of another multi-core chip architecture provided for an embodiment of this application;
[0030] Figure 3 A schematic diagram of the architecture of a third multi-core chip provided in an embodiment of this application;
[0031] Figure 4 A schematic diagram of the architecture of a fourth multi-core chip provided in an embodiment of this application;
[0032] Figure 5 A schematic diagram illustrating a public resource access method provided in this application embodiment;
[0033] Figure 6 This is a schematic diagram illustrating the specific process of another public resource access method provided in an embodiment of this application. Detailed Implementation
[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0035] This application provides a method for accessing common resources in a multi-core chip, which improves the efficiency of the processor inside the multi-core chip in accessing common resource modules, thereby meeting higher real-time requirements and improving the overall performance of the chip.
[0036] The terms "first," "second," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0037] The following examples and embodiments are to be understood as illustrative only. While this specification may refer to "a," "an," or "some" examples or embodiments in several places, this does not mean that every such reference relates to the same example or embodiment, nor does it mean that the feature applies only to a single example or embodiment. Individual features of different embodiments may also be combined to provide other embodiments. Furthermore, terms such as "comprising" and "including" should be understood not to limit the described embodiments to consisting only of those features mentioned; such examples and embodiments may also include features, structures, units, modules, etc., not specifically mentioned.
[0038] The various embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be noted that the order in which the embodiments are presented in this application represents only a chronological order and does not represent the superiority or inferiority of the technical solutions provided by the embodiments.
[0039] See Figure 1 This application provides a multi-core chip, comprising:
[0040] Multiple processors 01, for example Figure 1 The processors N0 to Nn are shown.
[0041] The multi-core chip also includes: at least one mapping terminal 22 of the control unit 21 of the public resource module 02;
[0042] At least one of the processors 01 is connected to the mapping terminal 22 of the control unit 21 of the public resource module 02 via the synchronization bus 11, and realizes read and write access to the mapping terminal 22 of the control unit 21 of the public resource module 02.
[0043] Each of the processors 01 is connected to the common resource module 02 via the asynchronous bus 12 and enables read-only access to the control unit 21 of the common resource module 02;
[0044] The mapping terminal 22 of the control unit 21 of the public resource module 02 is the same as the control unit 21 in the public resource module 02.
[0045] The processor, such as a CPU, DSP (Digital Signal Processor), etc.
[0046] The public resource module 02 includes, for example, a clock control module, an audio input / output module (ADC, DAC, etc.), a USB module for external communication, etc.
[0047] The control unit 21 may be, for example, a register, or of other types of memory.
[0048] In a synchronous bus architecture, processors and shared resource modules connected to the synchronous bus use a unified clock signal for synchronization. The protocol is simple, resulting in faster communication speeds and less interface logic. Synchronous communication, i.e., communication via a synchronous bus, typically requires a unified, fixed-length clock standard to control the data transmission process. Each operation and signal is given at a fixed time point. In synchronous communication, modules use a unified, fixed-length clock standard and must complete their specified operations within the same timeframe. Master and slave modules are forced to synchronize. For multiple modules with different speeds, the slowest module must set the clock standard, causing faster modules to transmit according to the slower module's standard. Therefore, synchronous communication is generally used only when the bus length is short and access times are relatively consistent.
[0049] In an asynchronous bus architecture, there is no clock signal line. Therefore, the asynchronous bus architecture communicates through a handshake protocol (acknowledgment signal) for communication between processors with different access speeds and modules sharing common resources. Asynchronous communication, i.e., communication via an asynchronous bus, unlike synchronous communication, does not have a unified clock standard and uses an acknowledgment method. In asynchronous communication, the master device initiates a request, and the slave device is controlled by the master device. Compared to synchronous communication, asynchronous communication does not have a fixed-length clock, but it adds a request line and an acknowledgment line. The request line is used by the master device to send a request signal to the slave device, and the acknowledgment line is used by the slave device to send an acknowledgment signal to the master device.
[0050] In multi-core processing systems, not all common resource modules are accessed by multiple core processors at any given time. Depending on the application scenario, some common resource modules may only be accessed by one core processor in certain situations. In such cases, these clearly designated common resource modules can maximize their effectiveness by switching access methods according to the working scenario. For example, if the DSP is used to process audio information, and the audio output to the speaker is handled by the DSP, then the path from the DSP to the DAC module is the same as the path from the DSP to the DAC module. In other words, the DAC module should be controlled by the DSP, rather than the DSP completing the audio effects and then notifying the CPU to output data to the DAC module. In other words, the read / write access control of the DAC module should be switched to the DSP, and the audio data processed by the DSP can be directly transmitted to the DAC module.
[0051] In other words, the area of a DAC module depends on its resolution, conversion accuracy, conversion speed, linearity, etc. The audio data source is either a DSP or a CPU. To maintain continuous data output, a first-in-first-out (FIFO) queue is typically used to buffer the data at the front end. Therefore, if the DAC module's data source is processed by a general-purpose CPU, the DAC module can switch the audio data source to the CPU for synchronous access. If the audio data is processed using a special algorithm by the DSP, switching the DAC module's FIFO port to the DSP for synchronous access will be more convenient for audio stream processing.
[0052] Therefore, this application provides a method in a multi-core processor asynchronous bus access architecture to add a multi-core processor switching access architecture via a synchronous bus based on the attributes of the common resource module, ensuring maximum utilization of the common resource module and improving the overall access efficiency of the chip. For example, when the audio algorithm is completely controlled by the DSP, the DSP can directly output the processing result data to the DAC module output after completing the sound effect processing. At this time, the CPU module can enter sleep mode or do other things without having to check whether the DSP has finished processing the sound effect or refresh the DAC data.
[0053] It should be noted that, Figure 1 The illustration only depicts the case of a single public resource module Mm. The technical solution provided in this application embodiment is applicable to the case of multiple public resource modules, that is, different processors can access multiple different public resource modules in read and write mode or in read-only mode. This application embodiment only uses the public resource module Mm as an example for illustration. The same applies to other public resource modules, and will not be described in detail here.
[0054] The mapping terminal of the control unit of the public resource module described in this application embodiment can be set to correspond one-to-one with the processor. The mapping terminal can be set inside the processor or outside the processor.
[0055] In some embodiments, see Figure 2 The multi-core chip includes multiple mapping terminals 22 of the control units 21 of the common resource modules 02; wherein, the mapping terminal 22 of the control unit 21 of each common resource module 02 is correspondingly set to a processor 01, and different processors 01 are connected to the mapping terminals 22 of the control units 21 of different common resource modules 02 through different synchronization buses 11.
[0056] For example: Figure 2 The processor N0 shown is connected to a mapping terminal 22 of the control unit 21 of the common resource module Mm 02 via a synchronization bus 11; Figure 2 The processor Nn shown is connected to another mapping terminal 22 of the control unit 21 of the common resource module Mm 02 via another synchronization bus 11.
[0057] In some embodiments, see Figure 3 At least one of the processors 01 is connected to the mapping terminal 22 of the control unit 21 of the public resource module 02 via the asynchronous bus 13, and enables read-only access to the mapping terminal 22 of the control unit 21 of the public resource module 02.
[0058] For example: Figure 3 The processors N0 to Nn-1 shown are connected to the asynchronous bus 13a, which is connected to the mapping terminal 22a of the control unit of the common resource module Mm, enabling read-only access to the mapping terminal 22a of the control unit of the common resource module Mm. This allows other processors to read parameters from the mapping terminal 22a of the control unit of the common resource module Mm when processor Nn obtains exclusive read / write access to the common resource module Mm. This allows them to obtain the necessary information and determine whether processor Nn has released its exclusive read / write access to the common resource module Mm, thus enabling other processors to obtain exclusive read / write access to the common resource module Mm. Therefore, time-sharing exclusive read / write access to the same common resource module by multiple processors can be achieved.
[0059] Similarly, Figure 3 The processors N1 to Nn shown are connected to the asynchronous bus 13b, which is connected to the mapping terminal 22b of the control unit of the common resource module Mm, and enables read-only access to the mapping terminal 22b of the control unit of the common resource module Mm.
[0060] In summary, the embodiments of this application enable that while the mapping terminal of the control unit of a common resource module is being read and written by one processor (via a synchronous bus), other processors can also perform read-only access to the mapping terminal of the control unit of the common resource module (via an asynchronous bus), thereby realizing time-sharing exclusive read and write access to the same common resource module by multiple processors.
[0061] In other words, the multi-core chip architecture provided in this application, combined with the time-sharing characteristics of common resource modules, incorporates synchronous and asynchronous buses inside or outside different processors. Common resource modules with high real-time requirements, frequent operations, and high speeds are mapped to the corresponding synchronous buses connected to different processors according to the principle of time-sharing. For example, common resource module Mm is a digital-to-analog converter (DAC) module. General audio information processing does not require a dedicated DSP; a CPU with DSP instructions can also be used. However, for requirements such as audio information synthesis and mixing, most cases are handled by a DSP processor. Therefore, the DAC module or its audio data FIFO control unit can be designed with a multi-core time-sharing exclusive access architecture. In scenarios with performance requirements, the DAC module or some of its control units can be switched to the DSP processor for synchronous access, significantly reducing the latency of the audio processing channel. Thus, in practical applications with time-sharing scenarios, common resource modules can achieve high performance utilization, improving the overall system performance.
[0062] Furthermore, in multi-core collaborative scenarios, although a common resource module is switched to the synchronous bus of a processor, other processors can still read the relevant information of the common resource module through the common asynchronous bus (asynchronous bus 12), or through the asynchronous bus (asynchronous bus 13a, 13b) set up one-to-one with the processor, thereby realizing information sharing, which improves the utilization efficiency of the common resource module and provides a convenient channel for multi-core cooperation, facilitating the unified scheduling of the chip system.
[0063] In some embodiments, the multi-core chip further includes:
[0064] At least one of the aforementioned public resource modules.
[0065] In other words, the public resource module described in this application embodiment can be located inside the multi-core chip.
[0066] In some embodiments, see Figure 4 The public resource module 02 also includes:
[0067] The control selection terminal 23 is used to select a processor based on the parameters in the control unit 21 of the local public resource module 02, so that the selected processor can access the local public resource module 02 for reading and writing through the bus (synchronous bus or asynchronous bus).
[0068] The control selection terminal 23 can select a processor based on the priority parameters of different processors configured in the control unit 21, or it can select a processor based on the time-sharing parameters of different processors (i.e., according to time parameters). The specific selection method can be determined according to actual needs, and is not limited in this embodiment.
[0069] For example Figure 4 As shown, the control selection terminal 23 can select the processor Nn to read and write to the local public resource module 02 through the synchronization bus 11a based on the parameters in the control unit 21. The specific implementation process includes the processor Nn reading and writing to the mapping terminal 22a of the control unit 21 through the synchronization bus 11a, and synchronizing the data in the mapping terminal 22a to the control unit 21.
[0070] Similarly, the control selection terminal 23 can also select the processor N0 to read and write to the local public resource module 02 through the synchronization bus 11b based on the parameters in the control unit 21. The specific implementation process includes the processor N0 reading and writing to the mapping terminal 22b of the control unit 21 through the synchronization bus 11b, and synchronizing the data in the mapping terminal 22b to the control unit 21.
[0071] Therefore, in some embodiments, if the processor selected by the control selection terminal is a processor that reads and writes to the local public resource module through the synchronization bus, then the selected processor's read and write access to the local public resource module through the synchronization bus includes: synchronizing the mapping terminal of the control unit of the local public resource module connected to the selected processor with the control unit of the local public resource module.
[0072] Of course, the control selection terminal 23 can also select the processor N1 (or any other processor) to read and write to the local public resource module 02 through the asynchronous bus 12 based on the parameters in the control unit 21.
[0073] In some embodiments, see Figure 4 The public resource module 02 also includes:
[0074] The execution unit 24 is used to execute corresponding functions based on the parameters in the control unit 21 of the local public resource module 02, under the control of the processor selected by the control selection terminal 23.
[0075] In some embodiments, the processor may also be referred to as a core processor, kernel, etc.
[0076] In some embodiments, the control unit may be a module with storage function, such as a register, and its functions include: allocating exclusive read and write access control rights of local public modules to the processor, and also including controlling the FIFO read and write path, etc.
[0077] In some embodiments, a mapping terminal for the control signal parameters (i.e., another control unit) of the FIFO buffer of the corresponding common resource module can be set for at least one processor, thereby further improving the access efficiency of the common resource module and increasing the data transmission speed. For example, common resource modules with data transmission functions such as DACs and USBs are generally equipped with FIFO buffers, and therefore also have corresponding control units for storing the control signal parameters of the FIFO buffers, and a mapping terminal for the control unit for storing the control signal parameters of the FIFO buffers can be set for at least one processor.
[0078] In addition, for scenarios with low real-time requirements, each processor 01 can also connect to the common resource module 02 via the asynchronous bus 12 and access the control unit 21 of the common resource module 02 for read and write operations. To ensure access correctness, a module such as a mailbox can be used to first confirm access permissions to the common resource module. Only when a processor obtains exclusive read and write access permissions to the common resource module can it perform read and write access. Alternatively, when multiple processors need to access the same common resource module simultaneously, exclusive read and write access permissions can be allocated to the common resource module according to the priority of each processor.
[0079] It should be noted that the read and write access described in the embodiments of this application includes read and / or write operations on the control unit of the public resource module (including the control unit in the public resource module, and / or the mapping terminal of the control unit in the public resource module) and / or the execution unit of the public resource module.
[0080] The read-only access described in this application embodiment includes read operations on the control unit of the public resource module (including the control unit in the public resource module and / or the mapping terminal of the control unit in the public resource module).
[0081] The method provided in the embodiments of this application is described below.
[0082] See Figure 5 On the processor side, this application provides a public resource access method, applied to the multi-core chip provided in the above-described embodiment of this application. The method includes:
[0083] S101. Determine that the local processor has obtained time-sharing exclusive read and write access permissions to the public resource module;
[0084] S102. Read and write access to the mapping end of the control unit of the public resource module is realized through the synchronization bus, and the data in the mapping end of the control unit of the public resource module is synchronized to the control unit of the public resource module.
[0085] For example, see Figure 4 The processor Nn obtains exclusive read and write access to the public resource module Mm, and realizes read and write access to the mapping terminal 22a of the control unit of the public resource module Mm through the synchronization bus 11a, and synchronizes the data in the mapping terminal 22a of the control unit of the public resource module Mm to the control unit 21 of the public resource module Mm.
[0086] As can be seen, in this embodiment, the parameters of the control unit (control unit) of the public resource module are updated to the parameters of the mapping terminal of the control unit of the public resource module on a core processor that has obtained the right to use it. That is, the core processor obtains the right to use the public resource module. The core processor that has obtained the right to use it can perform read and write operations on the execution unit of the public resource module. When the use is completed, the right to use it is released, and the core processor modifies the parameters of the mapping terminal of the control unit of the public resource module. These parameters are synchronized to the control unit of the public resource module, so that the public resource module is released and can be switched to other core processors for control. That is, the control selection terminal of the public resource module switches the right to use the public resource module to the corresponding core processor according to the stored parameters of the control unit.
[0087] In some embodiments, the method further includes:
[0088] When the local processor does not have time-sharing exclusive access to the public resource module, read-only access to the public resource module is achieved through the asynchronous bus.
[0089] For example, see Figure 4 Processor Nn acquires exclusive read / write access to the common resource module Mm, and accesses the mapping terminal 22a of the control unit of the common resource module Mm via the synchronous bus 11a, synchronizing the data in the mapping terminal 22a of the control unit of the common resource module Mm to the control unit 21 of the common resource module Mm. Afterwards, processor Nn releases the exclusive read / write access to the common resource module Mm, and can then access the common resource module Mm only via the asynchronous bus 13a (specifically, access to the mapping terminal 22a of the control unit of the common resource module Mm only via the asynchronous bus 13a).
[0090] See Figure 6 On the public resource module side (specifically, it may be the aforementioned control selection terminal, or other functional modules, etc.), another embodiment of this application provides a public resource access method applied to the multi-core chip provided in the above-mentioned embodiments of this application. The method includes:
[0091] S201. When multiple processors are connected to the local public resource module through different synchronization buses, the first target processor that currently has read and write access permissions to the control unit of the local public resource module is determined based on the parameters in the control unit of the local public resource module.
[0092] S202. Through the synchronization bus, the mapping terminal of the control unit of the local public resource module accessed by the first target processor for reading and writing is synchronized with the data of the control unit of the local public resource module.
[0093] For example, see Figure 4 If the processor Nn is configured with the highest priority in the control unit 21 of the public resource module Mm, then the first target processor with read and write access permissions to the control unit 21 of the local public resource module Mm is determined to be the processor Nn. The processor Nn then obtains exclusive read and write access permissions to the public resource module Mm, realizes read and write access to the mapping terminal 22a of the control unit of the public resource module Mm through the synchronization bus 11a, and synchronizes the data in the mapping terminal 22a of the control unit of the public resource module Mm to the control unit 21 of the public resource module Mm.
[0094] In some embodiments, the method further includes:
[0095] When multiple processors are connected to the local public resource module via an asynchronous bus, a second target processor with read-only access rights to the control unit of the local public resource module is determined.
[0096] The system receives a read-only access request from the second target processor with read-only access rights to the control unit of the local public resource module via an asynchronous bus, and provides the read data.
[0097] Method 1, for example, see Figure 4Assuming that the first target processor with read / write access to the control unit 21 of the local public resource module Mm is processor Nn, and processors N0 to Nn-1 are all connected to the public resource module 02 via asynchronous bus 12, then, for example, if the second target processor with read-only access to the control unit 21 of the local public resource module Mm is determined to be processor N0, then the asynchronous bus 12 can be used to receive the read-only access request from processor N0 to the control unit 21 of the local public resource module Mm and provide the read data.
[0098] Method 2, for example, see Figure 4 Assuming that the first target processor with read / write access rights to the control unit 21 of the local public resource module Mm is processor Nn, and processors N0 to Nn-1 are all connected to the public resource module 02 via asynchronous bus 13a (specifically, connected to the mapping terminal 22a of the control unit of the public resource module Mm via asynchronous bus 13a, and then connected to the public resource module Mm via the mapping terminal 22a of the control unit of the public resource module Mm), then, for example, if the second target processor with read-only access rights to the mapping terminal 22a of the control unit of the local public resource module Mm (equivalent to the control unit 21 of the local public resource module Mm) is determined to be processor N0, then the processor N0 is further received via asynchronous bus 13a for read-only access to the mapping terminal 22a of the control unit of the local public resource module Mm (equivalent to the control unit 21 of the local public resource module Mm), and the read data is provided.
[0099] It should be noted that the first target processor and the second target processor mentioned above can be the same processor or different processors.
[0100] It should be noted that the division of units in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.
[0101] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0102] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A multi-core chip comprising a plurality of processors, characterized by, The multi-core chip also includes: a mapping terminal for the control unit of at least one common resource module; At least one of the processors is connected to the mapping terminal of the control unit of the common resource module via a synchronization bus, and enables read and write access to the mapping terminal of the control unit of the common resource module. Each of the processors is connected to the common resource module via an asynchronous bus and enables read-only access to the control unit of the common resource module; The mapping terminal of the control unit of the public resource module is the same as that of the control unit in the public resource module.
2. The multi-core chip of claim 1, wherein, The multi-core chip includes mapping terminals for control units of multiple common resource modules; wherein, the mapping terminal of each control unit of the common resource module is correspondingly configured with a processor, and different processors are connected to the mapping terminals of control units of different common resource modules through different synchronization buses.
3. The multi-core chip of claim 1, wherein, At least one of the processors is connected to the mapping terminal of the control unit of the common resource module via an asynchronous bus, and enables read-only access to the mapping terminal of the control unit of the common resource module.
4. The multi-core chip of claim 1, wherein, The multi-core chip also includes: At least one of the aforementioned public resource modules.
5. The multi-core chip of claim 4, wherein, The public resource module also includes: The control selection terminal is used to select a processor based on parameters in the control unit of the local public resource module, such that the selected processor can access the local public resource module for read and write operations via the bus.
6. The multi-core chip of claim 5, wherein, If the selected processor is a processor that reads and writes to the local public resource module through the synchronization bus, then the selected processor's read and write access to the local public resource module through the synchronization bus includes: synchronizing the mapping terminal of the control unit of the local public resource module connected to the selected processor with the control unit of the local public resource module.
7. A public resource access method, characterized by, Applied to the multi-core chip according to any one of claims 1 to 6, the method includes: Determine if the local processor obtains time-sharing exclusive read / write access to the public resource module; The synchronous bus enables read and write access to the mapping terminal of the control unit of the common resource module, and synchronizes the data in the mapping terminal of the control unit of the common resource module to the control unit of the common resource module.
8. The method of claim 7, wherein, The method further includes: When the local processor does not have time-sharing exclusive access to the public resource module, read-only access to the public resource module is achieved through the asynchronous bus.
9. A public resource access method, characterized by, Applied to the multi-core chip according to any one of claims 1 to 6, the method includes: When multiple processors are connected to the local public resource module through different synchronization buses, the first target processor with read and write access permissions to the control unit of the local public resource module is determined based on the parameters in the control unit of the local public resource module. Through a synchronization bus, the mapping terminal of the control unit of the local public resource module accessed by the first target processor for reading and writing is synchronized with the data of the control unit of the local public resource module.
10. The method of claim 9, wherein, The method further includes: When multiple processors are connected to the local public resource module via an asynchronous bus, a second target processor with read-only access rights to the control unit of the local public resource module is determined. The system receives a read-only access request from the second target processor with read-only access rights to the control unit of the local public resource module via an asynchronous bus, and provides the read data.