A multi-chip RFSoC high-speed data transmission method and system based on a master-slave architecture

Abstract

This invention belongs to the field of high-speed data transmission technology, specifically relating to a high-speed data transmission method and system based on a master-slave architecture with multiple RFSOC chips. It includes: one master RFSOC chip and multiple slave RFSOC chips. The master RFSOC chip is responsible for parameter issuance, instruction distribution, instruction parsing, data acquisition, data processing and storage, and DMA data readback functions; the slave RFSOC chips are responsible for instruction parsing, data acquisition, data processing and storage, and GTY data backhaul functions. Compared with existing technologies, the advantages of this invention are: the system adopts a master-slave architecture, uses RFSOC chips, establishes a hierarchical transmission mechanism, and maintains the master device's core control position while expanding the data acquisition capabilities of slave devices through high-speed interfaces through a combination of GTY and DMA instruction transmission, data backhaul, and data reading methods. Furthermore, the hierarchical transmission mechanism balances system throughput and data transmission efficiency.

Description

Technical Field

[0001] This invention belongs to the field of high-speed data transmission technology, specifically relating to a high-speed data transmission method and system for multi-chip RFSOC based on a master-slave architecture. Background Technology

[0002] With the rapid development of quantum computing, quantum communication and other fields, the demand for high-speed, high-precision, multi-channel synchronous data acquisition and high-speed data transmission is becoming increasingly urgent. However, traditional data acquisition systems face problems such as low efficiency of multi-node collaboration, insufficient real-time performance, and bottlenecks in massive data transmission in quantum computing, quantum communication and other scenarios.

[0003] Traditional data acquisition solutions typically employ a discrete architecture, consisting of an independent main control processor, an FPGA coprocessor, and multiple high-speed ADC chips. Data acquisition and transmission are achieved through JESD204B and PCIe interfaces. Master-slave devices communicate via RS485 / CAN bus, relying on hardware trigger lines and custom communication protocols for multi-device collaboration, resulting in significant performance bottlenecks. At the architectural level, there are limitations in cross-chip data transfer latency and interface bandwidth. Master-slave communication is constrained by bus speed, leading to large command latency. Expanding to multiple devices requires physical wiring and suffers from poor clock synchronization accuracy. The system's real-time performance and scalability are insufficient for high-precision applications such as ultra-high-speed, low-latency quantum computing. Summary of the Invention

[0004] This invention proposes a high-speed data transmission method and system for multi-chip RFSoC based on a master-slave architecture for quantum state readers. It addresses the issues of limited acquisition channels and slow data reading rates in traditional solutions by implementing parameter distribution from the master PS terminal, instruction distribution from the master PL terminal, instruction parsing from the master / slave PL terminals, RF-ADC data acquisition, data processing and storage, and DMA data readback during the radio frequency signal acquisition process. It is particularly suitable for multi-channel high-speed data acquisition systems.

[0005] The specific technical solution is a high-speed data transmission system based on a master-slave architecture for multiple RFSoC chips. The system adopts a one-master-multiple-slave architecture, and the master-slave interaction is carried out through GTY. It adopts an RFSoC chip, which integrates the processor, FPGA and high-performance ADC inside the chip, and the instruction interaction within the chip is carried out through AXI; Includes: one main RFSoC chip and multiple slave RFSoC chips. The main RFSoC chip is responsible for parameter distribution, instruction parsing, data acquisition, data processing and storage, and DMA data readback functions. The RFSoC chip is responsible for instruction parsing, data acquisition, data processing and storage, and GTY data backhaul functions.

[0006] Preferably, the main RFSoC chip has a built-in main PS terminal and a main PL terminal, and the slave RFSoC chip has a built-in slave PS terminal and a slave PL terminal. The main PL terminal is used to receive control commands issued by the main PS terminal, parse and generate configuration parameters and task commands corresponding to the slave RFSoC chip, and distribute the commands to the control execution unit of the main PL terminal or the slave PL terminal. Each RFSoC chip has a built-in multi-channel RF-ADC sampling channel and a data preprocessing module for the acquisition, preprocessing and forwarding of target signals.

[0007] Preferably, the master RFSoC chip and the slave RFSoC chip interact via a GTY10Gbps line rate.

[0008] Preferably, the main RFSoC chip has a built-in DMA unified backhaul module for aggregating all preprocessed data back from the RFSoC chip.

[0009] Preferably, it consists of one master RFSoC chip and multiple slave RFSoC chips.

[0010] A high-speed data transmission method for multi-chip RFSOC based on a master-slave architecture, employing the high-speed data transmission system described above, includes the following steps in the master / slave RFSOC signal acquisition and transmission process: Step S101: Send parameters from the main PS terminal; Step S102: Distribute instructions from the main PL terminal; Step S103: Master / Slave PL instruction parsing; Step S104: Master / Slave PL terminal data acquisition; Step S105: Master / Slave PL terminal data processing and storage; Step S106: Read DMA data from the main PS terminal.

[0011] Preferably, the instruction distribution method is as follows: the main RFSoC chip controls the main PS terminal to send parameters to the main PL terminal according to the configuration of user parameters. After the main PL terminal detects the control parameters, it determines whether they are main RFSoC parameters or slave RFSoC parameters, and completes the instruction distribution.

[0012] Preferably, GTY command transmission and data backhaul: The communication logic between the master and slave RFSoCs is completed through the GTY 10Gbps line rate. The PL end of the master RFSoC sends parameter commands to the PL end of the slave RFSoC through GTY to realize command transmission; the PL end of the slave RFSoC sends the stored data back to the PL end of the master RFSoC through GTY to realize data backhaul.

[0013] Preferably, DMA data reading: Data reading is mainly completed in the main RFSoC. When the PL receives the data reading command, it reads the data from the main / slave memory through DMA, realizes the rapid data back to the PS, and completes the data processing on the PS, displaying it in front of the user in the form of graphics or intuitive data to meet the user's data acquisition needs.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The system adopts a master-slave architecture, uses an RFSoC chip, establishes a hierarchical transmission mechanism, and maintains the master device's core control status through a combination of GTY and DMA command transmission, data return, and data reading methods. At the same time, it expands the data acquisition capabilities of slave devices through high-speed interfaces and balances system throughput and data transmission efficiency through the hierarchical transmission mechanism.

[0015] 2. It adopts an RFSoC chip, which integrates the processor, FPGA and high-performance ADC inside the chip. The chip has a high degree of integration and the instruction interaction within the chip is carried out through AXI, resulting in low latency and high accuracy.

[0016] 3. Master-slave interaction is conducted through GTY, which features high line speed and fast data exchange.

[0017] 4. Data transmission is achieved through DMA, resulting in high throughput, low latency, low CPU overhead, and high real-time performance. Attached Figure Description

[0018] Figure 1 This is a block diagram of the master-slave RFSoC high-speed data transmission system in this invention.

[0019] Figure 2 This is a flowchart of the master-slave RFSoC high-speed data transmission system. Detailed Implementation

[0020] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. However, this application can be implemented in many different forms and is not limited to the embodiments described in this specification. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0021] This invention employs a master-slave architecture. The PS (Power Switch) of the master RFSoC parses control commands through the PL (Power Line Controller). If a master control command is detected, the system directly controls the local RF-ADC to complete data acquisition, processing, and storage. Upon triggering a readback command, the data is transmitted back to the PS at high speed via DMA. If a slave device command is identified, the command is transmitted to the corresponding slave device's PL via the GTY (Gateway Technology) high-speed interface, triggering the slave device's RF-ADC to complete data acquisition and storage. During readback, the slave device's data is transmitted back to the master device's PL via GTY. Subsequently, the master device uploads multiple data streams to the PS via DMA, achieving high-speed data acquisition and transmission through master-slave collaboration. This architecture maintains the master device's core control role while expanding the slave device's data acquisition capabilities through a high-speed interface and balancing system throughput and transmission efficiency through a hierarchical transmission mechanism.

[0022] The main RFSoC, short for Radio Frequency System on Chip, is the main controller of the system. It is responsible for coordinating the acquisition, storage, and data interaction of local and multiple slave devices, and is the core control chip of the RF test and measurement system.

[0023] The PS (Processing System) side is the general-purpose processor part of the RFSoC chip based on the ARM architecture. It is responsible for running the operating system, upper-layer applications, control logic scheduling, and realizing functions such as human-computer interaction, algorithm processing, and system management. It is interconnected with the PL side through a high-speed internal bus.

[0024] The PL side, or Programmable Logic side, is the reconfigurable logic part of the RFSoC chip based on the FPGA architecture. It can realize functions such as high-speed data stream processing, interface protocol parsing, and real-time control logic through hardware programming. It has the advantages of parallel processing and low latency. In this application, it mainly undertakes tasks such as instruction parsing, data preprocessing, and high-speed interface control.

[0025] The local RF-ADC (Radio Frequency Analog-to-Digital Converter) is a dedicated analog-to-digital conversion module integrated within the main RFSoC. It can directly sample and quantize RF analog signals without the need for additional intermediate frequency conversion circuits. It supports direct sampling of RF signals at the GHz level and is used to realize the RF signal acquisition function of the main device.

[0026] DMA, or Direct Memory Access, is a technology that enables high-speed data transfer without the involvement of the processor. It uses a dedicated controller to directly transfer data in batches between peripherals and memory, and between memory modules, significantly reducing the processor load. It is used to achieve high-speed data transfer between the PL-side memory and the PS-side memory.

[0027] GTY, or Gigabit Transceiver Y, is a high-performance serial transceiver module integrated in FPGA / RFSoC chips. It supports transmission rates of up to tens of Gbps and can implement high-speed interface protocols such as PCIe, Ethernet, and JESD204B. In this application, it is used for high-speed interaction of command transmission and data acquisition between master and slave devices.

[0028] The slave device RF-ADC (Radio Frequency Analog-to-Digital Converter) is an RF-to-digital converter module integrated in the slave device's RFSoC. It receives control commands from the master device to complete the acquisition of RF signals for the corresponding channel. The sampled data is first stored locally on the slave device and then transmitted back to the master device through the GTY interface to achieve multi-channel synchronous acquisition expansion.

[0029] This paper proposes a high-speed data transmission method and system based on a master-slave architecture for multi-chip RFSoCs, primarily used in the radio frequency signal acquisition process of superconducting quantum computer measurement and control systems. This invention mainly focuses on improving the ADC signal acquisition and transmission process.

[0030] The working principle of the multi-chip RFSoC high-speed data transmission system proposed in this invention establishes a master-slave architecture, employing RFSoC chips. The processor, FPGA, and high-performance ADC are integrated within the chip, resulting in high chip integration. Intra-chip instruction interaction is performed via AXI, offering low latency and high precision. Master-slave interaction is performed via GTY, providing high line rates and fast data exchange. Data transmission is achieved through DMA, resulting in high throughput, low latency, low CPU overhead, and high real-time performance. The master RFSoC chip, acting as the master control chip, is primarily responsible for parameter issuance, instruction distribution, instruction parsing, data acquisition, data processing and storage, and DMA data readback functions. The slave RFSoC chips are primarily responsible for instruction parsing, data acquisition, data processing and storage, and GTY data return functions. The specific implementation details are explained in the following examples.

[0031] In one embodiment, the system mainly consists of one master RFSoC chip and two slave RFSoC chips, combined with Figure 1-2 Understandably, the main functional modules of the transmission system in this invention are as follows: Figure 1 As shown, the workflow is as follows Figure 2 As shown.

[0032] (I) Explanation of the structure and operation relationship of the technical solution like Figure 1 As shown, Figure 1 The master RFSoC chip is labeled as master, and the slave RFSoC chips are labeled as slave 1 and slave 2, respectively. The master RFSoC chip has a built-in master PS terminal and master PL terminal, and the slave RFSoC chips have built-in slave PS terminals and slave PL terminals. The master PL terminal is used to receive control commands issued by the master PS terminal, parse and generate the corresponding configuration parameters and task commands for the slave RFSoC chips, and distribute the commands to the control execution units of the master PL terminal or slave PL terminal. Each RFSoC chip has a built-in multi-channel RF-ADC sampling channel and a data preprocessing module for the acquisition, preprocessing, and forwarding of target signals.

[0033] like Figure 2 As shown, the master / slave RFSoC signal acquisition and transmission process in this invention includes the following steps: Step S101: Send parameters from the main PS terminal; Step S102: Distribute instructions from the main PL terminal; Step S103: Master / Slave PL instruction parsing; Step S104: Master / Slave PL terminal data acquisition; Step S105: Master / Slave PL terminal data processing and storage; Step S106: Read DMA data from the main PS terminal.

[0034] (II) Explanation of the Principles of the Technical Solution The key technical points and principles of this invention are explained below: 1. Main RFSoC instruction distribution In this invention, the main RFSoC chip acts as the master control chip. Based on user parameter configuration, it controls the main PS terminal to send parameters to the main PL terminal. After detecting the control parameters, the main PL terminal determines whether they are main or slave RFSoC parameters and then distributes the instructions. When it determines they are main RFSoC parameters, the instructions are directly sent to the main PL terminal control logic. When it determines they are slave RFSoC parameters, high-speed instruction transmission is achieved using a GTY 10Gbps line rate, sending the instructions to the slave RFSoC's PL terminal control logic. Figure 2 It can be from the 1PL end or from the 2PL end.

[0035] 2. Master / Slave RFSoC Data Acquisition In this invention, instruction parsing, data acquisition, processing, and storage are primarily implemented within the PL logic. When the PL receives a user instruction, it first parses the instruction to determine the user-selected acquisition channel and the required computational logic. Then, it controls the corresponding channel's RF-ADC to acquire data and performs logical operations and storage on the acquired data.

[0036] 3. Main RFSOC data reading In this invention, data reading is primarily completed within the main RFSoC. Upon receiving a data read command, the PL terminal reads data from the master / slave memory via DMA, enabling rapid data transmission back to the PS terminal. The PS terminal then processes the data and displays it graphically or intuitively to the user, meeting their data acquisition needs. When it is determined that data is being read from the main RFSoC, the main PL terminal directly retrieves the data from memory according to the read command and sends it to the PS terminal via DMA. When it is determined that data is being read from the slave RFSoC, the PL terminal first retrieves the data from memory according to the read command, then transmits the read data to the main PL terminal via GTY, and finally, the main PL terminal sends the data to the PS terminal via DMA. This data reading method, combining GTY and DMA, maintains the master device's core control role while expanding the slave device's data acquisition capabilities through a high-speed interface, and balances system throughput and data transmission efficiency through a hierarchical transmission mechanism.

[0037] 4. GTY command transmission and data return This solution utilizes the GTY 10Gbps line rate to establish communication between the master and slave RFSoCs. The master RFSoC's PL (Power Line Controller) sends parameter commands to the slave RFSoC's PL via the GTY, achieving command transmission. Conversely, the slave RFSoC's PL sends stored data back to the master RFSoC's PL via the GTY, achieving data return. This high-speed GTY interface facilitates master / slave interaction, expanding the slave device's data acquisition capabilities while improving transmission efficiency.

[0038] This invention presents a master-slave architecture system employing an RFSoC chip. It establishes a hierarchical transmission mechanism and maintains the master device's core control role through a combination of GTY and DMA for instruction transmission, data return, and data reading. This is achieved by extending the data acquisition capabilities of slave devices via high-speed interfaces and balancing system throughput and data transmission efficiency through the hierarchical transmission mechanism. The RFSoC chip integrates the processor, FPGA, and high-performance ADC internally, resulting in high chip integration. Intra-chip instruction interaction is performed via AXI, offering low latency and high accuracy. Master-slave interaction is conducted via GTY, providing high line rates and fast data exchange. Data transmission is achieved through DMA, resulting in high throughput, low latency, low CPU overhead, and high real-time performance.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A multi-chip RFSoC high-speed data transmission system based on master-slave architecture, characterized in that, The system adopts a master-slave architecture, with master-slave interaction conducted via GTY; It adopts an RFSoC chip, which integrates the processor, FPGA and high-performance ADC inside the chip, and the instruction interaction within the chip is carried out through AXI; Includes: one main RFSoC chip and multiple slave RFSoC chips. The main RFSoC chip is responsible for parameter distribution, instruction parsing, data acquisition, data processing and storage, and DMA data readback functions. The RFSoC chip is responsible for instruction parsing, data acquisition, data processing and storage, and GTY data backhaul functions.

2. The high-speed data transmission system for multiple RFSoCs based on a master-slave architecture according to claim 1, characterized in that, The main RFSoC chip has a built-in main PS terminal and a main PL terminal, while the slave RFSoC chip has a built-in slave PS terminal and a slave PL terminal. The main PL terminal is used to receive control commands issued by the main PS terminal, parse and generate the corresponding configuration parameters and task commands for the slave RFSoC chip, and distribute the commands to the control execution unit of the main PL terminal or the slave PL terminal. Each RFSoC chip has a built-in multi-channel RF-ADC sampling channel and a data preprocessing module, which are used to realize the acquisition, preprocessing and forwarding of target signals.

3. The multi-chip RFSoC high-speed data transfer system based on master-slave architecture of claim 1, wherein, The master RFSoC chip and the slave RFSoC chip interact via a GTY10Gbps line rate.

4. The high-speed data transmission system for multiple RFSoCs based on a master-slave architecture according to claim 1, characterized in that, The main RFSoC chip has a built-in DMA unified backhaul module, which is used to aggregate all preprocessed data returned from the RFSoC chip.

5. The multi-chip RFSoC high-speed data transfer system based on master-slave architecture of claim 1, wherein, It consists of one main RFSoC chip and multiple slave RFSoC chips.

6. A multi-chip RFSOC high-speed data transmission method based on a master-slave architecture, characterized in that, Using the system described in any one of claims 1-2, the master / slave RFSoC signal acquisition and transmission process includes the following steps: Step S101: Send parameters from the main PS terminal; Step S102: Distribute instructions from the main PL terminal; Step S103: Master / Slave PL instruction parsing; Step S104: Master / Slave PL terminal data acquisition; Step S105: Master / Slave PL terminal data processing and storage; Step S106: Read DMA data from the main PS terminal.

7. The multi-die RFSOC high-speed data transfer method based on master-slave architecture according to claim 6, wherein, Command distribution method: The main RFSoC chip controls the main PS terminal to send parameters to the main PL terminal according to the user parameter configuration. After the main PL terminal detects the control parameters, it determines whether they are main RFSoC parameters or slave RFSoC parameters, and completes the command distribution.

8. The multi-die RFSOC high-speed data transfer method based on master-slave architecture of claim 6, wherein, GTY command transmission and data feedback: The communication logic between the master and slave RFSoCs is completed through the GTY 10Gbps line rate. The PL end of the master RFSoC sends parameter commands to the PL end of the slave RFSoC through the GTY to realize command transmission; the PL end of the slave RFSoC sends the stored data back to the PL end of the master RFSoC through the GTY to realize data feedback.

9. The multi-die RFSOC high-speed data transfer method based on master-slave architecture of claim 6, wherein, DMA data reading: Data reading is mainly completed in the main RFSoC. When the PL receives the data reading command, it reads the data from the master / slave memory through DMA, realizes the rapid data back to the PS, and completes the data processing on the PS, displaying it to the user in a graphical or intuitive way to meet the user's data acquisition needs.

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