RISC-V anti-quantum SoC architecture and defense method based on dynamic semantic mask and global taint tracking
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-01
- Publication Date
- 2026-08-11
AI Technical Summary
此外，传统的防推测屏障与流水线冲刷（Pipeline Flush）不仅带来巨大的性能惩罚，其译码阶段单一静态掩码生成的控制逻辑也极易遭受电磁故障注入（EMFI）的单点打击
[0023]1、彻底免疫乱序微架构物理泄漏：本发明实施例通过高阶时间共享掩码（HO-TSM）架构和基于代码的掩码与阈值实现混合架构（CBM-TI）进行底层硬件架构重构，从物理和代数层面切断了寄存器重命名和公共数据总线串扰造成的掩码降维与模拟重组。
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Abstract
Description
Technical Field
[0001] This invention belongs to the interdisciplinary fields of microelectronic integrated circuit design, computer architecture and cryptography. It relates to a RISC-V quantum-resistant SoC architecture and defense method based on dynamic semantic masking and global taint tracing, especially for the design of RISC-V out-of-order processor microarchitecture for quantum-resistant cryptography (PQC) deployment. Specifically, it is an instruction set extension and system-on-a-chip (SoC) fusion scheme with immunity to common bus analog state crosstalk, resistance to register renaming leakage and resistance to transient execution attacks. Background Technology
[0002] In the deployment of post-quantum cryptography to embedded and edge devices, introducing tightly coupled cryptographic instruction set extensions (CISE) in RISC-V is the mainstream approach to improve computing power and energy efficiency. However, in pursuit of high performance, modern processors widely adopt microarchitectural mechanisms such as out-of-order execution, forwarding, and speculative execution.
[0003] Recent silicon-based physical side-channel tests demonstrate that traditional software masks or static fully pipelined masks face severe backlash from semiconductor analog physics in modern out-of-order microarchitectures. First, register renaming introduces register overwriting outside of software control, leading to a reduction in the mask's security order. Second, in dense common data buses (CDBs) and forward networks, the mask share of concurrent instructions generates physical coupling and crosstalk through parasitic capacitances in the underlying interconnects, allowing high-frequency electromagnetic probes to directly capture the key characteristics of "analog-state reassembly." Furthermore, traditional anti-speculation barriers and pipeline flushing not only incur significant performance penalties, but their single static mask generation control logic during the decoding stage is also highly susceptible to single-point attacks from electromagnetic fault injection (EMFI). Summary of the Invention
[0004] To address the aforementioned issues, this invention provides a RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking. Through dynamic semantic masking and global taint tracking, it ensures the efficient operation of quantum-resistant algorithms while being immune to side-channel attacks and speculative execution vulnerabilities, thereby improving physical-level security and reducing register resource overhead.
[0005] Another objective of this invention is to provide a defense method for RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking.
[0006] The technical solution adopted in this invention is a RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking, including a RISC-V out-of-order processor core. The core comprises a pipelined instruction fetch unit, a decoding unit, a register renaming unit, an out-of-order issue unit, an execution unit, and a write-back unit. The architecture also includes:
[0007] The domain detection layer and mask control unit are integrated into the decoding unit. They are used to dynamically identify the algebraic domain semantics of cryptographic instructions during the instruction decoding and distribution stage, and to perform dynamic randomization masking on operands transparently at the hardware level according to the algebraic domain semantics, thereby eliminating the dependence on a single fixed random number generation timing.
[0008] The tightly coupled quantum-resistant cryptographic functional unit is physically adjacent to the execution unit. It adopts a high-order time-sharing mask architecture and a hybrid architecture processing mask share based on code masking and thresholding to immunize the physical side channel leakage caused by register renaming and overwriting and data forwarding bus crosstalk at the microarchitecture physical layer.
[0009] The global taint tracking controller maintains a global taint mask to track the flow of sensitive data in the kernel pipeline. When speculative execution or context switching occurs, it performs fine-grained data isolation or memory encryption based on the global taint mask.
[0010] Furthermore, the domain detection layer infers whether the current instruction belongs to a key operation resistant to quantum cryptography by parsing the opcode, function code, and operand register address in the standard RISC-V instruction stream and combining them with the preset cryptographic algorithm status bits in the control and status register.
[0011] Furthermore, the mask control unit is configured to adaptively switch between Boolean mask, affine mask, and arithmetic mask according to the algebraic domain semantics, and to split plaintext operands into multiple random mask shares.
[0012] Furthermore, the transparency refers to transparency to the upper-layer software stack. When the hardware microarchitecture executes standard RISC-V cryptographic extension instructions, it automatically takes over the data on the underlying internal data path, completing the plaintext mask splitting, independent calculation, and reassembly.
[0013] Furthermore, the tightly coupled quantum-resistant cryptographic functional unit processes... During modulus multiplication and addition and physical shift truncation instructions, a high-order time-sharing mask architecture is used to implement cross-cycle glitch extension PINI security guarantees.
[0014] Furthermore, the underlying data path of the tightly coupled quantum-resistant cryptographic functional unit satisfies a strong non-interference property, thereby blocking key reconstruction through parasitic capacitance coupling radiation when multiple mask shares are transmitted concurrently on a common data bus or forward network.
[0015] Furthermore, the global taint mask is implemented in hardware as an array of metadata flag bits that are mapped one-to-one with the key microarchitectural structures of the processor.
[0016] Furthermore, the global taint tracking controller adds additional tracking fields to the reorder cache, reservation station, and memory access queue of the RISC-V out-of-order processor core to synchronize the taint marking of registered operands.
[0017] Furthermore, the global taint tracking controller establishes a linkage between the branch predictor, the out-of-order scheduler, and the system interrupt controller; only when a sensitive operand marked by the global taint mask enters an unresolved branch prediction or asynchronous interrupt stack sequence, an isolation latch is forcibly inserted at the functional unit entry point or a memory encryption engine is triggered to replace global pipeline flushing, thereby minimizing processor performance loss while ensuring defense against transient execution attacks.
[0018] A defense method for RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking includes the following steps:
[0019] S1. In the RISC-V instruction decoding and distribution stage, the domain detection layer identifies the dominant algebraic domain semantics of each quantum cryptographic instruction; in conjunction with the mask control unit, operand randomization is transparently performed within the hardware pipeline without modifying the instruction encoding, and the mask scheme is dynamically selected according to the instruction semantics.
[0020] S2. Within the tightly coupled quantum-resistant cryptographic functional unit, the underlying data path is upgraded to a high-order time-sharing mask architecture. Time-division multiplexing technology is used to alternately calculate different mask shares within the same physically tightly coupled quantum-resistant cryptographic functional unit. At the same time, a hybrid architecture is implemented by combining code-based masks and thresholds, and randomized registers that satisfy strong non-interference properties are inserted into the pipeline.
[0021] S3. Introduces a lightweight global taint masking mechanism to accurately track the flow of all sensitive data and instructions related to tightly coupled quantum-resistant cryptographic functional units; hardware-level operand isolation or transparent memory encryption is triggered only when a tainted sensitive operand enters an undecided branch or a stack sequence.
[0022] The beneficial effects of this invention are:
[0023] 1. Completely immune to physical leakage of out-of-order microarchitecture: The embodiments of the present invention reconstruct the underlying hardware architecture through a high-order time-shared mask (HO-TSM) architecture and a code-based mask and threshold implementation hybrid architecture (CBM-TI), which cuts off the mask dimensionality reduction and simulation reassembly caused by register renaming and crosstalk of the common data bus from the physical and algebraic levels.
[0024] 2. Adaptive Security with Zero-Code Modification: This invention utilizes a dynamic masking framework combining a field detection layer (FDL) and a mask control unit (MCU) to achieve security against different cryptographic algorithms (such as...) without modifying existing RISC-V extended instruction encoding. Runtime adaptive optimal mask protection (such as M2-KEM of the modulus).
[0025] 3. Extremely low hardware resource and performance overhead: The embodiments of the present invention utilize global taint masking mechanism, fine-grained anomaly tracking and defense module (TrackRISC-Defense) and other fine-grained tracking technologies to achieve anti-speculation execution side channel while only bringing negligible register resource overhead and extremely low performance penalty. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a diagram of the overall hardware architecture of the SoC in an embodiment of the present invention.
[0028] Figure 2 This is a flowchart of the defense method according to an embodiment of the present invention.
[0029] Figure 3 This is an instruction pipeline diagram of the integrated dynamic semantic mask in an embodiment of the present invention.
[0030] Figure 4 This is a flowchart of global taint tracking and anomaly handling in an embodiment of the present invention. Detailed Implementation
[0031] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0032] Example 1,
[0033] A RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking, such as Figure 1 As shown, it includes:
[0034] The RISC-V out-of-order processor core includes a pipelined instruction fetch unit, a decode unit, a register renaming unit, an out-of-order issue unit, an execution unit, and a write-back unit. Each unit is connected through internal data paths and control logic to support out-of-order instruction execution.
[0035] The Field Detection Layer (FDL) and the Mask Control Unit (MCU), integrated into the instruction decoding and distribution stage, dynamically identify the dominant algebraic field semantics of cryptographic instructions at runtime and transparently perform operand randomization within the pipeline, adaptively switching between Boolean, affine, or arithmetic masks based on the instruction semantics. The FDL and MCU perform operand mask splitting without modifying the original binary encoding of the RISC-V cryptographic extension instructions. This mechanism, through transparent mapping within the hardware pipeline, eliminates the dependence on a single fixed random number generation timing, thereby resisting electromagnetic fault injection (EMFI) attacks targeting the decoding stage.
[0036] Transparent mapping refers to being transparent to the upper-level software stack (including the programmer, compiler, operating system, and source code of the cryptographic algorithm). This means that software developers can write quantum-resistant cryptographic algorithms without modifying the original code or calling any special assembly instructions for masking operations. The hardware microarchitecture automatically takes over the data on the underlying internal data path when executing standard RISC-V cryptographic extension instructions, performing plaintext masking, independent computation, and reassembly. Because all of this is done automatically within the hardware, the upper-level software is completely unaware of this complex process—that is, it is transparent to the software.
[0037] The tightly coupled quantum-resistant cryptographic functional unit (hereinafter referred to as the cryptographic functional unit or CFU) is physically attached to the execution unit. Internally, it employs a high-order time-shared masking architecture (HO-TSM) and a code-based masking and thresholding hybrid architecture to process mask shares, thereby immune to register renaming / overwriting and data forwarding bus crosstalk at the microarchitecture physical layer. The cryptographic functional unit processes... When performing modulo-digital multiplication and addition and physical shift truncation instructions, the HO-TSM architecture is used to achieve cross-cycle glitch extension PNI security guarantee. At the same time, the multi-share physical routing of its underlying data path satisfies the strong non-interference (SNI) attribute limit to ensure that when multiple mask shares are transmitted concurrently on a common data bus or forwarding network, their parasitic capacitance coupling radiation cannot be used by high-frequency electromagnetic probes to reconstruct high-order key statistical moments.
[0038] The global taint tracking controller maintains a global taint mask to precisely track the state of cryptographic instructions and their derived data throughout the out-of-order pipeline, achieving fine-grained anti-speculation execution isolation and context switching protection. In hardware implementation, the global taint mask is an array of metadata flags that are mapped one-to-one with the processor's critical microarchitectural structures; in static data state, it is stored in an extended bit field of the physical register file; during dynamic instruction flow, these taint flags, along with operand tags, are synchronously registered in the reorder cache (ROB), reserved stations, and additional tracking fields of the memory access queue.
[0039] The global taint tracking controller establishes a linkage between the branch predictor, the out-of-order scheduler, and the system interrupt controller. The hardware will force the insertion of an isolation latch or trigger the memory encryption engine at the functional unit entry point only when a data operand marked as sensitive by the global taint mask encounters an unresolved branch prediction or asynchronous interrupt push. This replaces the traditional global pipeline flush, minimizing processor performance loss while ensuring defense against transient execution attacks.
[0040] This architecture employs a decoupled and parallel design to eliminate the timing pressure of taint propagation. First, the global taint mask is transmitted in parallel with the operand tag broadcast network as only 1-bit metadata, without occupying the load of the wide data bus, thereby reducing the RC latency of physical connections. Second, an early evaluation mechanism is adopted, in the wake-up and selection logic of the out-of-order issue phase, the taint state check and instruction dependency graph parsing are executed in parallel, and their time consumption is hidden in the original microarchitecture critical path, realizing zero-timing penalty for the arithmetic execution pipeline.
[0041] Example 2,
[0042] A defense method for RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking, such as Figure 2 As shown, it includes the following steps:
[0043] S1. Instruction Semantics Aware Dynamic Masking Framework (FDL+MCU):
[0044] like Figure 3As shown, in the RISC-V instruction decoding and distribution stage, a Field Detection Layer (FDL) is introduced to identify the dominant algebraic field semantics of each quantum-resistant instruction at runtime. The FDL parses the opcode, function code (Funct3 / Funct7), and operand register address in the standard RISC-V instruction stream, and combines this with the preset cryptographic algorithm status bits in the Control and Status Register (CSR) to infer whether the current instruction belongs to a key operation of quantum-resistant cryptography (PQC) (such as NTT transformation, polynomial multiplication, etc.). In conjunction with the Mask Control Unit (MCU), operand randomization is transparently performed within the hardware pipeline without modifying the instruction encoding, and Boolean, affine, or arithmetic masking schemes are dynamically selected based on the instruction semantics. When the FDL identifies sensitive instruction semantics, it sends a control signal to the Mask Control Unit (MCU). The MCU intercepts the plaintext operands read from the physical register file and automatically splits them into multiple random mask shares on the internal data path of the microarchitecture. Depending on whether the instruction is a Boolean operation (such as bitwise operations) or an arithmetic operation (such as modulo addition and multiplication), the MCU dynamically activates the corresponding Boolean or arithmetic mask hardware logic array via a multiplexer. All of this is done at the lowest hardware level, requiring no modification to the standard RISC-V instruction set encoding (ISA) executed at the upper layer. This dynamic allocation mechanism completely eliminates the single point of vulnerability inherent in static mask generation.
[0045] S2. Execution path of High-Order Time-Shared Mask (HO-TSM) for Immune Renaming and Crosstalk:
[0046] Within the cryptographic functional unit, the underlying data path is upgraded to a High-Order Time-Shared Mask (HO-TSM) architecture, significantly optimizing area and latency while providing Probe-Isolating Non-Interference (PINI) security. Simultaneously, a hybrid architecture (CBM-TI) is implemented using code-based masking and thresholding to defend against extreme combinational logic glitches under the Strong Non-Interference (SNI) security assumption. This microarchitecture's physical-level isolation completely prevents unintentional overwrite leaks caused by register renaming in the out-of-order core and dismantles analog electromagnetic coupling on the common data bus.
[0047] Traditional fully pipelined masking schemes typically require physically replicating the entire arithmetic logic unit (ALU) multiple times, resulting in extremely high area overhead. This invention employs a High-Order Time-Shared Masking (HO-TSM) architecture, utilizing time-division multiplexing technology to alternately compute different mask shares within the same physical cryptographic functional unit using different clock cycles. This avoids a significant increase in hardware combinational logic resources and greatly reduces area overhead. Combined with a code-based masking and thresholding implementation hybrid architecture (CBM-TI), randomized register barriers satisfying strong non-interference (SNI) properties are inserted between pipeline stages. This ensures that during multi-cycle time-division computation and common data bus (CDB) transmission, transient glitch and parasitic capacitance coupling on the physical interconnects do not lead to physical-level analog state recombination between different shares, thereby achieving physical-level side-channel isolation.
[0048] S3. Fine-grained speculative control based on global taint tracking:
[0049] like Figure 4 As shown, a lightweight global taint mask mechanism is introduced into the processor microarchitecture to accurately track the flow status of all sensitive data and instructions related to cryptographic functional units. When the processor experiences speculative execution, miss pauses, or operating system context switching, the system no longer performs coarse-grained global pipeline flushing. If the data is not sensitive (i.e., ordinary data), out-of-order scheduling and speculative execution are performed normally. When an exception is encountered, regular pipeline flushing is performed. Only when a tainted sensitive operand enters an unresolved branch or stack sequence is hardware-level operand isolation or transparent memory encryption triggered to replace global pipeline flushing.
[0050] The embodiments of this invention pertain to the defense of chip microarchitecture and integrated circuit hardware layers. They delve into the out-of-order execution pipeline of RISC-V processors and fundamentally solve the physical electromagnetic radiation leakage (SCA) at the transistor level of integrated circuits and transient execution vulnerabilities (such as Spectre attacks) caused by speculative execution of microarchitecture through hardware logic (FDL, MCU, HO-TSM).
[0051] The global taint tracing method of this invention addresses unintentional overwriting caused by physical register renaming and parasitic capacitance crosstalk on the common data bus (CDB) within the processor's microsecond-level pipeline. This invention not only simultaneously immunizes against two major hardware security vulnerabilities—physical side-channel attacks and transient execution attacks—at the same SoC level, but also achieves both performance and area optimization without modifying the original instruction set encoding or causing global pipeline flushing. It overcomes the technical difficulty in modern multi-issue out-of-order processors of resisting both stringent timing constraints and hardware interconnect coupling and glitches.
[0052] The advantage of this invention lies in achieving hardware root-of-trust level security, making it more suitable for edge computing nodes, Internet of Things (IoT) security chips, control MCUs for intelligent connected vehicles, and hardware security modules (HSMs). This is because devices in these scenarios are frequently exposed to physical attack environments, allowing attackers to easily place probes close to the chip to measure power consumption / electromagnetic radiation, or exploit speculative execution vulnerabilities to steal data.
[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.
Claims
1. A RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking, comprising a RISC-V out-of-order processor core, said core including a fetch unit, a decode unit, a register renaming unit, an out-of-order issue unit, an execution unit, and a write-back unit cascaded in a pipeline, characterized in that, The architecture also includes: The domain detection layer and the mask control unit are integrated into the decoding unit. They are used to dynamically identify the algebraic domain semantics of cryptographic instructions during the instruction decoding and distribution stage, and to perform dynamic randomization masking on operands transparently at the hardware level based on the algebraic domain semantics. The tightly coupled quantum-resistant cryptographic functional unit is physically adjacent to the execution unit. It adopts a high-order time-sharing mask architecture and a hybrid architecture processing mask share based on code masking and thresholding to immunize the physical side channel leakage caused by register renaming and overwriting and data forwarding bus crosstalk at the microarchitecture physical layer. The global taint tracking controller maintains a global taint mask to track the flow of sensitive data in the kernel pipeline. When speculative execution or context switching occurs, it performs fine-grained data isolation or memory encryption based on the global taint mask.
2. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The domain detection layer infers whether the current instruction belongs to a key operation resistant to quantum cryptography by parsing the opcode, function code, and operand register address in the standard RISC-V instruction stream and combining them with the preset cryptographic algorithm status bits in the control and status register.
3. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The mask control unit is configured to adaptively switch between Boolean masks, affine masks, and arithmetic masks according to the algebraic domain semantics, and to split plaintext operands into multiple random mask shares.
4. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The transparency refers to the transparency to the upper-layer software stack. When the hardware microarchitecture executes standard RISC-V cryptographic extension instructions, it automatically takes over the data on the underlying internal data path, and completes the plaintext mask splitting, independent calculation, and reassembly.
5. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The tightly coupled quantum-resistant cryptographic functional unit processes... During modulus multiplication and addition and physical shift truncation instructions, a high-order time-sharing mask architecture is used to implement cross-cycle glitch extension PINI security guarantees.
6. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 5, characterized in that, The underlying data path of the tightly coupled quantum-resistant cryptographic functional unit satisfies a strong non-interference property, thereby blocking key reconstruction through parasitic capacitance coupling radiation when multiple mask shares are transmitted concurrently on a common data bus or forward network.
7. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The global taint mask is implemented in hardware as an array of metadata flags that are mapped one-to-one with the key microarchitectural structures of the processor.
8. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The global taint tracking controller adds additional tracking fields to the reorder cache, reservation station, and memory access queue of the RISC-V out-of-order processor core to synchronize the taint marking of registered operands.
9. The RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking according to claim 1, characterized in that, The global taint tracking controller establishes a linkage between the branch predictor, the out-of-order scheduler, and the system interrupt controller; only when a sensitive operand marked by the global taint mask enters an unresolved branch prediction or asynchronous interrupt push sequence, an isolation latch is forcibly inserted at the functional unit entry point or a memory encryption engine is triggered to replace global pipeline flushing.
10. The defense method for RISC-V quantum-resistant SoC architecture based on dynamic semantic masking and global taint tracking as described in claim 1, characterized in that, Includes the following steps: S1. In the RISC-V instruction decoding and distribution stage, the domain detection layer identifies the dominant algebraic field semantics of each quantum-resistant cryptographic instruction; In conjunction with the mask control unit, operand randomization is performed transparently within the hardware pipeline without modifying the instruction encoding, and the mask scheme is dynamically selected based on the instruction semantics. S2. Within the tightly coupled quantum-resistant cryptographic functional unit, the underlying data path is upgraded to a high-order time-sharing mask architecture. Time-division multiplexing technology is used to alternately calculate different mask shares within the same physically tightly coupled quantum-resistant cryptographic functional unit. At the same time, a hybrid architecture is implemented by combining code-based masks and thresholds, and randomized registers that satisfy strong non-interference properties are inserted into the pipeline. S3. Introduces a lightweight global taint masking mechanism to accurately track the flow of all sensitive data and instructions related to tightly coupled quantum-resistant cryptographic functional units; hardware-level operand isolation or transparent memory encryption is triggered only when a tainted sensitive operand enters an undecided branch or a stack sequence.