A multi-threaded DSP based on VLIW architecture and a BNN calculation fusion method thereof

Abstract

The application provides a multi-threaded DSP based on a VLIW architecture and a BNN calculation fusion method thereof, the method performs BNN weight sparsification processing and generates a bit mask matrix, loads binary weights, a bit mask and input quantized values into VLIW general registers; performs XNOR operation after zero weight is shielded by the bit mask, performs Popcount operation and error detection based on the calculation result; dynamically determines a threshold value according to the distribution density of the last layer to obtain binary excitation values; analyzes and infers the complexity based on the binary excitation values, combines the load and priority of real-time control threads, and dynamically allocates VLIW execution units. The method realizes sparse BNN hardware acceleration and single-cycle bit operation, improves inference accuracy through a dynamic threshold, guarantees calculation reliability through hardware error correction, simultaneously dynamically schedules real-time control and AI inference, greatly reduces the loss of inference resources, and improves system energy efficiency, real-time performance and stability.

Description

Technical Field

[0001] This invention relates to the field of industrial automatic control technology, and in particular to a multi-threaded DSP based on VLIW architecture and its BNN calculation and fusion method. Background Technology

[0002] With the widespread application of wide-bandgap semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) in power electronics, the switching frequency of industrial control systems has increased from tens of kilohertz to hundreds of kilohertz or even megahertz, placing unprecedentedly stringent demands on the real-time performance, computing power, and energy efficiency of controllers. Meanwhile, intelligent algorithms based on artificial intelligence, such as fault diagnosis, state prediction, and adaptive control, are gradually being integrated into industrial control systems. Binary neural networks, with their extremely low computational complexity and memory footprint, have become the preferred solution for deploying AI algorithms in embedded systems.

[0003] Currently, mainstream DSP products in the industrial control field mostly adopt VLIW architecture and hardware multithreading technology to achieve high parallel computing and real-time task scheduling. However, traditional DSPs have a significant architectural mismatch problem when processing binary neural networks: their instruction sets are mainly optimized for floating-point and fixed-point operations, lacking native bitwise operation instruction support. They need to convert 1-bit binary weights and input data into 32-bit or 64-bit full-precision data before performing multiplication and addition operations. This not only leads to more than 90% waste of computing resources, but also creates a serious memory bandwidth bottleneck. Meanwhile, existing technologies for implementing BNN computation on multi-threaded DSPs based on VLIW architecture still have many shortcomings: 1) They do not utilize the weight sparsity commonly found in BNNs, and still perform invalid XNOR and Popcount operations on zero weights, wasting a lot of computing resources; 2) They adopt a static multi-threaded resource allocation method, which cannot dynamically adjust computing resources according to real-time task load and AI inference complexity, resulting in excessive control task latency under high load or idle computing resources under low load; 3) They use a preset fixed threshold for binarization decision, which cannot adapt to the distribution differences of different input samples; 4) They can only process each network layer of BNN serially, and cannot fully utilize the multi-issue capability of VLIW architecture to achieve inter-layer pipeline parallelism, thus limiting the overall inference throughput. Summary of the Invention

[0004] The purpose of this invention is to provide a multi-threaded DSP based on VLIW architecture and its BNN computation fusion method. By reconstructing the VLIW architecture and integrating sparse BNN computation, dynamic threshold decision and hardware error correction, the energy efficiency, real-time performance and inference accuracy of BNN computation of multi-threaded DSP can be improved.

[0005] To achieve the above objectives, the present invention provides the following solution: A multi-threaded DSP and its BNN computation fusion method based on VLIW architecture includes the following steps: The weights of the BNN are sparsified and the corresponding bit mask matrix is ​​generated. The binary weight matrix, bit mask matrix and input quantization value are loaded into the VLIW general-purpose register to obtain the weight vector, bit mask vector and input vector. The intermediate result vector is obtained by performing a bitwise AND operation on the weight vector and the input vector using the bitmask vector, and then performing an XNOR operation on the masked weight vector and the input vector. The intermediate result vector is mapped to a dedicated hardware counting pipeline, and Popcount and error detection operations are performed to obtain the accumulated result and error detection signal. The dynamic decision threshold of the current layer is calculated based on the distribution density of the output of the previous layer in the VLIW general-purpose register, and the accumulated result is compared with the dynamic decision threshold to obtain the binary excitation value of the next layer. Complexity inference is performed on the binary stimulus values, and the VLIW execution units are dynamically allocated to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread.

[0006] Optionally, the specific steps of the sparsity reduction process include: Sort the trained BNN weights by absolute value; Based on a preset sparsity threshold, the weights of items whose absolute values ​​are less than the sparsity threshold are set to zero. The non-zero weights are quantized to +1 or -1 to obtain a binary weight matrix; A bitmask matrix is ​​generated based on the binary weight matrix; in the bitmask matrix, 1 indicates that the weight at the corresponding position is non-zero, and 0 indicates that the weight at the corresponding position is zero.

[0007] Optionally, the BNN weights are sparsified to generate a corresponding bitmask matrix, and the binary weight matrix, bitmask matrix, and input quantized values ​​are loaded into a VLIW general-purpose register to obtain a weight vector, bitmask vector, and input vector, including: The binary weight matrix is ​​divided into multiple weight vectors by rows, and each weight vector contains N binary weights; The bitmask matrix is ​​divided into multiple bitmask vectors by rows, and each bitmask vector has the same length as the corresponding weight vector. The input quantized values ​​are divided into multiple input vectors by columns, and each input vector contains N binary inputs; The weight vector, bitmask vector, and input vector are loaded into three separate register files in the VLIW general-purpose register set.

[0008] Optionally, the bitmask vector is used to perform a bitwise AND operation on the weight vector and the input vector, and an XNOR operation is performed on the masked weight vector and the input vector to obtain an intermediate result vector, including: During the instruction issuance phase, the weight vector, bitmask vector, and input vector are read simultaneously from three register files; In the first sub-cycle of the execution phase, a bitwise AND operation is performed on the weight vector based on the bitmask vector to obtain the masked weight vector. In the second sub-cycle of the execution phase, a bitwise AND operation is performed on the input vector based on the bitmask vector to obtain the masked input vector; In the third sub-cycle of the execution phase, an XNOR operation is performed on the masked weight vector and the masked input vector to obtain an intermediate result vector.

[0009] Optionally, the intermediate result vector is mapped to a dedicated hardware counting pipeline, and Popcount and error detection operations are performed to obtain the accumulated result and error detection signal, including: The intermediate result vector is input into the parallel Popcount calculation unit to obtain the accumulated result; the Popcount calculation unit consists of N 1-bit adders, which are used to complete the counting of N bits in one clock cycle; The intermediate result vector is input into the parity calculation unit to calculate the parity bit of the intermediate result vector; The parity bit is compared with the pre-stored parity bit; if they do not match, an error detection signal is obtained. If the error detection signal is a single-bit error, the accumulated result is automatically corrected by the hardware error correction circuit; if the error detection signal is a multi-bit error, an interrupt signal is generated and the CPU is notified to process it.

[0010] Optionally, the dynamic decision threshold of the current layer is calculated based on the distribution density of the previous layer's output in the VLIW general-purpose register, and the accumulated result is compared with the dynamic decision threshold to obtain the binary excitation value of the next layer, including: Count the number of "1"s in the binary excitation values ​​output by the previous layer, and record the count as C; The distribution density of the output of the previous layer is calculated based on C; the formula for calculating the distribution density is: Where D is the distribution density, This represents the total number of neurons output from the previous layer. Based on the distribution density and preset accuracy requirements, the dynamic decision threshold for the current layer is calculated; the formula for calculating the dynamic decision threshold is: Where T is the dynamic decision threshold. This is the proportionality coefficient. This is the offset. This represents the number of inputs to each neuron in the current layer. Load the dynamic decision threshold into a dedicated threshold register; The accumulated result is compared with the dynamic decision threshold. If the accumulated result is greater than or equal to the dynamic decision threshold, the output binary stimulus value is "1"; if the accumulated result is less than the dynamic decision threshold, the output binary stimulus value is "0".

[0011] Optionally, complexity inference is performed on the binary stimulus values, and the VLIW execution units are dynamically allocated to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread, including: Count the number of "1"s in the binary excitation values ​​output by the current layer, and record the count as K; The inference complexity index of the current layer is calculated based on K; the formula for calculating the inference complexity index is: , where R is the reasoning complexity index and Q is the total number of neurons output by the current layer; Reasoning tasks are classified into different levels of reasoning complexity based on the reasoning complexity index; the reasoning complexity levels include: low complexity, medium complexity, or high complexity.

[0012] Optionally, the complexity inference of the binary stimulus values ​​is performed, and the VLIW execution units are dynamically allocated to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread. This also includes: The task queue length and task priority of the real-time control thread are monitored using a hardware priority detector; When the task priority is the highest, 75% of the VLIW execution units are allocated to the control thread, and the remaining 25% of the VLIW execution units continue to perform AI inference tasks. When the task priority is not the highest, VLIW execution units are allocated according to the reasoning complexity level. When the task queue length is empty, all VLIW execution units are allocated to the AI ​​inference thread.

[0013] Optionally, when the task priority is not the highest, VLIW execution units are allocated according to the inference complexity level, including: When the inference complexity level is low, 25% of the VLIW execution units are allocated to the AI ​​inference thread, and the remaining 75% of the VLIW execution units are allocated to the control thread. When the inference complexity level is medium, allocate 50% of the VLIW execution units to the AI ​​inference thread and allocate the remaining 50% of the VLIW execution units to the control thread. When the inference complexity level is high, 75% of the VLIW execution units are allocated to the AI ​​inference thread, and the remaining 25% of the VLIW execution units are allocated to the control thread.

[0014] Optionally, when three consecutive BNN layers are all of high complexity, the priority of the AI ​​inference thread is increased by one level; when three consecutive BNN layers are all of low complexity, the priority of the AI ​​inference thread is decreased by one level; the priority range of the AI ​​inference thread is: lower than the highest priority control thread and higher than the lowest priority background thread.

[0015] According to specific embodiments provided by the present invention, the following technical effects are disclosed: The multi-threaded DSP and its BNN calculation fusion method based on VLIW architecture provided by the present invention include: performing sparsification processing on the BNN weights and generating corresponding bitmask matrices, and loading the binary weight matrix, bitmask matrix and input quantization value into the VLIW general-purpose register to obtain a weight vector, a bitmask vector and an input vector; performing a bitwise AND operation on the weight vector and input vector through the bitmask vector, and performing an XNOR operation on the masked weight vector and input vector to obtain an intermediate result vector; mapping the intermediate result vector to a dedicated hardware counting pipeline, and performing Popcount operation and error detection operation to obtain an accumulation result and an error detection signal; calculating the dynamic decision threshold of the current layer according to the distribution density of the output of the previous layer in the VLIW general-purpose register, and comparing the accumulation result with the dynamic decision threshold to obtain the binary stimulus value of the next layer; performing complexity inference on the binary stimulus value, and dynamically allocating the VLIW execution unit to the AI ​​inference thread and the real-time control thread in combination with the task load and priority of the real-time control thread. This method achieves hardware acceleration of sparse BNN and single-cycle bit operations, improves inference accuracy through dynamic thresholding, ensures computational reliability by combining hardware error correction, and balances real-time control and AI inference with dynamic scheduling, significantly reducing the consumption of training resources and improving system energy efficiency, real-time performance and stability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a multi-threaded DSP and its BNN computation fusion method based on the VLIW architecture, according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1 As shown, this embodiment of the invention provides a multi-threaded DSP and its BNN computation fusion method based on VLIW architecture, including the following steps: Step 100: Sparsify the BNN weights and generate the corresponding bit mask matrix. Load the binary weight matrix, bit mask matrix and input quantization value into the VLIW general-purpose register to obtain the weight vector, bit mask vector and input vector. Step 200: Perform a bitwise AND operation on the weight vector and the input vector using the bitmask vector, and then perform an XNOR operation on the masked weight vector and the input vector to obtain an intermediate result vector; Step 300: Map the intermediate result vector to a dedicated hardware counting pipeline, and perform Popcount and error detection operations to obtain the accumulated result and error detection signal; Step 400: Calculate the dynamic decision threshold of the current layer based on the distribution density of the output of the previous layer in the VLIW general-purpose register, and compare the accumulated result with the dynamic decision threshold to obtain the binary excitation value of the next layer; Step 500: Perform complexity inference on the binary stimulus value, and dynamically allocate the VLIW execution unit to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread.

[0021] In the specific implementation process, step 100 realizes two core stages: offline weight preprocessing and online data loading. In this embodiment, the offline preprocessing stage is executed after the model training is completed. First, the full-precision weight matrix of the first convolutional layer of the 3-layer BNN model optimized for industrial motor bearing fault diagnosis is obtained. Its original size is 32×3×3×3 (32 output channels, 3 input channels, 3×3 convolutional kernels). After being expanded into a two-dimensional calculation matrix, the size is 32 rows × 27 columns, containing a total of 864 single-precision floating-point weight elements. After calculating the absolute value of each of the 864 weight elements, they are sorted in global ascending order. According to the design principle of "precision first, energy efficiency second" in industrial control scenarios, a 75% structured sparsity threshold is preset, that is, the 216 weights with the largest absolute value are retained, and the remaining 648 weights with absolute values ​​less than the threshold are forcibly set to zero, thus completing the structured sparsity processing of the weights. Then, a symbolic binarization mapping is performed on the non-zero weights: elements with weight values ​​greater than 0 are quantized to binary "1" (corresponding to +1 in logical operations), and elements with weight values ​​less than 0 are quantized to binary "0" (corresponding to -1 in logical operations), generating a 32×27 binary weight matrix. Based on this binary weight matrix, a corresponding bitmask matrix is ​​generated element by element. For each position (i,j) in the matrix, if the binary weight matrix [i][j] ≠ 0, the bitmask matrix [i][j] is set to "1"; if the binary weight matrix [i][j] = 0, the bitmask matrix [i][j] is set to "0". The size of the bitmask matrix is ​​exactly the same as that of the binary weight matrix, and each element occupies only 1 bit of storage space.

[0022] The online data loading phase is dynamically executed during system power-on initialization and inference. Upon system power-on, the DMA controller, connected via the AXI4 high-speed bus, transfers the binary weight matrix and bitmask matrix stored in the external QSPI Flash in batches of 128-bit burst transfers (burst length = 16) to the dedicated weight buffer and bitmask buffer in the on-chip 256KB high-speed SRAM. During the transfer, a DMA hardware CRC-16 check mechanism is enabled, performing cyclic redundancy checks on every 128-bit data block. If the check fails, a retransmission is automatically triggered to ensure data transmission integrity. Regarding real-time input data, the motor vibration signal sample values ​​from the 12-bit ADC are first processed by a hardware binary quantization unit: the current sample value is compared with the dynamic zero point calculated from the moving average of the previous 100 sample values. Values ​​greater than or equal to zero are quantized as "1", and values ​​less than zero are quantized as "0", generating an input vector sequence of length 27.

[0023] Furthermore, following the 64-bit physical width of the VLIW general-purpose registers in this embodiment, all matrices and vectors are divided into 64-bit aligned vectors. For the binary weight matrix, it is divided into 32 weight vectors by row, each original weight vector having a length of 27. Any portion shorter than 64 bits is padded with 37 zeros at the end to form a 64-bit aligned standard weight vector. The corresponding bitmask matrix is ​​divided into 32 64-bit aligned bitmask vectors by row, with the bitmask elements corresponding to the zero-padding positions uniformly set to "0". For the input vector sequence, it is divided into one 27-bit input vector by column, similarly padded with 37 zeros to form a 64-bit aligned standard input vector. The divided vectors are loaded in batches into three independent physical register files of the VLIW general-purpose register group: weight vectors are loaded into a dedicated weight register file (WRF), bitmask vectors into a dedicated bitmask register file (MRF), and input vectors into a dedicated input register file (IRF). Each register file contains 32 64-bit physical registers. Hardware register renaming technology is used to dynamically map physical registers to logical registers, automatically resolving data-related conflicts between instructions during read-after-write (RAW) and write-after-read (WAR) operations, thereby improving instruction-level parallelism.

[0024] Furthermore, this embodiment employs a ping-pong double buffering mechanism to achieve complete overlap between data preloading and computation. Each independent register file is divided into two buffers, each containing 16 registers, labeled Buffer A and Buffer B, respectively. During inference, when a vector in Buffer A is being used by the VLIW execution unit for computation of the current neuron, the DMA controller automatically initiates a background transfer, preloading the weight vector, bitmask vector, and input vector corresponding to the next neuron into the idle Buffer B. Once all vectors in Buffer A have been computed, a seamless switch between buffers is achieved through a single-cycle register file switching instruction. At this point, Buffer B becomes the current computation buffer, while Buffer A begins preloading the corresponding data for the next neuron. This mechanism completely hides the data transfer time within the computation time, eliminating the constraint of data loading latency on inference speed inherent in traditional DSPs.

[0025] It should be noted that step 100 eliminates redundant weights in the BNN model through offline structured sparsity processing, significantly reducing the amount of invalid XOR NOT and bit counting operations from the source. At the same time, the generated bitmask matrix, which can be directly parsed by hardware, provides precise control signals. Furthermore, the vectorized partitioning method, which precisely matches the physical bit width of the VLIW register, fully utilizes the single instruction multiple data parallel computing capability of the VLIW architecture. Meanwhile, the use of three independent dedicated register files avoids access conflicts between different types of data, significantly improving the VLIW instruction issue efficiency and execution throughput. The introduction of the ping-pong double buffering mechanism enables complete overlap and parallelism of data transmission and computation operations, eliminating the memory bandwidth bottleneck commonly found in traditional DSPs that limits the BNN inference speed.

[0026] In the specific implementation process, step 200 is performed on an industrial control-specific DSP platform based on a 64-bit superscalar VLIW architecture. Relying on the VLIW's multi-issue instruction architecture and three-stage sub-cycle pipeline execution mechanism, the entire process is completed within a single clock cycle. In this embodiment, the DSP's main frequency is 500MHz, with a single clock cycle of 2ns, internally divided into three equal-length sub-cycles, each approximately 667ps. Specifically, during the compilation phase, the VLIW compiler packages the weight masking, input masking, and XNOR operation into a single Very Long Instruction Word (VLIW) containing three operation slots, with an instruction length of 192 bits. Each operation slot corresponds to an independent Arithmetic Logic Unit (ALU). During the instruction issuance phase, the VLIW instruction scheduler simultaneously sends read requests to three independent register files: the dedicated weight register file (WRF) to read the 64-bit weight vector W[63:0] corresponding to the current neuron, the dedicated bitmask register file (MRF) to read the corresponding 64-bit bitmask vector M[63:0], and the dedicated input register file (IRF) to read the corresponding 64-bit input vector X[63:0]. The three read operations are executed in complete parallel without any access conflicts, and the total time does not exceed one subcycle.

[0027] The first sub-cycle of the execution phase completes the bitwise AND masking operation of the weight vector. This operation is performed by a dedicated weight masking hardware unit consisting of 64 parallel 1-bit AND gates. Each bit M[i] of the bitmask vector serves as the control signal for the corresponding AND gate, and each bit W[i] of the weight vector serves as the data input for the corresponding AND gate. For each bit i (0≤i≤63), the logic of the bitwise AND operation is: masked weight bit W'[i] = W[i] & M[i]. When M[i] = 0, regardless of the value of W[i], W'[i] is always 0 to completely mask the calculated bit corresponding to zero weight; when M[i] = 1, W'[i] is equal to the original weight bit W[i] to retain the valid weight information. Since all 64 bitwise AND operations are executed in parallel, the entire weight masking process can be completed at the end of the first sub-cycle, and the result is directly latched into the output register of the weight masking unit, waiting for the operation of the next sub-cycle.

[0028] The second sub-cycle of the execution phase completes the bitwise AND masking operation of the input vector. This operation is performed by a dedicated input masking hardware unit consisting of 64 parallel 1-bit AND gates, and its working principle is exactly the same as that of the weight masking unit: each bit M[i] of the bitmask vector serves as the control signal for the corresponding AND gate, and each bit X[i] of the input vector serves as the data input for the corresponding AND gate. For each bit i (0≤i≤63), the logic of the bitwise AND operation is: masked input bit X'[i] = X[i] & M[i]. When M[i] = 0, X'[i] is always 0, masking the invalid calculation of the corresponding input bit; when M[i] = 1, X'[i] is equal to the original input bit X[i], retaining the valid input information. This operation is also completed within one sub-cycle, and the result is latched into the output register of the input masking unit. It is worth noting that the VLIW pipeline uses an overlapped execution mechanism, where the input masking operation is being performed by the current instruction while the weight masking operation has already begun by the next instruction, achieving instruction-level pipeline parallelism and further improving the overall computational throughput.

[0029] The third sub-cycle of the execution phase completes the XNOR (Exclusive NOR) operation between the masked weight vector and the masked input vector. This operation is performed by a dedicated XNOR calculation unit consisting of 64 parallel 1-bit XNOR gates, whose inputs are the masked weight vector W'[63:0] and the masked input vector X'[63:0] generated in the first two sub-cycles. For each bit i (0≤i≤63), the logic of the XNOR operation is: intermediate result bit R[i]=~(W'[i]^X'[i]), that is, when W'[i] and X'[i] have the same value, R[i] outputs 1; when they have different values, R[i] outputs 0. From the perspective of BNN computation principles, this XNOR operation is equivalent to the multiplication of binary weights and binary inputs: when the weight is 1 and the input is 1, the product is 1, corresponding to R[i]=1; when the weight is -1 and the input is 1, the product is -1, corresponding to R[i]=0; when the weight is 1 and the input is -1, the product is -1, corresponding to R[i]=0; when the weight is -1 and the input is -1, the product is 1, corresponding to R[i]=1. All 64-bit XNOR operations are executed in parallel, generating a complete 64-bit intermediate result vector R[63:0] at the end of the third sub-cycle, and writing it directly to the dedicated intermediate result register file (IRRF).

[0030] It should be noted that step 200 achieves real-time hardware-level filtering of the computational bits corresponding to zero weights through dual-path bitwise AND masking operations driven by bitmasks, avoiding invalid XNOR operations performed on zero weights and reducing the amount of XNOR computation. Relying on the multi-issue instruction capability and three-stage sub-cycle pipeline design of the VLIW architecture, the three operations of weight masking, input masking, and XNOR operation are integrated into a single clock cycle, realizing single-cycle execution of 64-bit parallel bit operations and improving the calculation speed. Furthermore, a dedicated hardware computing unit is used, eliminating the dependence on floating-point and fixed-point operations and eliminating the need for data type conversion, which significantly reduces the consumption of computing resources and energy. At the same time, the pipelined overlapping execution mechanism further improves the instruction-level parallelism, providing extremely high computational throughput for the entire BNN inference process, and significantly improving the system's real-time performance and energy efficiency.

[0031] In the specific implementation process, step 300 is also implemented on an industrial control-specific DSP platform based on a 64-bit superscalar VLIW architecture, relying on a dedicated two-stage hardware counting pipeline independent of the general-purpose execution unit. Specifically, the 64-bit intermediate result vector R[63:0] is stored in a dedicated intermediate result register file (IRRF). When the VLIW instruction scheduler issues a dedicated instruction, the intermediate result vector is directly mapped to the entry register of the dedicated counting pipeline. For neurons with more than 64 inputs, the pipeline has a built-in 32-bit auto-accumulator register, which automatically accumulates the Popcount results of multiple consecutive 64-bit vectors until all input vectors have been processed. In this embodiment, the number of inputs for each neuron in the first layer of the motor fault diagnosis BNN model is 27, so the calculation result of a single 64-bit vector is the initial accumulation result of that neuron.

[0032] The dedicated Popcount calculation unit adopts a 64-input binary tree adder structure, which consists of 63 1-bit full adders and half adders cascaded in layers, forming a 6-level fully parallel addition tree. The first stage divides the 64-bit input into 32 groups of 2 bits each, and uses 32 half-adders to count the number of 1s in each group, outputting 32 2-bit intermediate results. The second stage divides these 32 2-bit results into 16 groups of 2 bits each, and uses 16 full adders to sum each group, outputting 16 3-bit intermediate results. The third stage divides these 16 3-bit results into 8 groups of 2 bits each, and uses 8 full adders to output 8 4-bit intermediate results. The fourth stage divides these 8 4-bit results into 4 groups of 2 bits each, and uses 4 full adders to output 4 5-bit intermediate results. The fifth stage divides these 4 5-bit results into 2 groups of 2 bits each, and uses 2 full adders to output 2 6-bit intermediate results. The sixth stage adds the 2 6-bit results using a single full adder to obtain the final 7-bit Popcount result. Intermediate results are latched between each adder stage via edge-triggered registers to ensure all operations are completed within one clock cycle.

[0033] This embodiment employs an extended two-dimensional parity check (EDC) mechanism to achieve automatic single-bit error correction. First, the 64-bit intermediate result vector is logically organized into an 8x8 two-dimensional matrix. The hardware simultaneously calculates the row parity bit and the column parity bit for each row and column, generating a total of 8 row parity bits and 8 column parity bits, forming a 16-bit real-time parity code. During the offline preprocessing stage, for each weight vector and its corresponding bitmask vector, the expected two-dimensional parity code for all valid input combinations is calculated through simulation and stored together with the binary weight matrix in a dedicated parity code buffer in the on-chip SRAM. During runtime, when the intermediate result vector enters the verification unit, the hardware automatically calculates its real-time parity code and reads the corresponding pre-stored expected parity code through a dedicated cache port accessed in a single cycle. The two are then XORed bit-by-bit to generate an error signature.

[0034] Furthermore, if all error signature bits are 0, it indicates that the intermediate result vector has no bit errors, and the result output by the Popcount calculation unit is directly used as the valid accumulation result. If exactly one row parity bit and one column parity bit in the error signature are 1, it is determined to be a single-bit error. The hardware accurately locates the flipped bit in the intermediate result vector based on the error row and column numbers, automatically inverts and corrects the bit, and re-inputs it into the Popcount calculation unit to obtain the correct accumulation result. If multiple row parity bits or multiple column parity bits in the error signature are 1, it is determined to be a multi-bit error that cannot be automatically corrected. The hardware immediately generates a non-maskable interrupt (NMI) signal and sends it to the interrupt controller of the DSP core. At the same time, it stores the erroneous intermediate result vector, real-time checksum, expected checksum, and current neuron number into a dedicated error status register set for the CPU to perform fault diagnosis and processing. The corrected valid accumulation result is finally written to a dedicated accumulation result register file.

[0035] It should be noted that step 300 achieves complete parallelism between the core bit counting operation and general control calculation of the BNN through an independent dedicated hardware counting pipeline. The 64-bit tree adder structure ensures the completion of the bit counting operation in a single cycle, significantly improving the calculation speed and eliminating the constraint of bit counting operation on the BNN inference speed. Furthermore, based on the introduced extended two-dimensional parity check mechanism, not only is real-time error detection achieved during the calculation process, but also instantaneous single-bit hardware faults are automatically corrected, greatly improving the reliability and stability of BNN calculation in industrial control scenarios and avoiding system loss of control due to calculation errors. The hardware automatic accumulation mechanism and transparent error correction mechanism do not require any software intervention, significantly reducing the CPU load. At the same time, the hierarchical interrupt handling mechanism for multi-bit errors ensures the system's fault recoverability.

[0036] In the specific implementation, the Popcount operation in steps 400 and 300 is executed in complete parallel, without increasing the total latency of BNN inference. The statistical process of the output distribution density of the previous layer starts immediately after all neurons in the previous layer have outputted, and is executed by a dedicated 32-bit hardware Popcount statistical unit independent of the general ALU. The 27 binary activation values ​​output from the input layer are fed into this statistical unit in parallel, with high-order bits automatically padded with 0s to 32-bit alignment. The statistical unit uses the same tree-structured adder as step 300, and completes the counting of the number of "1"s in the 27 binary values ​​within one clock cycle to obtain the count value C. Subsequently, the hardware calculates the Popcount value according to the distribution density formula. The distribution density D of the output of the previous layer is automatically calculated, where M is the total number of neurons in the output of the previous layer. In this embodiment, M=27.

[0037] The calculation of the dynamic decision threshold is executed in parallel by a dedicated 16-bit fixed-point arithmetic unit, starting simultaneously with the Popcount operation of the first neuron in the current layer. The hardware reads the scaling factor obtained from offline calibration for motor fault diagnosis scenarios from a dedicated parameter area of ​​the on-chip SRAM. =0.8 and offset =-2, according to the dynamic threshold formula Perform calculations. This represents the number of inputs to each neuron in the current layer. In this embodiment, M=N=27, and the formula can be simplified to: Substituting C=15, we get T=0.8×15-2=10. This calculation process uses 16-bit fixed-point arithmetic, with a precision set to 8 integer bits and 8 decimal bits. The calculation of the dynamic threshold can be completed before the accumulation result of the first neuron in the current layer is generated, ensuring that the threshold is ready when the accumulation result reaches the comparison unit, without any waiting delay.

[0038] Furthermore, the calculated dynamic decision threshold T is immediately loaded into a dedicated 64-bit threshold register in the VLIW architecture. This register has single-cycle read / write capability and can be automatically reloaded before each network layer calculation. Subsequently, the accumulated result of each neuron is sequentially fed into a dedicated comparator for parallel comparison with the dynamic threshold in the threshold register. If the accumulated result is greater than or equal to the dynamic threshold T, the output binary activation value is "1"; if the accumulated result is less than the dynamic threshold T, the output is "0". The generated 32 binary activation values ​​are simultaneously written to two locations: one is the next layer input register file, serving as input data for the next layer BNN calculation; the other is the input buffer of the distribution density statistics unit, providing the distribution data of the previous layer's output for the next layer's dynamic threshold calculation, forming a closed-loop adaptive threshold adjustment mechanism.

[0039] It should be noted that step 400, through distribution density statistics and dynamic threshold calculation, solves the problem that using a fixed decision threshold cannot adapt to the differences in the distribution of different input samples. It can adaptively adjust the binarization threshold according to the actual characteristics of the input data, thereby improving the inference accuracy while maintaining extremely low computational overhead. Furthermore, the fully parallel execution of dynamic threshold calculation and Popcount operation ensures that the entire process does not increase the total latency of BNN inference, maintaining the high real-time performance of the system. In addition, the closed-loop adaptive threshold adjustment mechanism enables the entire BNN model to adapt to the complex and ever-changing input environment of industrial sites, significantly improving the robustness and generalization ability of the model.

[0040] In the specific implementation process, the DSP in step 500 contains 8 independent VLIW arithmetic logic execution units, which can simultaneously run AI inference threads, real-time control threads, and background management threads. Thread priorities are divided into 5 levels, with level 0 being the highest and level 4 the lowest. Emergency control tasks run at level 0 (highest priority), the AI ​​inference thread initially has a priority of level 2, ordinary control tasks run at levels 1-3, and the background management thread runs at level 4 (lowest priority). Specifically, the inference complexity analysis process starts immediately after all binary activation values ​​of the current layer are generated and is executed by a dedicated 32-bit hardware statistics unit. For the first convolutional layer of the BNN containing 32 output neurons in this embodiment, the total number of neurons output by the current layer is Q=32. The hardware statistics unit counts the number of "1"s K among the 32 binary activation values ​​within one clock cycle. Subsequently, the hardware calculates the inference complexity exponent using the formula... The system automatically calculates the complexity index, and the hardware has preset thresholds for classifying complexity levels: when R < 0.2, it is considered low complexity; when 0.2 ≤ R < 0.4, it is considered medium complexity; and when R ≥ 0.4, it is considered high complexity.

[0041] Furthermore, the real-time control thread status is continuously monitored by an independent hardware priority detector, which scans the task queue and priority register of the real-time control thread with a sampling period of 10 ns. The hardware priority detector maintains a task queue of length 16, with each queue item containing task priority, execution time, and deadline information. The detector continuously calculates the length of the task queue and extracts the highest priority task currently waiting to be executed. When a level 0 highest priority task is detected in the task queue, a highest priority preemption signal is immediately sent to the execution unit scheduler; when the task queue is detected to be empty, an idle signal is sent; otherwise, the current highest task priority and queue length information are sent. For example, when the motor is running normally, the real-time control thread mainly performs speed regulation and temperature monitoring tasks, with a priority of level 2, and the task queue length is usually 2-3 items; when motor overcurrent is detected, a level 0 emergency stop task is immediately generated and inserted at the head of the task queue.

[0042] Furthermore, the execution unit dynamic scheduler allocates resources according to rules based on complexity level and the real-time control thread status. When a highest-priority preemption signal is received, the scheduler immediately allocates 75% of the VLIW execution units to the real-time control thread, reserving only 25% of the execution units to continue executing AI inference tasks. When a task queue idle signal is received, the scheduler allocates all execution units to the AI ​​inference thread to maximize inference speed. When the task priority is not the highest and the queue is not empty, allocation is based on complexity level: for low complexity, 25% of the execution units are allocated to the AI ​​inference thread and 75% to the control thread; for medium complexity, 50% of the execution units are allocated to each thread; and for high complexity, 75% of the execution units are allocated to the AI ​​inference thread and 25% to the control thread. Execution unit switching is achieved through hardware register remapping, with a switching time of less than one clock cycle, incurring no task switching overhead.

[0043] Furthermore, the dynamic adjustment mechanism for the AI ​​inference thread priority is implemented by a dedicated continuous complexity detector, which records the complexity levels of the three most recent BNN layers. When three consecutive BNN layers are detected to be of high complexity, the priority of the AI ​​inference thread is automatically increased by one level, up to a maximum of level 1, and always lower than the level 0 highest priority control thread. When three consecutive BNN layers are detected to be of low complexity, the priority of the AI ​​inference thread is automatically decreased by one level, down to a minimum of level 3, and always higher than the level 4 background thread. For example, when the second, third, and fourth layers of the BNN model are all of high complexity, the AI ​​thread priority is increased from the initial level 2 to level 1. At this time, in non-highest priority control task scenarios, the AI ​​thread will obtain the same resource competition rights as ordinary control tasks.

[0044] It should be noted that step 500 constructs a fully adaptive VLIW execution unit dynamic scheduling mechanism through inference complexity analysis and real-time control status monitoring, which solves the contradiction between real-time control and AI inference that the traditional static resource allocation method cannot take into account. Furthermore, while ensuring the absolute real-time performance of the highest priority control task, it can dynamically adjust resource allocation according to the actual computing needs of AI inference, thereby improving the overall resource utilization and AI inference throughput of the system. At the same time, the dynamic adjustment mechanism of AI thread priority further optimizes the rationality of resource allocation, avoiding the problem of excessive suppression of long-term high-complexity inference tasks or waste of resources by low-complexity tasks.

[0045] The beneficial effects of this invention are as follows: 1) Redundant weights were eliminated from the source through offline structured sparsity processing. Combined with the real-time hardware masking mechanism of bitmasking, invalid XNOR and Popcount operations were avoided for zero weights, reducing the core computation load and improving the equivalent computation speed. Furthermore, based on the ping-pong double buffering mechanism, the data transmission and computation operations were fully overlapped and parallelized, eliminating the memory bandwidth bottleneck, significantly improving the energy efficiency and inference speed of BNN computation, and significantly reducing hardware resource consumption. 2) Based on the dynamic threshold decision mechanism of the output distribution density of the previous layer, the binarization threshold can be adaptively adjusted according to the actual distribution characteristics of the input samples. This solves the problem of accuracy decline caused by the inability of fixed thresholds to adapt to the differences in the distribution of different input samples. It improves inference accuracy while maintaining extremely low computational overhead. Furthermore, an adaptive threshold adjustment mechanism is constructed, which enables the entire BNN model to adapt to the complex and ever-changing noise environment and working conditions in industrial sites. This significantly improves the robustness and generalization ability of the model, and significantly enhances the inference accuracy and environmental adaptability of the BNN model. 3) Based on the extended two-dimensional parity check mechanism, real-time error detection is realized in the BNN calculation process, which can accurately locate the position of single-bit errors without generating any additional delay; at the same time, a multi-bit error hierarchical interrupt handling mechanism is established to ensure the system's fault recoverability. 4) An adaptive execution unit dynamic scheduling mechanism was constructed, and resource allocation was carried out in combination with the BNN inference complexity and the load and priority of the real-time control thread. This solved the contradiction between the traditional static resource allocation method and the AI ​​inference, which could not take into account the real-time control and AI inference. It improved the overall hardware resource utilization of the system, increased the AI ​​inference throughput, and avoided idle computing resources under low load. At the same time, a dynamic adjustment mechanism for AI inference thread priority was introduced to avoid the problem of excessive suppression of long-term high-complexity inference tasks or waste of resources by low-complexity tasks.

[0046] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0047] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A multi-threaded DSP based on VLIW architecture and its BNN computation fusion method, characterized in that, Includes the following steps: The weights of the BNN are sparsified and a corresponding bitmask matrix is ​​generated. The binary weight matrix, the bitmask matrix and the input quantization value are loaded into the VLIW general-purpose register to obtain the weight vector, the bitmask vector and the input vector. The weight vector and the input vector are bitwise ANDed using the bitmask vector, and an XNOR operation is performed on the masked weight vector and the input vector to obtain an intermediate result vector. The intermediate result vector is mapped to a dedicated hardware counting pipeline, and Popcount and error detection operations are performed to obtain the accumulated result and error detection signal. The dynamic decision threshold of the current layer is calculated based on the distribution density of the output of the previous layer in the VLIW general-purpose register, and the accumulated result is compared with the dynamic decision threshold to obtain the binary excitation value of the next layer. Complexity inference is performed on the binary stimulus value, and the VLIW execution unit is dynamically allocated to the AI ​​inference thread and the real-time control thread in combination with the task load and priority of the real-time control thread.

2. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, The specific steps of sparsification include: Sort the trained BNN weights by absolute value; Based on a preset sparsity threshold, the weights of items whose absolute values ​​are less than the sparsity threshold are determined to be zero. The non-zero weights are quantized to +1 or -1 to obtain a binary weight matrix; The bitmask matrix is ​​generated based on the binary weight matrix; in the bitmask matrix, 1 indicates that the weight at the corresponding position is non-zero, and 0 indicates that the weight at the corresponding position is zero.

3. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, The BNN weights are sparsified to generate a corresponding bitmask matrix. The binary weight matrix, the bitmask matrix, and the input quantized value are loaded into a VLIW general-purpose register to obtain a weight vector, a bitmask vector, and an input vector, including: The binary weight matrix is ​​divided into multiple weight vectors by rows, and each weight vector contains N binary weights; The bitmask matrix is ​​divided into multiple bitmask vectors by rows, and each bitmask vector has the same length as the corresponding weight vector; The input quantized value is divided into multiple input vectors by columns, and each input vector contains N binary inputs; The weight vector, the bitmask vector, and the input vector are loaded into three independent register files of the VLIW general purpose register group, respectively.

4. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, A bitwise AND operation is performed on the weight vector and the input vector using the bitmask vector, and an XNOR operation is performed on the masked weight vector and the input vector to obtain an intermediate result vector, including: During the instruction issuance phase, the weight vector, the bitmask vector, and the input vector are read simultaneously from three register files. In the first sub-cycle of the execution phase, a bitwise AND operation is performed on the weight vector based on the bitmask vector to obtain the masked weight vector. In the second sub-cycle of the execution phase, a bitwise AND operation is performed on the input vector based on the bitmask vector to obtain the masked input vector; In the third sub-cycle of the execution phase, an XNOR operation is performed on the masked weight vector and the masked input vector to obtain the intermediate result vector.

5. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, The intermediate result vector is mapped to a dedicated hardware counting pipeline, and Popcount and error detection operations are performed to obtain the accumulated result and error detection signal, including: The intermediate result vector is input to the parallel Popcount calculation unit to obtain the accumulated result; the Popcount calculation unit consists of N 1-bit adders, which are used to complete the counting of N bits in one clock cycle; The intermediate result vector is input into the parity calculation unit to calculate the parity bit of the intermediate result vector; The parity check bit is compared with the pre-stored parity check bit; if they are inconsistent, the error detection signal is obtained. If the error detection signal is a single-bit error, the accumulated result is automatically corrected by the hardware error correction circuit; if the error detection signal is a multi-bit error, an interrupt signal is generated and the CPU is notified to process it.

6. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, The dynamic decision threshold of the current layer is calculated based on the distribution density of the previous layer's output in the VLIW general-purpose register, and the accumulated result is compared with the dynamic decision threshold to obtain the binary excitation value of the next layer, including: Count the number of "1"s in the binary excitation values ​​output by the previous layer, and record the count as C; The distribution density of the output of the previous layer is calculated based on C; the formula for calculating the distribution density is: Where D is the distribution density, This represents the total number of neurons output by the previous layer. Based on the distribution density and the preset accuracy requirements, the dynamic decision threshold for the current layer is calculated; the formula for calculating the dynamic decision threshold is: Where T is the dynamic decision threshold. This is the proportionality coefficient. This is the offset. This represents the number of inputs to each neuron in the current layer. Load the dynamic decision threshold into a dedicated threshold register; The accumulated result is compared with the dynamic decision threshold. If the accumulated result is greater than or equal to the dynamic decision threshold, the output binary stimulus value is "1"; if the accumulated result is less than the dynamic decision threshold, the output binary stimulus value is "0".

7. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 1, characterized in that, Complexity inference is performed on the binary stimulus value, and the VLIW execution unit is dynamically allocated to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread, including: Count the number of "1"s in the binary excitation values ​​output by the current layer, and record the count as K; The inference complexity index of the current layer is calculated based on K; the formula for calculating the inference complexity index is: , where R is the reasoning complexity index and Q is the total number of neurons output by the current layer; The reasoning task is divided into different reasoning complexity levels according to the reasoning complexity index; the reasoning complexity levels include: low complexity, medium complexity, or high complexity.

8. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 7, characterized in that, The complexity inference of the binary stimulus value is performed, and the VLIW execution unit is dynamically allocated to the AI ​​inference thread and the real-time control thread based on the task load and priority of the real-time control thread. The method also includes: The task queue length and task priority of the real-time control thread are monitored using a hardware priority detector; When the task priority is the highest, 75% of the VLIW execution units are allocated to the control thread, and the remaining 25% of the VLIW execution units continue to perform AI inference tasks. When the task priority is not the highest, the VLIW execution unit is allocated according to the reasoning complexity level. When the task queue length is empty, all VLIW execution units are allocated to the AI ​​inference thread.

9. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 8, characterized in that, When the task priority is not the highest, the VLIW execution unit is allocated according to the inference complexity level, including: When the inference complexity level is low, 25% of the VLIW execution units are allocated to the AI ​​inference thread, and the remaining 75% of the VLIW execution units are allocated to the control thread. When the inference complexity level is medium complexity, 50% of the VLIW execution units are allocated to the AI ​​inference thread, and the remaining 50% of the VLIW execution units are allocated to the control thread. When the inference complexity level is high complexity, 75% of the VLIW execution units are allocated to the AI ​​inference thread, and the remaining 25% of the VLIW execution units are allocated to the control thread.

10. The multi-threaded DSP and its BNN computation fusion method based on VLIW architecture according to claim 7, characterized in that, When three consecutive BNN layers are all of the aforementioned high complexity, the priority of the AI ​​inference thread is increased by one level; When three consecutive BNN layers are of the low complexity, the priority of the AI ​​inference thread is reduced by one level; the priority range of the AI ​​inference thread is: lower than the highest priority control thread and higher than the lowest priority background thread.

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