An arm core board data security protection method and system

Abstract

This invention relates to the field of data security protection technology, specifically disclosing a data security protection method and system for ARM core boards. By matching data within the ARM core board with a pre-established sensitive content database, sensitive and non-sensitive datasets are distinguished. Hardware isolation methods are used to establish mutually isolated sensitive and non-sensitive data processing domains, storing different types of data separately. When a sensitive data processing domain needs to transmit a data block to a non-sensitive data processing domain, a secure transmission access control mechanism is introduced to scan the content. If the detected data block does not contain sensitive content, transmission is allowed; if it contains sensitive content, transmission is blocked and a security alarm is triggered. This method effectively solves the problem in existing technologies where, due to unexpected situations such as high load, software defects, or abnormal resource management within the ARM core board, sensitive and non-sensitive data can be mixed or leaked.

Description

Technical Field

[0001] This application relates to the field of data security protection technology, and more specifically, to a data security protection method and system for an ARM core board. Background Technology

[0002] In modern industrial environments, especially in smart factories, ARM core boards play a crucial role, managing and processing data streams from various communication protocols such as CAN, RS485, and Ethernet. These systems are designed to transmit data efficiently while ensuring stable operation and data security. With the continuous upgrading of production lines and the incorporation of new technologies, achieving a balance between high-speed data processing, resource management, and preventing the leakage of sensitive information is particularly critical.

[0003] For example, in a pharmaceutical manufacturing environment, when an ARM core board is processing a large volume of Ethernet data streams from an ultra-high resolution holographic imaging system while undergoing routine software updates, unexpected situations such as high load and software defects can lead to intermittent resource shortages within the core board (e.g., abnormal memory buffer management or excessive CPU load). This can disrupt the precise time synchronization between different bus data streams (e.g., Ethernet defect analysis results and CAN bus physical location information), causing data misalignment. More seriously, this internal instability can also lead to data security risks. Specifically, during cross-bus data conversion and transmission within the core board, sensitive production formula data fragments that should be securely isolated or erased may be mistakenly copied into non-sensitive data (e.g., batch identification codes on the CAN bus) and transmitted outwards. Faced with this unexpected and temporary data content confusion or leakage caused by internal resource management imbalances and software defects, existing data security protection methods, primarily focused on preventing external intrusion and encrypting and authenticating intended data streams, are ineffective in identifying and preventing such incidents.

[0004] There is currently no effective technical solution to the above problems. Summary of the Invention

[0005] The purpose of this application is to provide a data security protection method and system for ARM core boards, which aims to solve the problem that sensitive data and non-sensitive data are mixed up or leaked due to unexpected situations such as high load, software defects or abnormal resource management within the ARM core board, and that existing technologies cannot identify and prevent this.

[0006] To solve the above problems, the solution proposed in this application is as follows: As one aspect of this application, a method for protecting data security on an ARM core board is provided, comprising: Step S1: Match the data stored in the ARM core board with the pre-established sensitive content database to distinguish between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. Step S2: Use hardware isolation methods to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board, and store the sensitive dataset and non-sensitive dataset in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively; Step S3: When a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain, a data transmission request is initiated to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain. Step S4: In response to a request from a sensitive data processing domain to transfer a data block to a non-sensitive data processing domain, the secure transmission access control mechanism performs the following operations: The data block to be transmitted is scanned to detect whether it contains sensitive content that matches the feature information stored in the sensitive content database; If it is detected that the data block does not contain sensitive content, then the data block is allowed to be transmitted to the non-sensitive data processing domain. If the data block is confirmed to contain sensitive content, the transmission of the data block to be transmitted will be blocked, and a security alarm will be triggered.

[0007] Furthermore, in step S1, the feature information related to known sensitive data stored in the sensitive content database includes at least one of the following: The encrypted hash value of sensitive data; Regular expressions used to identify sensitive data patterns; Semantic patterns used to identify the semantic meaning of sensitive data.

[0008] Furthermore, in step S4, the content scanning of the data block to be transmitted includes: Calculate the hash value of the data block and match it with the encrypted hash value of sensitive data blocks pre-stored in the sensitive content database; And by using the regular expression rules pre-stored in the sensitive content database, pattern matching is performed on the content of the data block; Furthermore, the semantic rules pre-stored in the sensitive content database are used to perform keyword and context analysis on the content of the data block.

[0009] Furthermore, step S2 includes: Step S21: Use TrustZone technology to create a normal world operating environment and a secure world operating environment located inside the ARM core board; Step S22: Establish a sensitive data processing domain in the secure world operating environment, allocate a hardware-protected first memory region for the sensitive data processing domain, and store the sensitive dataset in the first memory region; Step S23: Establish the non-sensitive data processing domain in the normal world operating environment, allocate a second memory region isolated from the first memory region for the non-sensitive data processing domain, and store the non-sensitive dataset in the second memory region.

[0010] Furthermore, step S22 also includes: A write authentication unit integrated in the sensitive data processing domain is used to intercept all write requests to the hardware-protected first memory region in real time. The write authentication unit stores an immutable write source whitelist, which specifies internal modules or execution contexts authorized to write data to sensitive data processing domains. When a write request to the first memory region is received, the write authentication unit extracts the source identifier of the write request and compares it with the write source whitelist. The source identifier of the write request is at least one of the CPU core identifier, bus master identifier, or security context identifier. If the comparison between the source identifier of the write request and the write source whitelist indicates that the source identifier of the write request is not in the write source whitelist, the write authentication unit performs hardware forced write blocking to prevent the execution of the write request and triggers an emergency alarm.

[0011] Furthermore, step S22 also includes: The write authentication unit also stores an immutable list of sensitive data type signatures, which includes the characteristics of sensitive data that are allowed to be written into the sensitive data processing domain. While the source identifier of the write request is compared with the write source whitelist, the data content in the write request is subjected to feature verification to verify whether it conforms to the features of at least one sensitive data in the sensitive data type signature list. The execution of the write request is permitted when it is determined that the data content of the write request conforms to the characteristics of at least one sensitive data in the sensitive data type signature list.

[0012] Furthermore, in step S4, after confirming that the data block contains sensitive content, blocking the transmission of the data block to be transmitted, and triggering a security alarm, the method further includes: A security alarm log is generated and written to a read-only log area preset within the sensitive data processing domain. The security alarm log includes the time when the alarm was triggered, the detected sensitive content fragment, the data source domain information, and the data target domain information.

[0013] Furthermore, after step S4, the following steps are also included: Step S5: Monitor the frequency of security alarms triggered by the secure transmission access control mechanism in real time, and initiate an emergency response operation when the alarm frequency detected within a preset time window exceeds a preset threshold.

[0014] Furthermore, the emergency response operation includes at least one of the following operations: Perform a data erasure operation on the buffer located in the sensitive data processing domain; Increase the execution priority of tasks associated with sensitive data processing and secure transmission access control mechanisms, and decrease the execution priority of tasks not associated with sensitive data processing and secure transmission access control mechanisms.

[0015] As a second aspect of this application, an ARM core board data security protection system is provided, comprising: A sensitive dataset differentiation module is used to match the data stored in the ARM core board with a pre-established sensitive content database to differentiate between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. A sensitive data processing domain establishment module is used to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board using a hardware isolation method, and to store sensitive datasets and non-sensitive datasets in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively. A data transmission request module is used to initiate a data transmission request to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain when a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain. A data block transmission request execution module is used to respond to a request from a sensitive data processing domain to transmit a data block to a non-sensitive data processing domain. The secure transmission access control mechanism performs the following operations: scans the data block to be transmitted to detect whether it contains sensitive content matching the characteristic information stored in the sensitive content database; if the data block does not contain sensitive content, transmission of the data block to the non-sensitive data processing domain is allowed; if the data block is confirmed to contain sensitive content, transmission of the data block to be transmitted is blocked, and a security alarm is triggered.

[0016] As described above, the ARM core board data security protection method and system provided in this application distinguishes between sensitive and non-sensitive datasets by matching data within the ARM core board with a pre-established sensitive content database. Hardware isolation is then used to establish mutually isolated sensitive and non-sensitive data processing domains, storing different types of data separately. When a sensitive data processing domain needs to transmit a data block to a non-sensitive data processing domain, a secure transmission access control mechanism is introduced to scan the content. If the detected data block does not contain sensitive content, transmission is allowed; if it contains sensitive content, transmission is blocked and a security alarm is triggered. This method effectively solves the problem of confusion or leakage of sensitive and non-sensitive data within the ARM core board due to unexpected situations such as high load, software defects, or abnormal resource management. Through hardware isolation and content scanning, the accidental leakage of sensitive data within the core board can be fundamentally prevented, improving the security of data transmission and avoiding the risk of erroneous copying and transmission of sensitive production data fragments due to internal instability. Attached Figure Description

[0017] Figure 1 A flowchart illustrating a data security protection method for an ARM core board provided in this application embodiment; Figure 2 A structural block diagram of an ARM core board data security protection system provided in this application embodiment; Figure reference numerals: 100, ARM core board data security protection system; 101, sensitive dataset differentiation module; 102, sensitive data processing domain establishment module; 103, data transmission request module; 104, data block transmission request execution module. Detailed Implementation

[0018] To better illustrate the present invention, the invention will now be described in further detail with reference to the accompanying drawings.

[0019] It should be understood that, in order to make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0020] The following description uses at least one specific embodiment as an example. In this embodiment: Firstly, such as Figure 1 As shown, a method for protecting data security on an ARM core board is provided, including: Step S1: Match the data stored in the ARM core board with the pre-established sensitive content database to distinguish between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. Step S2: Use hardware isolation methods to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board, and store the sensitive dataset and non-sensitive dataset in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively; Step S3: When a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain, a data transmission request is initiated to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain. Step S4: In response to a request from a sensitive data processing domain to transfer a data block to a non-sensitive data processing domain, the secure transmission access control mechanism performs the following operations: The data block to be transmitted is scanned to detect whether it contains sensitive content that matches the feature information stored in the sensitive content database; If it is detected that the data block does not contain sensitive content, then the data block is allowed to be transmitted to the non-sensitive data processing domain. If the data block is confirmed to contain sensitive content, the transmission of the data block to be transmitted will be blocked, and a security alarm will be triggered.

[0021] This application establishes a hardware-isolated data processing domain within the ARM core board and introduces a secure transmission access control mechanism to scan the content of cross-domain data transmission, thereby identifying and preventing accidental leakage of sensitive data during internal transmission. This solves the problem of data confusion and leakage caused by imbalances in internal resource management and software defects in the prior art.

[0022] Specifically, in step S1, the data stored within the ARM core board is matched against a pre-established sensitive content database to distinguish between sensitive and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. For example, a full scan of all data stored within the ARM core board can be performed, and the scan results compared with the feature information in the sensitive content database. The sensitive content database can also be manually configured by entering known sensitive data features, such as specific file types, keyword lists, or data formats.

[0023] In step S2, a hardware isolation method is used to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains within the ARM core board, and the sensitive datasets and non-sensitive datasets are stored in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively. For example, the Memory Protection Unit (MPU) or Memory Management Unit (MMU) functions provided by the ARM processor can be used to allocate independent memory regions and access permissions to different data processing domains, thereby achieving hardware-level isolation.

[0024] In step S3, when a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain, a data transmission request is initiated to the secure transmission access control mechanism established between the sensitive and non-sensitive data processing domains. For example, when an application in the sensitive data processing domain needs to send its processing result to another application in the non-sensitive data processing domain, that application will submit a data transmission request to the secure transmission access control mechanism through a specific system call or API interface.

[0025] In step S4, in response to a request from a sensitive data processing domain to transmit a data block to a non-sensitive data processing domain, the secure transmission access control mechanism performs the following operations: It scans the data block to be transmitted to detect whether it contains sensitive content matching the characteristic information stored in the sensitive content database. If the data block does not contain sensitive content, transmission to the non-sensitive data processing domain is permitted; if sensitive content is confirmed, transmission of the data block is blocked, and a security alarm is triggered. For example, the secure transmission access control mechanism can calculate the hash value of the data block and compare it with the hash values ​​of sensitive data pre-stored in the sensitive content database to quickly identify known sensitive data.

[0026] This application establishes hardware-isolated sensitive and non-sensitive data processing domains within the ARM core board and introduces a secure transmission access control mechanism to scan the content of cross-domain data transmissions. This method isolates sensitive data and rigorously reviews the content of all cross-domain transmitted data. Compared to existing technologies, this application, firstly, ensures the security of sensitive data within the processing domain through hardware isolation; even if the non-sensitive data processing domain is attacked or malfunctions, the sensitive data will not be directly exposed. Secondly, the secure transmission access control mechanism scans the content at critical stages of data transmission, enabling real-time detection and prevention of accidental leakage of sensitive data. Even data obfuscation caused by internal resource management imbalances or software defects can be effectively identified. For example, in a pharmaceutical production line scenario, when sensitive production formula data fragments are mistakenly copied to a non-sensitive data buffer and attempted to be transmitted, the secure transmission access control mechanism can detect this sensitive content, block the transmission, and trigger a security alarm, thereby effectively preventing the leakage of sensitive information. This proactive internal data flow review mechanism enhances the data security protection capabilities of the ARM core board in complex industrial environments.

[0027] Specifically, in some embodiments of the above-mentioned ARM core board data security protection method, the feature information related to known sensitive data stored in the sensitive content database includes at least one of the following: Cryptographic hash value of sensitive data; regular expression used to identify patterns in sensitive data; semantic pattern used to identify the semantic meaning of sensitive data.

[0028] Furthermore, the content scanning of the data block to be transmitted includes: Calculate the hash value of the data block and match it with the encrypted hash value of sensitive data blocks pre-stored in the sensitive content database; And by using the regular expression rules pre-stored in the sensitive content database, pattern matching is performed on the content of the data block; Furthermore, the semantic rules pre-stored in the sensitive content database are used to perform keyword and context analysis on the content of the data block.

[0029] Specifically, the encrypted hash value of the sensitive data refers to a fixed-length string of numbers or letters obtained by performing an encrypted hash operation on known sensitive data. The purpose is to provide a fast and accurate way to identify perfectly matching sensitive data. For example, sensitive information can be hashed using SHA-256 or MD5, and these hash values ​​can be pre-stored in a sensitive content database. When it is necessary to detect whether a data block contains such sensitive content, simply calculate the hash value of the data block to be detected and compare it with the hash value in the database to achieve efficient identification.

[0030] Regular expressions used to identify sensitive data patterns can be understood as a text pattern matching tool. Their purpose is to identify sensitive data with specific formats by defining specific character sequence rules. For example, a pattern used to identify the proportion of active ingredients could be "Active Ingredient [AZ]:\s\d{1,3}\.\d{1,2}%", or a pattern to identify a specific temperature range in a mixing process curve could be "Temperature:\s(3[0-9]|4[0-5])\.\d{1}C". These regular expressions are compiled and stored in a database. When an access control system scans data blocks, it uses these regular expressions to perform pattern matching on the data content.

[0031] Semantic patterns used to identify the semantic meaning of sensitive data specifically utilize Natural Language Processing (NLP) techniques to identify sensitive information with specific semantic meanings by analyzing the context and keywords of the text. For example, semantic pattern recognition can be achieved through keyword lists and context rules. For instance, a database might contain keywords such as "active ingredient," "mixing process," "formulation number," and "batch parameters." When an access control system detects these keywords in a data block, it further examines the surrounding values ​​or text to determine whether they constitute sensitive information.

[0032] Furthermore, step S2 includes: Step S21: Use TrustZone technology to create a normal world operating environment and a secure world operating environment located inside the ARM core board; Step S22: Establish a sensitive data processing domain in the secure world operating environment, allocate a hardware-protected first memory region for the sensitive data processing domain, and store the sensitive dataset in the first memory region; Step S23: Establish the non-sensitive data processing domain in the normal world operating environment, allocate a second memory region isolated from the first memory region for the non-sensitive data processing domain, and store the non-sensitive dataset in the second memory region.

[0033] Specifically, TrustZone technology is a hardware security extension provided by ARM processors. Its core idea is to divide processor and memory resources into two independent execution environments: a normal world runtime environment and a secure world runtime environment. These two environments are isolated from each other at the hardware level, ensuring that code and data in the secure world cannot be accessed or tampered with by code in the normal world. The normal world runtime environment is typically used to run general-purpose operating systems and applications, such as Linux or Android, handling non-sensitive data and routine tasks. The secure world runtime environment, on the other hand, is a protected environment used to perform sensitive operations and handle sensitive data, such as key management, DRM (Digital Rights Management), or secure boot.

[0034] Furthermore, the sensitive data processing domain is established within a secure world operating environment, where all operations on sensitive data are performed in a hardware-isolated and trusted environment. The first memory region allocated to this sensitive data processing domain is hardware-protected; only code from the secure world can access this memory, and any attempts to access it from the ordinary world will be blocked by the hardware. Simultaneously, the non-sensitive data processing domain is established within the ordinary world operating environment to process data that does not contain sensitive information. The second memory region allocated to this non-sensitive data processing domain is hardware-isolated from the first memory region, ensuring that even if the ordinary world is attacked, it cannot directly access or affect the sensitive data in the secure world.

[0035] This application's solution introduces ARM's TrustZone technology to divide the internal resources of the ARM core board into a normal world operating environment and a secure world operating environment, thereby providing a clear and hardware-enforced isolation boundary for sensitive and non-sensitive data. Specifically, the sensitive data processing domain is placed in the secure world operating environment and allocated a hardware-protected first memory area, ensuring that sensitive datasets are protected from potential malware or attacks in the normal world during storage and processing. Even if the normal world operating environment is compromised, it cannot directly access or tamper with sensitive data and code in the secure world. Simultaneously, the non-sensitive data processing domain is established in the normal world operating environment and allocated a separate second memory area, ensuring that the processing of non-sensitive data does not affect the security of sensitive data. This hardware-based isolation mechanism fundamentally solves the potential vulnerabilities and efficiency problems of traditional software isolation, providing a higher level of protection for data security on the ARM core board.

[0036] In some of the above implementations, although sensitive and non-sensitive data processing domains are isolated from each other within the ARM core board by using TrustZone technology, and a first memory area protected by hardware is allocated to the sensitive data processing domain, unauthorized write operations may still threaten the data integrity within the sensitive data processing domain.

[0037] Therefore, step S22 further includes: A write authentication unit integrated in the sensitive data processing domain is used to intercept all write requests to the hardware-protected first memory region in real time. The write authentication unit stores an immutable write source whitelist, which specifies internal modules or execution contexts authorized to write data to sensitive data processing domains. When a write request to the first memory region is received, the write authentication unit extracts the source identifier of the write request and compares it with the write source whitelist. The source identifier of the write request is at least one of the CPU core identifier, bus master identifier, or security context identifier. If the comparison between the source identifier of the write request and the write source whitelist indicates that the source identifier of the write request is not in the write source whitelist, the write authentication unit performs hardware forced write blocking to prevent the execution of the write request and triggers an emergency alarm.

[0038] Specifically, the write authentication unit refers to a hardware or firmware logic module integrated within the sensitive data processing domain. Its main function is to control access to all operations attempting to write to the first memory region. This unit is designed to intercept all write requests to the hardware-protected first memory region in real time, ensuring that any write attempt must be reviewed. The write source whitelist stored within the write authentication unit is immutable and is typically protected by hardware fuses, one-time programmable memory (OTP), or trusted firmware signing mechanisms to prevent malicious tampering. This whitelist explicitly defines the internal modules or execution contexts authorized to write data to the sensitive data processing domain, such as specific CPU cores, bus masters, or specific trusted applications running in a secure environment.

[0039] In practical applications, when a write request to the first memory region is received, the write authentication unit extracts the source identifier of the write request. This source identifier can be a CPU core identifier, used to identify the specific CPU core initiating the write operation; it can also be a bus master identifier, used to identify the bus master device initiating the write operation; or it can be a security context identifier, used to identify the currently executing security context, such as a specific trusted application ID. The extracted source identifier is then compared with a preset write source whitelist. If the comparison result indicates that the source identifier of the write request is not in the write source whitelist, meaning the write request comes from an unauthorized source, the write authentication unit will perform a hardware-forced write block. This write operation will be physically blocked at the hardware level, preventing the write to the first memory region from being completed, thus effectively protecting the integrity of sensitive data. Simultaneously, the system will trigger an emergency alarm to notify the security monitoring system or administrator of a potential security threat.

[0040] Furthermore, step S22 also includes: The write authentication unit also stores an immutable list of sensitive data type signatures, which includes the characteristics of sensitive data that are allowed to be written into the sensitive data processing domain. While the source identifier of the write request is compared with the write source whitelist, the data content in the write request is subjected to feature verification to verify whether it conforms to the features of at least one sensitive data in the sensitive data type signature list. The execution of the write request is permitted when it is determined that the data content of the write request conforms to the characteristics of at least one sensitive data in the sensitive data type signature list.

[0041] Specifically, the immutable sensitive data type signature list can be understood as a set of rules pre-configured and embedded within the authentication unit, which defines which types of data are considered sensitive data and what identifiable characteristics these sensitive data should possess.

[0042] The feature verification of the data content in the write request refers to the following: when the write authentication unit receives a write request for the first memory region, in addition to verifying the source identifier of the write request, it also analyzes the data payload carried by the request in parallel or serially. This analysis aims to compare the characteristics of the data content with preset characteristics in the sensitive data type signature list. For example, the first N bytes of the data can be extracted for pattern matching, or the data can be structured and parsed to identify its type. The purpose is to ensure that the data to be written conforms to the storage requirements of the sensitive data processing domain in terms of type, thereby maintaining data compliance within that area.

[0043] In practical applications, a write request is only allowed to execute when the source identifier of the write request is confirmed to be legitimate, and the data content of the write request, after feature verification, is determined to meet at least one of the sensitive data characteristics in the sensitive data type signature list. This means that even if the source is authorized, the write operation will still be blocked if the data it attempts to write does not conform to the type expected by the sensitive data processing domain, thus forming a dual verification mechanism.

[0044] In some preferred embodiments, it is assumed that the sensitive data processing domain of the ARM core board is designed to store encryption keys and digital certificates. In this case, the immutable sensitive data type signature list written into the authentication unit can be configured to include the following characteristics: 1. Specific length range of encryption keys (e.g., 128 bits, 256 bits) and entropy requirements.

[0045] 2. The X.509 standard format header identifier and signature algorithm type of the digital certificate.

[0046] 3. Do not write any executable code or unstructured text data.

[0047] Specifically, when an authorized encryption module attempts to write a newly generated encryption key to the first memory region, the write authentication unit first verifies whether the source identifier of the encryption module is on the write source whitelist. If the verification passes, the write authentication unit further performs feature verification on the content of the key data. For example, it checks whether the length of the key data conforms to a preset range and may perform entropy analysis. If the key data conforms to the encryption key features defined in the signature list, the write operation is allowed to proceed.

[0048] Conversely, if the encryption module (even if authorized) attempts to write ordinary log text or a binary file that does not conform to the X.509 standard, the write authentication unit, after successful source verification, will find that the data content does not meet any of the sensitive data characteristics defined in the sensitive data type signature list. In this case, the write authentication unit will perform a hardware-forced write block, preventing the log text or binary file from being written to the first memory area and triggering an emergency alarm.

[0049] In some of the above implementations, when the secure transmission access control mechanism detects that the data block to be transmitted contains sensitive content, it will block the data transmission and trigger a security alarm. However, simply triggering an alarm may not be sufficient for subsequent security audits, event tracing, or in-depth analysis. The lack of detailed recording and persistent storage mechanisms for alarm events makes it difficult to effectively implement responses and improvements after a security incident occurs.

[0050] In response, in step S4, after confirming that the data block contains sensitive content, blocking the transmission of the data block to be transmitted and triggering a security alarm, the method further includes: A security alarm log is generated and written to a read-only log area preset within the sensitive data processing domain. The security alarm log includes the time when the alarm was triggered, the detected sensitive content fragment, the data source domain information, and the data target domain information.

[0051] Specifically, a security alert log is a structured collection of data recording security alert events. Its purpose is to provide detailed contextual information about the events that occurred, facilitating subsequent analysis and processing. This log is designed to include several key fields; for example, the alert trigger time is used to precisely record the point in time the event occurred. Detected sensitive content fragments refer to specific sensitive data segments identified during the scanning process. Data source domain information and data destination domain information respectively identify the source and target processing domains of the attempt to transmit sensitive data.

[0052] Writing security alarm logs to a pre-defined read-only log area within the sensitive data processing domain can be understood as allocating a special memory or storage space within the sensitive data processing domain. This area is configured with read-only attributes, meaning that once log information is written, it cannot be modified or deleted. The purpose is to ensure the immutability of alarm logs and prevent malicious actors from tampering with or destroying evidence after an alarm is triggered.

[0053] By generating and persistently storing detailed alarm logs immediately after a security alarm is triggered, the problem of volatile and difficult-to-trace alarm information in the basic solution is solved. When the secure transmission access control mechanism detects sensitive content and blocks transmission, the system no longer simply issues a momentary alarm signal, but actively captures all key information related to the event, including the time of the event, the specific sensitive content fragment, and the data processing domain involved. This information is structured and encapsulated into a security alarm log and written to a read-only log area within the sensitive data processing domain. This read-only characteristic ensures the integrity and authenticity of the log; even if the system is subsequently attacked, the recorded alarm information is difficult to tamper with or delete, thus providing a data foundation for subsequent security analysis and forensics. Therefore, through the continuous recording and protection of alarm logs, the solution in this application can effectively improve the traceability of security events.

[0054] Furthermore, after step S4, the following steps are also included: Step S5: Monitor the frequency of security alarms triggered by the secure transmission access control mechanism in real time, and initiate an emergency response operation when the alarm frequency detected within a preset time window exceeds a preset threshold.

[0055] Specifically, real-time monitoring of the frequency of security alarms triggered by the secure transmission access control mechanism refers to the system continuously tracking and recording all security alarm events issued by the secure transmission access control mechanism. These alarm events typically include key information such as timestamps, alarm types, data source domain information, and data destination domain information. Alarm frequency monitoring can be achieved by calculating the number of alarms occurring within a specific time period. For example, an alarm counter can be set up, incrementing each time the secure transmission access control mechanism triggers an alarm.

[0056] The preset time window can be understood as the time period used to evaluate alarm frequency, such as 1 minute, 5 minutes, 10 minutes, or longer. The preset threshold refers to the maximum number of alarms allowed within the preset time window. For example, if the preset time window is 1 minute and the preset threshold is 5 times, it means that if the number of security alarms exceeds 5 within any consecutive 1 minute, the system considers the alarm frequency to be too high. These parameters can be flexibly configured according to the security requirements and system performance of the actual application scenario.

[0057] When the detected alarm frequency exceeds a preset threshold, the system will initiate emergency response operations. Emergency response operations aim to provide rapid and proactive intervention against potential serious security threats to minimize losses and restore the system to a secure state. Specific emergency response operations may include, but are not limited to, performing data erasure operations on buffers located in sensitive data processing domains, and prioritizing tasks associated with sensitive data processing and secure transmission access control mechanisms while deprioritizing tasks not associated with these mechanisms.

[0058] In some preferred embodiments, this application is implemented as follows: assuming the system sets a preset time window of 1 minute and a preset threshold of 10 times. When the number of security alarms triggered by the secure transmission access control mechanism within 1 minute reaches or exceeds 10, the system will immediately initiate an emergency response operation.

[0059] The emergency response operations may include: performing data erasure operations on all buffers located in the sensitive data processing domain to ensure that any potentially malicious or sensitive residual data is completely removed; increasing the execution priority of critical tasks associated with sensitive data processing and secure transmission access control mechanisms to ensure that these security-related tasks have sufficient computing resources to accelerate the analysis and processing of security incidents; and simultaneously reducing the execution priority of non-core tasks not associated with sensitive data processing and secure transmission access control mechanisms to reduce system load and allocate more resources to security protection.

[0060] Specifically, the system sends instructions to the sensitive data processing domain to perform data erasure operations, ensuring that all temporarily stored PII data is securely deleted, preventing attackers from obtaining this data through buffer overflows or other means. Secondly, the operating system scheduler immediately prioritizes the logging module of the secure transmission access control mechanism, the security audit module, and the integrity monitoring task of the sensitive data processing domain, ensuring these critical security tasks receive the highest CPU time slices and memory access permissions. This allows for rapid recording of alarm details, analysis of attack patterns, and defensive measures. Simultaneously, the priority of non-critical tasks such as user interface rendering and background data synchronization is temporarily reduced to free up resources for security tasks. Through these measures, the system can quickly and decisively respond to potential persistent attacks, prevent further leakage of sensitive data, and provide resource guarantees for subsequent security analysis and recovery.

[0061] Secondly, such as Figure 2 As shown, an ARM core board data security protection system 100 is provided, comprising: Sensitive dataset differentiation module 101 is used to match the data stored in the ARM core board with a pre-established sensitive content database to differentiate between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. Sensitive data processing domain establishment module 102 is used to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board using a hardware isolation method, and to store sensitive datasets and non-sensitive datasets in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively. The data transmission request module 103 is used to initiate a data transmission request to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain when a data block in the sensitive data processing domain needs to be transmitted to the non-sensitive data processing domain. The data block transmission request execution module 104 is used to respond to a request from a sensitive data processing domain to transmit a data block to a non-sensitive data processing domain. The secure transmission access control mechanism performs the following operations: scanning the data block to be transmitted to detect whether it contains sensitive content matching the characteristic information stored in the sensitive content database; if the data block does not contain sensitive content, then the transmission of the data block to the non-sensitive data processing domain is allowed; if the data block is confirmed to contain sensitive content, then the transmission of the data block to be transmitted is blocked, and a security alarm is triggered.

[0062] As described above, the ARM core board data security protection method and system provided in this embodiment distinguishes between sensitive and non-sensitive datasets by matching data within the ARM core board with a pre-established sensitive content database. Hardware isolation is then used to establish mutually isolated sensitive and non-sensitive data processing domains, storing different types of data separately. When a sensitive data processing domain needs to transmit a data block to a non-sensitive data processing domain, a secure transmission access control mechanism is introduced to scan the content. If the detected data block does not contain sensitive content, transmission is allowed; if it contains sensitive content, transmission is blocked and a security alarm is triggered. This method effectively solves the problem of confusion or leakage of sensitive and non-sensitive data within the ARM core board due to unexpected situations such as high load, software defects, or abnormal resource management. Through hardware isolation and content scanning, accidental leakage of sensitive data within the core board can be fundamentally prevented, improving data transmission security and avoiding the risk of incorrect copying and transmission of sensitive production data fragments due to internal instability.

[0063] Finally, it should be noted that the above-described embodiments are merely specific implementations of this disclosure, used to illustrate the technical solutions of this disclosure, and not to limit them. The protection scope of this disclosure is not limited thereto. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features within the scope of the technology disclosed in this disclosure. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be covered within the protection scope of this disclosure.

Claims

1. A method for data security protection of an ARM core board, characterized in that, include: Step S1: Match the data stored in the ARM core board with the pre-established sensitive content database to distinguish between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. Step S2: Use hardware isolation methods to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board, and store the sensitive dataset and non-sensitive dataset in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively; Step S3: When a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain, a data transmission request is initiated to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain. Step S4: In response to a request from a sensitive data processing domain to transfer a data block to a non-sensitive data processing domain, the secure transmission access control mechanism performs the following operations: The data block to be transmitted is scanned to detect whether it contains sensitive content that matches the feature information stored in the sensitive content database; If it is detected that the data block does not contain sensitive content, then the data block is allowed to be transmitted to the non-sensitive data processing domain. If the data block is confirmed to contain sensitive content, the transmission of the data block to be transmitted will be blocked, and a security alarm will be triggered.

2. The ARM core board data security protection method according to claim 1, characterized in that, In step S1, the feature information related to known sensitive data stored in the sensitive content database includes at least one of the following: The encrypted hash value of sensitive data; Regular expressions used to identify sensitive data patterns; Semantic patterns used to identify the semantic meaning of sensitive data.

3. The ARM core board data security protection method according to claim 2, characterized in that, In step S4, the content scanning of the data block to be transmitted includes: Calculate the hash value of the data block and match it with the encrypted hash value of sensitive data blocks pre-stored in the sensitive content database; And by using the regular expression rules pre-stored in the sensitive content database, pattern matching is performed on the content of the data block; Furthermore, the semantic rules pre-stored in the sensitive content database are used to perform keyword and context analysis on the content of the data block.

4. The ARM core board data security protection method according to claim 1, characterized in that, Step S2 includes: Step S21: Use TrustZone technology to create a normal world operating environment and a secure world operating environment located inside the ARM core board; Step S22: Establish a sensitive data processing domain in the secure world operating environment, allocate a hardware-protected first memory region for the sensitive data processing domain, and store the sensitive dataset in the first memory region; Step S23: Establish the non-sensitive data processing domain in the normal world operating environment, allocate a second memory region isolated from the first memory region for the non-sensitive data processing domain, and store the non-sensitive dataset in the second memory region.

5. The ARM core board data security protection method according to claim 4, characterized in that, Step S22 further includes: A write authentication unit integrated in the sensitive data processing domain is used to intercept all write requests to the hardware-protected first memory region in real time. The write authentication unit stores an immutable write source whitelist, which specifies internal modules or execution contexts authorized to write data to sensitive data processing domains. When a write request to the first memory region is received, the write authentication unit extracts the source identifier of the write request and compares it with the write source whitelist. The source identifier of the write request is at least one of the CPU core identifier, bus master identifier, or security context identifier. If the comparison between the source identifier of the write request and the write source whitelist indicates that the source identifier of the write request is not in the write source whitelist, the write authentication unit performs hardware forced write blocking to prevent the execution of the write request and triggers an emergency alarm.

6. The ARM core board data security protection method according to claim 5, characterized in that, Step S22 further includes: The write authentication unit also stores an immutable list of sensitive data type signatures, which includes the characteristics of sensitive data that are allowed to be written into the sensitive data processing domain. While the source identifier of the write request is compared with the write source whitelist, the data content in the write request is subjected to feature verification to verify whether it conforms to the features of at least one sensitive data in the sensitive data type signature list. The execution of the write request is permitted when it is determined that the data content of the write request conforms to the characteristics of at least one sensitive data in the sensitive data type signature list.

7. The ARM core board data security protection method according to claim 1, characterized in that, In step S4, after confirming that the data block contains sensitive content, blocking the transmission of the data block to be transmitted, and triggering a security alarm, the method further includes: A security alarm log is generated and written to a read-only log area preset within the sensitive data processing domain. The security alarm log includes the time when the alarm was triggered, the detected sensitive content fragment, the data source domain information, and the data target domain information.

8. The ARM core board data security protection method according to claim 1, characterized in that, Following step S4, the method further includes: Step S5: Monitor the frequency of security alarms triggered by the secure transmission access control mechanism in real time, and initiate an emergency response operation when the alarm frequency detected within a preset time window exceeds a preset threshold.

9. The ARM core board data security protection method according to claim 8, characterized in that, The emergency response operation includes at least one of the following operations: Perform a data erasure operation on the buffer located in the sensitive data processing domain; Increase the execution priority of tasks associated with sensitive data processing and secure transmission access control mechanisms, and decrease the execution priority of tasks not associated with sensitive data processing and secure transmission access control mechanisms.

10. A data security protection system for an ARM core board, characterized in that, include: A sensitive dataset differentiation module is used to match the data stored in the ARM core board with a pre-established sensitive content database to differentiate between sensitive datasets and non-sensitive datasets. The sensitive content database stores feature information associated with known sensitive data. A sensitive data processing domain establishment module is used to establish mutually isolated sensitive data processing domains and non-sensitive data processing domains inside the ARM core board using a hardware isolation method, and to store sensitive datasets and non-sensitive datasets in the mutually isolated sensitive data processing domains and non-sensitive data processing domains respectively. A data transmission request module is used to initiate a data transmission request to the secure transmission access control mechanism established between the sensitive data processing domain and the non-sensitive data processing domain when a data block needs to be transmitted from the sensitive data processing domain to the non-sensitive data processing domain. A data block transmission request execution module is used to respond to a request from a sensitive data processing domain to transmit a data block to a non-sensitive data processing domain. The secure transmission access control mechanism performs the following operations: scans the data block to be transmitted to detect whether it contains sensitive content matching the characteristic information stored in the sensitive content database; if the data block does not contain sensitive content, transmission of the data block to the non-sensitive data processing domain is allowed; if the data block is confirmed to contain sensitive content, transmission of the data block to be transmitted is blocked, and a security alarm is triggered.

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