Power system transient stability evaluation method and system based on FPGA simulation engine

Abstract

This application discloses a method and system for evaluating the transient stability of power systems based on an FPGA simulation engine. The method includes: instantiating multiple simplified transient simulation engines within the FPGA; preprocessing the current power system operating section data, storing the generated shared parameters and anticipated fault set description tables in the on-chip shared parameter storage module and fault parameter storage module, respectively; grouping all engines using a time-division multiplexing strategy, with engines within each group accessing the shared parameter storage module using a round-robin arbitration strategy, and interleaving access to the shared parameter storage module between groups via a pipelined approach; assigning each fault scenario to each simulation engine, controlling the simultaneous start of simulation by a global synchronization start signal, and performing real-time stability evaluation of the power angle state of each generator at the current moment after each simulation step, and outputting the stability evaluation results. This application significantly reduces system power consumption and deployment costs.

Description

Technical Field

[0001] This application relates to the field of power system simulation technology, and in particular to a method and system for evaluating the transient stability of power systems based on an FPGA (Field Programmable Gate Array) simulation engine. Background Technology

[0002] With the increasing proportion of large-scale renewable energy grid integration in new power systems, the operation mode of power systems is becoming increasingly complex, and the transient stability problem after the system suffers large disturbances is becoming more and more prominent. The power system dispatch and operation center needs to conduct transient stability scans and assessments on a large number of anticipated fault scenarios under the current operating conditions to ensure that the system can still maintain stable operation after any credible fault occurs. This online dynamic security analysis task requires the completion of time-domain simulation calculations for hundreds to thousands of fault scenarios within a limited time window, which places extremely high demands on the computing speed.

[0003] Existing technology utilizes a CPU / GPU heterogeneous cluster to achieve parallel scanning of power system transient stability. The working principle is as follows: transient stability simulation software is deployed on multiple high-performance CPU servers. Fault scenarios from a set of anticipated faults are distributed to each server node according to a task allocation strategy. Each node uses a multi-core CPU or GPU to perform time-domain simulations of its assigned fault scenarios sequentially or in small batches in parallel. During the simulation, the trapezoidal implicit integration method is used to solve the system's differential-algebraic equations in millisecond-level steps. The simulation time window is typically set to 5 to 10 seconds after the fault. This solution is applied to online security analysis systems in provincial and higher-level power dispatch centers. Its main drawback is:

[0004] First, the computational latency is significant, failing to meet real-time requirements. In parallel scanning schemes based on CPU / GPU clusters, inherent software and hardware overheads, such as operating system task scheduling, inter-process communication latency, cache misses due to memory hierarchy, and GPU kernel function startup delays, mean that a complete transient stability scan of hundreds to thousands of fault scenarios typically takes 3 to 30 minutes. This computational latency far exceeds the second-level response time window required for real-time operation control of power systems, causing online dynamic safety analysis results to lag significantly behind changes in system operating status, thus failing to provide truly real-time safety assessment support for scheduling and operation decisions.

[0005] Second, it consumes a lot of hardware resources, consumes a lot of power, and has high deployment costs. To improve computing speed, existing solutions usually require the deployment of computing clusters consisting of dozens of high-performance servers, equipped with a large number of high-end CPUs and GPUs. The power consumption of the entire system can reach several kilowatts to tens of thousands of watts. The data center space is large, and the procurement and maintenance costs are high, which limits the promotion and application of this technology in small and medium-sized scheduling centers and edge scenarios.

[0006] Third, parallel scalability is limited by the software architecture. In CPU / GPU solutions, the simulation tasks for each fault scenario are coarse-grained, limited by the number of operating system threads, the number of GPU stream processors, and communication bandwidth, making it difficult to infinitely expand the number of parallel simulation instances. As the size of the anticipated fault set increases, the computation time grows approximately linearly, lacking efficient hardware-level parallel scalability. Summary of the Invention

[0007] This application provides a method and system for evaluating the transient stability of power systems based on an FPGA simulation engine, which aims to improve the technical problems of existing technologies, such as large computational latency, high hardware resource consumption, high power consumption, high deployment cost, and limited parallel scalability due to software architecture.

[0008] In view of this, the first aspect of this application provides a method for evaluating the transient stability of a power system based on an FPGA simulation engine, comprising:

[0009] Multiple simplified transient simulation engines with identical structures are instantiated inside the FPGA chip, and each of the simplified transient simulation engines has an independent state variable storage space;

[0010] The current power system operation section data is preprocessed to generate shared parameters and a set of expected fault descriptions suitable for the simplified transient simulation engine, and the shared parameters and the set of expected fault descriptions are stored in the shared parameter storage module and the fault parameter storage module on the FPGA chip, respectively.

[0011] A grouping time-division multiplexing strategy is adopted to group all the simplified transient simulation engines. Each simplified transient simulation engine in each group accesses the shared parameters in the shared parameter storage module using a round-robin arbitration strategy. The groups access the shared parameters in the shared parameter storage module in an interleaved manner through a pipeline.

[0012] Each fault scenario is assigned to one of the simplified transient simulation engines. A global synchronization start signal controls each simplified transient simulation engine to start the simulation simultaneously. Each simplified transient simulation engine reads the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module to perform electromechanical transient time-domain simulation of the power system. After each simulation step, the power angle state of each generator at the current moment is evaluated in real time, and the stability evaluation result is output.

[0013] Optionally, the preprocessing of the current power system operating section data to generate shared parameters and a set of anticipated fault descriptions suitable for use by the simplified transient simulation engine includes:

[0014] Construct a node admittance matrix from the system network topology information and line parameters in the current power system operation section data;

[0015] Calculate the generator parameter vector required for the classical second-order or fourth-order electromechanical transient model, or the classical fourth-order electromechanical transient model, based on the current operating conditions and equipment parameters of each engine in the current power system operating section data.

[0016] The load data in the current power system operation section data is converted into ZIP model parameters to obtain the load parameter vector;

[0017] The admittance matrix, generator parameter vector, and load parameter vector in floating-point format are converted into admittance matrix, generator parameter vector, and load parameter vector in fixed-point format; the shared parameters include admittance matrix, generator parameter vector, and load parameter vector in fixed-point format.

[0018] Based on the system network topology information and a predefined list of fault types, a hypothetical fault set description table is generated. The hypothetical fault set description table includes the fault type code, fault location node number, fault application time, fault duration, fault clearance method, and the incremental value of the admittance matrix that needs to be modified for each fault scenario.

[0019] Optionally, the simplified transient simulation engine performs time-domain simulation of power system electromechanical transients based on the assigned fault scenarios, including:

[0020] After receiving the calculation start signal, the simplified transient simulation engine checks whether the current simulation time has reached the fault application time or the fault clearing time.

[0021] If the fault application time is reached, the simplified transient simulation engine will add the incremental value of the admittance matrix to the corresponding element of the ground state admittance matrix read from the local cache to form the admittance matrix during the fault period.

[0022] If the fault clearing time is reached, the simplified transient simulation engine removes the incremental value of the admittance matrix and modifies the admittance matrix according to the fault clearing method to form the post-fault admittance matrix.

[0023] The simplified transient simulation engine calculates the power angle derivative and angular velocity derivative of each generator based on the current state variable values, and calculates the power angle estimate and angular velocity estimate based on the power angle derivative and angular velocity derivative of each generator; it recalculates the power angle derivative and angular velocity derivative based on the power angle estimate and angular velocity estimate, calculates the corrected new state variable values ​​based on the average of the two power angle derivatives and angular velocity derivatives, and enters the next simulation step until the preset simulation time is reached.

[0024] Optionally, after each simulation step, a real-time stability assessment is performed on the power angle state of each generator at the current moment, and the stability assessment results are output, including:

[0025] After each simulation step, the difference between the maximum and minimum power angle values ​​of all generators in the power system at the current moment is calculated to obtain the maximum power angle deviation value;

[0026] If the maximum power angle deviation exceeds the preset instability threshold, an instability flag, the current simulation time, and the engine identifier of the instability will be output, and the subsequent step-size simulation calculation of the current fault simulation will be stopped.

[0027] Optionally, the method further includes:

[0028] The stability evaluation results of all the simplified transient simulation engines are scanned sequentially, and the maximum power angle deviation values ​​of all fault scenarios are sorted in descending order.

[0029] Unstable scenarios are marked as the first alarm level and a list of unstable faults is compiled. Fault scenarios with stability margins lower than the preset stability margin threshold are marked as the second alarm level. A comprehensive safety assessment report is generated, which includes the number of unstable faults, the list of unstable faults, the stability margin ranking table, and the identification of system weaknesses. The stability margin is the peak value of the maximum power angle difference.

[0030] The second aspect of this application provides a power system transient stability assessment system based on an FPGA simulation engine, comprising:

[0031] The management module is used to instantiate multiple simplified transient simulation engines with the same structure inside the FPGA chip, and each of the simplified transient simulation engines has an independent state variable storage space;

[0032] The data preprocessing module is used to preprocess the current power system operation section data, generate a shared parameter and a set of expected fault description tables suitable for the simplified transient simulation engine, and store the shared parameter and the set of expected fault description tables in the shared parameter storage module and the fault parameter storage module on the FPGA chip, respectively.

[0033] A bus arbiter is used to group all the simplified transient simulation engines using a group time-division multiplexing strategy. Each simplified transient simulation engine in each group accesses the shared parameters in the shared parameter storage module using a polling arbitration strategy. The groups access the shared parameters in the shared parameter storage module in an interleaved manner through a pipeline.

[0034] The task allocation module is used to allocate each fault scenario to each of the simplified transient simulation engines, so that each simplified transient simulation engine reads the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module and performs initialization operation. After the initialization is completed, it sends a ready signal to the global synchronization controller.

[0035] A global synchronization controller is used to send a global synchronization start signal to each of the simplified transient simulation engines after detecting that all of the simplified transient simulation engines have sent a ready signal, so that each of the simplified transient simulation engines can simultaneously perform electromechanical transient time-domain simulation of the power system according to the assigned fault scenario, and after each simulation step, perform a real-time stability assessment of the power angle state of each generator at the current moment and output the stability assessment result.

[0036] Optionally, the system may also include:

[0037] The results aggregation and output module is used to sequentially scan the stability evaluation results of all the simplified transient simulation engines, sort the maximum power angle deviation values ​​of all fault scenarios in descending order, mark unstable scenarios as the first alarm level and list unstable faults, mark fault scenarios with stability margins lower than the preset stability margin threshold as the second alarm level, and generate a comprehensive safety assessment report containing the number of unstable faults, the list of unstable faults, the stability margin ranking table, and the identification of system weak links. The stability margin is the peak value of the maximum power angle difference.

[0038] Optionally, the system may also include:

[0039] The external data interface module is used to connect to the power system energy management system or wide area measurement system via a PCIe interface or Ethernet interface to receive real-time updated power system operation section data; and to perform protocol parsing and integrity verification on the power system operation section data, extract the system status information at the current moment, and write the verified system status information into the input buffer of the external data interface module.

[0040] Optionally, the simplified transient simulation engine has a stability criterion evaluation module embedded within it;

[0041] The stability criterion evaluation module is specifically used to calculate the difference between the maximum and minimum power angle values ​​of all generators in the power system at the current moment after each simulation step, and obtain the maximum power angle deviation value. If the maximum power angle deviation value exceeds the preset instability threshold, the module outputs an instability flag, the current simulation moment and the identifier of the unstable engine, and stops the subsequent step simulation calculation of the current fault simulation.

[0042] Optionally, the system also includes an independent state variable storage module, which is used to equip each of the simplified transient simulation engines with an independent state variable storage space. The state variable storage space of each simplified transient simulation engine is used to save the electromechanical transient state quantities under its current simulation scenario, as well as the intermediate variables and intermediate quantities of the node voltage solution in the simulation process.

[0043] As can be seen from the above technical solutions, this application has the following advantages:

[0044] The power system transient stability assessment method based on FPGA simulation engines provided in this application improves the efficiency of transient stability scanning across the entire anticipated fault set by deploying a large number of parallel simplified transient simulation engines with identical structures but independent states within the FPGA chip. This leverages the fine-grained hardware parallelism capabilities of the FPGA to simultaneously launch hundreds of fault scenario simulation instances. Furthermore, a time-division multiplexing strategy is employed to coordinate access to the shared parameter storage module by each simulation engine, thereby enhancing the efficiency of transient stability scanning across the entire anticipated fault set. This application utilizes an FPGA hardware-level parallel architecture, allowing hundreds of simulation engines to execute truly simultaneously at the hardware level. There is no operating system scheduling overhead or process communication latency. The total computation time for scanning all fault scenarios is approximately equal to the computation time of a single scenario plus minimal parameter loading and result aggregation overhead, resulting in an overall computation time that can be compressed to the second or even sub-second level. This application achieves true real-time online dynamic security assessment without the limitation of software architecture on parallel scalability. It employs a grouped time-division multiplexing strategy to efficiently coordinate concurrent access to the shared parameter storage module by hundreds of parallel simulation engines, minimizing storage access conflicts during the simulation calculation phase. This application can instantiate hundreds of simplified transient simulation engines with identical structures and completely independent states within the FPGA chip. Each engine is independently responsible for the complete electromechanical transient time-domain simulation of a pre-existing fault scenario. All engines are started simultaneously through a global synchronization signal to achieve true hardware-level large-scale parallel simulation. Only one or a few FPGA acceleration boards are needed to complete all computational tasks. The power consumption of a single board is typically within tens of watts, and the overall system power consumption is reduced by one to two orders of magnitude compared to CPU / GPU solutions. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating a power system transient stability assessment method based on an FPGA simulation engine, provided in an embodiment of this application;

[0047] Figure 2 This is a schematic diagram of a power system transient stability assessment system based on an FPGA simulation engine, provided as an embodiment of this application. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0049] Definitions:

[0050] FPGA (Field Programmable Gate Array): A semiconductor integrated circuit device whose internal logic functions can be reconfigured by the user after leaving the factory using a hardware description language. FPGA contains a large number of programmable logic units, configurable interconnect resources, on-chip memory (Block RAM), and digital signal processing units (DSPSlices), enabling highly parallel hardware computing architectures suitable for deploying large-scale parallel numerical computing tasks.

[0051] Transient stability refers to the ability of a power system to maintain synchronous operation after being subjected to large disturbances (such as short-circuit faults, line tripping, generator tripping, etc.). Transient stability analysis usually requires time-domain numerical simulation of the system's differential-algebraic equations, observation of the generator power angle oscillation trajectory after the fault, and determination of whether the system recovers to a new steady-state operating point after the disturbance.

[0052] Contingency Set: A predefined set of possible fault scenarios in online power system security analysis, typically including N-1 faults (any single component out of service) and some N-2 faults. Performing stability simulation evaluations on each fault scenario in the contingency set is a core task for power system dispatch and operation centers in conducting dynamic security analysis. The number of fault scenarios typically ranges from hundreds to thousands.

[0053] On-Chip Bus Arbiter: A hardware logic module in an FPGA or on-chip system used to coordinate access to shared storage resources or communication buses by multiple master devices. When multiple parallel simulation engines simultaneously request to read shared power system network parameters, the arbiter authorizes access sequentially according to a preset priority strategy or round-robin strategy, avoiding data conflicts and ensuring data consistency.

[0054] Time-domain simulation is a simulation method that uses numerical integration to solve the differential-algebraic equations of a power system step by step, obtaining the complete trajectory of the changes of each state variable of the system over time after a fault. Commonly used numerical integration methods include the improved Euler method and the trapezoidal implicit integration method. The simulation step size is usually on the order of milliseconds, and the simulation time window is generally several seconds to more than ten seconds after the fault.

[0055] For easier understanding, please refer to Figure 1 This application provides a method for evaluating the transient stability of a power system based on an FPGA simulation engine, including:

[0056] Step 110: Instantiate multiple simplified transient simulation engines with identical structures inside the FPGA chip;

[0057] Traditional online assessment of power system transient stability primarily relies on high-performance CPU server clusters or GPU acceleration platforms, using software-level parallel computing to accelerate batch simulations of fault scenarios. However, limited by the general-purpose processor architecture of CPUs / GPUs, software parallel solutions have inherent bottlenecks in terms of task scheduling overhead, memory access latency, and power efficiency, making it difficult to complete transient stability scans of the entire anticipated fault set in real-time (within seconds). FPGA, as a customizable hardware parallel computing platform, possesses advantages such as large-scale fine-grained parallelism, low-latency deterministic computation, and low power consumption, providing a new technical path for rapid online transient stability scanning.

[0058] This application instantiates a large number of Simplified Transient Simulation Engines (STSEs) with identical structures within an FPGA chip, resulting in a parallel simulation engine array. Each STSE is an independent hardware computing unit, containing a numerical integrator for generator electromechanical transient equations, a solver for network algebraic equations, fault application and clearing control logic, and stability criterion evaluation logic. All STSEs share the same set of power system network parameter data (such as node admittance matrices and generator steady-state parameters), but each STSE has its own independent state variable storage space (including state variables such as power angle, angular velocity, and transient electromotive force of each generator), enabling each STSE to run simulations of different fault scenarios independently without interference. Depending on the resource capacity of the FPGA chip, hundreds of STSEs can be instantiated on a single FPGA. For larger sets of anticipated faults, multiple FPGAs can be cascaded or executed in batches to cover all fault scenarios.

[0059] When configuring the simplified transient simulation engine, the FPGA configuration bitstream is first loaded via JTAG or Flash to initialize the internal logic of the FPGA. After initialization, the following key operating parameters are set through the configuration registers on the FPGA chip: the number of STSE instances (determined based on FPGA chip resources and the size of the target power system model, e.g., 256), the simulation step size (e.g., 10 milliseconds), the simulation time window length (e.g., 5 seconds after a fault, corresponding to 500 simulation steps), the instability threshold (e.g., a fixed-point value corresponding to 180 degrees), and the fixed-point scaling factor. These parameters are written to the global configuration register on the FPGA chip for all modules to read during runtime. The initialization phase also includes the grouping configuration of the on-chip bus arbiter (e.g., dividing the 256 engines into 16 groups of 16 engines each) and the Bank partitioning configuration for shared parameter storage.

[0060] This application instantiates hundreds of simplified transient simulation engines with identical structures and completely independent states within an FPGA chip. Each engine independently handles the complete electromechanical transient time-domain simulation of a anticipated fault scenario. A global synchronization start signal simultaneously activates all engines, achieving true hardware-level large-scale parallel simulation. This architecture innovatively maps the power system transient stability scanning problem into an FPGA hardware parallel computing problem, achieving ideal parallel scaling efficiency.

[0061] Step 120: Preprocess the current power system operation section data to generate a shared parameter and expected fault set description table suitable for use in a simplified transient simulation engine, and store the shared parameter and expected fault set description table into the shared parameter storage module and fault parameter storage module on the FPGA chip, respectively.

[0062] Real-time power system operation profile data can be obtained from the Power System Energy Management System (EMS) or Wide Area Measurement System (WAMS). This profile data includes active and reactive power output of each generator, bus voltage amplitude and phase angle, line power flow, and system network topology information. The raw profile data can be transmitted to the FPGA board via a high-speed interface (such as PCIe or Ethernet) through an external data interface and written to an off-chip buffer. Subsequently, the FPGA chip's internal data preprocessing module performs format conversion, data verification, and network parameter calculations on the raw profile data, generating shared parameters and a set of anticipated fault descriptions suitable for use by the simplified transient simulation engine within the FPGA chip. Before simulation starts, the shared parameters are loaded into the shared parameter storage module on the FPGA chip, and the set of anticipated fault descriptions is loaded into the fault parameter storage module on the FPGA chip. The shared parameters and the anticipated fault set description table include the admittance matrix, generator parameter vector, and load parameter vector; the anticipated fault set description table includes description information for each fault scenario, including fault type code, fault location node number, fault application time, fault duration, fault clearing method, and the incremental value of the admittance matrix that needs to be modified.

[0063] This application divides the simulation data into two categories: shared parameters read by all engines and dynamic state variables (fault description information) private to each engine. The data is stored using shared Block RAM and distributed RAM, respectively, to maximize the number of instantiable simulation engines with limited on-chip storage resources on the FPGA.

[0064] Furthermore, the preprocessing of current power system operation section data includes:

[0065] Construct node admittance matrices from system network topology information and line parameters in the current power system operation section data; calculate generator parameter vectors required for classical second-order or fourth-order electromechanical transient models based on the current operating conditions and equipment parameters of each engine in the current power system operation section data; convert load data in the current power system operation section data into ZIP model parameters to obtain load parameter vectors; convert the floating-point format admittance matrix, generator parameter vectors, and load parameter vectors into fixed-point format admittance matrix, generator parameter vectors, and load parameter vectors to obtain shared parameters; generate a descriptive table of anticipated fault sets based on system network topology information and a predefined list of fault types.

[0066] After acquiring new cross-sectional data, the parameter preprocessing process is initiated. First, the node admittance matrix is ​​calculated based on the current system network topology and line parameters (including line resistance, reactance, and ground susceptance). The diagonal elements of the admittance matrix are the sum of the admittances of all branches connected to that node plus the node's ground susceptance; the off-diagonal elements are the negative values ​​of the admittances of the branches connecting the two nodes. For branches containing transformers, admittance corrections are made based on the transformer ratio and connection group. After calculation, the admittance matrix is ​​converted to Compacted Sparse Column (CSC) format for storage, retaining only non-zero elements and their row indices and column pointers to reduce storage space. For a typical 500-node power system, the number of non-zero elements in the admittance matrix is ​​approximately 2000 to 3000. Secondly, based on the current operating conditions and equipment parameters of each generator, the parameters required for the classical second-order model are calculated: mechanical power equals the generator's active power output (ignoring mechanical losses), the transient electromotive force amplitude is calculated based on the generator terminal voltage, active power output, reactive power output, and transient reactance, and the initial power angle is determined based on the phasor relationship between the transient electromotive force and the terminal voltage. Thirdly, ZIP model parameters (constant impedance / constant current / constant power model parameters) are calculated for each load node, and the constant impedance portion can be converted into equivalent admittance and superimposed on the diagonal elements of the admittance matrix. Finally, all parameters are converted from floating-point format to 32-bit fixed-point format and written to the corresponding bank in the shared parameter storage module according to a predefined address mapping scheme. Simultaneously, the preprocessing module on the FPGA chip generates a pre-defined fault set description table based on a predefined fault type list and the current system network topology information. The description information for each fault scenario includes the fault type code, fault location node number, fault application time, fault duration, fault clearing method, and the incremental value of the admittance matrix to be modified. The fault description table is written to the fault parameter storage module on the FPGA chip.

[0067] The classical second-order generator model and improved Euler method numerical integration employed in this application provide sufficient qualitative judgment accuracy (i.e., correctly distinguishing between stable and unstable scenarios) in rapid transient stability scanning applications. For scenarios requiring higher-precision quantitative analysis, the generator model within the STSE can be upgraded to a fourth- or sixth-order detailed model. Correspondingly, the resource consumption of a single STSE increases, but the simulation accuracy is significantly improved. The numerical precision of 32-bit fixed-point numbers is approximately equal to 4 to 5 significant digits of floating-point numbers, which fully meets the accuracy requirements for transient stability determination (based on whether the power angle difference exceeds 180 degrees).

[0068] Step 130: Use a grouping time-division multiplexing strategy to group all simplified transient simulation engines. Within each group, the simplified transient simulation engines access the shared parameters in the shared parameter storage module using a round-robin arbitration strategy. Between groups, access to the shared parameters in the shared parameter storage module is staggered in a pipeline manner.

[0069] This application utilizes a bus arbiter on the FPGA chip to coordinate access to a shared parameter storage module by hundreds of STSEs. Since all STSEs run the same system network model, static data such as the network admittance matrix and generator rated parameters can be stored in the FPGA's on-chip Block RAM and shared by all simulation engines. The bus arbiter employs a time-division multiplexing strategy to group the STSEs. Within each group, simplified transient simulation engines use a round-robin arbitration strategy to access the shared parameter storage module. Access to the shared parameter storage module is interleaved between groups via a pipelined approach, thereby maximizing storage bandwidth utilization while ensuring no data conflicts. For frequently accessed hot parameter data, the bus arbiter also supports copying it to the local cache of each group to reduce access contention. The bus arbitrator employs a two-level arbitration architecture: the first level is intra-group arbitration, which divides all STSEs into several groups based on physical location and access mode (e.g., 8 or 16 STSEs per group). Within each group, a round-robin arbitration strategy is used to authorize each engine to access the corresponding shared memory bank in a fixed order. The second level is inter-group coordination, which uses a global clock synchronization signal to ensure that each group accesses different banks of the shared memory within its allocated time window, avoiding cross-group access conflicts. The bus arbitrator also integrates an access request queue and a priority promotion mechanism. When an engine's access waiting time exceeds a threshold, its priority is automatically promoted to prevent starvation. The clock frequency of the bus arbitrator is consistent with the operating clock of the simulation engine (typically 200MHz to 400MHz), and the delay of a single arbitration decision is 1 to 2 clock cycles. This application designs a two-level arbitration architecture combined with a step-size start-time parameter prefetching strategy to efficiently coordinate the concurrent access of hundreds of parallel simulation engines to the shared parameter storage, minimizing storage access conflicts during the simulation calculation phase.

[0070] Step 140: Assign each fault scenario to each simplified transient simulation engine one by one. Control each simplified transient simulation engine to start the simulation simultaneously through the global synchronization start signal. This allows each simplified transient simulation engine to read the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module to perform electromechanical transient time-domain simulation of the power system. After each simulation step, perform real-time stability evaluation on the power angle state of each generator at the current moment and output the stability evaluation results.

[0071] After the shared parameters are loaded, the fault scenarios in the expected fault dataset description table are assigned to each STSE one by one. The allocation strategy can be a simple sequential mapping: fault scenario numbers 0 to N-1 are assigned to STSE numbers 0 to N-1 respectively (where N is the number of STSE instances). If the total number of fault scenarios exceeds N, the next batch will be allocated after the first batch of N scenarios has been simulated. After receiving the assigned fault scenario number, each STSE reads the description information of the fault scenario from the fault parameter storage module and loads it into the fault control register inside the simulation engine. At the same time, each STSE initializes all generator state variables in its independent state variable storage to steady-state operating values: the power angle is initialized to the initial power angle value calculated in the preprocessing stage, and the angular velocity deviation is initialized to zero. After initialization, each STSE sends a ready signal to the global synchronization controller.

[0072] After detecting that all STSEs have sent ready signals, the global synchronization controller issues a global start signal, and all STSEs simultaneously enter the simulation execution state. Each STSE independently performs time-domain numerical integration calculations for fault application, simulation during the fault, fault clearance, and post-fault recovery processes based on its assigned fault scenario description information (including fault type, fault location, fault duration, fault clearing method, etc.). Within each simulation step, the STSE sequentially completes the numerical integration of the generator electromechanical equations (updating power angle and angular velocity), the solution of the network equations (updating node voltages), and the convergence check of state variables. During the simulation, the stability criterion evaluation logic built into each STSE monitors the power angle deviation of each generator in real time. Once the maximum power angle difference of the system exceeds a preset threshold (the default threshold is 180 degrees, configurable), the fault scenario is determined to be transiently unstable, and the simulation is terminated early to shorten the calculation time for that scenario.

[0073] The simulation execution process proceeds step by step according to the simulation step size. The calculation process within each step is as follows:

[0074] At the start of each simulation step, the bus arbiter performs a parameter prefetch operation, broadcasting the shared admittance matrix and related parameters required for the current step from the Bank in the shared parameter storage module to the local buffers of each group. After prefetching is complete, the bus arbiter issues a calculation start signal.

[0075] Upon receiving the calculation start signal, each STSE first checks whether the current simulation time has reached the fault application time or the fault clearing time. If the fault application time has been reached, the simulation engine adds the incremental value of the admittance matrix stored in the fault control register to the corresponding element of the ground state admittance matrix read from the local cache, forming the admittance matrix during the fault period (this admittance matrix takes effect incrementally within the engine). If the fault clearing time has been reached, the simulation engine removes the incremental value and further modifies the admittance matrix according to the fault clearing method (such as removing the admittance element corresponding to the faulty line), forming the post-fault admittance matrix (also takes effect incrementally within the engine). In this application, each simulation engine modifies the admittance matrix elements online during the simulation process using a fixed-point incremental superposition method based on the assigned fault scenario description to simulate fault application and clearing. This eliminates the need to store the complete admittance matrix for each fault scenario, saving storage resources and providing a hardware-efficient method for parameterizing fault scenarios.

[0076] After the admittance matrix is ​​determined, each STSE performs a two-stage calculation using the improved Euler method. The first stage (prediction): Calculate the power angle derivative and angular velocity derivative of each generator based on the current state variable values. The predicted values ​​(including power angle and angular velocity estimates) are obtained by adding the current value to the step size and multiplying by the derivative. For example, the power angle estimate is obtained by adding the current power angle value to the product of the step size and the power angle derivative. The second stage (correction): Recalculate the derivatives based on the predicted values. The average of the two derivatives is multiplied by the step size and added to the current value to obtain the corrected state variable values ​​at the new time. The calculation of electromagnetic power in each stage requires the current node voltage information. The node voltage is obtained through iterative solution of the network equations within the STSE; the iterative solution process uses sparse admittance matrix multiplication and addition operations.

[0077] After the state variables are updated, the stability criterion evaluation logic embedded in STSE immediately calculates the difference between the maximum and minimum power angles of all generators at the current moment, obtaining the maximum power angle deviation value. If the maximum power angle deviation value exceeds the preset instability threshold, the engine writes the instability flag, the current simulation time, and the numbers of the two generators with the largest power angle difference into the result register, and stops the subsequent step-by-step simulation calculation for this fault scenario. If the preset instability threshold is not exceeded and the current simulation time has not reached the end of the simulation time window, the simulation engine continues to the next simulation step. If the current simulation time has reached the end of the simulation time window and the power angle difference is always within the preset instability threshold, the engine writes the stability flag and the maximum peak power angle difference recorded during the simulation (as a stability margin) into the result register and ends the simulation.

[0078] At the end of each simulation step, the global synchronization controller waits for all still-running STSEs to complete the current step calculation before issuing the prefetch and calculation signal for the next step, ensuring global synchronization. STSEs that have terminated prematurely do not participate in the synchronization wait.

[0079] Once all STSEs have completed simulation (i.e., all engines either output a stability flag at the end of the simulation time window or output an instability flag midway through the simulation), the result registers of all STSEs are scanned sequentially to read the stability judgment result, maximum power angle deviation value, instability occurrence time, and key generator number for each fault scenario. After collection, all fault scenarios are sorted from largest to smallest by maximum power angle deviation value. Unstable scenarios are marked as first alarm level (e.g., red alarm level) and a list of unstable faults is compiled. Fault scenarios with smaller stability margins (i.e., below a preset threshold) are marked as second alarm level (e.g., yellow alarm level, where the first alarm level is higher than the second alarm level). A comprehensive safety assessment report is generated, containing the number of unstable faults, the list of unstable faults, a stability margin ranking table, and system weakness identification. This report can be transmitted to the upper-level scheduling application system via an external data interface module for visualization and decision support.

[0080] It should be noted that when the resources of a single FPGA are insufficient to accommodate a sufficient number of simulation engines to cover all anticipated fault sets, a distributed parallel simulation scheme can be adopted, in which multiple FPGAs are cascaded through high-speed serial links (such as GTH / GTY transceivers). In this scheme, each FPGA carries a portion of the simulation engines, and the FPGAs synchronize clocks and exchange necessary global configuration information and result data through high-speed links (shared network static parameters can be stored locally on each FPGA to reduce interconnect bandwidth pressure). The advantage of this scheme is that it can linearly scale parallelism, breaking through the resource limitations of a single FPGA. The disadvantage is that the synchronization and communication overhead between multiple FPGAs will reduce the overall system efficiency, and the hardware complexity and cost of multi-board systems will increase. This application prioritizes the single-FPGA scheme to obtain the minimum communication latency and the simplest system architecture. When single-chip resources are insufficient, multi-FPGA cascading can be used as an expansion option, but it is recommended to prioritize increasing the number of engines that a single FPGA can accommodate by simplifying the simulation model (such as reducing the order of the generator model).

[0081] Besides the above-mentioned solutions, dedicated ASIC chips can also be designed to implement parallel simplified transient simulation engine arrays similar to those in this application. The advantages of ASIC solutions lie in higher chip area utilization, higher operating frequencies (up to GHz levels), and stronger computational performance per unit power consumption. However, the disadvantages of ASIC solutions are significant: First, ASIC design cycles are long (typically requiring 12 to 24 months), tape-out costs are extremely high (tape-out costs for advanced process nodes can reach millions to tens of millions of yuan), and once tape-out is completed, the circuit functionality is fixed, unable to adapt to changes in the scale of the power system model or the needs of simulation algorithm upgrades; second, ASIC solutions lack flexibility, and when the power system adds generators or lines, causing changes in model scale, the ASIC chip may not be adaptable and needs to be redesigned. In contrast, the FPGA solution adopted in this application has reconfigurable flexibility, and can adapt to power system models of different scales and different simulation algorithm requirements by resynthesizing and programming the bitstream, with a short development cycle and low iteration cost.

[0082] Compared with parallel scanning schemes for power system transient stability based on CPU / GPU heterogeneous clusters, the scheme in this application has significant advantages. In terms of computational speed, the CPU / GPU scheme inevitably limits parallel efficiency due to software and hardware overhead such as operating system task scheduling, inter-process communication, GPU kernel function startup latency, and cache misses caused by memory hierarchy. A complete scan of hundreds of fault scenarios typically takes several minutes to tens of minutes. This application adopts an FPGA hardware-level parallel architecture, where hundreds of simulation engines truly execute simultaneously at the hardware level. There is no operating system scheduling overhead or inter-process communication latency. The total computation time for scanning all fault scenarios is approximately equal to the computation time of a single scenario plus a minimal parameter loading and result aggregation overhead, which can be compressed to the second or even sub-second level, achieving true real-time online dynamic safety assessment.

[0083] In terms of hardware cost and power consumption, CPU / GPU cluster solutions typically require dozens of high-performance servers and multiple high-end GPU cards, with total system power consumption reaching several kilowatts to tens of thousands of watts, large footprint, and complex operation and maintenance. This application only requires one or a few FPGA acceleration boards to complete all computing tasks, with single board power consumption typically within tens of watts, reducing overall system power consumption by one to two orders of magnitude compared to CPU / GPU solutions. The low power consumption and small size characteristics make this application suitable not only for large computer room environments in provincial dispatch centers but also for compact deployment scenarios in regional dispatch centers and even at the edge of substations. Furthermore, the deterministic execution characteristics of FPGA hardware ensure that the computation time for each scan is highly stable and predictable, unaffected by operating system load fluctuations and background process interference. This is of significant value for applications requiring extremely high time determinism, such as online security analysis of power systems.

[0084] The online transient stability assessment method for power systems based on an FPGA parallel simulation engine described in this application can be applied to online safety analysis in provincial power dispatch centers. Provincial power dispatch centers need to perform N-1 fault scans on large-scale power systems containing hundreds of generators and thousands of lines, with the anticipated fault set typically containing 500 to 2000 fault scenarios. Traditional CPU cluster solutions require 5 to 20 minutes to complete a full scan, which is insufficient to keep up with the rapid changes in system operation. After deploying the solution described in this application, a single high-end FPGA can instantiate 300 to 500 simulation engines. Combined with a batch execution strategy, transient stability scans of all fault scenarios can be completed within seconds, providing dispatch operators with real-time safety assessment information synchronized with the current operating status.

[0085] This application can also be applied to the rapid safety verification of power grids with high penetration of new energy sources. With the large-scale integration of wind and solar power, the operation mode of the power system changes frequently, and traditional offline stability analysis can no longer meet the safety verification requirements. This application can be deployed at new energy collection stations or regional dispatch centers to continuously scan the transient stability of the system at a rate of seconds. When an impending change in the operation mode (such as a large fluctuation in wind power output) is detected that may lead to transient instability of the system, an early warning signal is issued in a timely manner.

[0086] This application's solution can also be applied to on-site safety assessments at the substation edge. Its low-power characteristics allow it to be deployed on embedded computing platforms within substations to perform on-site transient stability assessments of critical fault scenarios in the power grid within the substation's jurisdiction, without relying on communication links with remote dispatch centers, thus enhancing the autonomous safety decision-making capabilities at the edge.

[0087] Please refer to Figure 2 This application also provides a power system transient stability assessment system based on an FPGA simulation engine, including:

[0088] The management module is used to instantiate multiple simplified transient simulation engines with the same structure inside the FPGA chip. Each simplified transient simulation engine has an independent state variable storage space.

[0089] The data preprocessing module is used to preprocess the current power system operation section data, generate shared parameters and expected fault set description tables suitable for simplifying the transient simulation engine, and store the shared parameters and expected fault set description tables in the shared parameter storage module and fault parameter storage module on the FPGA chip, respectively.

[0090] The bus arbiter is used to group all simplified transient simulation engines using a group time-division multiplexing strategy. Each simplified transient simulation engine in each group accesses the shared parameters in the shared parameter storage module using a polling arbitration strategy. The groups access the shared parameters in the shared parameter storage module in an interleaved manner through a pipeline.

[0091] The task allocation module is used to assign each fault scenario to each simplified transient simulation engine, so that each simplified transient simulation engine reads the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module and performs initialization operations. After initialization is completed, it sends a ready signal to the global synchronization controller.

[0092] The global synchronization controller is used to send a global synchronization start signal to each simplified transient simulation engine after detecting that all simplified transient simulation engines have sent ready signals. This enables each simplified transient simulation engine to simultaneously perform electromechanical transient time-domain simulation of the power system according to the assigned fault scenario. After each simulation step, it performs a real-time stability assessment of the power angle state of each generator at the current moment and outputs the stability assessment results.

[0093] As a further improvement, the system also includes an external data interface module, which is used to connect to the power system energy management system or wide area measurement system via a PCIe interface or Ethernet interface to receive real-time updated power system operation section data; and to perform protocol parsing and integrity verification on the power system operation section data, extract the system status information at the current moment, and write the verified system status information into the input buffer of the external data interface module.

[0094] The external data interface module serves as a communication bridge between the system and external power system data sources. This module connects to the power system's EMS / SCADA or WAMS system via a PCIe 3.0 / 4.0 interface or a Gigabit / 10 Gigabit Ethernet interface to receive real-time updated power system operation profile data. Internally, the data interface module implements functions such as communication protocol parsing, data frame verification, CRC integrity checking, and data cache management. The interface module employs a double-buffering mechanism, ensuring that receiving a new round of operation profile data does not affect the current round of simulation calculations being performed within the FPGA, thus ensuring a pipelined operation of data updates and simulation execution.

[0095] The data preprocessing module is responsible for converting the floating-point format runtime profile data received from the external data interface module into the fixed-point format required by the FPGA simulation engine, and for calculating and organizing network parameters. Specific processing includes: converting system network topology and line parameters into node admittance matrices; converting generator operating data into parameter vectors required by classical second- or fourth-order electromechanical transient models; converting load data into constant impedance / constant current / constant power (ZIP) model parameters; and generating a pre-defined fault set description table based on a predefined list of fault types. The floating-point to fixed-point conversion in the preprocessing module uses a configurable scaling factor and bit width setting (typically 32-bit fixed-point numbers, with 16 integer bits and 16 fractional bits) to achieve a balance between computational accuracy and hardware resource consumption. All shared parameters after preprocessing are written to the shared parameter storage area.

[0096] The shared parameter storage module is built on the FPGA's on-chip Block RAM and is used to store static parameters of the power system (such as the ground-state admittance matrix and generator rated parameters) that are shared and read by all parallel simulation engines. The stored content includes node admittance matrices (containing real and imaginary parts, stored in a compressed sparse row or column format to save storage space), generator parameter vectors (including inertial time constant, damping coefficient, transient reactance, mechanical power, etc.), load model parameters, and a network topology index table. For a typical power system model with hundreds of nodes, the Block RAM capacity required for the shared parameter storage is approximately several hundred KB to several MB, which can be implemented within the on-chip storage resources of current mainstream FPGA chips. To improve the efficiency of concurrent reading by multiple engines, the shared parameter storage is divided into multiple independent banks, each of which can simultaneously serve different groups of simulation engines.

[0097] The bus arbiter is the core control logic that coordinates access to shared parameter storage by hundreds of parallel simulation engines. The arbiter employs a two-level arbitration architecture: the first level is intra-group arbitration, dividing all STSEs into several groups based on physical location and access mode (e.g., 8 or 16 STSEs per group). Within each group, a round-robin arbitration strategy is used to authorize each engine to access its corresponding shared storage bank in a fixed order. The second level is inter-group coordination, ensuring that each group accesses different banks of the shared storage within its allocated time window through a global clock synchronization signal, avoiding cross-group access conflicts. The arbiter also integrates an access request queue and a priority promotion mechanism. When an engine's access waiting time exceeds a threshold, its priority is automatically promoted to prevent starvation. The arbiter's clock frequency is consistent with the simulation engine's operating clock (typically 200MHz to 400MHz), and the delay for a single arbitration decision is 1 to 2 clock cycles. The core working principle of the on-chip bus arbiter is based on a grouped time-division multiplexing strategy. Taking 256 STSEs instantiated as an example, the arbiter divides the 256 engines into 16 groups of 16 engines each. The shared parameter storage is divided into 16 independent banks, each capable of responding to read requests independently. In normal operation, the arbiter controls the 16 groups to access each bank alternately according to a fixed schedule, controlled by a global synchronization clock. Since the simulation progress of all STSEs remains consistent under the control of the global synchronization signal, the range of shared parameter addresses that each engine needs to access within the same simulation step is also largely the same. The arbiter leverages this characteristic by prefetching the required shared parameters for each simulation step at the beginning and broadcasting them to the local parameter caches of each group. During subsequent calculations, each engine directly reads parameter data from its local cache, thus minimizing shared storage access conflicts during the simulation calculation phase. In special circumstances (such as when an engine needs to access different admittance matrix correction parameters due to different fault clearance methods), the arbiter initiates an on-demand access mode, handling access requests through a priority polling strategy.

[0098] Each STSE is equipped with an independent state variable storage module, implemented using on-chip distributed RAM or small-capacity Block RAM on the FPGA. The state variable storage space of each engine stores electromechanical transient state variables such as power angle, angular velocity, and transient electromotive force of all generators in the current simulation scenario, as well as intermediate variables and node voltage calculations during the simulation process. Independent state variable storage ensures that the simulation process between engines is completely independent; a fault scenario setting or intermediate simulation state in one engine will not affect the calculation results of other engines.

[0099] A stability criterion evaluation module is embedded within each STSE, performing real-time evaluation of the power angle state of each generator at the end of each simulation step. The evaluation logic uses the maximum power angle difference criterion: it calculates the maximum power angle difference between any two generators in the system at the current moment. If this value exceeds a preset instability threshold (the default threshold is 180 degrees, which is configurable), the current fault scenario is determined to be transiently unstable, the simulation of that engine is immediately terminated, and the instability flag and key indicators are written to the result register. If the maximum power angle difference is still within the threshold when the simulation runs to the end of the preset simulation time window (e.g., 5 seconds after the fault), the scenario is determined to be transiently stable.

[0100] As a further improvement, the system also includes a results aggregation and output module. This module is responsible for collecting all STSE simulation results, performing statistical analysis, and formatting the output. After all STSEs have completed their simulations (or after the set maximum waiting time has elapsed), this module sequentially reads the stability assessment results, simulation termination time, maximum power angle deviation value, and key generator numbers for each engine, and writes them to the results aggregation buffer. The aggregation module sorts the results by stability margin from smallest to largest, marks unstable fault scenarios, generates an unstable fault list and a stability margin sorting table, and transmits the results to the upper-level scheduling application system through an external data interface module.

[0101] After introducing the functions of each module, the complete workflow of this system is described below:

[0102] Step 1: FPGA hardware platform initialization and simulation engine configuration.

[0103] Upon system power-on or reconfiguration, the FPGA configuration bitstream is first loaded via JTAG or Flash to initialize the FPGA's internal logic. The configuration bitstream contains all hardware logic after pre-synthesis and placement / routing, including all circuitry for the external data interface module, data preprocessing module, shared parameter storage module, on-chip bus arbiter, parallel simulation engine array, and result aggregation and output module. After initialization, the system management module sets the following key operating parameters via the on-chip configuration register: the number of STSE instances (determined based on FPGA chip resources and the target power system model size, e.g., 256), simulation step size (e.g., 10 milliseconds), simulation time window length (e.g., 5 seconds after a fault, corresponding to 500 simulation steps), instability threshold (e.g., a fixed-point value corresponding to 180 degrees), and fixed-point scaling factor. These parameters are written to the FPGA's on-chip global configuration register for all modules to read during runtime. The initialization phase also includes grouping configuration of the on-chip bus arbiter (e.g., dividing the 256 engines into 16 groups of 16 engines each) and bank partitioning configuration of the shared parameter storage.

[0104] Step 2: Real-time acquisition and transmission of power system operation section data.

[0105] The system continuously monitors data update messages from the EMS / SCADA or WAMS systems via an external data interface module. Upon receiving new power system operation data, the interface module performs protocol parsing and integrity verification on the data frame, extracting the current system status information, including: active and reactive power output and terminal voltage of all generators, voltage amplitude and phase angle of all buses, active and reactive power flow of all lines, and the current system topology connection status (switch position information). Verified data is written to the input buffer of the external interface module. The input buffer employs a double-buffered structure; new data is written to the backup buffer, and after writing, a pointer is used to switch it to the current valid buffer, ensuring that data updates do not interfere with ongoing simulation calculations. The data acquisition cycle is synchronized with the data refresh cycle of the EMS / SCADA system, typically every few seconds to tens of seconds.

[0106] Step 3: Data preprocessing and shared parameter storage loading.

[0107] After detecting an update to the input buffer, the data preprocessing module initiates the parameter preprocessing process. First, it calculates the node admittance matrix based on the current system topology and line parameters. The admittance matrix calculation uses a branch-by-branch accumulation method: it initializes all elements of the admittance matrix to zero, then scans all branches in the system one by one. For each branch, its admittance value is accumulated into the corresponding four positions in the admittance matrix (two diagonal elements and two mutual admittance elements). After calculation, the admittance matrix is ​​converted to CSC sparse format. Second, it calculates the classical second-order model parameters for each generator: based on the generator terminal voltage, active power output, reactive power output, and transient reactance, it calculates the amplitude and phase angle of the transient electromotive force, and sets the mechanical power to be equal to the current active power output. Third, it calculates the ZIP model parameters for each load node, and the constant impedance portion can be converted into equivalent admittance and superimposed on the diagonal elements of the admittance matrix. Finally, all parameters are converted from floating-point format to 32-bit fixed-point format and written to the corresponding bank in the shared parameter storage according to a predefined address mapping scheme. The preprocessing module simultaneously generates a set of anticipated fault descriptions based on a predefined list of fault types and the current system topology. The description information for each fault scenario includes the fault type code, fault location node number, fault application time, fault duration, fault clearing method, and the incremental value of the admittance matrix that needs to be modified. The fault description table is written to the fault parameter storage area on the FPGA chip.

[0108] Step 4: Simulation task allocation and engine initialization.

[0109] After the shared parameters are loaded, the task allocation module assigns the fault scenarios from the anticipated fault set to each STSE one by one. The allocation strategy is a simple sequential mapping: fault scenario numbers 0 to N-1 are assigned to STSE numbers 0 to N-1 respectively (where N is the number of STSE instances). If the total number of fault scenarios exceeds N, the next batch will be allocated after the first batch of N scenarios has been simulated. After receiving the assigned fault scenario number, each STSE reads the fault description information of that scenario from the fault parameter storage area and loads it into the fault control register inside the engine. At the same time, each STSE initializes all generator state variables in its independent state variable storage to steady-state operating values: the power angle is initialized to the initial power angle value calculated in the preprocessing stage, and the angular velocity deviation is initialized to zero. After initialization, each STSE sends a ready signal to the global synchronization controller.

[0110] Step 5: Global synchronous startup and parallel simulation execution.

[0111] After detecting that all STSEs have sent ready signals, the global synchronization controller issues a global synchronization start signal, and all STSEs simultaneously enter the simulation execution state. The simulation execution process proceeds step by step according to the simulation step size, and the calculation flow within each step is as follows:

[0112] At the start of each simulation step, the on-chip bus arbiter performs a parameter prefetch operation, broadcasting the shared admittance matrix and related parameter data required for the current step from the shared memory bank to the local cache of each group. After prefetching is complete, the arbiter issues a computation start signal.

[0113] Upon receiving the calculation start signal, each STSE first checks whether the current simulation time has reached the fault application time or the fault clearing time. If the fault application time has been reached, the engine adds the incremental value of the admittance matrix stored in the fault control register to the corresponding element of the ground-state admittance matrix read from the local cache to form the admittance matrix during the fault period (this admittance matrix takes effect incrementally within the engine). If the fault clearing time has been reached, the engine removes the incremental value and further modifies the admittance matrix according to the fault clearing method (such as removing the admittance element corresponding to the faulty line) to form the post-fault admittance matrix (also takes effect incrementally within the engine).

[0114] After the admittance matrix is ​​determined, each STSE performs a two-stage calculation using the improved Euler method. The first stage (prediction): Calculate the power angle derivative and angular velocity derivative of each generator based on the current state variable values. The predicted value is obtained by adding the current value to the step size and multiplying by the derivative. The second stage (correction): Recalculate the derivatives based on the predicted values. The corrected state variable values ​​are obtained by averaging the two derivatives, multiplying by the step size, and adding the current value. The calculation of electromagnetic power in each stage requires the current node voltage information. The node voltage is obtained through iterative solving of the network equations within the STSE; the iterative solution process uses sparse admittance matrix multiplication and addition operations.

[0115] After the state variables are updated, the stability criterion evaluation logic embedded in STSE immediately calculates the difference between the maximum and minimum power angles of all generators at the current moment. If the difference exceeds the instability threshold, the engine writes the instability flag, the current simulation moment, and the numbers of the two generators with the largest power angle differences into the results register, and stops the subsequent step-size simulation calculations for that scenario. If the threshold is not exceeded and the current simulation moment has not reached the end of the simulation time window, the engine continues to the next step. If the current simulation moment has reached the end of the simulation time window and the power angle difference remains within the threshold, the engine writes the stability flag and the maximum peak power angle difference recorded during the simulation into the results register and ends the simulation.

[0116] At the end of each simulation step, the global synchronization controller waits for all still-running STSEs to complete the current step calculation before issuing the prefetch and calculation signal for the next step, ensuring global synchronization. STSEs that have terminated prematurely do not participate in the synchronization wait.

[0117] Step Six: Aggregate Scan Results and Generate a Security Assessment Report.

[0118] Once all STSEs have completed simulation (i.e., all engines either output a stability flag at the end of the simulation time window or output an instability flag midway through the simulation), the results aggregation and output module initiates the results collection process. This module sequentially scans the result registers of all STSEs, reading the stability assessment results, maximum power angle deviation value, instability occurrence time, and key generator numbers for each fault scenario. After collection, the aggregation module performs the following processing: all fault scenarios are sorted from largest to smallest by maximum power angle deviation value; unstable scenarios are marked as first alarm level and a list of unstable faults is compiled; scenarios with smaller stability margins are marked as second alarm level. The aggregation module generates a comprehensive safety assessment report data structure containing the number of unstable faults, the list of unstable faults, a stability margin ranking table, and system vulnerability identifiers. This data is then transmitted to the upper-level scheduling application system via an external data interface module for visualization and decision support.

[0119] Step 7: Cyclic updates and continuous operation.

[0120] After a transient stability scan is completed, the system automatically enters a waiting state. When the external data interface module receives a new round of operational section data updates, the system restarts the parameter preprocessing, task allocation, and parallel simulation processes from step three, enabling continuous tracking and real-time safety assessment of changes in the power system's operating status. Due to the deterministic execution characteristics of the FPGA hardware platform, the computation time for each scan is highly predictable and stable, allowing dispatchers to continuously obtain dynamic safety assessment results synchronized with the current operating status.

[0121] In summary, this application instantiates a large number of structurally identical STSEs within the FPGA. Each STSE acts as an independent hardware computing unit responsible for the complete transient stability simulation of a fault scenario. Unlike the SIMT (Single Instruction, Multithreaded) parallel mode of GPUs, each STSE in this invention is a completely independent hardware logic entity with independent control logic, data paths, and state variable storage, and is not constrained by a unified instruction flow. This means that different STSEs can perform fault application or fault clearance operations at different times (because the fault duration varies in different fault scenarios), without causing other engines to wait idly due to instruction branches, thus achieving ideal parallel efficiency. Each STSE adopts a fully pipelined data path design, with numerical integration, matrix-vector multiplication and addition, and other operations executed sequentially according to pipeline stages, enabling the STSE throughput to reach a highly efficient hardware parallelism level.

[0122] This application divides the simulation data into two categories: one is the static parameters of the power system network shared by all fault scenarios (such as the ground-state admittance matrix and generator rated parameters), and the other is the dynamic state variables specific to each fault scenario (such as the current power angle and angular velocity of each generator). The former is stored in a shared Block RAM on the FPGA chip for all engines to read, while the latter is stored in a private distributed RAM for each engine. The advantages of this storage architecture are: shared parameters only need to be stored once, which greatly saves on-chip storage resources on the FPGA, enabling more STSEs to be instantiated with limited chip resources; at the same time, independent storage of state variables ensures the complete independence of the simulation process of each engine.

[0123] To address the bandwidth bottlenecks and access conflicts that may result from hundreds of engines simultaneously accessing the shared parameter storage module, this application designs a two-level grouped time-division multiplexing arbitration mechanism. Combined with a parameter prefetching and broadcasting strategy at the start of the step size, this minimizes shared storage access conflicts during the simulation calculation phase. The arbitrator's hardware overhead is extremely small (less than one-thousandth of the FPGA logic resources), yet it effectively ensures the efficient concurrent operation of hundreds of engines.

[0124] Each STSE's embedded stability criterion evaluation logic can immediately determine the stability state of the current fault scenario after each simulation step. Once it is determined to be unstable, the engine immediately stops the calculation of subsequent steps for that scenario and outputs an instability flag and key indicators, allowing the results aggregation module to complete the collection of results for that scenario earlier, thereby shortening the maximum completion time of the overall scan (especially when executing in batches, it can enter the next batch of scenarios earlier).

[0125] Compared with parallel scanning schemes for power system transient stability based on CPU / GPU heterogeneous clusters, the scheme in this application has significant advantages. In terms of computational speed, the CPU / GPU scheme inevitably limits parallel efficiency due to software and hardware overhead such as operating system task scheduling, inter-process communication, GPU kernel function startup latency, and cache misses caused by memory hierarchy. A complete scan of hundreds of fault scenarios typically takes several minutes to tens of minutes. This application adopts an FPGA hardware-level parallel architecture, where hundreds of simulation engines truly execute simultaneously at the hardware level. There is no operating system scheduling overhead or inter-process communication latency. The total computation time for scanning all fault scenarios is approximately equal to the computation time of a single scenario plus a minimal parameter loading and result aggregation overhead, which can be compressed to the second or even sub-second level, achieving true real-time online dynamic safety assessment.

[0126] In terms of hardware cost and power consumption, CPU / GPU cluster solutions typically require dozens of high-performance servers and multiple high-end GPU cards, with total system power consumption reaching several kilowatts to tens of thousands of watts, large footprint, and complex operation and maintenance. This application only requires one or a few FPGA acceleration boards to complete all computing tasks, with single board power consumption typically within tens of watts, reducing overall system power consumption by one to two orders of magnitude compared to CPU / GPU solutions. The low power consumption and small size characteristics make this application suitable not only for large computer room environments in provincial dispatch centers but also for compact deployment scenarios in regional dispatch centers and even at the edge of substations. Furthermore, the deterministic execution characteristics of FPGA hardware ensure that the computation time for each scan is highly stable and predictable, unaffected by operating system load fluctuations and background process interference. This is of significant value for applications requiring extremely high time determinism, such as online security analysis of power systems.

[0127] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0128] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus.

[0129] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0133] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for executing all or part of the steps of the methods described in the various embodiments of this application through a computer device (which may be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0134] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for evaluating the transient stability of a power system based on an FPGA simulation engine, characterized in that, include: Multiple simplified transient simulation engines with identical structures are instantiated inside the FPGA chip, and each of the simplified transient simulation engines has an independent state variable storage space; The current power system operation section data is preprocessed to generate shared parameters and a set of expected fault descriptions suitable for the simplified transient simulation engine, and the shared parameters and the set of expected fault descriptions are stored in the shared parameter storage module and the fault parameter storage module on the FPGA chip, respectively. A grouping time-division multiplexing strategy is adopted to group all the simplified transient simulation engines. The simplified transient simulation engines in each group use a round-robin arbitration strategy to access the shared parameters in the shared parameter storage module. The groups access the shared parameters in the shared parameter storage module in an interleaved manner through a pipeline. Each fault scenario is assigned to one of the simplified transient simulation engines. A global synchronization start signal controls each simplified transient simulation engine to start the simulation simultaneously. Each simplified transient simulation engine reads the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module to perform electromechanical transient time-domain simulation of the power system. After each simulation step, the power angle state of each generator at the current moment is evaluated in real time, and the stability evaluation result is output.

2. The power system transient stability assessment method based on FPGA simulation engine according to claim 1, characterized in that, The preprocessing of current power system operating section data to generate shared parameters and a set of anticipated fault descriptions suitable for use by the simplified transient simulation engine includes: Construct a node admittance matrix from the system network topology information and line parameters in the current power system operation section data; Calculate the generator parameter vector required for the classical second-order or fourth-order electromechanical transient model, or the classical fourth-order electromechanical transient model, based on the current operating conditions and equipment parameters of each engine in the current power system operating section data. The load data in the current power system operation section data is converted into ZIP model parameters to obtain the load parameter vector; The admittance matrix, generator parameter vector, and load parameter vector in floating-point format are converted into admittance matrix, generator parameter vector, and load parameter vector in fixed-point format; the shared parameters include admittance matrix, generator parameter vector, and load parameter vector in fixed-point format. Based on the system network topology information and a predefined list of fault types, a hypothetical fault set description table is generated. The hypothetical fault set description table includes the fault type code, fault location node number, fault application time, fault duration, fault clearance method, and the incremental value of the admittance matrix that needs to be modified for each fault scenario.

3. The power system transient stability assessment method based on FPGA simulation engine according to claim 2, characterized in that, The simplified transient simulation engine performs time-domain simulation of power system electromechanical transients based on the assigned fault scenarios, including: After receiving the calculation start signal, the simplified transient simulation engine checks whether the current simulation time has reached the fault application time or the fault clearing time. If the fault application time is reached, the simplified transient simulation engine will add the incremental value of the admittance matrix to the corresponding element of the ground state admittance matrix read from the local cache to form the admittance matrix during the fault period. If the fault clearing time is reached, the simplified transient simulation engine removes the incremental value of the admittance matrix and modifies the admittance matrix according to the fault clearing method to form the post-fault admittance matrix. The simplified transient simulation engine calculates the power angle derivative and angular velocity derivative of each generator based on the current state variable values, and calculates the power angle estimate and angular velocity estimate based on the power angle derivative and angular velocity derivative of each generator; it recalculates the power angle derivative and angular velocity derivative based on the power angle estimate and angular velocity estimate, calculates the corrected new state variable values ​​based on the average of the two power angle derivatives and angular velocity derivatives, and enters the next simulation step until the preset simulation time is reached.

4. The power system transient stability assessment method based on FPGA simulation engine according to claim 1, characterized in that, After each simulation step, a real-time stability assessment is performed on the power angle state of each generator at the current moment, and the stability assessment results are output, including: After each simulation step, the difference between the maximum and minimum power angle values ​​of all generators in the power system at the current moment is calculated to obtain the maximum power angle deviation value; If the maximum power angle deviation exceeds the preset instability threshold, an instability flag, the current simulation time, and the engine identifier of the instability will be output, and the subsequent step-size simulation calculation of the current fault simulation will be stopped.

5. The power system transient stability assessment method based on FPGA simulation engine according to claim 4, characterized in that, The method further includes: The stability evaluation results of all the simplified transient simulation engines are scanned sequentially, and the maximum power angle deviation values ​​of all fault scenarios are sorted in descending order. Unstable scenarios are marked as the first alarm level and a list of unstable faults is compiled. Fault scenarios with stability margins lower than the preset stability margin threshold are marked as the second alarm level. A comprehensive safety assessment report is generated, which includes the number of unstable faults, the list of unstable faults, the stability margin ranking table, and the identification of system weaknesses. The stability margin is the peak value of the maximum power angle difference.

6. A power system transient stability assessment system based on an FPGA simulation engine, characterized in that, include: The management module is used to instantiate multiple simplified transient simulation engines with the same structure inside the FPGA chip, and each of the simplified transient simulation engines has an independent state variable storage space; The data preprocessing module is used to preprocess the current power system operation section data, generate a shared parameter and a set of expected fault description tables suitable for the simplified transient simulation engine, and store the shared parameter and the set of expected fault description tables in the shared parameter storage module and the fault parameter storage module on the FPGA chip, respectively. A bus arbiter is used to group all the simplified transient simulation engines using a group time-division multiplexing strategy. Each simplified transient simulation engine in each group accesses the shared parameters in the shared parameter storage module using a polling arbitration strategy. The groups access the shared parameters in the shared parameter storage module in an interleaved manner through a pipeline. The task allocation module is used to allocate each fault scenario to each of the simplified transient simulation engines, so that each simplified transient simulation engine reads the fault description information of the corresponding fault scenario from the expected fault set description table in the fault parameter storage module and performs initialization operation. After the initialization is completed, it sends a ready signal to the global synchronization controller. A global synchronization controller is used to send a global synchronization start signal to each of the simplified transient simulation engines after detecting that all of the simplified transient simulation engines have sent a ready signal, so that each of the simplified transient simulation engines can simultaneously perform electromechanical transient time-domain simulation of the power system according to the assigned fault scenario, and after each simulation step, perform a real-time stability assessment of the power angle state of each generator at the current moment and output the stability assessment result.

7. The power system transient stability assessment system based on FPGA simulation engine according to claim 6, characterized in that, The system also includes: The results aggregation and output module is used to sequentially scan the stability evaluation results of all the simplified transient simulation engines, sort the maximum power angle deviation values ​​of all fault scenarios in descending order, mark unstable scenarios as the first alarm level and list unstable faults, mark fault scenarios with stability margins lower than the preset stability margin threshold as the second alarm level, and generate a comprehensive safety assessment report containing the number of unstable faults, the list of unstable faults, the stability margin ranking table, and the identification of system weak links. The stability margin is the peak value of the maximum power angle difference.

8. The power system transient stability assessment system based on FPGA simulation engine according to claim 6, characterized in that, The system also includes: The external data interface module is used to connect to the power system energy management system or wide area measurement system via a PCIe interface or Ethernet interface to receive real-time updated power system operation section data; and to perform protocol parsing and integrity verification on the power system operation section data, extract the system status information at the current moment, and write the verified system status information into the input buffer of the external data interface module.

9. The power system transient stability assessment system based on FPGA simulation engine according to claim 6, characterized in that, The simplified transient simulation engine has a stability criterion evaluation module embedded within it; The stability criterion evaluation module is specifically used to calculate the difference between the maximum and minimum power angle values ​​of all generators in the power system at the current moment after each simulation step, so as to obtain the maximum power angle deviation value. If the maximum power angle deviation exceeds the preset instability threshold, an instability flag, the current simulation time, and the engine identifier of the instability will be output, and the subsequent step-size simulation calculation of the current fault simulation will be stopped.

10. The power system transient stability assessment system based on FPGA simulation engine according to claim 6, characterized in that, The system also includes an independent state variable storage module, which is used to equip each of the simplified transient simulation engines with an independent state variable storage space. The state variable storage space of each simplified transient simulation engine is used to save the electromechanical transient state quantities under its current simulation scenario, as well as the intermediate variables and intermediate quantities of the node voltage solution in the simulation process.

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