Control method of an electromagnetic compatibility optimization device and electromagnetic compatibility optimization device

Abstract

This application discloses a control method and an electromagnetic compatibility (EMC) optimization device, comprising: acquiring the type of abnormal coil structure in a prototype capable of generating or receiving electromagnetic interference, and the detection results of EMC testing corresponding to the abnormal coil structure; determining an equivalent model of the abnormal coil structure based on its type, the equivalent model including at least one of a series RLC resonant model, a loop inductor model, and a micro-inductive coupling model; determining the risk level of the abnormal coil structure based on the detection results and the equivalent model, the detection results including at least one of the magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning; and generating and prompting corresponding EMC optimization strategies based on the type and risk level. This application aims to improve the EMC performance of the prototype.

Description

Technical Field

[0001] This application relates to the field of electromagnetic compatibility design, specifically to a control method and an electromagnetic compatibility optimization device. Background Technology

[0002] Existing electromagnetic compatibility optimization methods in this field are inefficient and lack specificity, making it difficult to adapt to the design requirements of miniaturized and high-frequency prototypes. This not only increases the cost of prototype modification but also prolongs the product development cycle. Summary of the Invention

[0003] The main purpose of this application is to propose a control method and an electromagnetic compatibility optimization device for improving the electromagnetic compatibility performance of the prototype.

[0004] This application proposes a control method for an electromagnetic compatibility optimization device, comprising the following steps: The types of abnormal coil structures in the prototype that can generate or receive electromagnetic interference are obtained, as well as the detection results of the electromagnetic compatibility test corresponding to the abnormal coil structure. Based on the type of the abnormal coil structure, an equivalent model of the abnormal coil structure is determined. The equivalent model includes at least one of the following: series RLC resonant model, loop inductor model, and micro inductor coupling model. Based on the detection results and the equivalent model, the risk level of the abnormal coil structure is determined. The detection results include at least one of the following: magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning. Based on the type and risk level, generate and suggest corresponding electromagnetic compatibility optimization strategies.

[0005] Optionally, the step of obtaining the type of abnormal coil structure in the prototype capable of generating or receiving electromagnetic interference includes: The location of the abnormal coil structure on the surface of the prototype is obtained, and the type of the abnormal coil structure is determined based on the determined location.

[0006] Optionally, the step of obtaining the location of the abnormal coil structure on the surface of the prototype includes: Obtain the PCB source file of the prototype; Based on the PCB source files of the prototype and preset rules, the location of the abnormal coil structure on the surface of the prototype is determined; The preset rules include: The component library is searched for components of type surface mount, their package size and coordinate position are extracted, and the surface mount component is identified as the abnormal coil structure. Analyze the signal network topology, identify closed loops consisting of a driving source, a load, and a return path, calculate the area of ​​the closed loop, and determine the loops whose area is greater than a preset area threshold as the abnormal coil structure. Read the internal structure keywords in the chip datasheet, or identify the high-frequency pins marked as switch nodes or clock outputs in the chip pins, and determine that the circuit formed by the high-frequency pins of the chip is the abnormal coil structure.

[0007] Optionally, determining the location of the abnormal coil structure on the prototype surface based on the prototype's PCB source file and preset rules includes: The signal network topology is analyzed to identify the location of the power chip on the sample surface. Based on the PCB source file of the prototype, the location of the SW pin of the power chip is determined, and the first electrical circuit to which the SW pin of the power chip belongs is determined. The first electrical circuit is formed by: SW pin, inductor, capacitor, PCB plane ground, chip ground pin, and internal pull-down pin of the chip. The abnormal coil structure includes: the first electrical circuit. Determining the type of the abnormal coil structure based on the determined location includes: Calculate the length of the path of the first electrical loop and the width of the current return path, and determine the area of ​​the loop based on the length of the path of the loop and the width of the current return path. If the area of ​​the circuit is greater than the preset area threshold, the first electrical circuit is determined to be a second type of abnormal coil structure.

[0008] Optionally, the step of obtaining the location of the abnormal coil structure on the surface of the prototype further includes: The results of scanning the prototype surface at a preset scanning frequency using a near-field probe and a spectrum analyzer are obtained, and the location of the abnormal coil structure on the prototype surface is determined based on the scanning results.

[0009] Optionally, the step of determining the type of the abnormal coil structure therein based on the determined location includes: When the abnormal coil structure is a surface-mount inductor, a ferrite bead, or a common-mode inductor, the type of the abnormal coil structure is determined to be a first-type abnormal coil structure. When the abnormal coil structure is a closed loop consisting of a drive source, a load, and a return path, or a three-dimensional loop consisting of a serpentine trace, a via, and a plane, the type of the abnormal coil structure is determined to be a second type of abnormal coil structure. When the abnormal coil structure is an inductor, transformer, or micro-magnetic structure integrated inside the chip, the type of the abnormal coil structure is determined to be a third type of abnormal coil structure.

[0010] Optionally, the step of determining the equivalent model of the abnormal coil structure based on the type of the abnormal coil structure includes: When the abnormal coil structure is the first type of abnormal coil structure, the equivalent inductance, parasitic capacitance, and equivalent resistance are extracted according to the component datasheet to determine the first equivalent model corresponding to the first type of abnormal coil structure; or, The first equivalent model corresponding to the abnormal coil structure is determined based on the fitting results of the measured S-parameters using a network analyzer. When the abnormal coil structure is the second type of abnormal coil structure, the second equivalent model corresponding to the second type of abnormal coil structure is determined according to the loop geometry, trace length, width, and interlayer distance; In the case where the abnormal coil structure is the third type of abnormal coil structure, the internal inductance value and coupling coefficient in the chip datasheet are consulted to determine the third equivalent model corresponding to the third type of abnormal coil structure. or, The third equivalent model corresponding to the third type of abnormal coil structure is determined based on the relevant parameters measured between the corresponding pins by the impedance analyzer. The first equivalent model is a series RLC resonance model; The second equivalent model is a loop inductance model; The third equivalent model is a micro inductive coupling model.

[0011] Optionally, the step of determining the risk level of the abnormal coil structure based on the detection results and the equivalent model includes: In a DC-DC power supply circuit, if the magnetic field strength for near-field scanning of the prototype surface exceeds a first preset strength, or the radiation emission value exceeds a preset standard value, or the radiation emission margin is less than a first preset margin, the risk level of the abnormal coil structure is determined to be high risk. If the magnetic field strength for near-field scanning of the prototype surface is greater than the first preset strength and less than the second preset strength, or if the radiation emission margin is between the second preset margin and the third preset margin, the risk level of the abnormal coil structure is determined to be medium risk. If the magnetic field strength during near-field scanning of the prototype surface is less than the second preset strength and the radiation emission margin is greater than the third preset margin, the risk level of the abnormal coil structure is determined to be low risk. The abnormal coil structure is a parasitic coil formed by clock signal lines and other high-speed signal lines and the ground layer. When the radiated emission value exceeds the preset standard value or the radiated emission margin is less than the first preset margin and the harmonics of the clock frequency fall in the preset frequency band, the risk level of the abnormal coil structure is determined to be high risk. If the radiation emission margin is between the second and third preset margins, or the amplitude of the odd harmonics of the clock frequency is between the first and second preset amplitudes and the loop area is greater than the first preset area threshold, the risk level of the abnormal coil structure is determined to be medium risk. If the radiation emission margin is greater than the third preset margin or the clock frequency is less than the preset frequency and the loop area is less than the second preset area threshold, the risk level of the abnormal coil structure is determined to be low risk. The abnormal coil structure is a single-turn coil made of long wires. When the length of the wires is greater than or equal to a first preset length, the risk level of the abnormal coil structure is determined to be high risk. If the length of the conductor is less than the first preset length but greater than the second preset length, the risk level of the abnormal coil structure is determined to be medium risk. If the length of the conductor is less than the second preset length, the risk level of the abnormal coil structure is determined to be low risk.

[0012] Optionally, the step of generating and suggesting corresponding electromagnetic compatibility optimization strategies based on the type and the risk level includes: When the risk level of the abnormal coil is high risk, a corresponding electromagnetic compatibility optimization strategy is generated and suggested based on the type. When the abnormal coil structure is the first type of abnormal coil structure, select a component with a saturation current value greater than or equal to a preset current value and a parasitic capacitance value less than or equal to a preset capacitance value; and / or, control the current loop length within a preset length; When the abnormal coil structure is the second type of abnormal coil structure, the loop area is controlled within a preset loop area; and / or, the via spacing is controlled within a preset spacing; and / or, the loop impedance is controlled within a preset range. When the abnormal coil structure is the third type of abnormal coil structure, the pin trace length is controlled within a preset trace length; and / or, a filter element is added at the pin.

[0013] This application also proposes an electromagnetic compatibility optimization device for performing the control method of the electromagnetic compatibility optimization device as described in any of the above claims.

[0014] The control method of the electromagnetic compatibility optimization device of this application includes the following steps: obtaining the type of abnormal coil structure in the prototype that can generate or receive electromagnetic interference, and the detection results after electromagnetic compatibility testing corresponding to the abnormal coil structure; determining the equivalent model of the abnormal coil structure based on the type of the abnormal coil structure, the equivalent model including at least one of the following: series RLC resonant model, loop inductor model, and micro inductor coupling model; determining the risk level of the abnormal coil structure based on the detection results and the equivalent model, the detection results including at least one of the following: magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning; and generating and prompting corresponding electromagnetic compatibility optimization strategies based on the type and risk level. Through the above settings, abnormal coil structures are classified and three types of equivalent models (series RLC resonant model, loop inductor model, and micro inductor coupling model) are established, transforming the concepts of "parasitic loop" and "hidden coil" that originally relied on engineer experience into visible geometric figures and calculable electrical parameters in EDA software, so that the electromagnetic compatibility optimization device can directly call the model for risk assessment. This transforms the traditional electromagnetic compatibility optimization work, which relies on engineers' experience, into a closed-loop optimization method based on quantitative standards and executed automatically by computer equipment, thereby significantly improving rectification efficiency, reducing costs, and shortening the R&D cycle. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a method for controlling the electromagnetic compatibility optimization device according to an embodiment of the present application; Figure 2 This is a schematic flowchart of the method for obtaining the type of abnormal coil structure in the prototype in the control method of the electromagnetic compatibility optimization device of this application; Figure 3 This is a schematic flowchart of the method for obtaining the location of abnormal coil structures on the surface of a prototype in the control method of the electromagnetic compatibility optimization device of this application; Figure 4 This is a schematic flowchart of another method for obtaining the location of abnormal coil structures on the surface of a prototype in the control method of the electromagnetic compatibility optimization device of this application; Figure 5 This is a flowchart illustrating the method for determining the type of abnormal coil structure based on a given location in the control method of the electromagnetic compatibility optimization device of this application. Figure 6 This is a schematic diagram of the method for determining the equivalent model of an abnormal coil structure based on the type of abnormal coil structure in the control method of the electromagnetic compatibility optimization device of this application. Figure 7 This is a schematic diagram of the method for determining the risk level of an abnormal coil structure in a DC-DC power supply circuit in the control method of the electromagnetic compatibility optimization device of this application. Figure 8 This is a flowchart illustrating the method for determining the risk level of a parasitic coil structure consisting of a clock signal line, other high-speed signal lines, and ground in the control method of the electromagnetic compatibility optimization device of this application. Figure 9 This is a flowchart illustrating the method for determining the risk level of a single-turn coil with a long conductor in the control method of the electromagnetic compatibility optimization device of this application. Figure 10 This is a schematic diagram of the process for generating and prompting corresponding electromagnetic compatibility optimization strategies based on type and risk level in the control method of the electromagnetic compatibility optimization device of this application.

[0017] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0020] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0021] Currently, existing electromagnetic compatibility optimization methods in this field are inefficient and lack specificity, making it difficult to adapt to the design requirements of miniaturized and high-frequency prototypes. This not only increases the cost of prototype modification but also prolongs the product development cycle.

[0022] As electronic devices become increasingly miniaturized and integrated, prototype motherboard designs are becoming more compact. Traditionally, large, and visible coils made of copper wire (such as transformers and power inductors) are gradually being replaced by miniaturized components or hidden parasitically inside the prototype. Designers often narrowly define "coil" and focus only on discrete, exposed coil components, neglecting the "hidden equivalent coils" that are widely present in prototypes.

[0023] This application provides an electromagnetic compatibility optimization method that systematically identifies and classifies hidden equivalent coils in prototypes, and formulates targeted control strategies based on their types and interference characteristics. This reduces the risk of electromagnetic compatibility test failures, shortens product development cycles, reduces prototype rectification costs, and simultaneously improves the electromagnetic compatibility performance and market competitiveness of prototypes.

[0024] Therefore, this application proposes a control method for an electromagnetic compatibility optimization device, referring to... Figure 1 In one embodiment of this application, the control method of the electromagnetic compatibility optimization device includes the following steps: S100. Obtain the type of abnormal coil structure in the prototype that can generate or receive electromagnetic interference, and the test results after electromagnetic compatibility testing of the abnormal coil structure. S200. Based on the type of abnormal coil structure, determine the equivalent model of the abnormal coil structure. The equivalent model includes at least one of the following: series RLC resonant model, loop inductor model, and micro inductor coupling model. S300. Based on the detection results and equivalent model, determine the risk level of the abnormal coil structure. The detection results include at least one of the following: magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning. S400 generates and suggests corresponding electromagnetic compatibility optimization strategies based on type and risk level.

[0025] It is important to understand that the electromagnetic compatibility optimization device contains a control module, which is used to execute the control methods described above.

[0026] Alternatively, the control module can be implemented using a main controller, such as an MCU, PLC, DSP (Digital Signal Processor), SOC (System on Chip), FPGA (Field Programmable Gate Array), etc.

[0027] In this embodiment, optionally, the electromagnetic compatibility optimization device first obtains the types of abnormal coil structures in the prototype that can generate or receive electromagnetic interference. These abnormal coil structures include: a first type of abnormal coil structure (surface-mount inductor, ferrite bead, or common-mode inductor); a second type of abnormal coil structure (a closed loop consisting of a drive source, load, and return path, or a three-dimensional loop consisting of serpentine traces, vias, and planes); and a third type of abnormal coil structure (inductors, transformers, or micro-magnetic structures integrated within the chip).

[0028] Optionally, the electromagnetic compatibility optimization device acquires the electromagnetic compatibility test results corresponding to the abnormal coil structure. The test results include at least one of the following: magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning.

[0029] Optionally, the equivalent model for the first type of abnormal coil structure is a series RLC resonant model, the equivalent model for the second type of abnormal coil structure is a loop inductor model, and the equivalent model for the third type of abnormal coil structure is a miniature inductor coupling model. The parameters of the equivalent model can be obtained through component datasheets, measured S-parameters from a network analyzer, loop geometry, chip datasheets, or impedance analyzers.

[0030] Optionally, the risk level of the abnormal coil structure can be determined as high-risk, medium-risk, or low-risk by combining the detection results and the equivalent model. For example: if the abnormal coil structure is located in a DC-DC power supply circuit, and the near-field scanning magnetic field strength exceeds a first preset strength, or the radiated emission value exceeds a standard value, or the radiated emission margin is less than a first preset margin, the risk level is determined to be high-risk; if the near-field scanning magnetic field strength on the prototype surface is greater than a first preset strength but less than a second preset strength, or the radiated emission margin is between a second and a third preset margin, the risk level of the abnormal coil structure is determined to be medium-risk; if the near-field scanning magnetic field strength on the prototype surface is less than a second preset strength but the radiated emission margin is greater than a third preset margin, the risk level of the abnormal coil structure is determined to be low-risk.

[0031] Optionally, based on the type and risk level of the abnormal coil structure, corresponding optimization strategies are generated and suggested: In the case of a high-risk Type I abnormal coil structure, the suggestion is to select components with a saturation current value greater than or equal to a preset current value and a parasitic capacitance value less than or equal to a preset capacitance value, and to control the current loop length within a preset length; In the case of a high-risk Type II abnormal coil structure, the suggestion is to control the loop area within a preset area, or control the via spacing within a preset spacing, or control the loop impedance within a preset range; In the case of a high-risk Type III abnormal coil structure, the suggestion is to control the pin trace length within a preset length, or to add a filter component at the pin.

[0032] In one example, taking a prototype DC-DC power module as an example, the electromagnetic compatibility optimization device analyzed the prototype's PCB source file and identified a high-frequency current loop formed by the SW pin of the DC-DC power chip, the inductor connected to it, the output capacitor, and the ground plane. This loop was identified as a typical abnormal coil structure due to its extremely high current change rate.

[0033] Meanwhile, the electromagnetic compatibility optimization device obtains the electromagnetic compatibility test results corresponding to the abnormal coil structure, including: the magnetic field strength distribution map obtained by scanning the prototype surface with a near-field probe, and the radiated emission values ​​and corresponding radiated emission margins in the 30MHz-1GHz frequency band measured by the prototype in the radiated emission test.

[0034] Based on the type of the abnormal coil structure (i.e., the high-frequency current loop of the DC-DC power supply) identified in step S100, the electromagnetic compatibility optimization device determines that it belongs to the "second type of abnormal coil structure" (a closed loop consisting of a driving source, a load, and a return path). Based on this type, the electromagnetic compatibility optimization device determines that its corresponding equivalent model is a loop inductance model.

[0035] Subsequently, the electromagnetic compatibility optimization device calculates the loop inductance value in the equivalent model based on the actual geometry of the loop—including the area of ​​the polygon enclosed by the loop, the trace length, the trace width, and the interlayer distance between the top and bottom ground planes. The electromagnetic compatibility optimization device combines the detection results (magnetic field strength, radiated emission value, radiated emission margin) obtained in step S100 with the loop inductance model established in step S200 to conduct a risk assessment.

[0036] For example, the electromagnetic compatibility optimization device determines that, in the scenario where the DC-DC power supply circuit is located, the peak value of the near-field scanning magnetic field strength exceeds a preset first preset strength threshold (e.g., 30 dBμV / m), and the radiated emission value exceeds the CISPR 11 standard limit at a harmonic point of a certain switching frequency (e.g., 200 MHz), with a corresponding negative radiated emission margin (-5 dB). Based on this, the electromagnetic compatibility optimization device determines the risk level of the abnormal coil structure as "high risk" according to preset risk assessment rules.

[0037] The electromagnetic compatibility (EMC) optimization device identifies the current abnormal coil structure as a "Type II abnormal coil structure" with a risk level of "high risk." It then generates and prompts corresponding EMC optimization strategies. These strategies include: prompting the designer to control the area of ​​the abnormal coil (high-frequency current loop) within a preset loop area (e.g., less than 2 mm²); and suggesting that the via spacing connecting the loop be controlled within a preset spacing (e.g., less than 1 mm) to reduce loop inductance.

[0038] Through the above settings, abnormal coil structures are classified and three equivalent models are established (series RLC resonant model, loop inductor model, and miniature inductor coupling model). The concepts of "parasitic loops" and "hidden coils," which originally relied on engineer experience, are transformed into visual geometric figures and calculable electrical parameters in EDA software. This allows the electromagnetic compatibility optimization device to directly call upon the model for risk assessment. This transforms traditional electromagnetic compatibility optimization work, which relies on engineer experience, into a closed-loop optimization method based on quantitative standards and executed automatically by computer equipment. This significantly improves rectification efficiency, reduces costs, and shortens the R&D cycle.

[0039] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 2 The steps for obtaining the type of abnormal coil structure in the prototype that can generate or receive electromagnetic interference include: S110. Locate the position on the surface of the prototype where there is an abnormal coil structure.

[0040] In this embodiment, optionally, in one example, the electromagnetic compatibility optimization device first obtains the PCB source file of the prototype (e.g., an Altium Designer or Cadence format file). The electromagnetic compatibility optimization device parses the PCB source file and searches for locations in the PCB layout that may constitute abnormal coil structures according to preset rules.

[0041] The electromagnetic compatibility (EMC) optimization device traverses the component library, retrieving all components of type SMD inductors and SMD ferrite beads, and extracts their package dimensions (e.g., 0805, 1206, etc.) and coordinate positions on the PCB. The EMC optimization device identifies these locations as potential sites for abnormal coil structures.

[0042] The electromagnetic compatibility (EMC) optimization device further analyzes the signal network topology, identifying closed loops consisting of a driver source, a load, and a return path to ground. For example, the EMC optimization device identifies a closed loop starting from the MCU's PWM output pin, passing through a current-limiting resistor, reaching an LED anode, and then returning to ground through the LED cathode. The EMC optimization device calculates that the area enclosed by this closed loop is 25 mm², which is greater than a preset area threshold (e.g., 10 mm²), thus determining that the location of this loop is a potential location for an abnormal coil structure.

[0043] The electromagnetic compatibility (EMC) optimization device reads the main control chip's datasheet (which is pre-imported into the device's knowledge base). By searching for internal structure keywords such as "SW," "LX," "Switch Node," and "Clock Output," it identifies the chip's switch node pins and clock output pins. The device then locates the positions of these high-frequency pins on the PCB and marks the electrical loops formed by these pins, surrounding components, vias, and ground planes, determining their coordinates as potential locations of abnormal coil structures.

[0044] S120. Based on the determined location, determine the type of abnormal coil structure therein.

[0045] In this embodiment, optionally, the electromagnetic compatibility optimization device determines the type of abnormal coil structure at each location based on the location determined in step S110. The types of abnormal coil structures include: a first type of abnormal coil structure (surface-mount inductor, ferrite bead, or common-mode inductor); a second type of abnormal coil structure (a closed loop consisting of a drive source, load, and return path, or a three-dimensional loop consisting of serpentine traces, vias, and planes); and a third type of abnormal coil structure (inductors, transformers, or micro-magnetic structures integrated within the chip).

[0046] For example, if the abnormal coil structure identified at this location is a surface-mount inductor, it is determined to be a first-type abnormal coil structure; if it is an electrical circuit formed by the SW pin of the power chip and inductors, capacitors, PCB ground planes, etc., it is determined to be a second-type abnormal coil structure; if it is an inductor integrated inside the chip, it is determined to be a third-type abnormal coil structure.

[0047] Through the above settings, the sequential logic of "first locate, then classify" is established. The electromagnetic compatibility optimization device not only knows which types of abnormal coil structures exist in the prototype, but also knows the specific physical location of each type of abnormal coil structure on the prototype surface. This provides spatial coordinates for the subsequent generation of optimization strategies, enabling the implementation of optimization strategies to be located at the specific physical location on the prototype surface, while also reducing the computational complexity of type identification, as type determination is only performed on these limited locations.

[0048] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 3 The steps for identifying the location of abnormal coil structures on the surface of the prototype include: S111. Obtain the PCB source file of the prototype; S112. Based on the PCB source file of the prototype and preset rules, determine the location of abnormal coil structures on the surface of the prototype; The preset rules include: The component library was searched for components of type surface mount, their package size and coordinate position were extracted, and the surface mount components were identified as abnormal coil structures. Analyze the signal network topology, identify closed loops consisting of a driving source, load, and return path, calculate the area of ​​the closed loop, and determine that loops with an area greater than a preset area threshold are abnormal coil structures. Read the internal structure keywords in the chip datasheet, or identify the high-frequency pins marked as switching nodes or clock outputs in the chip pins, and determine that the circuit formed by the high-frequency pins of the chip is an abnormal coil structure.

[0049] In this embodiment, optionally, the electromagnetic compatibility optimization device loads the prototype's PCB source file (e.g., a file in Altium Designer or Cadence format). The PCB source file contains information such as the prototype's component list, network connection relationships, stack-up structure, and trace geometry parameters (length, width, coordinates).

[0050] Optionally, the electromagnetic compatibility (EMC) optimization device filters all surface-mount components based on the "Component Type" field or package name prefix in the component attributes. For each filtered surface-mount component, the EMC optimization device extracts its component reference number, component type (inductor, bead, common-mode inductor, capacitor, resistor, etc.), package size (e.g., 3.2mm × 1.6mm corresponds to a 1206 package), and coordinate position. The EMC optimization device determines the coordinate positions of surface-mount components of inductor, bead, or common-mode inductor types as locations where abnormal coil structures may exist. Optionally, the EMC optimization device traverses all electrical networks in the PCB source file, filtering out signal networks that are neither power nor ground networks. For each signal network, the EMC optimization device analyzes the component pins it connects to. If a pin is marked as an output pin, the EMC optimization device identifies it as a driver source; if a pin is marked as an input pin, the EMC optimization device identifies it as a load. The EMC optimization device determines a complete closed loop formed from the driver source pin, through traces, vias, load pins, and then back to the driver source ground pin via a return path (reference ground plane or ground line). For each identified closed loop, the polygonal boundary enclosed by the loop (trace centerline, via location, equivalent edge of ground plane return path) is extracted, and its geometric area is calculated. The EMC optimization device compares the calculated loop area with a preset threshold (e.g., 10 mm² in this embodiment), determining that the location of a closed loop with a loop area greater than the preset threshold is a possible location of an abnormal coil structure.

[0051] It is important to understand that the preset thresholds in this embodiment are not dynamically calculated or real-time input variables, but rather parameters pre-set and stored in the device's memory by technical personnel based on standards, specifications, or experience. The preset area threshold of 10mm² is a recommended upper limit based on typical DC-DC power circuit theory and extensive experimental verification. Actual products can adjust this threshold according to operating frequency, current magnitude, and EMC limits. For example, high-current circuits can be relaxed to 20mm², while demanding applications can be tightened to 5mm². However, 10mm² serves as a general design guideline applicable to most portable electronic devices.

[0052] Optionally, the electromagnetic compatibility optimization device reads the datasheets of each major chip in the prototype (the datasheets are pre-imported into the knowledge base of the electromagnetic compatibility optimization device in a structured format). The electromagnetic compatibility optimization device searches a preset keyword list in the datasheet and, based on the search results, marks the pins associated with these keywords in the datasheet as high-frequency pins. Based on the connection relationships in the PCB source file, the electromagnetic compatibility optimization device determines the location of the electrical circuit formed by these high-frequency pins, external components (inductors, capacitors), and the ground plane as the location where abnormal coil structures may exist.

[0053] With the above settings, the three preset rules are designed for different types of abnormal coil structures, ensuring that the electromagnetic compatibility optimization device can identify and locate the abnormal coil regardless of its form, thus avoiding missed detections that may result from relying on a single rule.

[0054] Optionally, in another embodiment, determining the location of abnormal coil structures on the prototype surface based on the prototype's PCB source file and preset rules includes: Analyze the signal network topology to identify the location of the power chip on the sample surface, and based on the PCB source file of the prototype, determine the location of the SW pin of the power chip, and determine the first electrical circuit to which the SW pin of the power chip belongs. The first electrical circuit is formed by: SW pin, inductor, capacitor, PCB plane ground, chip ground pin, and internal pull-down of the chip; the abnormal coil structure includes the first electrical circuit. Based on the determined location, the type of abnormal coil structure can be identified as follows: Calculate the path length of the first electrical loop and the width of the current return path, and determine the loop area based on the path length and the width of the current return path. If the area of ​​the circuit is greater than a preset area threshold, the first electrical circuit is determined to be a second type of abnormal coil structure.

[0055] Optionally, the current return path refers to the physical path through which the high-frequency switching current returns from the load to the power supply. The width of the current return path refers to the lateral width of the conductor (usually the ground plane or ground line) occupied by the return current in the PCB layout.

[0056] Alternatively, the area of ​​the first electrical loop can be determined by calculating the product of the length of the path of the first electrical loop and the width of the current return path.

[0057] It should be understood that the preset thresholds in this embodiment are not dynamically calculated or real-time input variables, but parameters that are set in advance by technicians based on standards, specifications or experience and stored in the device memory.

[0058] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 4 The step of obtaining the location of the abnormal coil structure on the surface of the prototype also includes: S113. Obtain the results of scanning the surface of the prototype with a near-field probe and a spectrum analyzer at a preset scanning frequency; S114. Based on the scanning results, determine the location of the abnormal coil structure on the prototype surface.

[0059] In this embodiment, optionally, an operator uses a near-field probe to scan above the prototype surface. The near-field probe picks up the magnetic field signal radiated from the prototype surface and transmits the signal to a spectrum analyzer. The spectrum analyzer analyzes the received signal according to a preset scanning frequency range to obtain the magnetic field strength amplitude at different frequency points. The electromagnetic compatibility optimization device acquires this scanning result, which includes information on the distribution of electromagnetic radiation intensity at various locations on the prototype surface. In this embodiment, the preset scanning frequency is pre-set by technicians and stored in a configuration file of the computer-aided design software or in the memory of the automatic identification module. The preset scanning frequency can be set according to the prototype's operating frequency range, for example, covering the prototype's fundamental frequency and its harmonic frequencies, to ensure effective capture of electromagnetic interference signals generated by abnormal coil structures.

[0060] Optionally, the electromagnetic compatibility optimization device analyzes the scanning results output by the spectrum analyzer to identify locations where the magnetic field strength is significantly higher than the surrounding area. These locations with abnormal magnetic field strength are the possible locations of abnormal coil structures. For example, when the near-field probe scans at a certain coordinate position on the prototype surface, if the spectrum analyzer shows that the magnetic field strength at a certain frequency point at that position significantly exceeds the background noise level or exceeds a preset strength threshold, then the electromagnetic compatibility optimization device determines that coordinate position as the location of an abnormal coil structure.

[0061] It is important to understand that when using a near-field probe in conjunction with a spectrum analyzer for scanning, the sample can first be scanned in an unloaded environment or far from the sample to measure the magnetic field strength amplitude of the ambient background noise. The aforementioned preset intensity threshold is set to a value higher than the background noise by a certain margin (e.g., the average background noise plus 6dB or 10dB). In this embodiment, the preset intensity threshold is not a dynamically calculated or instantaneously input variable, but rather a parameter that is pre-set and stored in the device's memory by technicians based on standards, specifications, or experience.

[0062] By using the scanning method of the near-field probe and spectrum analyzer, the electromagnetic compatibility optimization device can directly locate the location of abnormal coil structures on the surface of the prototype without relying on the PCB source file. It is especially suitable for scenarios where the PCB source file cannot be obtained or where actual prototype verification is required.

[0063] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 5 The steps for determining the type of abnormal coil structure based on a given location include: S121. When the abnormal coil structure is a surface mount inductor, ferrite bead, or common mode inductor, the type of abnormal coil structure is determined to be a first-class abnormal coil structure. S122. When the abnormal coil structure is a closed loop consisting of a driving source, a load, and a return path, or a three-dimensional loop consisting of a serpentine trace, a via, and a plane, the type of abnormal coil structure is determined to be the second type of abnormal coil structure. S123. When the abnormal coil structure is an inductor, transformer or micro magnetic structure integrated inside the chip, the type of abnormal coil structure is determined to be a third type of abnormal coil structure.

[0064] In this embodiment, optionally, if the electromagnetic compatibility optimization device identifies an abnormal coil structure at a location on the prototype surface that is a surface mount inductor, a ferrite bead, or a common mode inductor, the type of the abnormal coil structure is determined to be a first-type abnormal coil structure.

[0065] Optionally, the electromagnetic compatibility optimization device analyzes the signal network topology and identifies the abnormal coil structure at the location of the abnormal coil structure on the prototype surface. If the abnormal coil structure is a closed loop formed by a drive source from the main control chip, passing through a microstrip line, reaching an external load, and then returning to the ground pin of the main control chip through the ground plane, or if it is a wiring structure in which a signal switches from the top layer through a via to the bottom layer and then returns to the top layer through another via, and the two vias and the middle ground plane form a three-dimensional loop perpendicular to the board surface, then the type of the abnormal coil structure is determined to be a second type of abnormal coil structure.

[0066] Optionally, if the electromagnetic compatibility optimization device identifies an abnormal coil structure at a location on the prototype surface that is an inductor, transformer, or micro-magnetic structure integrated within the chip, the type of the abnormal coil structure is determined to be a third-class abnormal coil structure.

[0067] With the above settings, the electromagnetic compatibility optimization device can classify the various abnormal coil structures in the prototype into three limited types, which facilitates subsequent risk level assessment and optimization strategy generation by calling the corresponding equivalent models for different types.

[0068] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 6 The steps for determining the equivalent model of an abnormal coil structure based on its type include: S210. When the abnormal coil structure is a first type of abnormal coil structure, extract the equivalent inductance, parasitic capacitance, and equivalent resistance according to the component datasheet to determine the first equivalent model corresponding to the first type of abnormal coil structure. or, The first equivalent model corresponding to the abnormal coil structure is determined based on the fitting results of the measured S-parameters using a network analyzer. S220. When the abnormal coil structure is a second type of abnormal coil structure, determine the second equivalent model corresponding to the second type of abnormal coil structure based on the loop geometry, trace length, width, and interlayer distance. S230. When the abnormal coil structure is a third type of abnormal coil structure, refer to the internal inductance value and coupling coefficient in the chip datasheet to determine the third equivalent model corresponding to the third type of abnormal coil structure. or, The third equivalent model corresponding to the third type of abnormal coil structure is determined based on the relevant parameters measured between the corresponding pins by the impedance analyzer. The first equivalent model is the series RLC resonance model; The second equivalent model is the loop inductance model; The third equivalent model is the micro-inductive coupling model.

[0069] In this embodiment, optionally, when the abnormal coil structure is determined to be a first type of abnormal coil structure (i.e., a surface-mount inductor, ferrite bead, or common-mode inductor), the electromagnetic compatibility optimization device reads the component's datasheet, extracts the equivalent inductance, parasitic capacitance, and equivalent resistance values ​​from the datasheet, and constructs a series RLC resonant model based on these parameters as the first equivalent model. Alternatively, the electromagnetic compatibility optimization device obtains the S-parameters measured by a network analyzer for the abnormal coil structure, performs fitting processing on the measured S-parameters, and determines the series RLC resonant model corresponding to the abnormal coil structure as the first equivalent model based on the fitting result.

[0070] Optionally, if the abnormal coil structure is determined to be a second type of abnormal coil structure (i.e., a closed loop consisting of a driving source, a load, and a return path, or a three-dimensional loop consisting of serpentine traces, vias, and planes), the electromagnetic compatibility optimization device obtains the geometric shape information of the loop, including parameters such as trace length, trace width, and PCB layer distance. Based on these parameters, it calculates the equivalent inductance value of the loop and constructs a loop inductance model as a second equivalent model.

[0071] Optionally, if the abnormal coil structure is determined to be a third type of abnormal coil structure (i.e., an inductor, transformer, or micro-magnetic structure integrated within the chip), the electromagnetic compatibility optimization device consults the chip's datasheet to extract parameters such as internal inductance and coupling coefficients. Based on these parameters, a micro-inductor coupling model is constructed as the third equivalent model. Alternatively, the electromagnetic compatibility optimization device obtains relevant parameters measured by an impedance analyzer between the chip pins corresponding to the abnormal coil structure, and determines the micro-inductor coupling model corresponding to the abnormal coil structure as the third equivalent model based on the measured parameters.

[0072] With the above settings, the electromagnetic compatibility optimization device can determine the equivalent model of different types of abnormal coil structures using corresponding methods, providing a parameter basis for subsequent risk level assessment.

[0073] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 7 , Figure 8 , Figure 9 Based on the detection results and equivalent models, the steps for determining the risk level of abnormal coil structures include: refer to Figure 7 An abnormal coil structure is present in a DC-DC power supply circuit.

[0074] S310. If the magnetic field strength of the near-field scan of the prototype surface exceeds the first preset strength, or the radiation emission value exceeds the preset standard value, or the radiation emission margin is less than the first preset margin, the risk level of the abnormal coil structure is determined to be high risk. S320. If the magnetic field strength of the near-field scan of the prototype surface is greater than the first preset strength and less than the second preset strength, or the radiation emission margin is between the second preset margin and the third preset margin, the risk level of the abnormal coil structure is determined to be medium risk. S330. When the magnetic field strength for near-field scanning of the prototype surface is less than the second preset strength and the radiation emission margin is greater than the third preset margin, the risk level of the abnormal coil structure is determined to be low risk. refer to Figure 8 The abnormal coil structure is a parasitic coil formed by the clock signal line and other high-speed signal lines and the ground layer.

[0075] S340. If the radiated emission value exceeds the preset standard value or the radiated emission margin is less than the first preset margin and the harmonics of the clock frequency fall within the preset frequency band, the risk level of the abnormal coil structure is determined to be high risk. S350. When the radiation emission margin is between the second preset margin and the third preset margin, or the amplitude of the odd harmonic of the clock frequency is between the first preset amplitude and the second preset amplitude and the loop area is greater than the first preset area threshold, the risk level of the abnormal coil structure is determined to be medium risk. S360. If the radiation emission margin is greater than the third preset margin or the clock frequency is less than the preset frequency and the loop area is less than the second preset area threshold, the risk level of the abnormal coil structure is determined to be low risk. refer to Figure 9 The abnormal coil structure is a single-turn coil made of long wire.

[0076] S370. When the conductor length is greater than or equal to the first preset length, the risk level of the abnormal coil structure is determined to be high risk. S380. When the conductor length is less than the first preset length but greater than the second preset length, the risk level of the abnormal coil structure is determined to be medium risk. S390. If the conductor length is less than the second preset length, determine the risk level of the abnormal coil structure as low risk.

[0077] In this embodiment, optionally, the first preset intensity is the near-field scanning magnetic field intensity exceeding the background noise by 20dB; the preset standard value is the electromagnetic compatibility standard (such as CISPR 22 / 32, GB / T 9254, EN 55032, etc.) that the prototype needs to follow. The standard specifies corresponding radiated emission limits (usually in dBμV / m) for different frequency ranges; the radiated emission margin is the preset standard value (radiated emission limit) - the actual radiated emission test value. The first preset margin is 0dB. When the radiated emission margin is less than the first preset margin, it means that the actual test value has exceeded the standard limit.

[0078] It is important to understand that engineering experience shows that if the radiated emission test value exceeds the standard limit (margin < 0dB), it means that the product does not meet the requirements of electromagnetic compatibility regulations, cannot pass certification, and is a critical problem that must be solved.

[0079] Optionally, the second preset intensity is a near-field scanning magnetic field intensity that exceeds the background noise by 10dB; the second preset margin is 6dB, and the third preset margin is 12dB.

[0080] It should be understood that when the interference signal exceeds the background noise by less than 10dB, the distinction between the interference signal and the background noise is limited, the measured repeatability is poor, and it is generally considered to be within an acceptable electromagnetic environment level.

[0081] Alternatively, for example, various electromagnetic compatibility standards (such as CISPR 22 / 32, GB / T 9254, FCC Part 15, etc.) do not use the same limit across the entire frequency range, but rather divide different frequency bands, each corresponding to different limit requirements. Technicians use the frequency band with the strictest limit in the standard, which is most likely to be exceeded, as the preset frequency band for subsequent risk level determination.

[0082] Optionally, the first preset amplitude and the second preset amplitude are two thresholds used to measure the magnitude of the radiated energy of odd harmonics at the clock frequency. For example, the first preset amplitude is the fundamental amplitude minus 20 dB, and the second preset amplitude is the fundamental amplitude.

[0083] Optionally, the first preset area threshold is set to 5 mm².

[0084] Optionally, the preset frequency is set to 10MHz, and the second preset area threshold is set to 3mm².

[0085] Optionally, the first preset length is 100mm and the second preset length is 50mm.

[0086] Alternatively, the single-turn coil can be composed of long wires such as screen cable or camera cable.

[0087] It is important to understand that long wires such as screen cables and camera cables form a single-turn coil, which, from an electromagnetic compatibility perspective, is equivalent to a single-turn small coil antenna. The length of these wires directly determines the antenna coupling efficiency and interference reception capability. Therefore, the radiated emission and radiated immunity risks should be assessed according to the following standards: High risk: The wire length is ≥100mm (or its size is comparable to 1 / 4 wavelength in the frequency band of the equipment's radiation immunity test) and it will fail under a field strength of 10V / m.

[0088] Medium risk: With a wire length of 50mm to 100mm, a self-recovering anomaly occurs under a 10V / m field strength. Increasing the wire length improves the antenna's receiving efficiency, and the external 10V / m field strength can couple and create interference, but the circuit can recover to normal on its own.

[0089] Low risk: The conductor length is <50mm, and no anomalies were observed under a 10V / m field strength. The short conductor length results in low antenna reception efficiency, making it difficult for an external 10V / m field strength to couple and form effective interference.

[0090] It should be understood that the preset thresholds in this embodiment are not dynamically calculated or real-time input variables, but parameters that are set in advance by technicians based on standards, specifications or experience and stored in the device memory.

[0091] Thus, through the above settings, the electromagnetic compatibility optimization device can quantitatively determine the risk level of the abnormal coil structure based on the different circuit types or configurations, combined with the corresponding electromagnetic compatibility test results. This provides a basis for generating subsequent optimization strategies and improves the accuracy of electromagnetic compatibility optimization.

[0092] Optionally, according to some embodiments of this application, in one embodiment of this application, reference is made to... Figure 10 The steps for generating and suggesting corresponding electromagnetic compatibility optimization strategies based on type and risk level include: When the risk level of the abnormal coil is high, generate and suggest corresponding electromagnetic compatibility optimization strategies based on the type. S410. When the abnormal coil structure is a first-type abnormal coil structure, select a component with a saturation current value greater than or equal to a preset current value and a parasitic capacitance value less than or equal to a preset capacitance value; and / or, control the current loop length within a preset length. S420. When the abnormal coil structure is a second type of abnormal coil structure, the loop area is controlled within a preset loop area; and / or, the via spacing is controlled within a preset spacing; and / or, the loop impedance is controlled within a preset range. S430. In the case of a third-type abnormal coil structure, the pin trace length is controlled within a preset trace length; and / or, a filter element is added at the pin.

[0093] In this embodiment, optionally, the situation where the abnormal coil is of high risk is uncontrollable. Therefore, a corresponding electromagnetic compatibility optimization strategy is generated and prompted for the high-risk situation.

[0094] Optionally, if the first type of abnormal coil structure is determined to be high-risk, the electromagnetic compatibility optimization device prompts the technician to replace the component, requiring the new component to have a saturation current value greater than or equal to a preset current value (e.g., the preset current value is 1.2 times the maximum operating current of the circuit), and the new component to have a parasitic capacitance value less than or equal to a preset capacitance value (e.g., the preset capacitance value is 5pF). And / or, the electromagnetic compatibility optimization device prompts to control the length of the current loop within a preset length (e.g., the preset length is 10mm).

[0095] Optionally, if a second-type abnormal coil structure is determined to be high-risk, the electromagnetic compatibility (EMC) optimization device prompts the technician to modify the PCB layout to control the loop area within a preset loop area (e.g., a preset loop area of ​​1 cm²). And / or, the EMC optimization device prompts to control the via spacing within a preset spacing (e.g., a preset spacing of 5 mm). Simultaneously or alternatively, the device prompts to control the loop impedance within a preset range (e.g., a preset impedance range of 49.5 Ω to 50.5 Ω).

[0096] Optionally, if a third-type anomalous coil structure is determined to be high-risk, the electromagnetic compatibility (EMC) optimization device may prompt technicians to modify the PCB layout to keep the trace length of the pins connected to the anomalous coil structure within the chip within a preset trace length (e.g., a preset trace length of 15mm). And / or, the EMC optimization device may prompt the addition of filtering components (e.g., ferrite beads, capacitors, or common-mode inductors) at the chip pins corresponding to the anomalous coil structure.

[0097] It is important to understand that when the abnormal coil structure is of medium to low risk, the risk is controllable, therefore no control strategy is generated for medium to low risk situations.

[0098] It should be understood that the preset thresholds in this embodiment are not dynamically calculated or real-time input variables, but parameters that are set in advance by technicians based on standards, specifications or experience and stored in the device memory.

[0099] This application also provides an electromagnetic compatibility optimization device and a control method for performing an electromagnetic compatibility optimization device as described above.

[0100] Since the technical solution and effects of the electromagnetic compatibility optimization device have been described in detail in the description of the control method above, those skilled in the art can understand the specific structure and working principle of the device, so they will not be repeated here.

[0101] The above description is merely an exemplary embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the technical concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A control method of an electromagnetic compatibility optimization apparatus, characterized by, Includes the following steps: The location of the abnormal coil structure on the surface of the prototype and the detection results of the electromagnetic compatibility test corresponding to the abnormal coil structure are obtained, and the type of the abnormal coil structure is determined based on the determined location. When the abnormal coil structure is a surface-mount inductor, a ferrite bead, or a common-mode inductor, the type of the abnormal coil structure is determined to be a first-type abnormal coil structure. When the abnormal coil structure is a closed loop consisting of a drive source, a load, and a return path, or a three-dimensional loop consisting of a serpentine trace, a via, and a plane, the type of the abnormal coil structure is determined to be a second type of abnormal coil structure. When the abnormal coil structure is an inductor, transformer, or micro-magnetic structure integrated inside the chip, the type of the abnormal coil structure is determined to be a third type of abnormal coil structure. Based on the type of the abnormal coil structure, an equivalent model of the abnormal coil structure is determined. The equivalent model includes at least one of the following: series RLC resonant model, loop inductor model, and micro inductor coupling model. Based on the detection results and the equivalent model, the risk level of the abnormal coil structure is determined. The detection results include at least one of the following: magnetic field strength, radiated emission value, radiated emission margin, and radiated immunity of the prototype surface during near-field scanning. Based on the type and risk level, generate and suggest corresponding electromagnetic compatibility optimization strategies.

2. The control method of the electromagnetic compatibility optimization apparatus according to claim 1, wherein The step of obtaining the location of the abnormal coil structure on the surface of the prototype includes: Obtain the PCB source file of the prototype; Based on the PCB source files of the prototype and preset rules, the location of the abnormal coil structure on the surface of the prototype is determined; The preset rules include: The component library is searched for components of type surface mount, their package size and coordinate position are extracted, and the surface mount component is identified as the abnormal coil structure. Analyze the signal network topology, identify closed loops consisting of a driving source, a load, and a return path, calculate the area of ​​the closed loop, and determine the loops whose area is greater than a preset area threshold as the abnormal coil structure. Read the internal structure keywords in the chip datasheet, or identify the high-frequency pins marked as switch nodes or clock outputs in the chip pins, and determine that the circuit formed by the high-frequency pins of the chip is the abnormal coil structure.

3. The control method of the electromagnetic compatibility optimization apparatus according to claim 2, wherein The method of determining the location of the abnormal coil structure on the prototype surface based on the prototype's PCB source file and preset rules includes: The signal network topology is analyzed to identify the location of the power chip on the sample surface. Based on the PCB source file of the prototype, the location of the SW pin of the power chip is determined, and the first electrical circuit to which the SW pin of the power chip belongs is determined. The first electrical circuit is formed by: SW pin, inductor, capacitor, PCB plane ground, chip ground pin, and internal pull-down pin of the chip. The abnormal coil structure includes: the first electrical circuit. Determining the type of the abnormal coil structure based on the determined location includes: Calculate the length of the path of the first electrical loop and the width of the current return path, and determine the area of ​​the loop based on the length of the path of the loop and the width of the current return path. If the area of ​​the circuit is greater than the preset area threshold, the first electrical circuit is determined to be a second type of abnormal coil structure.

4. The control method of the electromagnetic compatibility optimization apparatus according to claim 1, wherein The step of obtaining the location of the abnormal coil structure on the surface of the prototype further includes: The results of scanning the prototype surface at a preset scanning frequency using a near-field probe and a spectrum analyzer are obtained, and the location of the abnormal coil structure on the prototype surface is determined based on the scanning results.

5. The control method of the electromagnetic compatibility optimization apparatus according to claim 1, wherein The step of determining the equivalent model of the abnormal coil structure based on the type of the abnormal coil structure includes: When the abnormal coil structure is the first type of abnormal coil structure, the equivalent inductance, parasitic capacitance, and equivalent resistance are extracted according to the component datasheet to determine the first equivalent model corresponding to the first type of abnormal coil structure; or, The first equivalent model corresponding to the abnormal coil structure is determined based on the fitting results of the measured S-parameters using a network analyzer. When the abnormal coil structure is the second type of abnormal coil structure, the second equivalent model corresponding to the second type of abnormal coil structure is determined according to the loop geometry, trace length, width, and interlayer distance; In the case where the abnormal coil structure is the third type of abnormal coil structure, the internal inductance value and coupling coefficient in the chip datasheet are consulted to determine the third equivalent model corresponding to the third type of abnormal coil structure. or, The third equivalent model corresponding to the third type of abnormal coil structure is determined based on the relevant parameters measured between the corresponding pins by the impedance analyzer. The first equivalent model is a series RLC resonance model; The second equivalent model is a loop inductance model; The third equivalent model is a micro inductive coupling model.

6. The control method of the electromagnetic compatibility optimization apparatus according to claim 5, wherein The step of determining the risk level of the abnormal coil structure based on the detection results and the equivalent model includes: In a DC-DC power supply circuit, if the magnetic field strength for near-field scanning of the prototype surface exceeds a first preset strength, or the radiation emission value exceeds a preset standard value, or the radiation emission margin is less than a first preset margin, the risk level of the abnormal coil structure is determined to be high risk. If the magnetic field strength for near-field scanning of the prototype surface is greater than the first preset strength and less than the second preset strength, or if the radiation emission margin is between the second preset margin and the third preset margin, the risk level of the abnormal coil structure is determined to be medium risk. If the magnetic field strength during near-field scanning of the prototype surface is less than the second preset strength and the radiation emission margin is greater than the third preset margin, the risk level of the abnormal coil structure is determined to be low risk. The abnormal coil structure is a parasitic coil formed by clock signal lines and other high-speed signal lines and the ground layer. When the radiated emission value exceeds the preset standard value or the radiated emission margin is less than the first preset margin and the harmonics of the clock frequency fall in the preset frequency band, the risk level of the abnormal coil structure is determined to be high risk. If the radiation emission margin is between the second and third preset margins, or the amplitude of the odd harmonics of the clock frequency is between the first and second preset amplitudes and the loop area is greater than the first preset area threshold, the risk level of the abnormal coil structure is determined to be medium risk. If the radiation emission margin is greater than the third preset margin or the clock frequency is less than the preset frequency and the loop area is less than the second preset area threshold, the risk level of the abnormal coil structure is determined to be low risk. The abnormal coil structure is a single-turn coil made of long wires. When the length of the wires is greater than or equal to a first preset length, the risk level of the abnormal coil structure is determined to be high risk. If the length of the conductor is less than the first preset length but greater than the second preset length, the risk level of the abnormal coil structure is determined to be medium risk. If the length of the conductor is less than the second preset length, the risk level of the abnormal coil structure is determined to be low risk.

7. The control method of the electromagnetic compatibility optimization apparatus according to claim 6, wherein The step of generating and suggesting corresponding electromagnetic compatibility optimization strategies based on the type and the risk level includes: When the risk level of the abnormal coil is high risk, a corresponding electromagnetic compatibility optimization strategy is generated and suggested based on the type. When the abnormal coil structure is the first type of abnormal coil structure, select a component with a saturation current value greater than or equal to a preset current value and a parasitic capacitance value less than or equal to a preset capacitance value; and / or, control the current loop length within a preset length; When the abnormal coil structure is the second type of abnormal coil structure, the loop area is controlled within a preset loop area; and / or, the via spacing is controlled within a preset spacing; and / or, the loop impedance is controlled within a preset range. When the abnormal coil structure is the third type of abnormal coil structure, the pin trace length is controlled within a preset trace length; and / or, a filter element is added at the pin.

8. An electromagnetic compatibility optimization apparatus, characterized by, The electromagnetic compatibility optimization device is used to execute the control method of the electromagnetic compatibility optimization device as described in any one of claims 1-7.

Images