Data transformation engine and data transformation engine verification method, apparatus and device

Abstract

The present application relates to the technical field of electric digital data processing, and especially relates to a data transformation engine and a data transformation engine verification method, device and equipment. The data transformation engine comprises an instruction receiving module, an instruction analysis module and a split instruction execution module; the split instruction execution module comprises an instruction completion counting module, a read address generation module and a write address generation module, and the instruction receiving module, the instruction analysis module, the instruction completion counting module, the read address generation module and the write address generation module are provided with a verification interface; the instruction completion counting module is used for counting the execution progress of an external instruction and feeding back instruction completion condition information; the read address generation module is used for generating a read address sequence; and the write address generation module is used for generating a write address sequence. The embodiment of the present application can optimize the architecture performance, improve the rationality of the architecture hardware of the data transformation engine, provide convenience for subsequent verification work and improve the verification flexibility.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, and in particular to a data transformation engine and a data transformation engine verification method, apparatus and equipment. Background Technology

[0002] The Data Transform Engine (DTE) is a core component in data processing systems and chip design, primarily responsible for instruction reception, parsing, execution, and data read / write address processing. The performance and functional correctness of the DTE directly determine the stability and efficiency of the entire data processing system.

[0003] In related technologies, a data transformation engine typically consists of an instruction receiving module, an instruction parsing module, an instruction execution module, and a read / write address data processing module. Each module is an independent hardware unit connected via internal signal interfaces. The instruction receiving module receives external instructions and forwards them to the instruction parsing module. The instruction parsing module parses key information from the external instructions. The instruction execution module implements all execution-related functions, including instruction counting, read address generation, and write address generation. The read / write address data processing module performs read address generation and write address generation.

[0004] The data transformation engine in related technologies suffers from an unreasonable hardware architecture. Firstly, the instruction execution module in these engines is an indivisible, independent hardware unit, integrating all execution-related functions such as instruction counting, read address generation, and write address generation. This high degree of hardware logic coupling makes it impossible to independently test and verify each sub-function. If a functional defect occurs, it's impossible to accurately locate the faulty hardware logic unit; the entire execution module must be checked, significantly increasing debugging difficulty and cost. Secondly, the read / write address data processing module in these engines is also an independent hardware unit, with some functional overlap with the instruction execution module. This leads to redundancy in the data transformation engine architecture, increasing chip area usage and the scope of hardware logic to be covered during verification, further increasing verification difficulty. Thirdly, these engines suffer from poor verification flexibility. The interfaces of the modules in these engines only consider hardware collaboration requirements, without reserving verification interfaces. Subsequent verification cannot directly monitor the working status of each module or read internal parameters; monitoring can only be done indirectly through external interfaces, resulting in extremely poor verification flexibility and an inability to adapt to verification needs. Summary of the Invention

[0005] This invention provides a data transformation engine and a data transformation engine verification method, apparatus, and device to solve the problems of unreasonable hardware architecture and poor verification flexibility of data transformation engines in related technologies.

[0006] According to one aspect of the present invention, a data transformation engine is provided, comprising: an instruction receiving module, an instruction parsing module, and a split instruction execution module; The split instruction execution module includes an instruction completion counting module, a read address generation module, and a write address generation module. The instruction receiving module, the instruction parsing module, the instruction completion counting module, the read address generation module, and the write address generation module are equipped with verification interfaces. The instruction receiving module is used to receive external instructions and forward the external instructions to the instruction parsing module; The instruction parsing module is used to parse key information in external instructions and send the instruction parsing information to the instruction completion counting module, the read address generation module, and the write address generation module respectively. The instruction completion counting module is used to count the execution progress of external instructions based on instruction parsing information and to provide feedback on instruction completion status. The read address generation module is used to generate a read address sequence based on instruction parsing information; The write address generation module is used to generate a write address sequence based on instruction parsing information.

[0007] According to another aspect of the present invention, a data transformation engine verification method is provided, comprising: After receiving the verification instructions of the data transformation engine, formal verification is performed on each of the sub-hardware modules of the data transformation engine to determine the functional completeness verification results of each sub-hardware module; wherein, the data transformation engine is the data transformation engine described in any embodiment of the present invention, and each sub-hardware module of the data transformation engine includes an instruction completion counting module, a read address generation module, and a write address generation module. If the functional completeness verification results of each subdivided hardware module are all passed, then the overall function of the data transformation engine is simulated, and the overall functional verification result of the data transformation engine is determined based on the functional information collected during the simulation through each verification interface in the data transformation engine.

[0008] According to another aspect of the present invention, a data transformation engine verification apparatus is provided, comprising: The formal verification unit is used to perform formal verification on each sub-hardware module of the data transformation engine after obtaining the verification instruction of the data transformation engine, and to determine the functional completeness verification result of each sub-hardware module; wherein, the data transformation engine is the data transformation engine described in any embodiment of the present invention, and each sub-hardware module of the data transformation engine includes an instruction completion counting module, a read address generation module, and a write address generation module. The simulation verification unit is used to simulate the overall function of the data transformation engine if the functional completeness verification results of each subdivided hardware module are all verified as passed. Based on the functional information collected during the simulation process through each verification interface in the data transformation engine, the overall functional verification result of the data transformation engine is determined.

[0009] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the data transformation engine verification method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the data transformation engine verification method according to any embodiment of the present invention.

[0011] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the data transformation engine verification method according to any embodiment of the present invention.

[0012] In the technical solution of this invention embodiment, the data transformation engine includes an instruction receiving module, an instruction parsing module, and a split instruction execution module. The split instruction execution module includes an instruction completion counting module, a read address generation module, and a write address generation module. Verification interfaces are provided in the instruction receiving module, instruction parsing module, instruction completion counting module, read address generation module, and write address generation module. The instruction receiving module receives external instructions and forwards them to the instruction parsing module. The instruction parsing module parses key information in the external instructions and sends the parsed information to the instruction completion counting module, read address generation module, and write address generation module respectively. The instruction completion counting module counts the execution progress of the external instructions based on the parsed information and provides feedback on instruction completion status. The read address generation module is used for... The read address sequence is generated based on the instruction parsing information; the write address generation module generates the write address sequence based on the instruction parsing information. This addresses the issues of unreasonable hardware architecture and poor verification flexibility in related technologies' data transformation engines. The read and write address data processing modules in related technologies are removed, and their functions are integrated into the read address generation module, write address generation module, and instruction parsing module. This avoids hardware redundancy, reduces chip area usage, and allows each hardware module to focus its functions more effectively, optimizing architecture performance and improving the rationality of the data transformation engine's hardware architecture. Verification interfaces set in the instruction receiving module, instruction parsing module, instruction completion counting module, read address generation module, and write address generation module facilitate subsequent verification work and improve verification flexibility. Each hardware module in the data transformation engine can perform independent unit verification and formal verification without requiring overall testing of the entire execution module, significantly reducing verification difficulty.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a data transformation engine provided in Embodiment 1 of this application.

[0016] Figure 2 This is a flowchart of a data transformation engine verification method provided in Embodiment 2 of the present invention.

[0017] Figure 3 This is a schematic diagram of the structure of a data transformation engine verification device provided in Embodiment 3 of the present invention.

[0018] Figure 4 A schematic diagram of the structure of an electronic device for implementing the data transformation engine verification method of this embodiment of the invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "target," "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Example 1 Figure 1 This is a schematic diagram of a data conversion engine provided in Embodiment 1 of this application. This embodiment is applicable to situations where a data processing system or chip uses a data conversion engine to implement functions such as instruction reception, parsing, execution, and data read / write address processing. Figure 1 As shown, the data transformation engine 100 may specifically include: an instruction receiving module 101, an instruction parsing module 102, and a split instruction execution module 103. Its structure and function are described below.

[0022] The split instruction execution module 103 includes an instruction completion counting module 31, a read address generation module 32, and a write address generation module 33. The instruction receiving module 101, the instruction parsing module 102, the instruction completion counting module 31, the read address generation module 32, and the write address generation module 33 are equipped with verification interfaces.

[0023] The instruction receiving module 101 is used to receive external instructions and forward them to the instruction parsing module 102.

[0024] The instruction parsing module 102 is used to parse key information in external instructions and send the instruction parsing information to the instruction completion counting module 31, the read address generation module 32, and the write address generation module 33 respectively.

[0025] The instruction completion counting module 31 is used to count the execution progress of external instructions based on instruction parsing information and provide feedback on instruction completion status.

[0026] The read address generation module 32 is used to generate a read address sequence based on the instruction parsing information.

[0027] The write address generation module 33 is used to generate a write address sequence based on the instruction parsing information.

[0028] Optionally, the instruction receiving module 101 is an independent hardware unit used to receive external instructions and forward them to the instruction parsing module 102. External instructions can refer to various data transformation engine instructions sent externally, such as data transfer instructions and data transformation instructions. The instruction receiving module 101 forwards external instructions to the instruction parsing module 102 to ensure the integrity and timeliness of instruction transmission. The instruction receiving module 101 reserves a verification interface. External devices can monitor the instruction receiving status through the verification interface of the instruction receiving module 101, facilitating the verification of the functional correctness of the instruction receiving module 101.

[0029] Optionally, the instruction parsing module 102 is an independent hardware unit used to parse key information in external instructions and send the parsed information to the instruction completion counting module 31, the read address generation module 32, and the write address generation module 33 respectively, providing accurate basis for instruction execution. Instruction parsing information refers to the key information in the external instructions parsed by the instruction parsing module 102. Key information in external instructions includes, but is not limited to, data size, source address, target address, and transformation rules. The instruction parsing module 102 reserves a verification interface. External devices can read the parsed instruction information through the verification interface of the instruction parsing module 102 to verify the correctness of the parsing logic.

[0030] Optionally, the split instruction execution module 103 adopts a split hardware design, no longer a single integrated hardware unit, but divided into three independent sub-hardware modules: instruction completion counting module 31, read address generation module 32, and write address generation module 33. Each module is functionally independent, can be verified separately, has decoupled hardware logic, and all have reserved verification interfaces.

[0031] Optionally, the instruction completion counting module 31 is an independent hardware unit used to count the execution progress of external instructions based on instruction parsing information and to feed back instruction completion information to the issuer of the external instruction. This facilitates the monitoring and control of instruction execution status during verification and provides hardware support for specifying the starting simulation position during simulation verification. The instruction completion information can be text describing the instruction completion status of the external instruction. External devices can read the counting status through the verification interface of the instruction completion counting module 31 to accurately verify the correctness of the counting logic.

[0032] Optionally, the read address generation module 32 is an independent hardware unit used to generate a read address sequence based on information such as the source address and data size in the instruction parsing information, ensuring that data can be accurately read from the specified source address. The read address sequence can refer to the address sequence for data reading. The read address generation module 32 has simple hardware logic. External devices can read the generated address sequence through the verification interface of the read address generation module 32, facilitating independent verification of the correctness of the address generation and reducing the verification difficulty.

[0033] Optionally, the write address generation module 33 is an independent hardware unit used to generate a write address sequence based on information such as the target address, data size, and transformation rules in the instruction parsing information, ensuring that data can be accurately written to the target address. The write address sequence can refer to the address sequence in which data is written. The write address generation module 33 and the read address generation module 32 are independently separated, with no hardware logic coupling, and can be verified separately. External devices can read the generated address sequence through the verification interface of the write address generation module 33 to verify the correctness of the address generation.

[0034] Optionally, the verification interface of the instruction receiving module 101 includes a status monitoring interface and a data reading interface; the status monitoring interface is used to monitor the instruction receiving status of the instruction receiving module; the data reading interface is used to read the instruction data received by the instruction receiving module 101; and the verification interface of the instruction parsing module 102 is used to read the instruction parsing information parsed by the instruction parsing module 102.

[0035] Optionally, the status monitoring interface is an interface provided in the instruction receiving module 101 for monitoring the instruction receiving status of the instruction receiving module 101. The data reading interface is an interface provided in the instruction receiving module 101 for reading the instruction data received by the instruction receiving module 101. The instruction data received by the instruction receiving module 101 includes external instructions received by the instruction receiving module 101. The instruction receiving module 101 can adopt asynchronous receiving hardware circuitry, supports multiple instruction formats, and can receive externally sent data transfer instructions, data transformation instructions, etc. After the instruction receiving module 101 completes the instruction reception, it can forward the instruction to the instruction parsing module 102 through a handshake signal to ensure that the instruction is not lost or confused. The instruction receiving module 101 reserves two verification interfaces, which are used to monitor the instruction receiving status and read the received instruction data, respectively, to facilitate verification of the module's functional correctness.

[0036] Optionally, the verification interface of the instruction parsing module 102 is an interface set within the instruction parsing module 102 for reading the instruction parsing information obtained by the instruction parsing module 102. The instruction parsing module 102 has built-in instruction parsing hardware logic circuitry, capable of extracting key information such as data size, source address, target address, transformation rules, and instruction type from the instruction. After parsing, the instruction parsing module 102 sends the instruction type and completion count requirement to the instruction completion count module 31, the source address and data size to the read address generation module 32, and the target address, data size, and transformation rules to the write address generation module 33, ensuring that each module obtains accurate instruction information. The instruction parsing module 102 reserves one verification interface for reading the parsed instruction information and verifying the correctness of the parsing logic.

[0037] Optionally, the verification interface of the instruction completion counting module 31 is used to read the counting status of the instruction completion counting module 31 and configure the starting counting position of the instruction completion counting module 31; the verification interface of the read address generation module 32 is used to read the read address sequence generated by the read address generation module 32; and the verification interface of the write address generation module 33 is used to read the write address sequence generated by the write address generation module 33.

[0038] Optionally, the verification interface of the instruction completion counting module 31 is an interface set in the instruction completion counting module 31 for reading the counting status of the instruction completion counting module 31 and configuring the starting counting position of the instruction completion counting module 31. The instruction completion counting module 31 can be implemented using a synchronous counter hardware circuit. According to the completion counting requirement sent by the instruction parsing module 102, it counts the instruction execution progress in real time. When the count reaches the completion threshold required by the instruction, it outputs an instruction completion signal and simultaneously feeds back the counting status to the verification interface of the instruction completion counting module 31 for easy monitoring of the counting status during the verification process. The instruction completion counting module 31 reserves one verification interface for reading the counting status and configuring the starting counting position.

[0039] Optionally, the verification interface of the read address generation module 32 is an interface set in the read address generation module 32 for reading the read address sequence generated by the read address generation module 32. The read address generation module 32 can employ address generator hardware circuitry to generate a continuous read address sequence based on the source address and data size, supporting multiple read granularities such as byte-by-byte and word-by-word. The read address generation module 32 can send the generated address sequence to the data reading unit through an internal signal interface, and simultaneously feed the address sequence back to the verification interface of the read address generation module 32 to facilitate verification of the correctness of the address generation. The read address generation module 32 reserves one verification interface for reading the generated address sequence. The data reading unit can be a hardware module or a software module for reading data.

[0040] Optionally, the verification interface of the write address generation module 33 is an interface set in the write address generation module 33 for reading the write address sequence generated by the write address generation module 33. The write address generation module 33 can employ address mapping hardware circuitry to generate the corresponding write address sequence based on the target address, data size, and transformation rules, supporting address mapping after data transformation. The write address generation module 33 can send the generated address sequence to the data writing unit through an internal signal interface, and simultaneously feed the address sequence back to the verification interface of the write address generation module 33 to facilitate verification of the correctness of address generation. The write address generation module 33 reserves one verification interface for reading the generated address sequence. The data writing unit can be a hardware module or a software module for writing data.

[0041] Optionally, the hardware connection relationship of the data conversion engine 100 is as follows: the output terminal of the instruction receiving module 101 is connected to the input terminal of the instruction parsing module 102 via a signal bus; the output terminal of the instruction parsing module 102 is connected to the input terminals of the instruction completion counting module 31, the read address generation module 32, and the write address generation module 33, respectively. The instruction receiving module 101, instruction parsing module 102, instruction completion counting module 31, read address generation module 32, and write address generation module 33 can all be connected to external verification devices through their respective verification interfaces, allowing for independent feedback of their working status, forming an optimized hardware architecture with independent functions, clear interfaces, and no redundancy. The data conversion engine 100 can be implemented using integrated circuit design technology.

[0042] In the technical solution of this invention embodiment, the data transformation engine includes an instruction receiving module, an instruction parsing module, and a split instruction execution module. The split instruction execution module includes an instruction completion counting module, a read address generation module, and a write address generation module. Verification interfaces are provided in the instruction receiving module, instruction parsing module, instruction completion counting module, read address generation module, and write address generation module. The instruction receiving module receives external instructions and forwards them to the instruction parsing module. The instruction parsing module parses key information in the external instructions and sends the parsed information to the instruction completion counting module, read address generation module, and write address generation module respectively. The instruction completion counting module counts the execution progress of the external instructions based on the parsed information and provides feedback on instruction completion status. The read address generation module is used for... The read address sequence is generated based on the instruction parsing information; the write address generation module generates the write address sequence based on the instruction parsing information. This addresses the issues of unreasonable hardware architecture and poor verification flexibility in related technologies' data transformation engines. The read and write address data processing modules in related technologies are removed, and their functions are integrated into the read address generation module, write address generation module, and instruction parsing module. This avoids hardware redundancy, reduces chip area usage, and allows each hardware module to focus its functions more effectively, optimizing architecture performance and improving the rationality of the data transformation engine's hardware architecture. Verification interfaces set in the instruction receiving module, instruction parsing module, instruction completion counting module, read address generation module, and write address generation module facilitate subsequent verification work and improve verification flexibility. Each hardware module in the data transformation engine can perform independent unit verification and formal verification without requiring overall testing of the entire execution module, significantly reducing verification difficulty.

[0043] The data transformation engine architecture in the technical solution of this invention is a dedicated hardware architecture. Based on the existing data transformation engine architecture, the instruction execution module is split and optimized, redundant modules are deleted, and verification interfaces are added, so that the hardware module division is more in line with verification requirements, which facilitates the subsequent unit verification and formal verification, while reducing hardware coupling and chip area occupation.

[0044] In the technical solution of this invention embodiment, the modules in the data transformation engine are connected through an internal signal bus, the verification interface adopts a standardized interface, supports connection with external verification equipment, and the module division strictly follows the principle of functional independence and easy verification to ensure the smooth progress of subsequent verification work.

[0045] The data transformation engine architecture in the technical solution of this invention is more reasonable and has better performance. By splitting the instruction execution module, each hardware module can be functionally independent and have clear interfaces, reducing hardware coupling, eliminating redundant modules, reducing chip area occupation, and reserving verification interfaces to facilitate subsequent verification. This solves the problems of existing monolithic modules that are difficult to accurately locate defects and have high verification difficulty, and improves the hardware stability and maintainability of the data transformation engine architecture.

[0046] Example 2 Figure 2 This is a flowchart illustrating a data transformation engine verification method according to Embodiment 2 of the present invention. This embodiment is applicable to verifying the functionality of the data transformation engine provided in the above embodiments of the present invention. The method can be executed by a data transformation engine verification device, which can be implemented in hardware and / or software and can be configured in an electronic device. This electronic device can be an electronic device installed in an enterprise for verifying the functionality of the data transformation engine. For example... Figure 2 As shown, the method includes: Step 201: After obtaining the verification instruction of the data transformation engine, perform formal verification on each sub-hardware module of the data transformation engine to determine the functional completeness verification result of each sub-hardware module.

[0047] The data transformation engine is the data transformation engine provided in the above embodiments of the present invention. The various sub-hardware modules of the data transformation engine include an instruction completion counting module, a read address generation module, and a write address generation module.

[0048] Optionally, the verification command for the data transformation engine can be a command sent by a technician to instruct the verification of the data transformation engine's functionality. The functional completeness verification result of the subdivision hardware module can be information determined through the verification of the data transformation engine's functionality, characterizing whether the subdivision hardware module functions correctly. The functional completeness verification result of the subdivision hardware module is either verification passed or defective. A verification passed result indicates that the subdivision hardware module functions normally. A verification defective result indicates that the subdivision hardware module is malfunctioning and has a defect.

[0049] Optionally, formal verification is performed on each sub-hardware module of the data transformation engine to determine the functional completeness verification result of each sub-hardware module. This includes: using attribute checking to perform formal verification on the instruction completion counting module, the read address generation module, and the write address generation module to determine the functional correctness verification result of the instruction completion counting module, the read address generation module, and the write address generation module; and determining the functional completeness verification result of the instruction completion counting module, the read address generation module, and the write address generation module based on the functional correctness verification result of the instruction completion counting module, the read address generation module, and the write address generation module.

[0050] Optionally, for each sub-hardware module, the functional correctness verification result can be information used to characterize whether the design of the sub-hardware module meets the attribute requirements of the sub-hardware module. The functional correctness verification result of the sub-hardware module is either pass or fail. A pass result indicates that the design of the sub-hardware module meets the attribute requirements of the sub-hardware module. A fail result indicates that the design of the sub-hardware module does not meet the attribute requirements of the sub-hardware module.

[0051] Optionally, an attribute-based verification method is used to perform formal verification on the instruction completion counting module, the read address generation module, and the write address generation module respectively, to determine the functional correctness verification results of the instruction completion counting module, the read address generation module, and the write address generation module. This includes: performing formal verification on the instruction completion counting module using a formal verification tool to determine the functional correctness verification result of the instruction completion counting module; performing formal verification on the read address generation module using a formal verification tool to determine the functional correctness verification result of the read address generation module; and performing formal verification on the write address generation module using a formal verification tool to determine the functional correctness verification result of the write address generation module.

[0052] Optionally, formal verification tools can be pre-configured software modules used to formally verify hardware modules and check whether the hardware module design meets the attribute requirements of the hardware module. Formal verification essentially uses mathematical methods to prove whether a hardware circuit design meets specific attribute requirements. Through mathematical modeling and logical reasoning, it exhaustively enumerates all possible hardware operating states to verify the correctness of the design. It does not rely on a large number of test cases and can ensure the functional completeness of each hardware module under all instruction types, data sizes, address ranges, and other scenarios, completely solving the problem that existing black-box verification cannot cover the entire test space. The attributes of the instruction receiving module can include hardware attributes such as instruction reception integrity. Formal verification can exhaustively enumerate all possible instruction input scenarios to verify whether the instruction receiving module can accurately receive and forward instructions without loss or errors. The module's operating status can be monitored through the verification interface of the instruction receiving module to ensure the correctness of the hardware logic. The attributes of the instruction parsing module can include instruction parsing accuracy. Formal verification can verify whether the instruction parsing module can correctly extract all key information from the instruction without parsing errors. The parsing results can be read through the verification interface to compare the consistency between the input instruction and the parsing result. The attributes of the instruction completion counting module can include attributes such as counting accuracy and the correctness of the completion signal triggering. Formal verification can be used to verify whether the instruction completion counting module can accurately count according to the instruction requirements and correctly output a completion signal when the count reaches the threshold. Different starting counting positions can be configured through the verification interface to verify the flexibility and correctness of the counting logic. The attributes of the read and write address generation modules can include address generation accuracy and address sequence continuity. Formal verification can be used to verify whether the read and write address generation modules can generate correct address sequences based on instruction parsing information, covering all possible data sizes and address ranges. The address sequences can be read through the verification interfaces of the read and write address generation modules to compare the consistency between the theoretical address and the actual generated address.

[0053] Optionally, during formal verification, if an attribute violation is found, the formal verification tool will generate specific counterexample waveforms to accurately pinpoint hardware module design defects (such as logic errors or timing deviations). This information is then promptly fed back to the hardware design team for modification. After modification, formal verification is performed again until all modules pass formal verification, ensuring the complete functionality of each hardware module. Simultaneously, by assuming a constraint environment, impossible input scenarios in reality can be eliminated, reducing the search space and accelerating the proof process.

[0054] Optionally, a formal verification tool can be used to perform formal verification on the instruction completion counter module to check whether the design of the instruction completion counter module meets the attribute requirements of the instruction completion counter module. If the design of the instruction completion counter module meets the attribute requirements, the functional correctness verification result of the instruction completion counter module is determined to be passed. If the design of the instruction completion counter module does not meet the attribute requirements, the functional correctness verification result of the instruction completion counter module is determined to be failed.

[0055] Optionally, if the functional correctness verification result of the instruction completion counting module is passed, then the functional completeness verification result of the instruction completion counting module is determined to be passed. If the functional correctness verification result of the instruction completion counting module is failed, then the functional completeness verification result of the instruction completion counting module is determined to be defective.

[0056] Optionally, a formal verification tool can be used to perform formal verification on the read address generation module to check whether the design of the read address generation module meets the attribute requirements. If the design of the read address generation module meets the attribute requirements, the functional correctness verification result of the read address generation module is determined to be passed. If the design of the read address generation module does not meet the attribute requirements, the functional correctness verification result of the read address generation module is determined to be failed.

[0057] Optionally, if the functional correctness verification result of the read address generation module is passed, then the functional completeness verification result of the read address generation module is determined to be passed. If the functional correctness verification result of the read address generation module is failed, then the functional completeness verification result of the read address generation module is determined to be defective.

[0058] Optionally, a formal verification tool can be used to perform formal verification on the write address generation module to check whether the design of the write address generation module meets the attribute requirements. If the design of the write address generation module meets the attribute requirements, the functional correctness verification result of the write address generation module is determined to be passed. If the design of the write address generation module does not meet the attribute requirements, the functional correctness verification result of the write address generation module is determined to be failed.

[0059] Optionally, if the functional correctness verification result of the write address generation module is passed, then the functional completeness verification result of the write address generation module is determined to be passed. If the functional correctness verification result of the write address generation module is failed, then the functional completeness verification result of the write address generation module is determined to be defective.

[0060] Step 202: If the functional completeness verification results of each subdivided hardware module are all verified as passed, then the overall function of the data transformation engine is simulated. Based on the functional information collected during the simulation through each verification interface in the data transformation engine, the overall functional verification result of the data transformation engine is determined.

[0061] Optionally, the overall functionality of the data transformation engine includes standard-size data transfer, oversized data transfer, and data transformation functions. Standard-size data transfer refers to the function of transferring standard-size data. Standard-size data can be data whose size is less than or equal to the target data size. The target data size can be a pre-set data size. Oversized data transfer refers to the function of transferring oversized data. Oversized data can be data whose size is greater than the target data size. Data transformation functions refer to the function of performing transformation operations such as transposition and padding on the transferred data.

[0062] Optionally, the overall function of the data transformation engine is simulated, and the overall function verification result of the data transformation engine is determined based on the functional information collected during the simulation through each verification interface in the data transformation engine. This includes: simulating the regular-size data transfer function of the data transformation engine and determining the verification result of the regular-size data transfer function based on the functional information collected during the simulation through each verification interface in the data transformation engine; simulating the ultra-large-size data transfer function of the data transformation engine and determining the verification result of the ultra-large-size data transfer function based on the functional information collected during the simulation through each verification interface in the data transformation engine; and simulating the data deformation function of the data transformation engine and determining the verification result of the data deformation function based on the functional information collected during the simulation through each verification interface in the data transformation engine.

[0063] Optionally, the conventional size data transfer function of the data transformation engine is simulated. Based on the functional information collected during the simulation through various verification interfaces in the data transformation engine, the verification result of the conventional size data transfer function of the data transformation engine is determined. This includes: transferring target conventional size data through the data transformation engine, obtaining functional information collected during the simulation through various verification interfaces in the data transformation engine; determining whether the obtained functional information is consistent with the expected functional information corresponding to the target conventional size data; if yes, the verification result of the conventional size data transfer function of the data transformation engine is determined to be passed; if no, the verification result of the conventional size data transfer function of the data transformation engine is determined to be failed. The verification result of the conventional size data transfer function of the data transformation engine can be information used to characterize whether the conventional size data transfer function of the data transformation engine is normal. The verification result of the conventional size data transfer function of the data transformation engine is either passed or failed. A passed verification result indicates that the conventional size data transfer function of the data transformation engine is normal. A failed verification result indicates that the conventional size data transfer function of the data transformation engine is abnormal. The target standard dimension data can be pre-set standard dimension data. The functional information collected by the verification interface during simulation refers to all information received by the verification interface during the data transformation engine's data transfer of the target standard dimension data. The expected functional information corresponding to the target standard dimension data can be pre-set functional information collected by each verification interface during simulation under normal standard dimension data transfer functionality.

[0064] Optionally, the ultra-large data transfer function of the data transformation engine is simulated. Based on the functional information collected during the simulation through various verification interfaces in the data transformation engine, the verification result of the ultra-large data transfer function of the data transformation engine is determined. This includes: transferring the target ultra-large data through the data transformation engine, obtaining the functional information collected during the simulation through various verification interfaces in the data transformation engine; determining whether the obtained functional information is consistent with the expected functional information corresponding to the target ultra-large data; if yes, the verification result of the ultra-large data transfer function of the data transformation engine is determined to be passed; if no, the verification result of the ultra-large data transfer function of the data transformation engine is determined to be failed. The verification result of the ultra-large data transfer function of the data transformation engine can be information used to characterize whether the ultra-large data transfer function of the data transformation engine is normal. The verification result of the ultra-large data transfer function of the data transformation engine is either passed or failed. A successful verification result indicates that the ultra-large data transfer function of the data transformation engine is normal. The verification result for the large-size data transfer function of the data transformation engine failed, indicating that the large-size data transfer function of the data transformation engine is abnormal. The target large-size data can be pre-set large-size data. The functional information collected by the verification interface during the simulation refers to all information received by the verification interface during the data transfer process of the data transformation engine on the target large-size data. The expected functional information corresponding to the target large-size data can be the pre-set functional information that each verification interface will collect during the simulation under the condition that the large-size data transfer function is normal.

[0065] Optionally, the data deformation function of the data transformation engine is simulated. Based on the functional information collected during the simulation through various verification interfaces in the data transformation engine, the verification result of the data deformation function of the data transformation engine is determined. This includes: transferring target data through the data transformation engine and deforming the target data during the data transfer; obtaining the functional information collected by various verification interfaces in the data transformation engine during the simulation; determining whether the obtained functional information is consistent with the expected functional information corresponding to the target data; if yes, the verification result of the data deformation function of the data transformation engine is determined to be passed; if no, the verification result of the data deformation function of the data transformation engine is determined to be failed. The verification result of the data deformation function of the data transformation engine can be information used to characterize whether the data deformation function of the data transformation engine is normal. The verification result of the data deformation function of the data transformation engine is either passed or failed. A passed verification result indicates that the data deformation function of the data transformation engine is normal. A failed verification result indicates that the data deformation function of the data transformation engine is abnormal. The target data can be pre-set data. The functional information collected by the verification interface during the simulation refers to all information received by the verification interface during the data transfer and data deformation process of the target data by the data transformation engine. The expected functional information corresponding to the target data can be the pre-set functional information that each verification interface will collect during the simulation process under the condition that the data deformation function is normal.

[0066] Optionally, after determining the functional completeness verification results of each sub-hardware module, the process further includes: if the functional completeness verification result of the target sub-hardware module is defective, then sending the functional completeness verification results and verification data of each sub-hardware module to the hardware design end. The hardware design end can be a terminal device used by the technician responsible for designing the data transformation engine. The verification data of the sub-hardware module can be all data related to the sub-hardware module obtained during the verification process.

[0067] The technical solution of this invention can perform formal verification on each sub-hardware module of the data transformation engine to ensure the functional completeness of each sub-hardware module. On the basis of ensuring the functional completeness of each sub-hardware module through formal verification, system-level simulation verification can be performed to verify the correctness of the collaborative work of each hardware module of the data transformation engine and whether the overall hardware function of the data transformation engine architecture meets the actual application requirements.

[0068] The technical solution of this invention can significantly improve verification completeness. This solution employs formal verification to verify each subdivided hardware module, exhaustively enumerating all possible hardware operating states through mathematical reasoning. This ensures the functional correctness of each module under all instruction types, data sizes, address ranges, and other scenarios, overcoming the shortcomings of existing black-box verification tests that are large in scope and cannot guarantee completeness, thus fundamentally improving verification quality. The application of formal verification also enables early verification, which can be initiated immediately after the hardware register transfer level (RTL) code is completed, without waiting for test platform development, further shortening the verification cycle.

[0069] The technical solution of this invention can be adapted to ultra-large data transfer scenarios, significantly improving simulation and debugging efficiency. This technical solution, combined with an optimized data transformation engine architecture (instruction completion counting module), supports specifying the starting coordinates or size of the simulation for ultra-large data transfer, avoiding full-process simulation and significantly shortening simulation time. For example, when testing a boundary scenario involving 10GB of data transfer, it is unnecessary to start full-process simulation from address 0. The starting counting position of the instruction completion counting module can be configured through the verification interface, directly specifying the simulation to start from the position 10GB-128 bytes, testing only the target boundary area, significantly shortening simulation time and improving debugging efficiency. When testing boundary scenarios, this technical solution can directly focus on the target area, reducing debugging difficulty, improving vulnerability modification efficiency, and solving the problem of existing solutions being unable to handle the verification and debugging time-consuming aspects of ultra-large data transfer. Simultaneously, the combination of simulation verification and formal verification takes into account both the needs of system-level verification and the completeness of module-level verification, further improving verification efficiency.

[0070] The technical solution of this invention can achieve hardware design and verification collaboration, shortening the verification convergence time. This solution integrates verification requirements into the hardware design phase, avoiding a disconnect between design and verification. Problems discovered during verification can be promptly fed back to the design phase, forming a closed-loop optimization. Simultaneously, it enhances verification personnel's understanding of the hardware design, optimizes verification test cases and environments, significantly shortens verification convergence time, and meets project schedule and verification quality requirements.

[0071] The technical solution of this invention can reduce the difficulty of verification modeling. The decomposed hardware modules in this invention have single functions, and verification modeling does not need to cover a complex overall architecture, significantly reducing modeling difficulty and time, and further improving verification efficiency. Simultaneously, the collaboration between hardware design and verification makes the design of the verification environment and reference model more closely match the actual hardware logic, improving modeling accuracy.

[0072] It should be noted that formal verification and simulation verification are not mutually exclusive, but rather complementary. Formal verification is used to verify key attributes at the hardware module level, ensuring the functional completeness of each sub-hardware module. Simulation verification is used for system-level integration verification, ensuring the correctness of the collaborative operation of each hardware module. The combination of the two provides dual assurance of module-level completeness verification and system-level overall verification. At the same time, through the collaboration between hardware design and verification, verification efficiency and quality are further improved. Moreover, the verification method is only compatible with the data transformation engine provided in the above embodiments of the present invention.

[0073] The technical solution of this invention can send data transfer instructions of different types and sizes to the data transformation engine architecture during the verification process of conventional size data transfer. By simulating and monitoring the collaborative work of each hardware module, and by reading the working status of each module through the verification interface, the correctness of the read and write requests and transferred data output by the data transformation engine architecture can be verified, ensuring that the overall function meets the standards.

[0074] The technical solution of this invention can test the data transfer function of ultra-large data (such as 10GB) during the ultra-large data transfer verification process. The starting counting position of the counting module is completed by configuring instructions through the verification interface of the data transformation engine architecture. The simulation start position is specified as 10GB-128byte. Only this boundary area is simulated, without the need to simulate the entire process from address 0. During the debugging process, the status of each module can be read directly through the verification interface to quickly locate and modify hardware vulnerabilities.

[0075] The technical solution of this invention can send a data deformation instruction during the data deformation scenario verification process to verify whether the hardware logic of the write address generation module can generate the correct write address sequence according to the transformation rules, whether the transported data meets the deformation requirements, and read the write address sequence and transport results through the verification interface to ensure the functional correctness of the data transformation engine architecture in complex scenarios.

[0076] Optionally, if hardware functional defects in the data transformation engine architecture are discovered during the verification process (such as address generation errors or counting deviations), this should be promptly reported to the hardware design team for adjustment and optimization of the hardware module logic. Simultaneously, based on the issues discovered during verification, verification test cases and the verification environment should be optimized, forming a closed loop of "hardware design-verification-optimization-re-verification." Furthermore, collaboration between hardware design and verification can enhance verification personnel's understanding of the internal hardware logic of the data transformation engine architecture, thereby improving the accuracy of verification test case design, verification environment development, and reference model design, ultimately enhancing the efficiency and quality of the entire verification process.

[0077] Example 3 Figure 3This is a schematic diagram of a data transformation engine verification device provided in Embodiment 3 of the present invention. The device can be configured in an electronic device. Figure 3 As shown, the device includes a formal verification unit 301 and a simulation verification unit 302.

[0078] The formal verification unit 301 is used to perform formal verification on each sub-hardware module of the data transformation engine after obtaining the verification instruction from the data transformation engine, and determine the functional completeness verification result of each sub-hardware module; wherein the data transformation engine is the data transformation engine provided in the above embodiment of the present invention, and each sub-hardware module of the data transformation engine includes an instruction completion counting module, a read address generation module, and a write address generation module; the simulation verification unit 302 is used to simulate the overall function of the data transformation engine if the functional completeness verification results of each sub-hardware module are all verified as passed, and determine the overall functional verification result of the data transformation engine based on the functional information collected during the simulation process through each verification interface in the data transformation engine.

[0079] The technical solution of this invention can perform formal verification on each sub-hardware module of the data transformation engine to ensure the functional completeness of each sub-hardware module. On the basis of ensuring the functional completeness of each sub-hardware module through formal verification, system-level simulation verification can be performed to verify the correctness of the collaborative work of each hardware module of the data transformation engine and whether the overall hardware function of the data transformation engine architecture meets the actual application requirements.

[0080] In an optional embodiment of the present invention, the formal verification unit 301 is specifically configured to: perform formal verification on the instruction completion counting module, the read address generation module, and the write address generation module using an attribute checking method, and determine the functional correctness verification results of the instruction completion counting module, the read address generation module, and the write address generation module; and determine the functional completeness verification results of the instruction completion counting module, the read address generation module, and the write address generation module based on the functional correctness verification results of the instruction completion counting module, the read address generation module, and the write address generation module.

[0081] In an optional embodiment of the present invention, the simulation verification unit 302 is specifically configured to: simulate the conventional size data transfer function of the data transformation engine, and determine the verification result of the conventional size data transfer function of the data transformation engine based on the functional information collected during the simulation through each verification interface in the data transformation engine; simulate the ultra-large size data transfer function of the data transformation engine, and determine the verification result of the ultra-large size data transfer function of the data transformation engine based on the functional information collected during the simulation through each verification interface in the data transformation engine; and simulate the data deformation function of the data transformation engine, and determine the verification result of the data deformation function of the data transformation engine based on the functional information collected during the simulation through each verification interface in the data transformation engine.

[0082] In an optional embodiment of the present invention, the simulation verification unit 302 is further configured to: if the functional completeness verification result of the target sub-hardware module is defective, send the functional completeness verification result and verification data of each sub-hardware module to the hardware design end.

[0083] The data transformation engine verification device provided in this embodiment of the invention can execute the data transformation engine verification method provided in any embodiment of the invention, and has the corresponding functional units and beneficial effects of the method execution.

[0084] Example 4 Figure 4 A schematic diagram of an electronic device 10, which can be used to implement the data transformation engine verification method of embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, electronic devices, blade electronic devices, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0085] like Figure 4As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory 12 or a random access memory 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 12 or loaded from storage unit 18 into the random access memory 13. The random access memory 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, read-only memory 12, and random access memory 13 are interconnected via a bus 14. An input / output interface 15 is also connected to the bus 14.

[0086] Multiple components in electronic device 10 are connected to input / output interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0087] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, central processing units, graphics processing units, various special-purpose artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as data transformation engine verification methods.

[0088] In some embodiments, the data transformation engine verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on a heterogeneous hardware accelerator via read-only memory and / or a communication unit. When the computer program is loaded into random access memory and executed by a processor, one or more steps of the data transformation engine verification method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the data transformation engine verification method by any other suitable means (e.g., by means of firmware).

[0089] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays, application-specific integrated circuits (ASICs), application-specific standard products (ASICs), systems-on-a-chip (SoCs), payload programmable logic devices (PLCs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or electronic device.

[0091] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0092] To provide user interaction, the systems and techniques described herein can be implemented on a heterogeneous hardware accelerator, which includes: a display device (e.g., a cathode ray tube or liquid crystal display monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the heterogeneous hardware accelerator. Other types of devices can also be used to provide user interaction; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including sound input, voice input, or haptic input).

[0093] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data electronic devices), or computing systems that include middleware components (e.g., application electronic devices), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0094] A computing system can include clients and electronic devices. Clients and electronic devices are generally geographically separated and typically interact via communication networks. The client-electronic device relationship is created by computer programs running on the respective computers and establishing a client-electronic device relationship between them. Electronic devices can be cloud electronic devices, also known as cloud computing electronic devices or cloud servers, which are host products within the cloud computing service system. These address the shortcomings of traditional physical hosts and virtual private server services, such as high management difficulty and weak business scalability.

[0095] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data transformation engine, characterized in that, include: The module consists of an instruction receiving module, an instruction parsing module, and a split instruction execution module. The split instruction execution module includes three independent sub-hardware modules: an instruction completion counting module, a read address generation module, and a write address generation module. The instruction receiving module, the instruction parsing module, the instruction completion counting module, the read address generation module, and the write address generation module are equipped with verification interfaces. The instruction receiving module is used to receive external instructions and forward the external instructions to the instruction parsing module; The instruction parsing module is used to parse key information in external instructions and send the instruction parsing information to the instruction completion counting module, the read address generation module, and the write address generation module respectively. The instruction completion counting module is used to count the execution progress of external instructions based on instruction parsing information and to provide feedback on instruction completion status. The read address generation module is used to generate a read address sequence based on instruction parsing information; The write address generation module is used to generate a write address sequence based on instruction parsing information; Specifically, the external device monitors the instruction receiving status through the verification interface of the instruction receiving module to verify the correctness of the instruction receiving module's function; the external device reads the parsed instruction information through the verification interface of the instruction parsing module to verify the correctness of the parsing logic; the external device reads the counting status through the verification interface of the instruction completion counting module to verify the correctness of the counting logic; the external device reads the generated address sequence through the verification interface of the read address generation module to verify the correctness of the address generation independently; and the external device reads the generated address sequence through the verification interface of the write address generation module to verify the correctness of the address generation independently.

2. The data transformation engine according to claim 1, characterized in that, The verification interface of the instruction receiving module includes a status monitoring interface and a data reading interface; the status monitoring interface is used to monitor the instruction receiving status of the instruction receiving module; the data reading interface is used to read the instruction data received by the instruction receiving module. The verification interface of the instruction parsing module is used to read the instruction parsing information obtained by the instruction parsing module.

3. The data transformation engine according to claim 1, characterized in that, The verification interface of the instruction completion counting module is used to read the counting status of the instruction completion counting module and configure the starting counting position of the instruction completion counting module. The verification interface of the read address generation module is used to read the read address sequence generated by the read address generation module; The verification interface of the write address generation module is used to read the write address sequence generated by the write address generation module.

4. A data transformation engine verification method, characterized in that, include: After receiving the verification instructions of the data transformation engine, formal verification is performed on each of the sub-hardware modules of the data transformation engine to determine the functional completeness verification results of each sub-hardware module; wherein, the data transformation engine is the data transformation engine of any one of claims 1-3, and each sub-hardware module of the data transformation engine includes an instruction completion counting module, a read address generation module, and a write address generation module. If the functional completeness verification results of each sub-hardware module are all passed, then the overall function of the data transformation engine is simulated. Based on the functional information collected during the simulation through each verification interface of the data transformation engine, the overall functional verification result of the data transformation engine is determined. Specifically, the normal-size data transfer function of the data transformation engine is simulated, and the verification result of the normal-size data transfer function is determined based on the functional information collected during the simulation through each verification interface of the data transformation engine; the ultra-large-size data transfer function of the data transformation engine is simulated, and the verification result of the ultra-large-size data transfer function is determined based on the functional information collected during the simulation through each verification interface of the data transformation engine; the data deformation function of the data transformation engine is simulated, and the verification result of the data deformation function is determined based on the functional information collected during the simulation through each verification interface of the data transformation engine. The overall functions of the data transformation engine include regular size data transfer function, ultra-large size data transfer function, and data deformation function. The regular size data transfer function is for transferring regular size data, the ultra-large size data transfer function is for transferring ultra-large size data, and the data deformation function is for performing deformation operations on the transferred data, including transpose and fill.

5. The data transformation engine verification method according to claim 4, characterized in that, Formal verification was performed on each of the sub-hardware modules of the data transformation engine to determine the functional completeness verification results of each sub-hardware module, including: The instruction completion counting module, the read address generation module, and the write address generation module are formally verified using an attribute checking method to determine the functional correctness verification results of the instruction completion counting module, the read address generation module, and the write address generation module. Based on the functional correctness verification results of the instruction completion counting module, the read address generation module, and the write address generation module, respectively, determine the functional completeness verification results of the instruction completion counting module, the read address generation module, and the write address generation module.

6. The data transformation engine verification method according to claim 4, characterized in that, After determining the functional completeness verification results of each sub-hardware module, the following is also included: If the functional completeness verification result of the target sub-hardware module is that there is a defect, the functional completeness verification results and verification data of each sub-hardware module will be sent to the hardware design end.

7. A data transformation engine verification device, characterized in that, include: A formal verification unit is used to perform formal verification on each sub-hardware module of the data transformation engine after receiving the verification instructions from the data transformation engine, and to determine the functional completeness verification results of each sub-hardware module; wherein, the data transformation engine is the data transformation engine according to any one of claims 1-3, and each sub-hardware module of the data transformation engine includes an instruction completion counting module, a read address generation module, and a write address generation module. The simulation verification unit is used to simulate the overall function of the data transformation engine if the functional completeness verification results of each sub-hardware module are all passed. Based on the functional information collected during the simulation through each verification interface of the data transformation engine, the unit determines the overall functional verification result of the data transformation engine. Specifically, the unit simulates the standard-size data transfer function of the data transformation engine, determining the verification result based on the functional information collected during the simulation through each verification interface; it simulates the ultra-large-size data transfer function of the data transformation engine, determining the verification result based on the functional information collected during the simulation through each verification interface; and it simulates the data deformation function of the data transformation engine, determining the verification result based on the functional information collected during the simulation through each verification interface. The overall functions of the data transformation engine include regular size data transfer function, ultra-large size data transfer function, and data deformation function. The regular size data transfer function is for transferring regular size data, the ultra-large size data transfer function is for transferring ultra-large size data, and the data deformation function is for performing deformation operations on the transferred data, including transpose and fill.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that is executed by the at least one processor, which enables the at least one processor to perform the data transformation engine verification method according to any one of claims 4-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the data transformation engine verification method of any one of claims 4-6.

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