Phase training method and phase training apparatus

Abstract

The application provides a phase training method and a phase training device. The method is applied to a chip. The chip is provided with a first delay line and a second delay line. The delay step of the first delay line is greater than the delay step of the second delay line. The method comprises the following steps: acquiring an actual gear of a channel in the chip, an eye diagram scanning result corresponding to the actual gear and a virtual gear group. At least one virtual gear in the virtual gear group is determined based on a time jump amount when the first delay line and the second delay line are jointly adjusted. The actual gear is gear-enlarged based on the virtual gear group, so as to obtain an updated gear. The updated gear is detected based on the eye diagram scanning result, so as to obtain an updated scanning result corresponding to the updated gear. The target gear is determined from the actual gear based on the updated gear and the updated scanning result. The first delay line and / or the second delay line is controlled to be adjusted to the target gear. The method can adjust the signal delay of the chip to reduce the bit error rate.

Description

Technical Field

[0001] This application relates to the field of chips, and more specifically, to a phase training method and a phase training device. Background Technology

[0002] When chips transmit data through a high-speed serial / parallel interface, the receiving end typically uses a digitally controlled delay chain to finely adjust the clock phase in order to locate the optimal data sampling point.

[0003] In related technologies, the optimal sampling level is determined by comparing eye diagram widths. However, because chip manufacturing is affected by parameters such as process technology, voltage, and temperature, directly comparing eye diagram widths can cause discrepancies between the detection results and the actual situation, thereby reducing the reliability of data sampling at the receiver and increasing the bit error rate. Therefore, how to adjust the signal delay of the chip to reduce the bit error rate has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a phase training method and a phase training device. The method can adjust the signal delay of a chip to reduce the bit error rate.

[0005] In a first aspect, a phase training method is provided, which is applied to a chip. The chip has a first delay line and a second delay line, and the delay step of the first delay line is larger than the delay step of the second delay line. The method includes: acquiring the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and a virtual gear position group; the virtual gear position group includes at least one virtual gear position, which is determined based on the time jump amount when the first delay line and the second delay line are jointly adjusted; expanding the actual gear position based on the virtual gear position group to obtain an updated gear position; compensating the updated gear position based on the eye diagram scan result to obtain an updated scan result corresponding to the updated gear position; determining the target gear position from the actual gear positions based on the updated gear position and the updated scan result; and controlling the first delay line and / or the second delay line to adjust to the target gear position.

[0006] The above technical solution expands the actual gears based on a virtual gear group to obtain updated gears. It then compensates for the detection results of the updated gears based on eye diagram scans, obtaining updated scan results corresponding to the updated gears. Finally, based on the updated gears and the updated scan results, it determines the target gear from the actual gears and adjusts to the target gear. By introducing a coarse-adjustment delay line and a fine-adjustment delay line combined with a time jump, a virtual gear group is constructed. This virtual gear group is then used to expand the timing space of the actual gears and compensate for the detection results, eliminating the risk of misjudgment in discrete gear search and ensuring the logical continuity of the obtained updated gears. Furthermore, by locating the physically optimal gear based on the updated gear and the updated scan results and adjusting to that gear, signal delay adjustment of the chip is achieved, significantly improving the timing margin and jitter resistance of high-frequency links and reducing the bit error rate of signal transmission. In addition, by calibrating and replacing analog circuit modifications through logic algorithms, modifications to the expensive analog physical layout are avoided, reducing the cost of delay adjustment and effectively enhancing the chip's mass production capability and cross-process node versatility.

[0007] In one possible implementation, the actual gears are expanded based on the virtual gear group to obtain updated gears, including: determining the first gear in the actual gears that needs to be adjusted together; adding the virtual gears in the virtual gear group before the first gear to obtain updated gears.

[0008] The above technical solution identifies the first gear that needs to be adjusted in the actual gear position, adds a virtual gear from the virtual gear group before the first gear position to obtain the updated gear position; by inserting the virtual gear group before the actual gear that needs to be adjusted, an updated gear position with logical continuity is constructed, thereby eliminating the influence of the delay gap of the switching point in the hierarchical delay chain on the eye diagram scan through the virtual gear position, and ensuring the accurate positioning of the optimal sampling gear position without changing the analog circuit.

[0009] In one possible implementation, the updated gear position includes an actual gear position and a virtual gear position group; the updated gear position is compensated for based on the eye diagram scan results to obtain the updated scan results corresponding to the updated gear position, including: determining the eye diagram scan results as the updated scan results of the actual gear position; traversing the updated scan results of the actual gear position to determine the sampling window corresponding to the actual gear position; and compensating the virtual gear position for detection results based on the relative positional relationship between the sampling window and the virtual gear position group to obtain the updated scan results of the virtual gear position.

[0010] The above technical solution determines the updated scanning results of the actual gears in the updated gear positions by identifying the eye diagram scan results. It then iterates through the updated scanning results of the actual gear positions to determine the sampling window corresponding to each actual gear position. Based on the relative positional relationship between the sampling window and the virtual gear group, it compensates for the detection results of the virtual gear positions to obtain the updated scanning results of the virtual gear positions. By mapping the eye diagram scan results to the actual gear positions and performing differentiated compensation for the virtual gear positions according to the relative positional relationship between the sampling window and the virtual gear positions, it achieves the repair of nonlinear gaps, effectively avoids misjudgment of the optimal sampling window, and improves the accuracy of the optimal sampling window.

[0011] In one possible implementation, based on the relative positional relationship between the sampling window and the virtual gear group, the detection results of the virtual gears are compensated to obtain the updated scanning results of the virtual gears. This includes: when the sampling window contains the target gear group, a first logical value is determined as the updated scanning result of the virtual gears in the target gear group, wherein the sampling window is determined based on consecutive first logical values, and the target gear group is any virtual gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection results of the virtual gears in the target gear group are compensated based on the reference window length of the largest reference window in the sampling window to obtain the updated scanning results of the virtual gears in the target gear group; when the sampling window does not contain the target gear group, and the boundary of the sampling window is not adjacent to the target gear group, a second logical value is determined as the updated scanning result of the virtual gears in the target gear group, wherein the second logical value is the logical opposite of the first logical value.

[0012] The above technical solution, when the sampling window contains the target gear group, determines the first logical value as the updated scan result of the virtual gear in the target gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scan result of the virtual gear in the target gear group; otherwise, the second logical value is determined as the updated scan result of the virtual gear in the target gear group. Based on the three relative relationships between the sampling window and the virtual gear (i.e., inclusion relationship, boundary adjacency, and complete separation), compensation for the differentiated detection results of the virtual gears is achieved, thereby logically repairing the physical delay gap, eliminating the time jump of the layered delay chain at the coarse-fine adjustment switching point, and significantly improving the accurate positioning of the physical optimal sampling point.

[0013] In one possible implementation, the detection results of virtual gears in the target gear group are compensated based on the reference window length of the largest reference window in the sampling window to obtain the updated scanning results of virtual gears in the target gear group. This includes: determining the sampling window length of the sampling window adjacent to the target gear group; when the sampling window length is equal to the reference window length, determining the second logic value as the updated scanning result of virtual gears in the target gear group; when the sampling window length is less than the reference window length, determining the length difference between the reference window length and the sampling window length, and determining the updated scanning result of virtual gears in the target gear group based on the length difference and the number of virtual gears in the target gear group.

[0014] In one possible implementation, determining the update scan result of the virtual gears in the target gear group based on the length difference and the number of virtual gears in the target gear group includes: when the length difference is greater than or equal to the number of virtual gears, determining a first logical value as the update scan result of the virtual gears in the target gear group; when the length difference is less than the number of virtual gears, determining the virtual gears in the target gear group whose length difference starts from the initial virtual gear as the first virtual gear, and determining the virtual gears in the target gear group other than the first virtual gear as the second virtual gear; and determining the first logical value as the update scan result of the first virtual gear, and determining the second logical value as the update scan result of the second virtual gear.

[0015] The above technical solution, when the sampling window length equals the reference window length, indicates that the eye diagram window is normally closed, and the second logic value is determined as the updated scan result of the virtual gear. When the sampling window length is less than the reference window length, it indicates that the eye diagram window is abnormally closed, and the hidden eye width in the virtual gear is supplemented by combining the length difference with the number of virtual gears. By using the length difference between the reference window length and the sampling window length, and by making a fine comparison between the length difference and the number of virtual gears, the updated scan result of the virtual gear at the edge of the eye diagram is accurately compensated, accurately restoring the real eye diagram that is truncated by gaps, thereby improving the accuracy of the optimal gear.

[0016] In one possible implementation, the target gear is determined from the actual gears based on the updated gear and the updated scan results, including: traversing the updated scan results to determine the updated sampling window corresponding to the updated gear; determining the evaluation parameters of the updated sampling window based on the length of the updated sampling window; and performing gear conversion on the updated gear associated with the largest evaluation parameter in the evaluation parameters to obtain the target gear in the actual gears.

[0017] The above technical solution iterates through the update scan results to determine the update sampling window corresponding to the update level. Based on the length of the update sampling window, it determines the evaluation parameters of the update sampling window. The update level associated with the largest evaluation parameter in the evaluation parameters is converted to obtain the target level in the actual level. By traversing the update sampling window in the virtual domain containing the virtual level, the optimal level is selected and then mapped to the actual physical level. This avoids local misjudgment caused by physical nonlinearity, ensures the authenticity of the finally determined target level, and thus significantly improves the chip's anti-jitter capability and reduces the bit error rate of signal transmission.

[0018] In one possible implementation, the evaluation parameters of the updated sampling window are determined based on the length of the updated sampling window, including: determining the second level corresponding to the center position of the target sampling window, the target sampling window being used to indicate any sampling window in the updated sampling window; determining the level weight of the target sampling window based on the level of the second level, the updated level and level are in one-to-one correspondence, and the level and level weight are negatively correlated; and determining the evaluation parameters of the target sampling window by multiplying the level weight by the window length of the target sampling window.

[0019] The above technical solution determines the second gear corresponding to the center position of the target sampling window, determines the gear weight of the target sampling window based on the gear level of the second gear, and determines the evaluation parameter of the target sampling window by multiplying the gear weight by the window length of the target sampling window. By introducing a weight factor negatively correlated with the gear level, the sampling window length is evaluated with weight, avoiding the interference of high gear jitter on the optimal gear, and improving the accuracy and robustness of the target gear positioning.

[0020] In one possible implementation, obtaining the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group includes: obtaining the delay step of the second delay line; determining the number of virtual gear positions based on the ratio of the time jump amount to the delay step; and generating a virtual gear position group based on the number of virtual gear positions.

[0021] The above technical solution determines the number of virtual gears based on the ratio of the time jump amount during joint adjustment to the delay step of the second delay line, thereby generating a virtual gear group. By utilizing hardware deviations under different processes, voltages, and temperatures, the delay gap at the coarse-fine joint adjustment switching point can be eliminated without modifying the underlying analog circuit, thus reducing the complexity of hardware design while ensuring the accuracy of eye diagram scanning and phase training.

[0022] In one possible implementation, a mapping table is constructed between virtual gears and actual gears in the virtual gear group. The mapping table is used to map the updated gear from the virtual gear domain to the actual gear domain.

[0023] Secondly, a phase training device is provided, which is applied to a chip. The chip has a first delay line and a second delay line, and the delay step of the first delay line is larger than the delay step of the second delay line. The device includes: an acquisition module for acquiring the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and a virtual gear position group; the virtual gear position group includes at least one virtual gear position, which is determined based on the time jump amount when the first delay line and the second delay line are jointly adjusted; an expansion module for expanding the actual gear position based on the virtual gear position group to obtain an updated gear position; a compensation module for compensating the detection result of the updated gear position based on the eye diagram scan result to obtain an updated scan result corresponding to the updated gear position; a determination module for determining a target gear position from the actual gear positions based on the updated gear position and the updated scan result; and a control module for controlling the first delay line and / or the second delay line to adjust to the target gear position.

[0024] In one possible implementation, an expansion module is used to determine the first gear that needs to be adjusted in the actual gear position; virtual gears from the virtual gear group are added before the first gear to obtain the updated gear.

[0025] In one possible implementation, the updated gear position includes an actual gear position and a virtual gear position group; the compensation module is specifically used to determine the eye diagram scan result as the updated scan result of the actual gear position in the updated gear position; to traverse the updated scan result of the actual gear position to determine the sampling window corresponding to the actual gear position; and to compensate the detection result of the virtual gear position based on the relative position relationship between the sampling window and the virtual gear position group to obtain the updated scan result of the virtual gear position.

[0026] In one possible implementation, the compensation module is specifically used to determine the updated scan result of the virtual gear in the target gear group as a first logical value when the sampling window contains the target gear group, wherein the sampling window is determined based on continuous first logical values, and the target gear group is any virtual gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scan result of the virtual gear in the target gear group; when the sampling window does not contain the target gear group and the boundary of the sampling window is not adjacent to the target gear group, the second logical value is determined as the updated scan result of the virtual gear in the target gear group, wherein the second logical value is the logical opposite of the first logical value.

[0027] In one possible implementation, the compensation module is specifically used to determine the sampling window length of the sampling window adjacent to the target gear group; when the sampling window length is equal to the reference window length, the second logic value is determined as the update scan result of the virtual gear in the target gear group; when the sampling window length is less than the reference window length, the length difference between the reference window length and the sampling window length is determined, and the update scan result of the virtual gear in the target gear group is determined based on the length difference and the number of virtual gears in the target gear group.

[0028] In one possible implementation, the compensation module is specifically used to determine the first logical value as the update scan result of the virtual gears in the target gear group when the length difference is greater than or equal to the number of virtual gears; when the length difference is less than the number of virtual gears, the virtual gears in the target gear group with the length difference starting from the initial virtual gear are determined as the first virtual gears, and the virtual gears in the target gear group other than the first virtual gears are determined as the second virtual gears; and the first logical value is determined as the update scan result of the first virtual gears, and the second logical value is determined as the update scan result of the second virtual gears.

[0029] In one possible implementation, a determination module is specifically used to traverse the update scan results and determine the update sampling window corresponding to the update level; based on the length of the update sampling window, determine the evaluation parameters of the update sampling window; and perform level conversion on the update level associated with the maximum evaluation parameter in the evaluation parameters to obtain the target level in the actual level.

[0030] In one possible implementation, the determining module is specifically used to determine the second level corresponding to the center position of the target sampling window, the target sampling window is used to indicate any sampling window in the update sampling window; based on the level of the second level, the level weight of the target sampling window is determined, the update level and level are in one-to-one correspondence, the level and level are negatively correlated; the product of the level weight and the window length of the target sampling window is determined as the evaluation parameter of the target sampling window.

[0031] In one possible implementation, the acquisition module is specifically used to acquire the delay step of the second delay line; determine the number of virtual gears based on the ratio of the time jump amount to the delay step; and generate a virtual gear group based on the number of virtual gears.

[0032] Thirdly, a phase training device is provided, including a memory and a processor. The memory is used to store executable program code; the processor is used to call and run the executable program code from the memory, so that the phase training device performs the phase training method in the first aspect or any possible implementation of the first aspect.

[0033] Fourthly, a computer-readable storage medium is provided that stores computer program code, which, when run on a computer, causes the computer to execute the phase training method described in the first aspect or any possible implementation thereof.

[0034] Fifthly, a computer program product is provided, comprising: computer program code, which, when run on a computer, causes the computer to execute the phase training method in the first aspect or any possible implementation thereof.

[0035] This application expands the actual gear positions based on a virtual gear group to obtain updated gear positions. It then compensates for the detection results of the updated gear positions based on eye diagram scan results, obtaining updated scan results corresponding to the updated gear positions. Based on the updated gear positions and updated scan results, a target gear position is determined from the actual gear positions and adjusted to the target gear position. By introducing a coarse-adjustment delay line and a fine-adjustment delay line combined with a time jump, a virtual gear group is constructed. This virtual gear group is then used to expand the timing space of the actual gear positions and compensate for the detection results, eliminating the risk of misjudgment in discrete gear position searches and ensuring the logical continuity of the obtained updated gear positions. Furthermore, by locating the physically optimal gear position based on the updated gear position and updated scan results and adjusting to that position, signal delay adjustment of the chip is achieved, significantly improving the timing margin and jitter resistance of high-frequency links and reducing the bit error rate of signal transmission. In addition, by calibrating and replacing analog circuit modifications through logic algorithms, modifications to the expensive analog physical layout are avoided, reducing the cost of delay adjustment and effectively enhancing the chip's mass production capability and cross-process node versatility.

[0036] Based on this, this application replaces traditional analog circuit modifications with digital logic compensation, achieving high-precision phase training and eye diagram compensation without altering the underlying physical layout. The solution, implemented using digital logic circuits, possesses inherent portability across different process nodes (e.g., from 7nm to 28nm). The same logic code can be directly reused on chips with different process technologies without redesigning the analog bias circuit. This feature significantly shortens the design iteration cycle of chips across different process nodes and improves product mass production capabilities. Attached Figure Description

[0037] Figure 1 This is a schematic flowchart of a phase training method provided in an embodiment of this application; Figure 2 This is a schematic flowchart of another phase training method provided in the embodiments of this application; Figure 3 This is a schematic diagram illustrating a detection result compensation method provided in an embodiment of this application; Figure 4This is a schematic diagram of the structure of a phase training device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a phase training device provided in an embodiment of this application. Detailed Implementation

[0038] The technical solutions in this application will be clearly and thoroughly described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0040] In the physical layer design of high-speed serial / parallel interfaces, such as Universal Chiplet Interconnect Express (UCIe) and Double Data Rate Synchronous Dynamic Random Access Memory (DDR), clock and data recovery (CDR) or eye diagram calibration scenarios are typically used in the receiver. The receiver usually employs a digitally controlled delay chain for fine-tuning the clock phase to find the optimal data sampling point (i.e., the center of the eye diagram). To balance wide-range adjustment with low power consumption and small area, a layered delay chain structure is commonly used in the industry: this consists of cascaded coarse-tuning units (or coarse-tuning delay lines) responsible for wide-range adjustment and fine-tuning units (or fine-tuning delay lines, such as 16 levels) responsible for fine-tuning.

[0041] Ideally, the delay of one coarse adjustment step should be exactly equal to the sum of the delays of 16 fine adjustment steps. However, in actual chip manufacturing, due to variations in process, voltage, and temperature (PVT) parameters, as well as parasitic effects of the physical layout, the layered delay chain often experiences a time gap (manifested as DNL mismatch) at the coarse-fine adjustment switching point (such as the Fine Code overflowing from 15 and flipping to 0, while the Coarse Code increments by 1).

[0042] The related technologies typically have the following problems when performing eye diagram scanning and phase training: 1. Physical Center Misjudgment: Traditional scanning algorithms directly calculate the right-left eye width and center in the physical register range (0, 1, ..., 15, 16...). Because they ignore the physical delay gap at the switching point (i.e., the time jump amount of the coarse-fine joint adjustment), the algorithm may mistake a large time jump for a normal range step, causing the calculated mathematical center to deviate significantly from the true physical optimal sampling point, thus compressing the timing margin at high frequencies.

[0043] 2. Deterioration of high-frequency intrinsic jitter: The longer the delay chain (i.e., the higher the level), the greater the clock jitter it introduces. Existing search algorithms lack an active avoidance mechanism for high-level jitter deterioration when encountering multiple eye diagram windows of similar width. This can easily lock the sampling point in a non-optimal high-level region, resulting in a higher long-term bit error rate (BER) of the link.

[0044] 3. Traditional calibration is costly: Smoothing differential non-linearity (DNL) by modifying the bias of the underlying analog circuit is extremely expensive and difficult to port between different process nodes (for example, migrating from 7nm to 28nm requires redesigning the analog bias circuit), which hinders the rapid iteration of chip process technology.

[0045] In view of this, this application provides a phase training method and a phase training device. To overcome the drawbacks of related technologies that rely on adjustments to underlying analog circuits (such as bias adjustment and layout iteration), including high hardware overhead and difficulties in process portability, this application's method achieves this through two means: firstly, eye diagram timing feature reconstruction and nonlinear compensation based on the digital logic domain; secondly, a weighted evaluation mechanism negatively correlated with the physical delay series is introduced during phase training. Thus, high-precision sampling alignment and global locking of the low-intrinsic-jitter state are achieved without modifying the physical layout.

[0046] The optimal gear position determined by this application has the following advantages: 1. By combining the relative positional relationship between the sampling window and the virtual gear (i.e., cross-compensation and truncation compensation) to differentiate the detection results of the virtual gear, the true physical geometric properties of the signal are accurately restored in the digital domain, preventing eye diagram off-load at the gap of the high-speed PCIe / UCIe link, thereby improving the center sampling alignment accuracy.

[0047] 2. By introducing a weighting mechanism with high weights for low-end positions, and superimposing the eye diagram width amplification effect brought about by gap compensation, the system is strongly locked in a low-latency cascaded state, thereby actively avoiding intrinsic jitter and improving the long-term robustness of the link.

[0048] 3. Through engineering practice, this application only requires adding a small amount of table mapping and weighted logic calculation to the state machine or firmware to avoid modifying the expensive simulated physical layout, reducing hardware overhead design, and has extremely high mass production capability and cross-process node versatility.

[0049] It should be noted that the phase training method of this application is specifically a nonlinear compensation and phase training method for a layered delay chain. Specifically, it traverses the layered delay chain through real hardware testing, obtains the time jump amount of the delay chain at the coarse and fine adjustment cascade switching point, determines the number of virtual gears that need to be added based on the time jump amount, adds virtual gears at the coarse and fine adjustment cascade switching point, and performs nonlinear compensation based on actual measurement data to determine the phase training result.

[0050] Optionally, after the system is powered on, the link is reset, the interface is hot-plugged, or the device exits low-power / sleep mode, the phase training method returns the link state to the initial state, and a complete phase training can be re-executed.

[0051] Figure 1 This is a schematic flowchart of a phase training method provided in an embodiment of this application.

[0052] For example, the phase training method is applied to a chip, which has a first delay line and a second delay line, wherein the delay step size of the first delay line is larger than the delay step size of the second delay line. For example, the first delay line is a coarse-tuning delay line, and the second delay line is a fine-tuning delay line.

[0053] For example, such as Figure 1 As shown, the phase training method 100 includes S110 to S150.

[0054] S110: Obtain the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group.

[0055] The chip may contain multiple data lanes, each with independent delay chain characteristic parameters due to layout parasitic differences. Optionally, the steps of acquiring, expanding, compensating, and determining the target level in this application are performed independently on each lane. Of course, it is also possible to perform only the compensation and target level determination steps independently on each lane.

[0056] For example, the virtual gear group includes at least one virtual gear, which is determined based on the time jump amount when the first delay line and the second delay line are adjusted together. The first delay line is a coarse adjustment delay line, and the second delay line is a fine adjustment delay line. Ideally, the delay of one coarse adjustment step is the same as the sum of the delays of 16 fine adjustment steps, that is, the delay step of one coarse adjustment delay line is equal to the sum of the delay steps of 16 fine adjustment delay lines.

[0057] The time jump is the amount of time jump between the coarse and fine adjustment delay lines at the cascade switching point, also known as the switching gap. It represents the deviation between the actual and theoretical delay. For ease of explanation, the time jump variable caused by DNL mismatch during joint coarse and fine adjustment is called the "time jump." Ideally, one coarse adjustment step should equal the sum of N fine adjustment steps, but in reality, deviations exist due to layout parasites and circuit mismatches. The delay step value at this point is called the time jump (Gap). This time jump reflects the degree of delay distortion of the delay chain at the switching point, rather than the time consumed by the adjustment operation itself. The time jump indicates the delay deviation caused by the structural mismatch between the coarse and fine adjustment steps at the cascade switching point.

[0058] The joint adjustment of the coarse and fine delay lines refers to the switching point in the cascading adjustment process of the layered delay chain. Specifically, the coarse delay line needs to be incremented by 1, while the fine delay line flips from 15 to 0 to switch to the next delay level. For example, the actual delay levels include 0, 1, 2...127. When adjusting to level 2, the fine delay line is adjusted to 2, i.e., 0010; when adjusting to level 4, the fine delay line is adjusted to 4, i.e., 0100; when adjusting to level 16, the coarse delay line is incremented by 1, and the fine delay line flips to 0000. When the coarse and fine delay lines are jointly adjusted to level 16, the time jump is greater than the time jump of the fine delay line adjustment. In other words, the time jump from level 1 to level 2 is less than the time jump from level 15 to level 16. It should be understood that the joint adjustment of the coarse and fine adjustment delay lines refers to the simultaneous adjustment of the coarse and fine adjustment delay lines during the gear adjustment process, such as adjusting from gear 15 to gear 16.

[0059] For example, obtaining the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group includes: obtaining the delay step of the second delay line; determining the number of virtual gear positions based on the ratio of the time jump amount to the delay step; and generating a virtual gear position group based on the number of virtual gear positions.

[0060] It should be understood that a chip may contain multiple lanes, and the hierarchical delay chain characteristics of each lane differ due to layout parasitic differences. Therefore, the actual gear position, the initial detection result, and the virtual gear group are all independent parameters for the current lane, and phase training is performed independently on each lane.

[0061] The delay step size of the second delay line is the same as that of the fine-tuning delay line. When the fine-tuning and coarse-tuning delay lines are adjusted together, there will be jumps in time. If these time jumps are ignored, the determined optimal gear will be inaccurate. Therefore, based on the time jump amount of the joint adjustment of the fine-tuning and coarse-tuning delay lines and the delay step size of the fine-tuning delay line, the number of fine-tuning delay gears that the time jump spans, i.e., the number of virtual gears, is determined.

[0062] Specifically, the delay step size of the fine-tuning delay line and the time jump amount when the coarse-tuning delay line and fine-tuning delay line are jointly adjusted are determined. The ratio of the time jump amount to the delay step size of the fine-tuning delay line is determined. When this ratio is a positive integer, it is determined as the number of virtual gears. When the ratio is a non-positive integer, it is rounded down, rounded up, or rounded to the nearest integer to obtain the number of virtual gears (the specific rounding strategy can be determined according to the chip's jitter tolerance and bit error rate requirements). Further, based on the number of virtual gears, a virtual gear group is generated. For example, if adjusting the fine-tuning delay line requires 1ps and adjusting the coarse-tuning delay line and fine-tuning delay line together requires 5ps, then the number of virtual gears is determined to be 5, and the virtual gear group includes 5 virtual gears.

[0063] Optionally, the time jump amount when coarse and fine delay lines are adjusted together can be determined by testing the chip sample with an oscilloscope or other testing equipment. Alternatively, the time jump amount can be determined by real-time measurement during the power-on initialization phase using the chip's built-in delay measurement circuit. Of course, the time jump amount calibrated during the testing phase and written to non-volatile memory can also be used as the time jump amount. The method for determining the time jump amount can be determined according to the actual situation and is not specifically limited here.

[0064] For example, during the chip testing phase, the hierarchical delay chain is scanned step-by-step. At each level, the actual delay value is measured using an oscilloscope or on-chip detection circuit, and the eye diagram scan results showing whether data can be correctly received at each level are recorded. By analyzing the delay transitions between adjacent levels, the switching points of coarse and fine joint adjustment and the corresponding time jump amounts (i.e., time jump amounts) are identified.

[0065] The actual channel position in the chip can be determined through the chip configuration. The eye diagram scan result corresponding to the actual position is obtained through test data. The eye diagram scan result is either a first logic value or a second logic value, with the first logic value being the logical opposite of the second logic value. For example, if the first logic value is 1, then the second logic value is 0. Specifically, an eye diagram scan is performed by traversing each channel position, recording whether data can be correctly received at each position, thus obtaining the eye diagram scan result for each position. Continuous valid reception results form an eye diagram window (Data Eye Window).

[0066] The above technical solution determines the number of virtual gears based on the ratio of the time jump amount during joint adjustment to the delay step of the second delay line, thereby generating a virtual gear group. By utilizing hardware deviations under different processes, voltages, and temperatures, the delay gap at the coarse-fine joint adjustment switching point can be eliminated without modifying the underlying analog circuit, thus reducing the complexity of hardware design while ensuring the accuracy of eye diagram scanning and phase training.

[0067] S120 expands the actual gears based on the virtual gear group to obtain updated gears.

[0068] For example, expanding the actual gears based on virtual gear groups to obtain updated gears includes: determining the first gear in the actual gears that needs to be adjusted together; adding virtual gears from the virtual gear group before the first gear to obtain updated gears. The first gear is used to indicate the switching point gear whose gear value is exactly an integer multiple of the coarse adjustment step.

[0069] In practice, not every gear requires a combination of coarse and fine adjustment delay lines (e.g., adjusting from actual gear 1 to actual gear 10 only requires fine adjustment delay lines). Therefore, first determine the first gear that needs to be adjusted together. For example, actual gears include 0, 1, 2...127, and the first gear includes 16, 32, 48, etc.

[0070] Furthermore, given a first gear, virtual gears from the virtual gear group are added before each first gear to obtain updated gears. For example, if the virtual gear group includes 5 virtual gears, then 5 virtual gears are added before gear 16, 5 virtual gears are added before gear 32, and so on, until virtual gears from the virtual gear group are added before each first gear. It should be understood that the updated gears are obtained by expanding the actual gears through virtual gear groups, and the number of updated gears is greater than the number of actual gears.

[0071] It should be understood that "before the first gear" refers to the virtual gears in the virtual gear group that are inserted sequentially between the shifting gear (i.e., the first gear) and the previous adjacent actual gear.

[0072] The above technical solution identifies the first gear that needs to be adjusted in the actual gear position, adds a virtual gear from the virtual gear group before the first gear position to obtain the updated gear position; by inserting the virtual gear group before the actual gear that needs to be adjusted, an updated gear position with logical continuity is constructed, thereby eliminating the influence of the delay gap of the switching point in the hierarchical delay chain on the eye diagram scan through the virtual gear position, and ensuring the accurate positioning of the optimal sampling gear position without changing the analog circuit.

[0073] S130, based on the eye diagram scan results, performs detection result compensation on the update level to obtain the update scan result corresponding to the update level.

[0074] For example, based on the eye diagram scan results, the detection results of the update gear are compensated to obtain the update scan result corresponding to the update gear. There is a one-to-one correspondence between the update gear and the update scan result. The update scan result is either a first logic value or a second logic value, and consecutive first logic values ​​form a sampling window. For example, the first logic value is 1 and the second logic value is 0; or, the first logic value is 0 and the second logic value is 1. The update gear includes actual gears and virtual gear groups, and the number of update gears is greater than the number of actual gears.

[0075] For example, the detection result compensation for the updated gear based on the eye diagram scan result to obtain the updated scan result corresponding to the updated gear includes: determining the eye diagram scan result as the updated scan result of the actual gear in the updated gear; traversing the updated scan result of the actual gear to determine the sampling window corresponding to the actual gear; and performing detection result compensation for the virtual gear based on the relative position relationship between the sampling window and the virtual gear group to obtain the updated scan result of the virtual gear.

[0076] The updated gear positions include actual gear positions and virtual gear positions within the virtual gear position group. Each actual gear position has a corresponding eye diagram scan result, which is used as the updated scan result for the actual gear positions within the updated gear positions. After determining the detection results corresponding to the actual gear positions within the updated gear positions, each actual gear position has a corresponding updated scan result, but the virtual gear positions do not yet have corresponding updated scan results. The updated scan results for the actual gear positions are iterated through to determine the sampling window corresponding to each actual gear position. It should be understood that the sampling window may or may not include the virtual gear position group. Based on the relative positional relationship between the sampling window and the virtual gear position group, the detection results for the virtual gear positions are compensated to obtain the updated scan results for the virtual gear positions.

[0077] The above technical solution determines the updated scanning results of the actual gears in the updated gear positions by identifying the eye diagram scan results. It then iterates through the updated scanning results of the actual gear positions to determine the sampling window corresponding to each actual gear position. Based on the relative positional relationship between the sampling window and the virtual gear group, it compensates for the detection results of the virtual gear positions to obtain the updated scanning results of the virtual gear positions. By mapping the eye diagram scan results to the actual gear positions and performing differentiated compensation for the virtual gear positions according to the relative positional relationship between the sampling window and the virtual gear positions, it achieves the repair of nonlinear gaps, effectively avoids misjudgment of the optimal sampling window, and improves the accuracy of the optimal sampling window.

[0078] For example, based on the relative positional relationship between the sampling window and the virtual gear group, the detection result compensation of the virtual gear is performed to obtain the updated scanning result of the virtual gear, including: when the sampling window contains the target gear group, the first logic value is determined as the updated scanning result of the virtual gear in the target gear group, the sampling window is determined based on the continuous first logic value, and the target gear group is any virtual gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scanning result of the virtual gear in the target gear group; when the sampling window does not contain the target gear group, and the boundary of the sampling window is not adjacent to the target gear group, the second logic value is determined as the updated scanning result of the virtual gear in the target gear group, and the logic of the second logic value is the opposite of that of the first logic value.

[0079] After traversing the updated scan results of the actual gears and determining the sampling window corresponding to each actual gear, the detection results of each virtual gear in the virtual gear group are compensated to determine the updated scan result corresponding to the virtual gear. It should be understood that since the sampling window corresponds to the actual gear, and the virtual gear group is inserted between the actual gears, the sampling window may contain the virtual gear group, and the sampling window may also be adjacent to the virtual gear group. Conversely, the sampling window may not contain the virtual gear group, and the boundary of the sampling window may not be adjacent to the virtual gear group; that is, the actual gear contained in the sampling window may be separated from the virtual gear in the virtual gear group by other actual gears. Therefore, the updated scan results of the virtual gears are supplemented based on the relative positional relationship between the virtual gear group and the sampling window.

[0080] Each virtual gear group is sequentially identified as a target gear group, and it is determined whether the target gear group is contained within the sampling window, or whether the starting virtual gear in the target gear group is adjacent to the boundary of the sampling window. When the sampling window contains the target gear group, indicating that the sampling window spans the target gear group, the first logic value is determined as the updated scan result of the virtual gear in the target gear group. This detection result compensation can be called a span-type compensation, that is, the sampling window completely spans the virtual gear group. For example, if the target gear group includes 5 virtual gears, then the first logic value 1 is determined as the updated scan result corresponding to the 5 virtual gears.

[0081] When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, indicating that the sampling window ends exactly at the location of the target gear group (Gap), it may be due to the sampling window closing due to a time jump. In this case, the reference window length of the largest reference window appearing in the current channel is extracted. Combined with the effective width of the current truncated window, the hidden eye width (i.e., the hidden portion of the window) within the Gap is determined, and window padding is performed. That is, based on the reference window length of the largest reference window in the sampling window, the detection results of the virtual gears in the target gear group are compensated to obtain the updated scan results of the virtual gears in the target gear group. This detection result compensation can be called truncated compensation, meaning the sampling window ends at the boundary of the virtual gear group.

[0082] When the sampling window does not contain the target gear group, and the boundary of the sampling window is not adjacent to the target gear group, the second logic value is determined as the updated scan result of the virtual gears in the target gear group. For example, if the target gear group includes 5 virtual gears, then the second logic value 0 is determined as the updated scan result corresponding to the 5 virtual gears. This detection result compensation can be called isolation compensation, that is, the sampling window is completely separated from the virtual gear group.

[0083] The above technical solution, when the sampling window contains the target gear group, determines the first logical value as the updated scan result of the virtual gear in the target gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scan result of the virtual gear in the target gear group; otherwise, the second logical value is determined as the updated scan result of the virtual gear in the target gear group. Based on the three relative relationships between the sampling window and the virtual gear (i.e., inclusion relationship, boundary adjacency, and complete separation), compensation for the differentiated detection results of the virtual gears is achieved, thereby logically repairing the physical delay gap, eliminating the time jump of the layered delay chain at the coarse-fine adjustment switching point, and significantly improving the accurate positioning of the physical optimal sampling point.

[0084] For example, based on the reference window length of the largest reference window in the sampling window, the detection results of the virtual gears in the target gear group are compensated to obtain the updated scanning results of the virtual gears in the target gear group, including: determining the sampling window length of the sampling window adjacent to the target gear group; when the sampling window length is equal to the reference window length, determining the second logic value as the updated scanning result of the virtual gears in the target gear group; when the sampling window length is less than the reference window length, determining the length difference between the reference window length and the sampling window length, and determining the updated scanning result of the virtual gears in the target gear group based on the length difference and the number of virtual gears in the target gear group.

[0085] When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, determine the sampling window length of the sampling window adjacent to the target gear group (i.e., the sampling window length of the sampling window where the starting virtual gear is located). Determine whether the reference window length of the largest reference window (maximum eye width) among all sampling windows is equal to the sampling window length. It should be understood that since the reference window length is the window length of the maximum eye width, there will not be a window length greater than the reference window length.

[0086] When the sampling window length equals the reference window length, the second logical value is determined as the updated scan result of the virtual gear in the target gear group. It should be understood that, theoretically, the eye diagram width (i.e., the sampling window length) is the same; therefore, when the sampling window length equals the reference window length, it indicates that the eye diagram window is normally closed. Thus, the second logical value is determined as the updated scan result of the virtual gear in the target gear group.

[0087] When the sampling window length is less than the reference window length, it indicates that the eye diagram window is abnormally closed, i.e., closed due to gaps. Based on the length difference between the reference window length and the sampling window length, the virtual gears are padded with hidden eye widths. Then, based on the length difference and the number of virtual gears in the target gear group, the updated scan results for the virtual gears in the target gear group are determined.

[0088] For example, determining the update scan result of the virtual gears in the target gear group based on the length difference and the number of virtual gears in the target gear group includes: when the length difference is greater than or equal to the number of virtual gears, determining the first logical value as the update scan result of the virtual gears in the target gear group; when the length difference is less than the number of virtual gears, determining the virtual gears in the target gear group whose length difference starts from the initial virtual gear as the first virtual gear, and determining the virtual gears in the target gear group other than the first virtual gear as the second virtual gear; and determining the first logical value as the update scan result of the first virtual gear, and determining the second logical value as the update scan result of the second virtual gear.

[0089] When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the reference window length of the largest reference window in all sampling windows is 12. For example, when the sampling window length of the sampling window adjacent to the target gear group is 12, the updated scan result of the virtual gear in the target gear group is the second logical value. When the sampling window length adjacent to the target gear group is 7, the number of virtual gears in the target gear group is 5, the length difference between the reference window length and the sampling window length is 5, and the length difference is equal to the number of virtual gears (5), the updated scan result of the virtual gear in the target gear group is the first logical value to compensate the eye diagram window. When the sampling window length adjacent to the target gear group is 10, the length difference between the reference window length and the sampling window length is 2, and the length difference 2 is less than the number of virtual gears (5), the updated scan result of the first two virtual gears in the target virtual gear group is the first logical value, and the updated scan result of the last three virtual gears in the target virtual gear group is the second logical value.

[0090] The above technical solution, when the sampling window length equals the reference window length, indicates that the eye diagram window is normally closed, and the second logic value is determined as the updated scan result of the virtual gear. When the sampling window length is less than the reference window length, it indicates that the eye diagram window is abnormally closed, and the hidden eye width in the virtual gear is supplemented by combining the length difference with the number of virtual gears. By using the length difference between the reference window length and the sampling window length, and by making a fine comparison between the length difference and the number of virtual gears, the updated scan result of the virtual gear at the edge of the eye diagram is accurately compensated, accurately restoring the real eye diagram that is truncated by gaps, thereby improving the accuracy of the optimal gear.

[0091] Based on the relative positional relationship between the eye diagram sampling window and the virtual gear group, the compensation strategy for nonlinear compensation is divided into three types: cross-type, truncation type, and isolation type.

[0092] Spanning type: When the sampling window completely contains the virtual gear group, that is, the eye diagram window completely spans the gap area, all virtual gears in the group are marked as valid (first logic value), indicating that the delay points in the gap area can receive data normally.

[0093] Truncation type: When the boundary of the sampling window is adjacent to the starting virtual gear of the virtual gear group, that is, the eye diagram window is truncated by the gap, the gap is filled and compensated based on the maximum reference eye width appearing in the current channel to estimate the effective gear within the hidden eye width range.

[0094] Isolation type: When the sampling window is completely separated from the virtual gear group, that is, the gap area is outside the eye diagram's effective window, all virtual gears are marked as invalid (second logic value) and do not participate in the subsequent target gear search.

[0095] S140, based on the updated gear and the updated scan results, determines the target gear from the actual gear.

[0096] For example, determining the target gear from the actual gears based on the updated gear and the updated scan results includes: traversing the updated scan results to determine the updated sampling window corresponding to the updated gear; determining the evaluation parameters of the updated sampling window based on the length of the updated sampling window; and performing gear conversion on the updated gear associated with the largest evaluation parameter in the evaluation parameters to obtain the target gear from the actual gears.

[0097] It should be understood that there is a one-to-one correspondence between the update level and the update scan result. The update scan result is either a first logical value or a second logical value, and consecutive first logical values ​​can form an update sampling window. Therefore, given the update level and the update scan result, the update scan result is traversed to determine the update sampling window corresponding to the update level.

[0098] For each update sampling window, evaluation parameters are determined based on the window's length. These parameters indicate the eye diagram width and physical representation of the window's physical location. The largest evaluation parameter among multiple parameters is determined. Based on the update sampling window corresponding to the largest parameter, the update gear corresponding to the center position of that window is determined, and this update gear is mapped to the target gear in the actual gear group. During the mapping of update gears within the virtual gear group to target gears in the actual gear group, the actual gear closest to the update gear is identified as the target gear. When the update gear is equidistant from both ends of the actual gear group, the actual gear preceding the update gear is identified as the target gear. Alternatively, the target gear can be determined according to a pre-established proportional mapping rule. Specifically, when the virtual gear's index i in the virtual gear group satisfies i / n less than 1 / 2, it is mapped to the left-hand actual gear; when i / n is greater than or equal to 1 / 2, it is mapped to the right-hand actual gear. Here, n is the total number of virtual gears in the current gear group.

[0099] The above technical solution iterates through the update scan results to determine the update sampling window corresponding to the update level. Based on the length of the update sampling window, it determines the evaluation parameters of the update sampling window. The update level associated with the largest evaluation parameter in the evaluation parameters is converted to obtain the target level in the actual level. By traversing the update sampling window in the virtual domain containing the virtual level, the optimal level is selected and then mapped to the actual physical level. This avoids local misjudgment caused by physical nonlinearity, ensures the authenticity of the finally determined target level, and thus significantly improves the chip's anti-jitter capability and reduces the bit error rate of signal transmission.

[0100] In one example, the weight of the target sampling window is determined based on the second gear level using a pre-configured set of weight coefficients. The set of weight coefficients shows a negative correlation with the gear level and allows different weight configurations to be loaded based on process, voltage, and temperature (PVT) conditions.

[0101] Specifically, gear weights are implemented through a configurable weight matrix, which is a one-dimensional coefficient table with a length equal to the total number of virtual gears. Each entry corresponds to an independent weight coefficient for a gear. Higher weight coefficients correspond to lower gears, and vice versa. The weight matrix also allows for non-linear adjustments based on specific process deviations. During the initialization phase, the chip can load different weight matrix configurations from the firmware based on PVT test results.

[0102] For example, determining the evaluation parameters of the update sampling window based on the length of the update sampling window includes: determining the second level corresponding to the center position of the target sampling window, the target sampling window being used to indicate any sampling window in the update sampling window; determining the level weight of the target sampling window according to the level of the second level, the update level and level are in one-to-one correspondence, and the level and level weight are negatively correlated; and determining the evaluation parameters of the target sampling window by multiplying the level weight by the window length of the target sampling window.

[0103] Each updated sampling window is sequentially used as the target sampling window. The second gear corresponding to the center position of the target sampling window is determined, as well as the gear level of the second gear. Based on the gear level of the second gear, the gear weight of the target sampling window is determined. The gear level and the gear weight are linearly negatively correlated. The product of the gear weight and the window length of the target sampling window is determined as the evaluation parameter of the target sampling window.

[0104] The gear selection is determined sequentially from low to high, with each gear number serving as the gear level. It should be understood that updated gears include both virtual and actual gears. For example, actual gears include 0, 1, 2, 3…15, 16, 17…, and the virtual gear group includes 5 virtual gears. After expanding the actual gears through the virtual gear group, the updated gears include 0, 1, 2, 3…15, A, A, A, A, A, 16, 17…, where A represents a virtual gear. The gear levels are determined sequentially from low to high, including 0, 1, 2, 3…15, 16, 17, 18, 19, 20 (6, 17, 18, 19, and 20 are virtual gears), 21, 22…

[0105] The above technical solution determines the second gear corresponding to the center position of the target sampling window, determines the gear weight of the target sampling window based on the gear level of the second gear, and determines the evaluation parameter of the target sampling window by multiplying the gear weight by the window length of the target sampling window. By introducing a weight factor negatively correlated with the gear level, the sampling window length is evaluated with weight, avoiding the interference of high gear jitter on the optimal gear, and improving the accuracy and robustness of the target gear positioning.

[0106] For example, a mapping table between virtual gears and actual gears in a virtual gear group is constructed. The mapping table is used to map the updated gear from the virtual gear domain to the actual gear domain.

[0107] S150, control the first delay line and / or the second delay line to adjust to the target gear.

[0108] For example, once a target gear is determined, the first delay line and / or the second delay line are adjusted to the target gear. Specifically, after determining the target gear, the delay line can be adjusted to the target gear by fine adjustment only, or by a combination of fine adjustment and coarse adjustment.

[0109] The above technical solution expands the actual gears based on a virtual gear group to obtain updated gears. It then compensates for the detection results of the updated gears based on eye diagram scans, obtaining updated scan results corresponding to the updated gears. Finally, based on the updated gears and the updated scan results, it determines the target gear from the actual gears and adjusts to the target gear. By introducing a coarse-adjustment delay line and a fine-adjustment delay line combined with a time jump, a virtual gear group is constructed. This virtual gear group is then used to expand the timing space of the actual gears and compensate for the detection results, eliminating the risk of misjudgment in discrete gear search and ensuring the logical continuity of the obtained updated gears. Furthermore, by locating the physically optimal gear based on the updated gear and the updated scan results and adjusting to that gear, signal delay adjustment of the chip is achieved, significantly improving the timing margin and jitter resistance of high-frequency links and reducing the bit error rate of signal transmission. In addition, by calibrating and replacing analog circuit modifications through logic algorithms, modifications to the expensive analog physical layout are avoided, reducing the cost of delay adjustment and effectively enhancing the chip's mass production capability and cross-process node versatility. In particular, traditional analog compensation schemes are difficult to port between different process nodes (e.g., migrating from 7nm to 28nm requires redesigning the analog bias circuit), while the digital logic compensation scheme of this application has inherent process portability.

[0110] The phase training method will be described in detail below. The coarse-tuned delay line is the first delay line, and the fine-tuned delay line is the second delay line.

[0111] Figure 2This is a schematic flowchart of another phase training method provided in the embodiments of this application.

[0112] For example, such as Figure 2 As shown, the phase training method 200 includes S210 to S290.

[0113] S210: Obtain the time jump amount and the delay step of the fine adjustment delay line during coarse and fine combined adjustment. Based on the ratio of the time jump amount to the delay step, determine the number of virtual gears and then determine the virtual gear group.

[0114] For example, the combined coarse-fine adjustment of the coarse and fine delay lines refers to the switching point in the cascading adjustment process of the layered delay chain. That is, the coarse delay line needs to be incremented by 1, while the fine delay line flips from 15 to 0 to switch to the next delay level. For instance, the actual delay levels include 0, 1, 2...127. When adjusting to level 2, the fine delay line is adjusted to 2, i.e., 0010; when adjusting to level 4, the fine delay line is adjusted to 4, i.e., 0100; when adjusting to level 16, the coarse delay line is incremented by 1, and the fine delay line flips to 0000. However, the time jump when the coarse and fine delay lines are combined to adjust to level 16 is greater than the time jump of the fine delay line adjustment. In other words, the time jump from level 1 to level 2 is less than the time jump from level 15 to level 16. It should be understood that the joint adjustment of the coarse and fine adjustment delay lines refers to the simultaneous adjustment of the coarse and fine adjustment delay lines during the gear adjustment process, such as adjusting from gear 15 to gear 16.

[0115] When fine-tuning and coarse-tuning delay lines are adjusted together, there will be jumps in time. If these time jumps are ignored, the determined optimal gear will be inaccurate. Therefore, based on the time jump amount of the joint adjustment of fine-tuning and coarse-tuning delay lines and the delay step size of the fine-tuning delay line, the number of fine-tuning delay gears that the time jump spans, i.e., the number of virtual gears, is determined.

[0116] Specifically, the delay step size of the fine-tuning delay line is determined, and the time jump amount when adjusting the coarse and fine-tuning delay lines together is determined using an oscilloscope. The ratio of the time jump amount to the delay step size of the fine-tuning delay line is determined. When this ratio is a positive integer, it is determined as the number of virtual gears. When the ratio is a non-positive integer, it is rounded down to obtain the number of virtual gears. Further, based on the number of virtual gears, a virtual gear group is generated. For example, if adjusting the fine-tuning delay line requires 1ps, and adjusting the coarse and fine-tuning delay lines together requires 5ps, then the number of virtual gears is determined to be 5, and the virtual gear group includes 5 virtual gears.

[0117] Optionally, when calculating the number of virtual gears, a rounding strategy can be configured according to the application scenario of the chip: in high-precision scenarios (such as high-frequency interfaces), rounding up or rounding to the nearest whole number is used to maximize the compensation accuracy, while in low-power scenarios (such as low-frequency interfaces), rounding down is allowed to reduce the number of virtual gears and reduce hardware overhead.

[0118] S220, determine the first gear that needs to be adjusted in the actual gear, add the virtual gear in the virtual gear group before the first gear to obtain the updated gear.

[0119] For example, not every gear in the actual gear positions requires joint adjustment of both coarse and fine adjustment delay lines (e.g., adjusting actual gear 1 to actual gear 10 only requires fine adjustment delay lines). Therefore, the first gear in the actual gear positions that needs joint adjustment is first determined. For example, the actual gear positions include 0, 1, 2...127, and the first gear positions include 16, 32, 48, etc. Once the first gear positions are determined, virtual gears from the virtual gear group are added before each first gear position to obtain updated gear positions. For example, if the virtual gear group includes 5 virtual gears, then 5 virtual gears are added before gear 16, 5 virtual gears are added before gear 32, and so on, until virtual gears from the virtual gear group are added before each first gear position. It should be understood that by expanding the actual gear positions through virtual gear groups to obtain updated gear positions, the number of updated gear positions is greater than the number of actual gear positions.

[0120] S230, the eye diagram scan result is determined as the update scan result of the actual gear in the update gear, and the update scan result of the actual gear is traversed to determine the sampling window corresponding to the actual gear.

[0121] For example, the updated gear positions include actual gear positions and virtual gear positions within the virtual gear position group. Each actual gear position has a corresponding eye diagram scan result, which is used as the updated scan result for the actual gear positions in the updated gear positions. After determining the detection results corresponding to the actual gear positions in the updated gear positions, each actual gear position has a corresponding updated scan result, but the virtual gear positions do not yet have corresponding updated scan results. The updated scan results of the actual gear positions are traversed to determine the sampling window corresponding to each actual gear position. It should be understood that the sampling window may or may not include the virtual gear position group. Based on the relative positional relationship between the sampling window and the virtual gear position group, the detection results of the virtual gear positions are compensated to obtain the updated scan results for the virtual gear positions. Each virtual gear position group is sequentially determined as a target gear position group, and it is determined whether the target gear position group is included within the sampling window, or whether the starting virtual gear position in the target gear position group is adjacent to the boundary of the sampling window.

[0122] S240, when the sampling window contains the target gear group, the first logic value is determined as the updated scan result of the virtual gear in the target gear group.

[0123] For example, when the sampling window contains a target gear group, indicating that the sampling window spans the target gear group, the first logical value is determined as the updated scan result of the virtual gears in the target gear group. For instance, if the target gear group includes 5 virtual gears, the first logical value 1 is determined as the updated scan result corresponding to the 5 virtual gears.

[0124] S250, when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scanning result of the virtual gear in the target gear group.

[0125] It should be noted that in an ideal delay chain, the effective data window (eye width window) corresponding to each level is statistically consistent. Therefore, when a window is truncated by a gap, the maximum reference window length appearing in that channel can be approximated as the true width of the window before it was truncated, and the hidden eye width can be compensated accordingly.

[0126] For example, when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, it indicates that the sampling window ends exactly at the location of the target gear group (Gap). It may be that the sampling window is closed due to a time jump. Then, the reference window length of the largest reference window appearing in the current channel is extracted, and combined with the effective width of the current truncated window, the hidden eye width (i.e. the hidden part of the window) in the Gap is determined, and the window is filled.

[0127] When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, determine the sampling window length of the sampling window adjacent to the target gear group (i.e., the sampling window length of the sampling window where the starting virtual gear is located). Determine whether the reference window length of the largest reference window (maximum eye width) among all sampling windows is equal to the sampling window length. It should be understood that since the reference window length is the window length of the maximum eye width, there will not be a window length greater than the reference window length.

[0128] When the sampling window length equals the reference window length, the second logical value is determined as the updated scan result of the virtual gear in the target gear group. It should be understood that, theoretically, the eye diagram width (i.e., the sampling window length) is the same; therefore, when the sampling window length equals the reference window length, it indicates that the eye diagram window is normally closed. Thus, the second logical value is determined as the updated scan result of the virtual gear in the target gear group.

[0129] When the sampling window length is less than the reference window length, it indicates that the eye diagram window is abnormally closed, i.e., closed due to gaps. Based on the length difference between the reference window length and the sampling window length, the virtual gears are padded with hidden eye widths. Specifically, when the length difference is greater than or equal to the number of virtual gears, the first logical value is determined as the updated scan result of the virtual gears in the target gear group; when the length difference is less than the number of virtual gears, the virtual gears in the target gear group with the length difference starting from the initial virtual gear are determined as the first virtual gears, and the virtual gears in the target gear group other than the first virtual gears are determined as the second virtual gears; the first logical value is determined as the updated scan result of the first virtual gears, and the second logical value is determined as the updated scan result of the second virtual gears.

[0130] When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the reference window length of the largest reference window in all sampling windows is 12. For example, when the sampling window length of the sampling window adjacent to the target gear group is 12, the updated scan result of the virtual gear in the target gear group is the second logical value. When the sampling window length adjacent to the target gear group is 7, the number of virtual gears in the target gear group is 5, the length difference between the reference window length and the sampling window length is 5, and the length difference is equal to the number of virtual gears (5), the updated scan result of the virtual gear in the target gear group is the first logical value to compensate the eye diagram window. When the sampling window length adjacent to the target gear group is 10, the length difference between the reference window length and the sampling window length is 2, and the length difference 2 is less than the number of virtual gears (5), the updated scan result of the first two virtual gears in the target virtual gear group is the first logical value, and the updated scan result of the last three virtual gears in the target virtual gear group is the second logical value.

[0131] S260, when the sampling window does not contain the target gear group and the boundary of the sampling window is not adjacent to the target gear group, the second logic value is determined as the update scan result of the virtual gear in the target gear group.

[0132] For example, when the sampling window does not contain the target gear group and the boundary of the sampling window is not adjacent to the target gear group, the second logic value is determined as the updated scan result of the virtual gears in the target gear group. For instance, if the target gear group includes 5 virtual gears, then the second logic value 0 is determined as the updated scan result corresponding to the 5 virtual gears.

[0133] S270, iterate through the update scan results and determine the update sampling window corresponding to the update level.

[0134] For example, there is a one-to-one correspondence between the update level and the update scan result. The update scan result is either a first logical value or a second logical value, and consecutive first logical values ​​can form an update sampling window. Therefore, given the update level and update scan result, the update scan result is traversed to determine the update sampling window corresponding to the update level.

[0135] S280, based on the level of the second level corresponding to the target sampling window, determine the level weight of the target sampling window, and multiply the level weight by the window length of the target sampling window to determine the evaluation parameter of the target sampling window.

[0136] For example, each updated sampling window is sequentially used as the target sampling window. The second level corresponding to the center position of the target sampling window is determined, and the level grade of the second level is determined. Based on the level grade of the second level, the level weight of the target sampling window is determined. The level grade and the level weight are linearly negatively correlated. The product of the level weight and the window length of the target sampling window is determined as the evaluation parameter of the target sampling window.

[0137] The gear selection is determined sequentially from low to high, with each gear number serving as the gear level. It should be understood that updated gears include both virtual and actual gears. For example, actual gears include 0, 1, 2, 3…15, 16, 17…, and the virtual gear group includes 5 virtual gears. After expanding the actual gears through the virtual gear group, the updated gears include 0, 1, 2, 3…15, A, A, A, A, A, 16, 17…, where A represents a virtual gear. The gear levels are determined sequentially from low to high, including 0, 1, 2, 3…15, 16, 17, 18, 19, 20 (6, 17, 18, 19, and 20 are virtual gears), 21, 22…

[0138] Optionally, the weighting coefficients can be configured differently based on the chip's process, voltage, and temperature (PVT) conditions. In high-frequency or high-temperature scenarios, an additional attenuation coefficient (penalty factor) can be applied to the weights in higher frequency regions to further mitigate the risk of intrinsic jitter. The weighting configuration can be pre-stored in the chip's non-volatile memory and loaded during power-on initialization.

[0139] S290, perform gear conversion on the update gear associated with the largest evaluation parameter in the evaluation parameters to obtain the target gear, and adjust to the target gear.

[0140] For example, the largest evaluation parameter among multiple evaluation parameters is determined. Based on the update sampling window corresponding to the largest evaluation parameter, the update gear corresponding to the center position of the update sampling window is determined, and this update gear is mapped to the target gear in the actual gear range. During the process of mapping the update gear in the virtual gear range to the target gear in the actual gear range, the actual gear closest to the update gear is determined as the target gear. When the update gear is equidistant from the actual gears at both ends, the actual gear preceding the update gear is determined as the target gear. Further, after determining the target gear, it can be adjusted to the target gear solely through fine-tuning the delay line, or it can be adjusted to the target gear through a combination of fine-tuning and coarse-tuning delay lines.

[0141] In the process of mapping the updated gear in the virtual gear field to the target gear in the actual gear field, the target gear is determined according to the proportional mapping rule: Assume that the current virtual gear group contains n virtual gears, numbered from 1 to n. For the i-th virtual gear, when i / n is less than 1 / 2, it is mapped to the adjacent actual gear on the left; when i / n is greater than or equal to 1 / 2, it is mapped to the adjacent actual gear on the right.

[0142] For example, when inserting 5 virtual gears (n=5) between the actual gears Code 15 and Code 16, let's assume the virtual gears are v1, v2, v3, v4, and v5. Virtual gear v1 (i=1, 1 / 5 < 0.5) is mapped to the left-hand actual gear Code 15; virtual gear v2 (i=2, 2 / 5 < 0.5) is mapped to the left-hand actual gear Code 15; virtual gear v3 (i=3, 3 / 5 > 0.5) is mapped to the right-hand actual gear Code 16; virtual gear v4 (i=4, 4 / 5 > 0.5) is mapped to the right-hand actual gear Code 16; and virtual gear v5 (i=5, 5 / 5 > 0.5) is mapped to the right-hand actual gear Code 16.

[0143] The above technical solution expands the actual gear positions based on a virtual gear group to obtain updated gear positions. It then compensates for the detection results of the updated gear positions based on eye diagram scan results, obtaining updated scan results corresponding to the updated gear positions. Finally, based on the updated gear positions and the updated scan results, it determines the target gear position from the actual gear positions and adjusts to the target gear position. By introducing a coarse-adjustment delay line and a fine-adjustment delay line combined with a time jump, a virtual gear group is constructed. This virtual gear group is then used to expand the timing space of the actual gear positions and compensate for the detection results, eliminating the risk of misjudgment in discrete gear position searches and ensuring the logical continuity of the obtained updated gear positions. Furthermore, by locating the physically optimal gear position based on the updated gear position and the updated scan results and adjusting to that position, it achieves signal delay adjustment of the chip, significantly improving the timing margin and jitter resistance of the high-frequency link and reducing the bit error rate of signal transmission.

[0144] To more clearly illustrate the technical solution of this application, the following will combine... Figure 3 The three nonlinear compensation methods of this application are introduced.

[0145] Figure 3 This is a schematic diagram of a detection result compensation provided in an embodiment of this application.

[0146] For example, such as Figure 3 As shown in (a), the actual gear positions of the chip are determined to be 0, 1…14, 15, 16, 17… It should be understood that the actual gear position is the physical gear position within the actual gear position domain. The switching gear position (i.e., the first gear position) that needs to be adjusted jointly within the actual gear positions is 16. Therefore, the virtual gear position insertion point is between actual gear positions 15 and 16 (i.e., adding virtual gear positions from the virtual gear position group before the first gear position). Virtual gear positions V1, V2, V3, V4, and V5 from the virtual gear position group are inserted at the virtual gear position insertion point, resulting in gear position expansion within the actual gear position domain, thus obtaining the updated gear positions in the virtual gear position domain. Further, the detection results of the updated gear positions are compensated based on the eye diagram scan results of the actual gear positions to obtain the updated scan results corresponding to the updated gear positions.

[0147] For example, such as Figure 3 As shown in (b), the sampling window contains a virtual gear group. If the compensation is determined to be a cross-type compensation, then the first logic value 1 is determined as the update scan result of V1, V2, V3, V4, and V5 in the virtual gear group.

[0148] For example, such as Figure 3 As shown in (c), the boundary of the sampling window is adjacent to the starting virtual gear (i.e., V1) in the virtual gear group. The compensation is determined to be a truncated compensation. The reference window length is determined to be 12 and the sampling window length is 9. Then the update scan results of V1, V2, and V3 are determined as the first logic value 1, and the update scan results of V4 and V5 are determined as the second logic value 0.

[0149] For example, such as Figure 3 As shown in (d), the sampling window does not contain the virtual gear group, and the boundary of the sampling window is not adjacent to the virtual gear group. If the compensation is determined to be an isolation type compensation, then the second logic value 0 is determined to be the update scan result of V1, V2, V3, V4, and V5 in the virtual gear group.

[0150] It should be understood that the above examples are provided to help those skilled in the art understand the embodiments of this application, and are not intended to limit the embodiments of this application to the specific values ​​or scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or changes based on the above examples, and such modifications or changes also fall within the scope of the embodiments of this application.

[0151] The above text combined Figure 1 and Figure 3 The phase training method provided in the embodiments of this application has been described in detail; the following will be combined with Figure 4 and Figure 5 The phase training device embodiments of this application are described in detail below. It should be understood that the phase training device in the embodiments of this application can perform the various methods described in the foregoing embodiments of this application. That is, the specific working processes of the various products described below can be referred to the corresponding processes in the foregoing method embodiments.

[0152] Figure 4 This is a schematic diagram of the structure of a phase training device provided in an embodiment of this application.

[0153] For example, such as Figure 4 As shown, the phase training device 400 includes: Acquisition module 410: used to acquire the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group; the virtual gear position group includes at least one virtual gear position, and the at least one virtual gear position is determined based on the time jump amount when the first delay line and the second delay line are jointly adjusted; The expansion module 420 is used to expand the actual gears based on the virtual gear group to obtain updated gears; The compensation module 430 is used to compensate the detection results of the update level based on the eye diagram scan results, so as to obtain the update scan results corresponding to the update level. The determination module 440 is used to determine the target gear from the actual gear based on the updated gear and the updated scan results; The control module 450 is used to control the adjustment of the first delay line and / or the second delay line to the target gear.

[0154] In one possible implementation, the expansion module 420 is specifically used to determine the first gear that needs to be adjusted in the actual gear position; and to add the virtual gear in the virtual gear group before the first gear position to obtain the updated gear position.

[0155] In one possible implementation, the updated gear position includes an actual gear position and a virtual gear position group; the compensation module 430 is specifically used to determine the eye diagram scan result as the updated scan result of the actual gear position in the updated gear position; to traverse the updated scan result of the actual gear position to determine the sampling window corresponding to the actual gear position; and to compensate the detection result of the virtual gear position based on the relative position relationship between the sampling window and the virtual gear position group to obtain the updated scan result of the virtual gear position.

[0156] In one possible implementation, the compensation module 430 is specifically used to determine the first logical value as the updated scan result of the virtual gear in the target gear group when the sampling window contains the target gear group, wherein the sampling window is determined based on the continuous first logical values, and the target gear group is any virtual gear group; when the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the largest reference window in the sampling window to obtain the updated scan result of the virtual gear in the target gear group; when the sampling window does not contain the target gear group, and the boundary of the sampling window is not adjacent to the target gear group, the second logical value is determined as the updated scan result of the virtual gear in the target gear group, wherein the second logical value is the logical opposite of the first logical value.

[0157] In one possible implementation, the compensation module 430 is specifically used to determine the sampling window length of the sampling window adjacent to the target gear group; when the sampling window length is equal to the reference window length, the second logic value is determined as the update scan result of the virtual gear in the target gear group; when the sampling window length is less than the reference window length, the length difference between the reference window length and the sampling window length is determined, and the update scan result of the virtual gear in the target gear group is determined based on the length difference and the number of virtual gears in the target gear group.

[0158] In one possible implementation, the compensation module 430 is specifically used to determine the first logical value as the update scan result of the virtual gear in the target gear group when the length difference is greater than or equal to the number of virtual gears; when the length difference is less than the number of virtual gears, the virtual gear in the target gear group with the length difference starting from the initial virtual gear is determined as the first virtual gear, and the virtual gears in the target gear group other than the first virtual gear are determined as the second virtual gear; and the first logical value is determined as the update scan result of the first virtual gear, and the second logical value is determined as the update scan result of the second virtual gear.

[0159] In one possible implementation, the determining module 440 is specifically used to traverse the update scan results, determine the update sampling window corresponding to the update level, determine the evaluation parameters of the update sampling window based on the length of the update sampling window, and perform level conversion on the update level associated with the maximum evaluation parameter in the evaluation parameters to obtain the target level in the actual level.

[0160] In one possible implementation, the determining module 440 is specifically used to determine the second level corresponding to the center position of the target sampling window, the target sampling window is used to indicate any sampling window in the update sampling window; based on the level of the second level, the level weight of the target sampling window is determined, the update level and level are in one-to-one correspondence, the level and level are negatively correlated; the product of the level weight and the window length of the target sampling window is determined as the evaluation parameter of the target sampling window.

[0161] In one possible implementation, the acquisition module 410 is specifically used to acquire the delay step of the second delay line; determine the number of virtual gears based on the ratio of the time jump amount to the delay step; and generate a virtual gear group based on the number of virtual gears.

[0162] It should be noted that the aforementioned phase training device 400 is embodied in the form of a functional unit. The term "module" here can be implemented in software and / or hardware, without specific limitations.

[0163] For example, a "module" can be a software program, a hardware circuit, or a combination of both that implements the above functions. The hardware circuit may include an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components that support the described functions.

[0164] Therefore, the units of the various examples described in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0165] Figure 5 This is a schematic diagram of the structure of a phase training device provided in an embodiment of this application.

[0166] For example, such as Figure 5As shown, the phase training device 500 includes a memory 510 and a processor 520, wherein the memory 510 stores executable program code 530, and the processor 520 is used to call and execute the executable program code 530 to perform a phase training method.

[0167] For example, the memory 510 can be used to store related programs of the phase training method provided in the embodiments of this application; the processor 520 can call the related programs of the phase training method stored in the memory 510 to execute the phase training method of the embodiments of this application; for example, obtaining the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group; the virtual gear position group includes at least one virtual gear position, and the at least one virtual gear position is determined by the time jump amount when the first delay line and the second delay line are jointly adjusted; the actual gear position is expanded based on the virtual gear position group to obtain the updated gear position; the detection result compensation is performed on the updated gear position based on the eye diagram scan result to obtain the updated scan result corresponding to the updated gear position; the target gear position is determined from the actual gear position based on the updated gear position and the updated scan result; and the first delay line and / or the second delay line are controlled to adjust to the target gear position.

[0168] This embodiment can divide functional modules according to the above method example. For example, each module can correspond to a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0169] It should be noted that all relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0170] When using integrated units, the device may include a processing module and a storage module. The processing module may be a processor or a controller that can implement or execute various exemplary logic blocks, modules, and circuits shown in conjunction with the disclosure of this application. The processor may also be a combination of functions that implement computing capabilities, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc., and the storage module may be a memory.

[0171] In addition, the apparatus provided in the embodiments of this application may specifically be a chip, component or module. The chip may include a connected processor and a memory. The memory is used to store instructions. When the processor calls and executes the instructions, the chip can execute a phase training method provided in the above embodiments.

[0172] This application also provides a computer-readable storage medium storing computer program code, which, when run on a computer, causes the computer to execute the aforementioned method steps to implement the phase training method provided in the above embodiments. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, Digital Video Discs (DVDs), Compact Disc Read-Only Memory (CD-ROMs), microdrives, and magneto-optical disks, read-only memory (ROMs), random access memory (RAMs), erasable programmable read-only memory (EPROMs), electrically erasable programmable read-only memory (EEPROMs), dynamic random access memory (DRAMs), video random access memory (VRAMs), flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of media or device suitable for storing instructions and / or data.

[0173] This application also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement a phase training method provided in the above embodiments.

[0174] The computer-readable storage medium, computer program product, or chip provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0175] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0176] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0177] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A phase training method, characterized in that, The method is applied to a chip, wherein a first delay line and a second delay line are provided, and the delay step size of the first delay line is greater than the delay step size of the second delay line; the method includes: The actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group are obtained; the virtual gear position group includes at least one virtual gear position, and the at least one virtual gear position is determined based on the time jump amount when the first delay line and the second delay line are jointly adjusted; Based on the virtual gear group, the actual gear is expanded to obtain an updated gear; Based on the eye diagram scan results, the detection results of the update level are compensated to obtain the update scan results corresponding to the update level; Based on the updated gear position and the updated scan results, the target gear position is determined from the actual gear position; Control the first delay line and / or the second delay line to adjust to the target gear; The step of determining the target gear from the actual gear based on the updated gear and the updated scan result includes: Traverse the update scan results to determine the update sampling window corresponding to the update level; Based on the length of the updated sampling window, evaluation parameters for the updated sampling window are determined, and the evaluation parameters are used to indicate the eye diagram width and physical representation of the physical location of the updated sampling window; The update gear associated with the largest evaluation parameter in the evaluation parameters is converted to obtain the target gear in the actual gear.

2. The method according to claim 1, characterized in that, The step of expanding the actual gears based on the virtual gear group to obtain updated gears includes: Determine the first gear that needs to be adjusted in conjunction with the actual gear positions; The updated gear is obtained by adding a virtual gear from the virtual gear group before the first gear.

3. The method according to claim 1, characterized in that, The updated gear position includes the actual gear position and the virtual gear position group; The step of compensating the update level based on the eye map scan results to obtain the update scan result corresponding to the update level includes: The eye diagram scan result is determined as the update scan result of the actual gear in the update gear; The updated scan results of the actual gear position are traversed to determine the sampling window corresponding to the actual gear position; Based on the relative positional relationship between the sampling window and the virtual gear group, the detection results of the virtual gear are compensated to obtain the updated scan results of the virtual gear.

4. The method according to claim 3, characterized in that, The step of compensating for the detection results of the virtual gears based on the relative positional relationship between the sampling window and the virtual gear group to obtain the updated scan results of the virtual gears includes: When the sampling window contains a target gear group, the first logic value is determined as the update scan result of the virtual gear in the target gear group. The sampling window is determined based on consecutive first logic values, and the target gear group is any virtual gear group. When the boundary of the sampling window is adjacent to the starting virtual gear in the target gear group, the detection result compensation of the virtual gear in the target gear group is performed based on the reference window length of the maximum reference window in the sampling window to obtain the updated scanning result of the virtual gear in the target gear group. When the sampling window does not contain the target gear group and the boundary of the sampling window is not adjacent to the target gear group, the second logical value is determined as the update scan result of the virtual gear in the target gear group, and the second logical value is the opposite of the first logical value.

5. The method according to claim 4, characterized in that, The step of compensating for the detection results of the virtual gears in the target gear group based on the reference window length of the largest reference window in the sampling window, to obtain the updated scan results of the virtual gears in the target gear group, includes: Determine the sampling window length of the sampling window adjacent to the target gear group; When the sampling window length is equal to the reference window length, the second logical value is determined as the updated scan result of the virtual gear in the target gear group; When the sampling window length is less than the reference window length, the length difference between the reference window length and the sampling window length is determined. Based on the length difference and the number of virtual gears in the target gear group, the update scan result of the virtual gears in the target gear group is determined.

6. The method according to claim 5, characterized in that, The step of determining the updated scan result of the virtual gears in the target gear group based on the length difference and the number of virtual gears in the target gear group includes: When the length difference is greater than or equal to the number of virtual gears, the first logical value is determined as the update scan result of the virtual gears in the target gear group; When the length difference is less than the number of virtual gears, the virtual gear with the length difference starting from the initial virtual gear in the target gear group is determined as the first virtual gear, and the virtual gears in the target gear group other than the first virtual gear are determined as the second virtual gear; and the first logical value is determined as the update scan result of the first virtual gear, and the second logical value is determined as the update scan result of the second virtual gear.

7. The method according to claim 1, characterized in that, The step of determining the evaluation parameters of the update sampling window based on the length of the update sampling window includes: Determine the second level corresponding to the center position of the target sampling window, wherein the target sampling window is used to indicate any sampling window in the updated sampling window; Based on the gear level of the second gear, the gear weight of the target sampling window is determined. The updated gear and the gear level are in one-to-one correspondence, and the gear level and the gear weight are negatively correlated. The product of the gear weight and the window length of the target sampling window is determined as the evaluation parameter of the target sampling window.

8. The method according to any one of claims 1 to 6, characterized in that, The step of obtaining the actual channel level in the chip, the eye diagram scan result corresponding to the actual channel level, and the virtual channel level group includes: Obtain the delay step size of the second delay line; The number of virtual gears is determined based on the ratio of the time jump amount to the delay step size; The virtual gear group is generated based on the number of virtual gears.

9. A phase training device, characterized in that, The device is applied to a chip, the chip having a first delay line and a second delay line, the delay step of the first delay line being larger than the delay step of the second delay line; the device includes: The acquisition module is used to acquire the actual gear position of the channel in the chip, the eye diagram scan result corresponding to the actual gear position, and the virtual gear position group; the virtual gear position group includes at least one virtual gear position, and the at least one virtual gear position is determined based on the time jump amount when the first delay line and the second delay line are jointly adjusted; An expansion module is used to expand the actual gears based on the virtual gear group to obtain updated gears; The compensation module is used to compensate the detection results of the update level based on the eye diagram scan results, so as to obtain the update scan results corresponding to the update level; The determining module is used to determine the target gear from the actual gear based on the updated gear and the updated scan result; The control module is used to control the first delay line and / or the second delay line to adjust to the target gear. Specifically, the determining module is used to traverse the update scan results and determine the update sampling window corresponding to the update level; based on the length of the update sampling window, determine the evaluation parameters of the update sampling window, the evaluation parameters being used to indicate the eye diagram width and physical representation of the physical position of the update sampling window; and perform level conversion on the update level associated with the maximum evaluation parameter in the evaluation parameters to obtain the target level in the actual level.

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