Dff test structure combining controllable mux delay chain and balanced tree

Abstract

This invention relates to the field of integrated circuit testing technology, specifically to a DFF test structure combining a controllable MUX delay chain and a balanced tree. It includes an electrically connected controllable MUX delay chain module and a balanced tree buffer network. A DFF cross-test array is electrically connected to the balanced tree buffer network, and a result acquisition and processing module (SDFF) is electrically connected to the DFF cross-test array. A control logic module is electrically connected to the controllable MUX delay chain module. This invention utilizes a fully digital standard cell construction, achieving seamless integration with existing design flows. Its picosecond-level resolution, symmetric anti-bias design, and multi-array statistical analysis capabilities enable precise and efficient timing characterization of DFFs at advanced process nodes, providing strong support for chip timing convergence and yield improvement.

Description

Technical Field

[0001] This invention relates to a DFF test structure, and more particularly to a DFF test structure combining a controllable MUX delay chain and a balanced tree, belonging to the field of integrated circuit test technology. Background Technology

[0002] As integrated circuit feature sizes continue to shrink to advanced nodes, the setup and hold times of the diode flip-flop (DFF) play a crucial role in chip timing convergence. At 12nm and even 7nm processes, transistor threshold voltage fluctuations, metal interconnect delays, and stress effects can all introduce timing deviations on the order of nanoseconds or even picoseconds, making traditional static timing analysis insufficient to fully reflect the true behavior of the silicon wafer.

[0003] Currently, commonly used timing characteristic testing methods for DFFs mainly include: (1) external high-speed testing based on ATE; (2) scan chain structure combined with clock phase shift method; and (3) on-chip self-test scheme. However, these methods generally suffer from problems such as insufficient resolution, high testing complexity, high power consumption, or layout mismatch.

[0004] For example, the ATE testing method requires an external high-precision clock source to calculate the setup and hold window of the DFF by progressively scanning the clock phase. This method requires picosecond-level resolution under advanced processes, resulting in extremely high test instrument costs. Furthermore, external signal lines lead to parasitic effects, impacting measurement accuracy. The scan chain method, on the other hand, relies on a large number of cascaded latches and flip-flops, making precise control of measurement delay difficult.

[0005] Therefore, there is an urgent need for a setup / hold characteristic testing method that can directly achieve high resolution, symmetrical structure, and programmable control inside the chip, so as to complete process evaluation and model calibration in the early stages of standard cell development. Summary of the Invention

[0006] The purpose of this invention is to provide a DFF test structure that combines a controllable MUX delay chain with a balanced tree. Constructed with all-digital standard cells, it achieves seamless integration with existing design flows. Its picosecond-level resolution, symmetric anti-bias design, and multi-array statistical analysis capabilities enable precise and efficient timing characterization of DFFs at advanced process nodes, providing strong support for chip timing convergence and yield improvement.

[0007] To achieve the above objectives, the main technical solutions adopted by the present invention include: A DFF test structure combining a controllable MUX delay chain and a balanced tree includes an electrically connected controllable MUX delay chain module and a balanced tree buffer network. A DFF cross-test array is electrically connected to the balanced tree buffer network. A result acquisition and processing module SDFF is electrically connected to the DFF cross-test array. A control logic module is electrically connected to the controllable MUX delay chain module. The controllable MUX delay chain module is a delay chain composed of two standard unit multiplexers (MUX) cascaded together, including a fast delay chain DF and a slow delay chain DS. The input terminals of the fast delay chain DF and the slow delay chain DS are driven by the same reference clock EN_clk. The output terminal of the fast delay chain DF is DF_out, and the output terminal of the slow delay chain DS is DS_out. The balanced tree buffer network is used to symmetrically drive and allocate the delay signal of the controllable MUX delay chain module; The DFF cross-test array includes several DFF pair test units, each of which consists of two identical digital circuit D-type flip-flops (DFFs) connected in a cross-connection manner. The result acquisition and processing module SDFF has an array-based layout structure, which is used to repeatedly distribute test units at multiple locations on the chip for statistical analysis. The control logic module is used to select the output stage of the controllable MUX delay chain module to achieve finely adjustable delay difference.

[0008] Preferably, both the fast delay chain DF and the slow delay chain DS are composed of two stages of standard unit inverters and standard unit MUX connected in series; Each of the standard unit MUXs consists of two input terminals I0 and I1, one output terminal Z, and one selection terminal S. The S terminal of all standard unit MUXs is grounded, so that the signal propagates along the fixed input terminal.

[0009] Preferably, the balanced tree buffer network consists of two levels of standard unit inverters, the first level being inv4 and the second level being inv16, and the DF path and DS path are strictly symmetrical in topology.

[0010] Preferably, the balanced tree buffer network adopts a tree structure: The first stage, inv4, uses an inverter with first drive capability for edge signal shaping; The second stage, inv16, uses an inverter with a second driving capability greater than the first driving capability. Its output is directly connected to the clock and data terminals of each DFF pair.

[0011] Preferably, in each of the digital circuit D-type flip-flops (DFFs), the data terminal of the first digital circuit D-type flip-flop (DFF) is connected to the DF delay chain output and the clock terminal is connected to the DS delay chain output; The second digital circuit's D-type flip-flop (DFF) has its data terminal connected to the DS delay chain output and its clock terminal connected to the DF delay chain output.

[0012] Preferably, the DFF pair test units are distributed in an array across multiple regions of the chip, and each array contains multiple sets of digital circuit D-type flip-flops (DFFs) for statistical analysis of process fluctuations on the chip.

[0013] Preferably, the chip has multiple arrays arranged on it, located in the center, edge and corner regions of the chip, respectively, to capture on-chip variation effects.

[0014] The testing method for the DFF test structure combining the controllable MUX delay chain and the balanced tree includes the following steps: S1. Configure the control logic and set the number of output delay stages in the delay chain; S2. Input the reference clock signal to start the test sequence; S3. Gradually adjust the delay difference and monitor the DFF output switching status; S4. Determine the setup and hold time boundaries based on the DFF output flip probability. S5. Conduct statistical analysis on the test results from different regions to assess the impact of process fluctuations.

[0015] Preferably, the delay adjustment step size is 1 picosecond, and the measurement error is less than ±2 picoseconds.

[0016] Preferably, the mean and standard deviation of the test results of multiple arrays are calculated to obtain the distribution statistics of setup time and hold time; Calibrate time series models or assess the impact of process fluctuations based on statistical results.

[0017] The present invention has at least the following beneficial effects: 1. The all-digital standard cell construction enables seamless integration with existing design flows. Its picosecond-level resolution, symmetric anti-bias design, and multi-array statistical analysis capabilities enable precise and efficient timing characterization of DFFs at advanced process nodes, providing strong support for chip timing convergence and yield improvement.

[0018] 2. Corresponding to the two paths CLK_F and CLK_S, starting from the output of the controllable MUX delay chain module 1 and all the way to the port of each digital circuit D-type flip-flop (DFF), the number of inverters, their types, layout shapes, and wiring lengths are carefully matched to ensure strict symmetry of the topology. The layout design adopts common centroid and interdigitated layout techniques to further offset the influence of process gradient. Simulation shows that, under good matching conditions, the additional deviation between the two signals introduced by the balanced tree can be controlled within 0.5 picoseconds. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a general structural block diagram of the present invention; Figure 2 This is a schematic diagram of the controllable MUX delay chain structure of the present invention; Figure 3 This is a diagram of the working path structure of the controllable MUX delay link of the present invention; Figure 4 This is the balanced tree signal allocation topology diagram of the present invention; Figure 5 This is a test structure diagram of the DFF cross-connect pair of the present invention; Figure 6 This is a schematic diagram of the multi-array distribution on the chip of the present invention.

[0020] In the diagram, 1. Controllable MUX delay chain module; 101. Fast delay chain DF; 102. Slow delay chain DS; 103. Standard unit MUX; 2. Balanced tree buffer network; 201. Two-stage standard unit inverter; 3. DFF cross-test array; 301. DFF pair test unit; 302. Digital circuit D-type flip-flop (DFF); 4. Result acquisition and processing module SDFF; 5. Control logic module. Detailed Implementation

[0021] The following will describe in detail the implementation of this application with reference to the accompanying drawings and embodiments, so that the implementation process of how this application uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0022] like Figures 1-6As shown, the DFF test structure combining a controllable MUX delay chain and a balanced tree provided in this embodiment includes an electrically connected controllable MUX delay chain module 1 and a balanced tree buffer network 2. A DFF cross-test array 3 is electrically connected to the balanced tree buffer network 2, and a result acquisition and processing module SDFF 4 is electrically connected to the DFF cross-test array 3. A control logic module 5 is electrically connected to the controllable MUX delay chain module 1. Constructed with all-digital standard cells, it achieves seamless integration with existing design flows. Its picosecond-level resolution, symmetric anti-bias design, and multi-array statistical analysis capabilities enable it to accurately and efficiently complete the timing characterization of DFFs under advanced process nodes, providing strong support for chip timing convergence and yield improvement. Example 1: like Figure 1 As shown, the controllable MUX delay chain module 1 is a delay chain composed of two standard unit multiplexers (MUX) cascaded together, including a fast delay chain DF101 and a slow delay chain DS102. The input terminals of the fast delay chain DF101 and the slow delay chain DS102 are driven by the same reference clock EN_clk. The output terminal of the fast delay chain DF101 is DF_out, and the output terminal of the slow delay chain DS102 is DS_out. The balanced tree buffer network 2 is used to symmetrically drive and distribute the delay signal of the controllable MUX delay chain module 1. The DFF cross-test array 3 includes several DFF pair test units 301. Each DFF pair test unit 301 consists of two identical digital circuit D-type flip-flops DFF302, and they are cross-connected. The SDFF4 result acquisition and processing module has an array-based layout structure, which is used to repeatedly distribute test units at multiple locations on the chip for statistical analysis. The control logic module 5 is used to select the output stage of the controllable MUX delay chain module 1 to achieve finely adjustable delay difference. A reference clock signal CLK_ref is input to the controllable MUX delay chain module 1, which outputs two clock signals with controllable small delay difference: fast clock CLK_F and slow clock CLK_S. These two signals are buffered and distributed through a completely symmetrical 2 to eliminate the asymmetry caused by drive capability and wiring. The assigned signal is sent to the DFF cross-test array 3, which consists of multiple DFF pair test units 301. The control logic module 5 is responsible for configuring the delay amount of the controllable MUX delay chain module 1 and controlling the execution of the test sequence. The result acquisition and processing module SDFF4 scans and reads the output state of each digital circuit D-type flip-flop DFF302 and performs data processing and analysis.

[0023] Example 2: like Figure 2 and Figure 3 As shown, both the fast delay chain DF101 and the slow delay chain DS102 are composed of two-stage standard unit inverters 201 and standard unit MUX103 connected in series. Each standard unit MUX103 consists of two input terminals I0 and I1, one output terminal Z, and one selection terminal S. The S terminal of all standard unit MUX103 is grounded, so that the signal propagates along the fixed input terminal. The control logic module 5 contains a programmable counter or decoder, whose output controls a group of multiplexers. By fixing the S terminal to a logic low level, the signal propagates along the I1 path, which is equivalent to forming a linear delay. By selecting a single-stage controllable MUX delay chain module 1 with a specific size and threshold voltage, the controllable MUX delay chain module 1 on the fast delay chain DF101 and the slow delay chain DS102 under the same clk_in signal selected path can achieve an output signal delay of about 1 picosecond for the two delay chains, and the total link delay can reach about 200 picoseconds.

[0024] Example 3: like Figure 4 As shown, the balanced tree buffer network 2 consists of two levels of standard unit inverters 201, with the first level being inv4 and the second level being inv16. The DF path and DS path are strictly symmetrical in topology. The balanced tree buffer network 2 adopts a tree structure. The first stage, inv4, uses an inverter with the first drive capability for edge signal shaping. The second-stage inv16 uses inverters with a second driving capability greater than the first. Its output is directly connected to the clock and data terminals of each DFF pair, corresponding to the two paths CLK_F and CLK_S. Starting from the output of the controllable MUX delay chain module 1, it extends to the port of each digital circuit D-type flip-flop DFF302. The number of inverter stages, model, layout shape, and wiring length are carefully matched to ensure strict symmetry of the topology. The layout design employs common centroid and interdigitated layout techniques to further offset the effects of process gradients. Simulations show that, under good matching conditions, the additional deviation between the two signals introduced by the balanced tree can be controlled within 0.5 picoseconds.

[0025] Example 4: like Figure 5As shown, each DFF pair test unit includes two digital circuit D-type flip-flops: the data terminal of the first digital circuit D-type flip-flop (hereinafter referred to as DFF1) is connected to the output of the DF delay chain, and the clock terminal is connected to the output of the DS delay chain; the data terminal of the second digital circuit D-type flip-flop (hereinafter referred to as DFF2) is connected to the output of the DS delay chain, and the clock terminal is connected to the output of the DF delay chain. The basic unit of the DFF cross-test array 3 is a DFF pair test unit 301, which consists of two physically adjacent and identical digital circuit D-type flip-flops DFF302 from the same standard cell library. Its connection method is a cross connection: The clock input CK of DFF1 is connected to the slow clock CLK_S, and the data input D is connected to the fast clock CLK_F. The clock input CK of DFF2 is connected to the fast clock CLK_F, and the data input D is connected to the slow clock CLK_S. The innovation of this structure lies in its ability to examine two boundary conditions simultaneously in a single test: For DFF1, the fast clock drives the data and the slow clock drives the clock, which simulates the test conditions for setup time: whether the data change is early enough relative to the clock capture edge; For DFF2, the situation is exactly the opposite, simulating the test conditions for hold time: whether the data change is held long enough relative to the clock capture edge; This complementary structure can effectively cancel out common-mode interference caused by local voltage drops, temperature hotspots, or substrate noise, because these interferences have similar effects on the two DFFs and can be partially canceled out during comparative analysis, thereby improving the robustness and accuracy of measurements.

[0026] Example 5: like Figure 6 As shown, the DFF pair test units are distributed in array form in multiple areas of the chip. Each array contains multiple sets of digital circuit D-type flip-flops for statistical analysis of on-chip process fluctuations. Multiple arrays are arranged on the chip, located in the center, edge and corner areas of the chip, respectively, to capture on-chip variation effects. In order to study the impact of on-chip process fluctuations on timing, the test units of the present invention are repeatedly distributed in array form at different physical locations on the chip. In one complete embodiment, K test arrays are deployed on the chip, each array containing M groups of DFF pair test units 301 clusters, each cluster having P pairs of digital circuit D-type flip-flops DFF302, that is, a single array contains a total of 100 pairs of digital circuit D-type flip-flops DFF302. These arrays are arranged in typical locations on the chip: the central area, the four corners, the midpoints of the four sides, etc. During testing, the same delay scan procedure is performed on all arrays. By analyzing the setup / hold time measurements from different arrays, the mean µ and standard deviation σ can be calculated, thereby quantifying the global and local timing fluctuations on the chip. These post-silicon statistics are of great value for calibrating the static timing analysis (STA) model and optimizing the timing margin of the standard cell library.

[0027] like Figures 1-6 As shown, the test method for the DFF test structure combining a controllable MUX delay chain and a balanced tree provided in this embodiment includes the following steps: S1. Configure the control logic and set the number of output delay stages in the delay chain; S2. Input the reference clock signal to start the test sequence; S3. Gradually adjust the delay difference and monitor the DFF output flip state. The delay adjustment step size is 1 picosecond, and the measurement error is less than ±2 picoseconds. S4. Determine the setup and hold time boundaries based on the DFF output flip probability. S5. Perform statistical analysis on the test results of different regions, calculate the mean and standard deviation of the test results of multiple arrays, and obtain the distribution statistics of setup time and hold time. Calibrate timing models or assess the impact of process fluctuations based on statistical results. No external high-speed testing instruments are required, and the test process, data acquisition, and result analysis can be executed automatically, which greatly improves test efficiency and accuracy. Meanwhile, this method is applicable to DFF cell quality assessment and timing model calibration at different process nodes, and has wide applicability and flexibility.

[0028] If certain terms are used in the specification and claims to refer to specific components, those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The term "comprising" as used throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." "Approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error.

[0029] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a product or system comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a product or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the product or system that includes that element.

[0030] The foregoing description illustrates and describes several preferred embodiments of the present invention. However, as previously stated, it should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the inventive concept described herein through the foregoing teachings or techniques or knowledge in related fields. Any modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A DFF test structure combining controllable MUX delay chain and balanced tree, comprising controllable MUX delay chain module (1) and balanced tree buffer network (2) connected electrically, characterized in that, The balanced tree buffer network (2) is electrically connected to the DFF cross-test array (3), the DFF cross-test array (3) is electrically connected to the result acquisition and processing module SDFF (4), and the controllable MUX delay chain module (1) is electrically connected to the control logic module (5). The controllable MUX delay chain module (1) is a delay chain composed of two standard unit multiplexers (MUX) cascaded together, including a fast delay chain DF (101) and a slow delay chain DS (102). The input terminals of the fast delay chain DF (101) and the slow delay chain DS (102) are driven by the same reference clock EN_clk. The output terminal of the fast delay chain DF (101) is DF_out, and the output terminal of the slow delay chain DS (102) is DS_out. The balanced tree buffer network (2) is used to symmetrically drive and allocate the delay signal of the controllable MUX delay chain module (1); The DFF cross-test array (3) includes several DFF pair test units (301), each of which consists of two identical digital circuit D-type flip-flops (DFF) (302) and is cross-connected. The result acquisition and processing module SDFF (4) has an array-based layout structure, which is used to repeatedly distribute test units at multiple locations on the chip for statistical analysis; The control logic module (5) is used to select the output stage of the controllable MUX delay chain module (1) to achieve finely adjustable delay difference.

2. The DFF test structure of claim 1, wherein: Both the fast delay chain DF (101) and the slow delay chain DS (102) are composed of two-stage standard unit inverters (201) and standard unit MUX (103) connected in series; Each of the standard unit MUX (103) consists of two input terminals I0 and I1, one output terminal Z and one selection terminal S. The S terminal of all standard unit MUX (103) is grounded, so that the signal propagates along the fixed input terminal.

3. The DFF test structure of claim 1, wherein the controllable MUX delay chain is combined with a balanced tree. The balanced tree buffer network (2) consists of two levels of standard unit inverters (201), the first level is inv4 and the second level is inv16, and the DF path and DS path are strictly symmetrical in topology.

4. The DFF test structure of claim 1, wherein the controllable MUX delay chain is combined with a balanced tree. The balanced tree buffer network (2) adopts a tree structure: The first stage inv4 is an inverter using an inverter with first drive capability, used for edge signal shaping; The second stage, inv16, uses an inverter with a second driving capability greater than the first driving capability. Its output is directly connected to the clock and data terminals of each DFF pair.

5. The DFF test structure combining a controllable MUX delay chain and a balanced tree according to claim 1, characterized in that: In each of the digital circuit D-type flip-flops DFF (302), the data terminal of the first digital circuit D-type flip-flop DFF (302) is connected to the DF delay chain output and the clock terminal is connected to the DS delay chain output; The data terminal of the second digital circuit D-type flip-flop DFF (302) is connected to the output of the DS delay chain, and the clock terminal is connected to the output of the DF delay chain.

6. The DFF test structure of claim 1, wherein the controllable MUX delay chain is combined with a balanced tree. The DFF pair test units (301) are distributed in an array in multiple areas of the chip. Each array contains multiple sets of digital circuit D-type flip-flops (DFFs) (302) for statistical analysis of process fluctuations on the chip.

7. The DFF test structure of claim 6, wherein the controllable MUX delay chain is combined with a balanced tree. The chip has multiple arrays arranged on it, located in the center, edge and corner regions of the chip, to capture on-chip variation effects.

8. The test method of claim 1, wherein the test method is based on the DFF test structure of any one of claims 1 to 7 in combination with a controllable MUX delay chain and a balanced tree. Includes the following steps: S1. Configure the control logic and set the number of output delay stages in the delay chain; S2. Input the reference clock signal to start the test sequence; S3. Gradually adjust the delay difference and monitor the DFF output switching status; S4. Determine the setup and hold time boundaries based on the DFF output flip probability. S5. Conduct statistical analysis on the test results from different regions to assess the impact of process fluctuations.

9. The test method for a DFF test structure combining a controllable MUX delay chain and a balanced tree according to claim 8, characterized in that: The delay adjustment step size is 1 picosecond, and the measurement error is less than ±2 picoseconds.

10. The test method for a DFF test structure combining a controllable MUX delay chain and a balanced tree according to claim 8, characterized in that: The mean and standard deviation of the test results for multiple arrays are calculated to obtain the distribution statistics of setup time and hold time; Calibrate time series models or assess the impact of process fluctuations based on statistical results.

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