Integrated circuit limit capability determination method, apparatus, device, and storage medium

Abstract

This application relates to a method, apparatus, device, and storage medium for determining the ultimate capability of integrated circuits. The method includes: performing extreme condition tests on a preset number of target integrated circuits and obtaining test results, including censored data related to the failure of the target integrated circuits; verifying the reliability of the censored data to determine statistical reliability information of the target integrated circuits under extreme conditions, wherein the statistical reliability information includes quantization results with reliability intervals; obtaining an initial simulation model corresponding to the target integrated circuits and optimizing the initial simulation model based on the statistical reliability information to obtain a target simulation model, wherein the error between the simulation results of the target simulation model and the test results is less than a preset error threshold; performing extreme simulations under different stress scenarios based on the target simulation model, and determining the ultimate capability and failure cause of the integrated circuit based on each simulation result. This method can improve the reliability of the ultimate capability of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus, device, and storage medium for determining the limiting capabilities of integrated circuits. Background Technology

[0002] As electronic components continue to evolve towards higher density and higher performance, traditional quality and reliability testing technologies are becoming increasingly inadequate to meet the stringent reliability requirements of complex application scenarios. The reliability problems faced by electronic components are becoming more and more prominent, making it particularly important to systematically study the failure threshold of electronic components under high stress and to develop more effective reliability assurance technologies.

[0003] In existing methods, the structure of integrated circuits is modeled and the ultimate capability is assessed and determined based on the simulation model. However, there are certain differences between the simulation model and the actual device in terms of physical characteristics, manufacturing deviations, and packaging effects. Especially under extreme stress scenarios, material properties and multi-stress coupling will further amplify the deviation, making it impossible to effectively prove the correctness of the model simulation results. In other words, the reliability of the determined ultimate capability is low. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, device, and storage medium for determining the limits of integrated circuits that can improve the reliability of the limits of integrated circuits, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a method for determining the limiting capabilities of integrated circuits, including:

[0006] A predetermined number of target integrated circuits are subjected to extreme operating condition tests, and the test results are obtained, including censored data related to the failure of the target integrated circuits.

[0007] Based on the censored data, the credibility is verified to determine the statistical credibility information of the target integrated circuit under extreme operating conditions. The statistical credibility information includes the quantization results with credibility intervals.

[0008] Obtain the initial simulation model corresponding to the target integrated circuit, and optimize the initial simulation model based on statistical confidence information to obtain the target simulation model. The error between the simulation results and the test results of the target simulation model is less than a preset error threshold.

[0009] Based on the target simulation model, limit simulations are performed under different stress scenarios, and the ultimate capability and failure causes of the integrated circuit are determined based on the simulation results.

[0010] In one embodiment, the initial simulation model is optimized based on statistical reliability information to obtain the target simulation model, including:

[0011] The model parameters of the initial simulation model are adjusted based on the statistically reliable information until the difference between the simulation results obtained based on the adjusted simulation model and the statistically reliable information is less than a preset error threshold. The adjusted simulation model is then used as the target simulation model.

[0012] In one embodiment, the censored data includes right-censored data and interval-censored data; the failure duration of the target integrated circuit follows a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter. Confidence verification is performed based on the censored data to determine the statistically reliable information of the target integrated circuit under extreme operating conditions, including:

[0013] The joint likelihood function is determined based on the reliability function of right-censored data, interval-censored data, and the two-parameter Weibull distribution.

[0014] Obtain the prior distributions corresponding to the shape parameters and the scale parameters, and multiply the joint likelihood function with each prior distribution based on the Bayesian method to obtain the joint posterior distribution;

[0015] Statistically reliable information is determined based on the joint posterior distribution.

[0016] In one embodiment, the statistical confidence information includes median lifetime, conditional failure probability, and reliability under target stress. The statistical confidence information is determined based on a joint posterior distribution, including:

[0017] Sampling is performed based on the joint posterior distribution to determine the posterior samples for shape and scale parameters;

[0018] Substitute the posterior samples into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, conditional failure probability, and reliability under target stress.

[0019] In one embodiment, a predetermined number of target integrated circuits are subjected to extreme operating condition tests, and the test results are obtained, including:

[0020] Obtain a stress test plan for the target integrated circuit, which includes the stress type and the stress loading method determined based on the application environment parameters of the target integrated circuit;

[0021] The ultimate stress test scheme is used to test a preset number of target integrated circuit samples under extreme conditions and the test results are obtained.

[0022] In one embodiment, the stress scenario includes a single stress type scenario or a multi-stress type coupled scenario, and the stress type includes thermal stress, electrical stress, damp heat stress or mechanical stress.

[0023] Secondly, this application also provides an integrated circuit limit capability determination device, comprising:

[0024] The acquisition module is used to perform extreme condition tests on a preset number of target integrated circuits and acquire the test results, including censored data related to the failure of the target integrated circuits.

[0025] The verification module is used to perform credibility verification based on censored data and determine the statistical credibility information of the target integrated circuit under extreme operating conditions. The statistical credibility information includes quantization results with credibility intervals.

[0026] The optimization module is used to obtain the initial simulation model corresponding to the target integrated circuit, and optimize the initial simulation model according to statistical confidence information to obtain the target simulation model. The error between the simulation result and the test result of the target simulation model is less than a preset error threshold.

[0027] The determination module is used to perform limit simulations under different stress scenarios based on the target simulation model, and to determine the limit capability and failure cause of the integrated circuit based on the simulation results.

[0028] In one embodiment, the optimization module is specifically used to adjust the model parameters of the initial simulation model according to statistical confidence information until the difference between the simulation results obtained based on the adjusted simulation model and the statistical confidence information is less than a preset error threshold, and the adjusted simulation model is used as the target simulation model.

[0029] In one embodiment, the censored data includes right-censored data and interval-censored data; the failure duration of the target integrated circuit satisfies a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter. The verification module is specifically used to determine the joint likelihood function based on the reliability function of the right-censored data, the interval-censored data, and the two-parameter Weibull distribution; obtain the prior distributions corresponding to the shape parameter and the scale parameter, and multiply the joint likelihood function with each prior distribution based on the Bayesian method to obtain the joint posterior distribution; and determine the statistical confidence information based on the joint posterior distribution.

[0030] In one embodiment, the statistically reliable information includes median lifetime, conditional failure probability, and reliability under target stress. The optimization module is specifically used to sample based on the joint posterior distribution to determine posterior samples of shape parameters and scale parameters; and to substitute the posterior samples into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, conditional failure probability, and reliability under target stress.

[0031] In one embodiment, the acquisition module is specifically used to acquire the ultimate stress test plan of the target integrated circuit, the ultimate stress test plan including the stress type and the stress loading method determined according to the application environment parameters of the target integrated circuit; to perform extreme working condition tests on a preset number of target integrated circuit samples according to the ultimate stress test plan, and to acquire the test results.

[0032] In one embodiment, the stress scenario includes a single stress type scenario or a multi-stress type coupled scenario, and the stress type includes thermal stress, electrical stress, damp heat stress or mechanical stress.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the first aspects above.

[0034] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the first aspects above.

[0035] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the first aspects above.

[0036] The aforementioned method, apparatus, device, and storage medium for determining the ultimate capability of integrated circuits involve conducting extreme condition tests on a predetermined number of target integrated circuits and obtaining test results, including censored data related to the failure of the target integrated circuits; verifying the reliability of the censored data to determine the statistical reliability information of the target integrated circuits under extreme conditions, wherein the statistical reliability information includes quantization results with a reliability interval; obtaining an initial simulation model corresponding to the target integrated circuits and optimizing the initial simulation model based on the statistical reliability information to obtain a target simulation model, wherein the error between the simulation results of the target simulation model and the test results is less than a predetermined error threshold; conducting extreme simulations under different stress scenarios based on the target simulation model, and determining the ultimate capability and failure cause of the integrated circuits based on the simulation results. Since existing simulation models are based on ideal parameters, the physical differences between them and real integrated circuits can be amplified under extreme conditions. This application adjusts the model parameters of the initial simulation model by testing a small sample of integrated circuits and determining statistically reliable information based on the test results of the small sample. This allows the simulation results of the optimized simulation model to be close to the actual failure behavior, meaning that the simulation model can provide accurate limit capabilities. At the same time, testing based on a small sample avoids a surge in testing costs and a significant increase in the cycle time. Furthermore, model optimization after reliability verification quantifies the uncertainty of the test results from the small sample test. By optimizing the simulation model while ensuring the reliability of the results, the simulation results of the optimized simulation model can be close to the actual failure behavior. This allows for more extreme capability simulations based on the simulation model, replacing a large number of physical tests. In the process of determining the limit capabilities of integrated circuits, this ensures low cost, short cycle time, and reliable results. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a method for determining the limiting capabilities of an integrated circuit in one embodiment;

[0039] Figure 2 This is a flowchart illustrating the steps for obtaining test results in one embodiment;

[0040] Figure 3 This is a flowchart illustrating the steps for determining statistically reliable information in one embodiment;

[0041] Figure 4This is a flowchart illustrating the step of determining statistically reliable information in another embodiment;

[0042] Figure 5 This is a detailed flowchart illustrating the method for determining the limiting capabilities of integrated circuits in another embodiment;

[0043] Figure 6 This is a structural block diagram of an integrated circuit limit capability determination device in one embodiment;

[0044] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0047] As electronic components continue to evolve towards higher density and higher performance, traditional quality and reliability testing technologies are becoming increasingly inadequate to meet the stringent reliability requirements of complex application scenarios. The reliability problems faced by electronic components are becoming more and more prominent, making it particularly important to systematically study the failure threshold of electronic components under high stress and to develop more effective reliability assurance technologies.

[0048] In existing methods, the structure of integrated circuits is modeled and the ultimate capability is assessed and determined based on the simulation model. However, there are certain differences between the simulation model and the actual device in terms of physical characteristics, manufacturing deviations, and packaging effects. Especially under extreme stress scenarios, material properties and multi-stress coupling will further amplify the deviation, making it impossible to effectively prove the correctness of the model simulation results. In other words, the reliability of the determined ultimate capability is low.

[0049] Alternatively, purely physical testing methods can be used. For example, in conventional qualification and inspection processes, a large number of samples are required to obtain test results and improve the reliability of the results. However, extreme stress testing is time-consuming, leading to a surge in testing costs and a significant extension of the cycle, which is seriously contrary to the industry's need for rapid iteration in integrated circuit R&D. If the number of samples is reduced, it is difficult to meet the basic requirements of statistical analysis, and the test results are highly random and have low statistical reliability, making it impossible to form convincing evaluation conclusions.

[0050] In view of this, this application provides a method for determining the limits of integrated circuits that can improve the reliability of the limits. The method for determining the limits of integrated circuits provided in this application can be executed by an integrated circuit limits determination device, which can be implemented by software, hardware, or a combination of both. It can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device. In the following method embodiments, the execution subject is always described using a computer device as an example. The computer device can be a server, a computer, or a terminal, etc. This application does not limit the specific type of computer device.

[0051] In one exemplary embodiment, such as Figure 1 As shown, a method for determining the limiting capabilities of an integrated circuit is provided, including steps 101 to 104. Wherein:

[0052] Step 101: Perform extreme condition tests on a preset number of target integrated circuits and obtain the test results.

[0053] The test results include censored data related to the failure of the target integrated circuit.

[0054] The target integrated circuit can be any integrated circuit whose limit capability needs to be determined.

[0055] Optionally, when performing extreme operating condition tests on the target integrated circuit, the target integrated circuit can be tested using testing systems such as a controlled environment test chamber, a voltage pull-off test system, and a vibration and shock test bench.

[0056] Understandably, when testing a target integrated circuit, the testing system can simultaneously collect failure-related data, physical quantity test data, limit threshold data, failure mode data, etc., and record process data. Then, the above data is sent to the computer equipment as test results.

[0057] In other words, the test results obtained by computer equipment can include failure-related data, physical quantity test data, limit threshold data, failure mode data, process record data, etc.

[0058] The failure-related data may include censored data, which indicates that due to various reasons, the exact data related to the failure duration could not be obtained during the test; physical quantity measurements may include physical quantities such as the thermal distribution, electric field distribution, degree of deformation, and amount of moisture intrusion of the target integrated circuit during the test; limit threshold data may include the critical values ​​of each stress failure or the number of stress loading cycles corresponding to the failure of the target integrated circuit; failure mode data may include the failure location, failure mode, and failure condition; and process record data may include test conditions, test time, and other data related to the test process.

[0059] It should be noted that when performing extreme condition tests on the target integrated circuit, different types of stress are applied to the target integrated circuit to induce failure. For example, the stress type may include at least one of the following: thermal stress, electrical stress, damp heat stress, or mechanical stress.

[0060] In other words, the stress applied during extreme condition testing can be the ultimate stress, which refers to the maximum stress a material or structure can withstand under external loads. Exceeding this ultimate stress threshold will cause damage or permanent deformation of the material or structure, directly affecting the performance, reliability, and long-term stability of integrated circuits. It is one of the core components of integrated circuit reliability assessment. Its assessment needs to consider multiple dimensions, including material properties, manufacturing processes, and packaging design, to provide crucial physical boundary references for chip design.

[0061] Electrical stress refers to electrical loads such as voltage, current, and surges that exceed the rated range of a device. Exceeding a threshold can lead to electrical failures such as port breakdown and melting of the metallized aluminum strip, and is one of the most common types of overstress in integrated circuits. Thermal stress can be caused by a mismatch in the thermal expansion coefficients of different materials in the chip. Accumulation under temperature cycling and soldering conditions can lead to reliability issues such as interface delamination and silicon cracking around the TSV. Mechanical stress can come from external mechanical loads such as assembly, vibration, and impact. Exceeding limits can cause physical structural damage such as chip breakage, solder joint detachment, and pin breakage. Humid-heat stress is stress generated by the coupling of high temperature and high humidity environments. It accelerates moisture absorption in the package and electrochemical corrosion of metal leads, ultimately leading to failures such as parameter drift and circuit leakage / short circuits.

[0062] Optionally, when conducting extreme condition tests on a preset number of target integrated circuits, since the number of target integrated circuits is relatively small, the test can be conducted based on a small sample, which can avoid a surge in testing costs and a significant extension of the testing cycle.

[0063] The preset quantity can be determined based on the parameter complexity of the target integrated circuit and small sample statistical theory. For example, the preset quantity can be positively correlated with the parameter complexity.

[0064] In this application embodiment, the number of target integrated circuits subjected to extreme condition testing can be between 3 and 30, for example.

[0065] Step 102: Verify the credibility of the censored data to determine the statistical credibility information of the target integrated circuit under extreme operating conditions.

[0066] Optionally, since the extreme condition test on the preset number of target integrated circuits is a small sample test, the test results obtained may be random and uncertain. In order to ensure the credibility of the test results, it is necessary to verify the credibility of the test results and obtain statistically reliable information.

[0067] One possible approach is to conduct credibility assessment and verification based on probabilistic methods, such as Bayesian methods or full Weibull models. This approach, which involves completing extreme condition tests with a small sample size, can ensure reliability while significantly reducing testing costs and test cycles.

[0068] Optionally, when conducting credibility verification and evaluation, the test results of a small sample can be converted into quantitative results with probability boundaries (or credibility intervals), that is, statistical credibility information includes quantitative results with credibility intervals.

[0069] The statistically reliable information may include at least one of median lifetime and failure probability.

[0070] Step 103: Obtain the initial simulation model corresponding to the target integrated circuit, and optimize the initial simulation model based on statistical reliability information to obtain the target simulation model. The error between the simulation results and the test results of the target simulation model is less than the preset error threshold.

[0071] Optionally, an initial simulation model corresponding to the target integrated circuit can be constructed using simulation tools that support multi-physics coupling simulation. The initial simulation model can be a multi-physics coupling model covering electrical, thermal, mechanical, and damp-heat stresses, constructed based on the physical structure, material properties, manufacturing process parameters, and typical application scenarios of the target integrated circuit.

[0072] For example, the initial simulation model may include the following parts:

[0073] Geometric and Material Model: Input chip layout data, packaging structure and other geometric parameters, as well as basic parameters such as thermal conductivity and resistivity of each layer of material.

[0074] Multi-stress coupling control equations: Based on the theories of electromagnetics, thermal conductivity, solid mechanics and mass transfer, coupling control equations are established, including the electric field distribution equation of electrical stress, the thermal conduction equation of thermal stress, the deformation equilibrium equation of mechanical stress, and the water vapor diffusion equation of hygrothermal stress, clarifying the coupling relationship between each stress field.

[0075] Simulation parameter initialization: Based on the stress characteristics of different application scenarios such as automobiles, aerospace, and consumer electronics, targeted simulation ranges are set. For example, thermal stress covers -55℃ to 175℃, electrical stress covers 0.5 to 2.0 times the rated voltage, mechanical stress covers 0 to 1500g impact acceleration and 20Hz to 2000Hz vibration frequency, and damp heat stress covers humidity of 30% to 95% and temperature of 40℃ to 130℃, ensuring that the simulation model is adapted to the actual needs of different industries.

[0076] Optionally, after obtaining the initial simulation model, simulation can be performed based on the initial simulation model to obtain simulation results. The simulation results can be compared with the test results, and the parameters of the initial simulation model can be optimized and adjusted when the error between the simulation results and the test results is greater than a preset error threshold.

[0077] For example, the geometric parameters and material parameters of the initial simulation model can be adjusted, as can the simulation parameters corresponding to the force; however, this application does not limit this.

[0078] Optionally, when optimizing and adjusting the parameters of the initial simulation model, it can be based on an optimization algorithm. The optimization objective can be to minimize the error between statistically reliable information and simulation results. The optimization algorithm can be, for example, a genetic algorithm or a particle swarm optimization algorithm. This application embodiment does not limit this.

[0079] Step 104: Perform limit simulations under different stress scenarios based on the target simulation model, and determine the limit capability and failure cause of the integrated circuit based on the simulation results.

[0080] Among them, limit capability can refer to the maximum stress level or the longest operating time that an integrated circuit can withstand before it is about to fail or its performance verification degrades.

[0081] Optionally, after optimizing the initial simulation model based on the test results to obtain the target simulation model, the simulation results of the target simulation model can be close to the actual failure behavior. Therefore, a large number of extreme capability simulations can be carried out based on the target simulation model to replace a large number of physical tests.

[0082] Optionally, the stress scenario may include a single stress type scenario or a multi-stress type coupled scenario.

[0083] For example, when performing single-stress limit simulation, limit simulations can be carried out for the following four types of stress, and core analysis indicators can be output: thermal stress simulation outputs heat distribution, thermal resistance and high and low temperature limit thresholds; electrical stress simulation outputs electric field distribution, carrier density and voltage / frequency limit thresholds; damp heat stress simulation outputs water vapor diffusion path, temperature conduction path and damp heat limit thresholds; and mechanical stress simulation outputs deformation distribution, fatigue life and impact or vibration limit thresholds.

[0084] When performing multi-stress coupling limit simulation, it can simulate complex stress combinations in practical applications (such as electrical + thermal, thermal + humidity, electrical + thermal + humidity, etc.), analyze the synergistic effect between various stresses, and output the comprehensive limit threshold under coupled conditions.

[0085] Optionally, the results of single-stress or multi-stress coupling simulations can be integrated to determine the ultimate load-bearing capacity of the target integrated circuit under various stress scenarios, generate an evaluation report, and clarify the specific values ​​of each limit index. At the same time, by comparing the failure phenomena in the above-mentioned extreme working condition tests with the simulation data, the failure mechanism can be traced. For example, by locating the hot spot area of ​​high-temperature failure through thermal distribution simulation, analyzing the cause of breakdown failure caused by voltage pull-off through electric field distribution simulation, and clarifying the core causes of damp heat failure through water vapor diffusion path simulation, targeted suggestions can be provided for the structural optimization and material selection of integrated circuits.

[0086] Optionally, the simulation data obtained based on the target simulation model can be organized to establish the correspondence between stress parameters and limit thresholds, or the correspondence between different levels of stress and the performance data or structural data of the target integrated circuit can be established.

[0087] The aforementioned method for determining the ultimate capability of integrated circuits involves: conducting extreme condition tests on a predetermined number of target integrated circuits and obtaining test results, including censored data related to the failure of the target integrated circuits; verifying the reliability of the censored data to determine the statistical reliability information of the target integrated circuits under extreme conditions, wherein the statistical reliability information includes quantization results with a reliability interval; obtaining an initial simulation model corresponding to the target integrated circuits and optimizing the initial simulation model based on the statistical reliability information to obtain a target simulation model, wherein the error between the simulation results of the target simulation model and the test results is less than a predetermined error threshold; conducting extreme simulations under different stress scenarios based on the target simulation model, and determining the ultimate capability and failure cause of the integrated circuit based on each simulation result. Since existing simulation models are based on ideal parameters, the physical differences between them and real integrated circuits can be amplified under extreme conditions. This application adjusts the model parameters of the initial simulation model by testing a small sample of integrated circuits and determining statistically reliable information based on the test results of the small sample. This allows the simulation results of the optimized simulation model to be close to the actual failure behavior, meaning that the simulation model can provide accurate limit capabilities. At the same time, testing based on a small sample avoids a surge in testing costs and a significant increase in the cycle time. Furthermore, model optimization after reliability verification quantifies the uncertainty of the test results from the small sample test. By optimizing the simulation model while ensuring the reliability of the results, the simulation results of the optimized simulation model can be close to the actual failure behavior. This allows for more extreme capability simulations based on the simulation model, replacing a large number of physical tests. In the process of determining the limit capabilities of integrated circuits, this ensures low cost, short cycle time, and reliable results.

[0088] In one exemplary embodiment, such as Figure 2 As shown, a predetermined number of target integrated circuits are subjected to extreme operating condition tests, and the test results are obtained, including the following steps 201 to 202. Wherein:

[0089] Step 201: Obtain the ultimate stress test plan for the target integrated circuit. The ultimate stress test plan includes the stress type and the stress loading method determined according to the application environment parameters of the target integrated circuit.

[0090] In one possible approach, the structure and application scenario information of the target integrated circuit can be input into a neural network model, which then determines the corresponding ultimate stress test scheme based on the integrated circuit structure and application scenario.

[0091] The neural network model can be pre-trained, and its training dataset includes sample input data and corresponding sample testing schemes. The sample input data can include sample structure and sample application scenarios.

[0092] In another possible approach, when obtaining the ultimate stress test plan for the target integrated circuit, a scenario profile analysis can be performed first based on the target integrated circuit's scenario input data (e.g., material physical properties, product manuals, application scenarios, or other requirements) to clarify its application scenario and reliability objectives. Then, the target integrated circuit is decomposed into structural units to determine its constituent structure; for example, the target integrated circuit can be decomposed into units such as chips, packages, and leads. Next, the stress-scenario mapping is determined to identify the dominant failure and test triggers, thus clarifying the required ultimate stress test items, which yields the ultimate stress test plan.

[0093] For example, by controlling failure and test activation, it is possible to determine, according to preset rules, which stress is most likely to cause integrated circuit failure first in the current application scenario, and which test can effectively induce failure. This allows for focusing on failure modes, obtaining effective extreme stress test schemes, avoiding invalid tests, and improving test efficiency.

[0094] Step 202: Perform extreme working condition tests on a preset number of target integrated circuit samples according to the extreme stress test plan, and obtain the test results.

[0095] It should be noted that the obtained ultimate stress test scheme may include single stress ultimate stress testing, which can focus on core ultimate stress indicators and clarify the failure threshold under a single stress. The ultimate stress test scheme may also include multi-stress coupled ultimate stress testing, which is not limited in this embodiment.

[0096] Optionally, before conducting extreme condition tests on the target integrated circuit samples, routine reliability testing and verification can be performed on the integrated circuits, such as screening, qualification, or quality conformity tests. Integrated circuits that have undergone reliability testing and verification can be referred to as white-box devices, while those that have not can be referred to as black-box devices.

[0097] The aforementioned extreme stress testing scheme for the target integrated circuit includes determining the stress type and loading method based on the application environment parameters of the target integrated circuit. The scheme involves conducting extreme condition tests on a predetermined number of target integrated circuit samples and obtaining the test results. This allows for targeted stress loading based on the application scenario and structure of the target integrated circuit, achieving a balance between the effectiveness of the test results and the testing cost.

[0098] The optimization process of the initial simulation model is illustrated below, wherein the initial simulation model is optimized based on statistical reliability information to obtain the target simulation model, including:

[0099] The model parameters of the initial simulation model are adjusted based on the statistically reliable information until the difference between the simulation results obtained based on the adjusted simulation model and the statistically reliable information is less than a preset error threshold. The adjusted simulation model is then used as the target simulation model.

[0100] The statistically reliable information may include the median lifetime. Therefore, according to the process of adjusting the initial simulation model in step 103 above, comparing the simulation results with the test results can be done by obtaining the lifetime in the simulation results, comparing the lifetime with the median lifetime in the statistically reliable information, and optimizing and adjusting the parameters of the initial simulation model when the error is greater than the preset error threshold.

[0101] Alternatively, the statistical reliability information can also include the failure probability, which is the probability that the target integrated circuit will fail after a preset number of stress cycles. The simulation failure probability can be determined based on the initial simulation model and the preset number of stress cycles, according to the results of multiple simulations. Then, the simulation failure probability is compared with the failure probability in the statistical reliability information. If the difference is greater than a preset error threshold, the parameters of the initial simulation model are optimized and adjusted.

[0102] The model parameters of the initial simulation model can be adjusted to obtain a new simulation model. Limit simulation can then be performed based on the new simulation model to obtain new simulation results. If the difference between the new simulation results and the statistically reliable information is less than a preset error threshold, the new simulation model can be used as the target simulation model. If the difference between the new simulation results and the statistically reliable information is not less than the preset error threshold, the model parameters need to be adjusted until the difference between the simulation results of the adjusted simulation model and the statistically reliable information is less than the preset error threshold.

[0103] The process of adjusting the model parameters of the initial simulation model can be referred to in step 103 above, and will not be repeated here.

[0104] The parameters of the initial simulation model are adjusted based on statistically reliable information until the difference between the simulation results obtained from the adjusted model and the statistically reliable information is less than a preset error threshold. The adjusted simulation model is then used as the target simulation model. In this way, adjusting the parameters of the initial simulation model based on statistically reliable information quantifies the uncertainty of test results from small sample tests. While ensuring the reliability of the results, the simulation model is optimized so that the simulation results closely resemble actual failure behavior. This means that accurate limit capabilities can be obtained based on the simulation model, allowing for more limit capability simulations to be performed, replacing numerous physical tests. This enables low-cost, short-cycle, and reliable determination of integrated circuit limit capabilities.

[0105] In an exemplary embodiment, the censored data includes right-censored data and interval-censored data; the failure duration of the target integrated circuit follows a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter, such as... Figure 3 As shown, the credibility verification is performed based on the censored data to determine the statistical credibility information of the target integrated circuit under extreme operating conditions, including the following steps 301 to 303, wherein:

[0106] Step 301: Determine the joint likelihood function based on the right-censored data, interval-censored data, and the reliability function of the two-parameter Weibull distribution.

[0107] The right-censored data is the test data corresponding to the first integrated circuit that did not fail under the first preset number of cycles, including the number of the first integrated circuit and the first preset number of cycles; the interval censored data is the test data corresponding to the second integrated circuit that did not fail under the second preset number of cycles but failed under the third preset number of cycles, including the number of the second integrated circuit, the second number of cycles and the third preset number of cycles.

[0108] Optionally, without considering the influence of test conditions (temperature range, transition time, etc.) on the failure model, and assuming that the failure time follows a Weibull distribution, reliability assessment is performed using Bayesian methods, a full Weibull model, and numerical calculations. The probability density function and reliability function of the Weibull distribution are as follows:

[0109]

[0110]

[0111] in, These are shape parameters. It is a scale parameter.

[0112] Optionally, the first likelihood contribution corresponding to the right-censored data can be determined based on the reliability function and the right-censored data, and the second likelihood contribution corresponding to the interval-censored data can be determined based on the reliability function and the interval-censored data. The joint likelihood function can be determined based on the product of the first likelihood contribution and the second likelihood contribution.

[0113] For example, right-censored data could be 15 integrated circuits that did not fail after 20 cycles of stress loading, while interval-censored data could be 1 integrated circuit that did not fail after 1400 cycles of stress loading but failed after stepping to 1500 cycles of stress loading. Therefore, for 15 right-censored data: Time-independent failure, likelihood contribution is One interval of data was censored. No expiration time When the time limit expires, the likelihood contribution is:

[0114]

[0115] The joint likelihood function can be expressed as:

[0116]

[0117] Step 302: Obtain the prior distributions corresponding to the shape parameters and the scale parameters, and multiply the joint likelihood function with each prior distribution based on the Bayesian method to obtain the joint posterior distribution.

[0118] Optionally, since the Weibull distribution has no conjugate prior distribution, a no-information prior is used to minimize subjective influence, where the shape parameter... Corresponding prior distribution You can select Uniform no-information prior, scale parameter Corresponding prior distribution Select Scale-invariant priors.

[0119] According to Bayes' theorem, the joint posterior distribution can be expressed as:

[0120]

[0121] by , For example, substituting the likelihood function and the prior distribution, we get:

[0122]

[0123] Step 303: Determine statistically reliable information based on the joint posterior distribution.

[0124] Optionally, after determining the joint posterior distribution, sampling can be performed based on the joint posterior distribution to obtain posterior samples of shape and scale parameters, and statistically reliable information can be determined based on the posterior samples.

[0125] The statistically reliable information includes median lifetime, probability of conditional failure, and reliability under target stress. The process of determining the statistically reliable information is described below.

[0126] like Figure 4 As shown, determining statistically reliable information based on the joint posterior distribution includes the following steps 401 to 402. Wherein:

[0127] Step 401: Sampling is performed based on the joint posterior distribution to determine the posterior samples for shape and scale parameters.

[0128] Alternatively, the Metropolis-Hastings algorithm in Markov Chain Monte Carlo (MCMC) can be used to generate posterior samples.

[0129] For example, parameter initialization: Let Choose a normal distribution. ,in , Adjustments to control acceptance rate (typical value) For the i-th iteration, candidate parameters are generated. Calculate the acceptance rate:

[0130]

[0131] Run 10,000 iterations, followed by 1,000 annealing cycles to eliminate the influence of initial values. Posterior statistic and shape parameters of the MCMC sampling results. The posterior mean is 8.1, and the 95% confidence interval is... This indicates that the failure time distribution exhibits an increasing failure rate, consistent with the fatigue failure characteristics of temperature cycling. Scale parameters The posterior mean is 1450, with a 95% confidence interval. , representing characteristic lifetime.

[0132] Step 402: Substitute the posterior samples into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, conditional failure probability, and reliability under target stress.

[0133] Alternatively, the median lifetime formula can be expressed as:

[0134]

[0135] The probability of condition failure can be expressed as:

[0136]

[0137] in, This is the third iteration number. This represents the number of the second loop.

[0138] The reliability under target stress can be expressed as:

[0139]

[0140] Where t is the number of the first loop.

[0141] For example, based on shape parameters and scale parameters The posterior sample, based on the Weibull distribution median lifetime formula The calculated posterior median lifetime is 1442 cycles, with a 95% confidence interval. The fact that 1500 failures fell within this range, and were close to the posterior mean, indicates that the failure occurred within the reasonable lifespan.

[0142] For conditional failure probability analysis, based on 1400 failures without failure, the probability of conditional failure between 1400 and 1500 failures is calculated:

[0143]

[0144] The mean value of the post-test is 0.32, with a 95% confidence interval. Given that it has not failed in 1400 tests, the probability of failure between 1400 and 1500 tests is about 32%, which is within a reasonable range.

[0145] For reliability function analysis, the reliability function is... Posterior distribution: reliability The posterior mean is 0.43, and the 95% confidence interval is... The failure probability at 1500 cycles is 0.57, indicating that the probability of failure at 1500 cycles is relatively high.

[0146] For ease of understanding, such as Figure 5 As shown, the integrated circuit limit capability determination method provided in this application embodiment will be described below with a complete embodiment.

[0147] The target integrated circuit is identified in terms of its state. Integrated circuits that have undergone reliability testing and verification are called white-box devices, and integrated circuits that have not undergone reliability testing and verification are called black-box devices. For white-box devices, the limit capability can be determined directly. For black-box devices, the limit capability can be determined after reliability testing and verification, or the limit capability can be determined directly.

[0148] When determining the ultimate capability, scenario profile analysis is performed based on input data (such as material physical characteristics, product manuals, application scenarios or other requirements) to obtain the ultimate stress test scheme for the target integrated circuit. The ultimate stress test scheme includes the stress type determined according to the application environment parameters of the target integrated circuit and the loading method of the stress type.

[0149] Specifically, scenario profile analysis can include requirement identification (i.e., determining application scenarios and reliability targets), structural unit decomposition (taking integrated circuits as an example, decomposing them into units such as chips, packages, and leads), and stress-scenario mapping to determine dominant failures and test triggers.

[0150] According to the extreme stress test scheme, a preset number of target integrated circuit samples are subjected to extreme working condition tests, and the test results are obtained. The test results include right-censored data and interval-censored data;

[0151] An initial simulation model corresponding to the target integrated circuit is obtained. The failure duration of the target integrated circuit satisfies a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter. A joint likelihood function is determined based on the right-censored data, interval-censored data, and the reliability function of the two-parameter Weibull distribution. The prior distributions corresponding to the shape parameter and the scale parameter are obtained, and the joint likelihood function is multiplied by each of the prior distributions using a Bayesian method to obtain a joint posterior distribution. Sampling is performed based on the joint posterior distribution to determine the posterior samples of the shape parameter and the scale parameter. The posterior samples are substituted into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, the conditional failure probability, and the reliability under the target stress.

[0152] The model parameters of the initial simulation model are adjusted according to the statistical confidence information until the difference between the simulation result obtained based on the adjusted simulation model and the statistical confidence information is less than the preset error threshold. The adjusted simulation model is then used as the target simulation model.

[0153] Based on the target simulation model, limit simulations are performed under different stress scenarios, and the ultimate capability and failure cause of the integrated circuit are determined based on the simulation results.

[0154] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0155] Based on the same inventive concept, this application also provides an integrated circuit limit capability determination apparatus for implementing the aforementioned integrated circuit limit capability determination method. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the integrated circuit limit capability determination apparatus provided below can be found in the limitations of the integrated circuit limit capability determination method described above, and will not be repeated here.

[0156] In one exemplary embodiment, such as Figure 6 As shown, an integrated circuit limit capability determination device 600 is provided, including: an acquisition module 601, a verification module 602, an optimization module 603, and a determination module 604, wherein:

[0157] The acquisition module 601 is used to perform extreme condition tests on a preset number of target integrated circuits and acquire the test results, including censored data related to the failure of the target integrated circuits.

[0158] The verification module 602 is used to perform credibility verification based on the censored data and determine the statistical credibility information of the target integrated circuit under extreme operating conditions, wherein the statistical credibility information includes quantization results with credibility intervals;

[0159] The optimization module 603 is used to obtain the initial simulation model corresponding to the target integrated circuit, and optimize the initial simulation model according to statistical confidence information to obtain the target simulation model. The error between the simulation result and the test result of the target simulation model is less than a preset error threshold.

[0160] The determination module 604 is used to perform limit simulations under different stress scenarios based on the target simulation model, and to determine the limit capability and failure cause of the integrated circuit based on the simulation results.

[0161] In one embodiment, the optimization module 603 is specifically used to adjust the model parameters of the initial simulation model according to the statistical confidence information until the difference between the simulation result obtained based on the adjusted simulation model and the statistical confidence information is less than a preset error threshold, and then the adjusted simulation model is used as the target simulation model.

[0162] In one embodiment, the censored data includes right-censored data and interval-censored data; the failure duration of the target integrated circuit satisfies a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter. The optimization module 603 is specifically used to determine the joint likelihood function based on the reliability function of the right-censored data, the interval-censored data, and the two-parameter Weibull distribution; obtain the prior distributions corresponding to the shape parameter and the scale parameter, and multiply the joint likelihood function with each prior distribution based on the Bayesian method to obtain the joint posterior distribution; and determine the statistical confidence information based on the joint posterior distribution.

[0163] In one embodiment, the statistically reliable information includes median lifetime, conditional failure probability, and reliability under target stress. The optimization module 603 is specifically used to sample according to the joint posterior distribution to determine the posterior samples of shape parameters and scale parameters; and to substitute the posterior samples into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, conditional failure probability, and reliability under target stress.

[0164] In one embodiment, the acquisition module 601 is specifically used to acquire the ultimate stress test plan of the target integrated circuit. The ultimate stress test plan includes the stress type and the loading method of the stress type determined according to the application environment parameters of the target integrated circuit. The ultimate stress test plan is used to perform extreme working condition tests on a preset number of target integrated circuit samples and acquire the test results.

[0165] In one embodiment, the stress scenario includes a single stress type scenario or a multi-stress type coupled scenario, and the stress type includes thermal stress, electrical stress, damp heat stress or mechanical stress.

[0166] Each module in the aforementioned integrated circuit limit capability determination device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0167] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 7As shown, the computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data related to the integrated circuit limit capability determination method. The I / O interfaces are used for information exchange between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements an integrated circuit limit capability determination method.

[0168] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0169] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the first aspects above.

[0170] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the first aspects above.

[0171] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in any of the first aspects above.

[0172] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0173] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0174] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for determining the limiting capabilities of integrated circuits, characterized in that, The method includes: A predetermined number of target integrated circuits are subjected to extreme operating condition tests, and the test results are obtained. The test results include censored data related to the failure of the target integrated circuits. Based on the censored data, a credibility verification is performed to determine the statistical credibility information of the target integrated circuit under extreme operating conditions, wherein the statistical credibility information includes quantization results with credibility intervals; An initial simulation model corresponding to the target integrated circuit is obtained, and the initial simulation model is optimized according to the statistical confidence information to obtain the target simulation model. The error between the simulation result of the target simulation model and the test result is less than a preset error threshold. Based on the target simulation model, limit simulations are performed under different stress scenarios, and the ultimate capability and failure cause of the integrated circuit are determined based on the simulation results.

2. The method according to claim 1, characterized in that, The step of optimizing the initial simulation model based on the statistical reliability information to obtain the target simulation model includes: The model parameters of the initial simulation model are adjusted according to the statistical confidence information until the difference between the simulation result obtained based on the adjusted simulation model and the statistical confidence information is less than the preset error threshold. The adjusted simulation model is then used as the target simulation model.

3. The method according to claim 1, characterized in that, The censored data includes right-censored data and interval-censored data; the failure duration of the target integrated circuit follows a two-parameter Weibull distribution, which includes a shape parameter and a scale parameter; the credibility verification based on the censored data to determine the statistical credibility information of the target integrated circuit under extreme operating conditions includes: The joint likelihood function is determined based on the right-censored data, the interval-censored data, and the reliability function of the two-parameter Weibull distribution; Obtain the prior distributions corresponding to the shape parameters and the scale parameters, and multiply the joint likelihood function with each of the prior distributions based on the Bayesian method to obtain the joint posterior distribution; The statistically reliable information is determined based on the joint posterior distribution.

4. The method according to claim 3, characterized in that, The statistically reliable information includes median lifetime, conditional failure probability, and reliability under target stress. Determining the statistically reliable information based on the joint posterior distribution includes: Sampling is performed based on the joint posterior distribution to determine the posterior samples of the shape parameter and the scale parameter; The posterior samples are substituted into the median lifetime formula, conditional failure formula, and reliability formula of the two-parameter Weibull distribution to determine the median lifetime, the conditional failure probability, and the reliability under the target stress.

5. The method according to claim 1, characterized in that, The step of performing extreme condition tests on a preset number of target integrated circuits and obtaining the test results includes: A stress test plan for a target integrated circuit is obtained, wherein the stress test plan includes the stress type determined according to the application environment parameters of the target integrated circuit and the loading method of the stress type; The extreme stress test scheme is used to test a preset number of target integrated circuit samples under extreme conditions, and the test results are obtained.

6. The method according to claim 1, characterized in that, The stress scenarios include single-stress type scenarios or multi-stress type coupled scenarios, and the stress types include thermal stress, electrical stress, damp heat stress, or mechanical stress.

7. An integrated circuit limit capability determination device, characterized in that, The device includes: The acquisition module is used to perform extreme condition tests on a preset number of target integrated circuits and acquire test results, the test results including censored data related to the failure of the target integrated circuits; The verification module is used to perform credibility verification based on the censored data and determine the statistical credibility information of the target integrated circuit under extreme operating conditions, wherein the statistical credibility information includes quantization results with credibility intervals; An optimization module is used to obtain an initial simulation model corresponding to the target integrated circuit, and optimize the initial simulation model according to the statistical confidence information to obtain a target simulation model. The error between the simulation result of the target simulation model and the test result is less than a preset error threshold. The determination module is used to perform limit simulations under different stress scenarios based on the target simulation model, and to determine the limit capability and failure cause of the integrated circuit based on the simulation results.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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