Single-core integrated full protocol stack simulation method, system, storage medium and terminal

Abstract

This application provides a single-core integrated full protocol stack simulation method, system, storage medium, and terminal. The method includes the following steps: constructing a virtual single-core processor; integrating a full protocol stack on the virtual single-core processor; constructing a coprocessor, wherein the coprocessor is equipped with shared memory; and enabling the physical layer of the full protocol stack to exchange baseband IQ data with an external network simulator via the shared memory. The single-core integrated full protocol stack simulation method, system, storage medium, and terminal of this application integrate a full protocol stack on a single-core CPU and achieve data exchange through shared memory, thereby achieving a high-fidelity simulation effect.

Description

Technical Field

[0001] This application belongs to the technical field of chip design and relates to a single-core integrated full protocol stack simulation method, system, storage medium and terminal. Background Technology

[0002] Software simulation is a core technology that uses computer programs to simulate the operating mechanism, functional logic, data interaction, and environmental response of a real system. It can reproduce the system's operating conditions without relying on physical hardware and is widely used in various technical fields such as communication terminals, electronic equipment, aerospace, the Internet of Things, industrial control, and chip research and development.

[0003] In existing technologies, software emulation of the LTE protocol stack mainly includes the following modes:

[0004] (1) Traditional pure software simulation (such as NS-3, OPNet)

[0005] Typically, these network simulators build discrete, event-driven models at the application layer to simulate network traffic and protocol logic. They usually do not run real operating system kernels or commercial-grade protocol stack code, but rather abstract and model protocol behavior. This simulation mode lacks fidelity and cannot accurately simulate real operating system scheduling, hardware interrupt handling, and the resource contention and real-time interaction behavior of different layers of the protocol stack on a single CPU core. The simulation results deviate significantly from the behavior of real terminal devices, making them unsuitable for protocol stack development and in-depth debugging that require high precision.

[0006] (2) Virtualization-based general simulation platforms (such as other applications based on QEMU)

[0007] In existing technologies, some solutions utilize virtualization platforms such as QEMU to run a complete operating system, deploying the protocol stack as a user-space application within it. Alternatively, different parts of the protocol stack (such as PHY and higher layers) are separated and run on different virtual machines or kernels. However, the former introduces additional overhead and uncertainty in operating system scheduling, failing to accurately simulate the tightly coupled characteristics of the protocol stack running directly on an embedded single-core chip; while the latter reduces the single-core load, it introduces the complexity and unpredictable latency of inter-process communication (IPC), disrupting the timing consistency of protocol stack processing and failing to accurately reflect the actual operating environment of resource-constrained terminals like Cat.1bis. Summary of the Invention

[0008] The purpose of this application is to provide a single-core integrated full protocol stack simulation method, system, storage medium and terminal, which integrates the full protocol stack on a single-core CPU and realizes data exchange through shared memory, thereby achieving a high-fidelity simulation effect.

[0009] In a first aspect, this application provides a single-core integrated full protocol stack simulation method, the method comprising the following steps: constructing a virtual single-core CPU virtual single-core processor; integrating a full protocol stack on the virtual single-core CPU virtual single-core processor; constructing a coprocessor, wherein the coprocessor is provided with shared memory; and enabling the physical layer of the full protocol stack to exchange baseband IQ data with an external network simulator via the shared memory.

[0010] In one implementation of the first aspect, the virtual single-core processor and the coprocessor are constructed based on the QEMU virtual machine.

[0011] In one implementation of the first aspect, the full protocol stack adopts the LTE Cat.1bis protocol stack, the NB-IoT full protocol stack, or the 5G NR full protocol stack.

[0012] In one implementation of the first aspect, the physical layer exchanges baseband IQ data with the shared memory via a physical layer solid-core accelerator.

[0013] In one implementation of the first aspect, a coprocessor is further constructed, which enables the baseband IQ data exchange between the physical layer and the external network simulator through the shared memory.

[0014] In one implementation of the first aspect, the coprocessor further includes the shared memory and the network protocol stack; the shared memory directly exchanges the baseband IQ data with the physical layer, and the network protocol stack encapsulates / decapsulates the baseband IQ data before exchanging data with the external network simulator.

[0015] In one implementation of the first aspect, the coprocessor is built based on a QEMU virtual machine, or the coprocessor is set on the external network simulator.

[0016] In one implementation of the first aspect, the physical layer of the full protocol stack exchanges baseband IQ data with the external network simulator via a virtual DMA controller.

[0017] Secondly, the present invention provides a single-core integrated full protocol stack simulation system, the system comprising a first construction module, an integration module, a second construction module, and a switching module;

[0018] The first construction module is used to construct a virtual single-core CPU virtual single-core processor;

[0019] The integration module is used to integrate a full protocol stack on the virtual single-core CPU virtual single-core processor;

[0020] The second building module is used to build a coprocessor, wherein the coprocessor has shared memory;

[0021] The switching module is used to enable the physical layer of the full protocol stack to exchange baseband IQ data with an external network simulator via the shared memory.

[0022] Thirdly, the present invention provides a terminal, the terminal comprising: a processor and a memory;

[0023] The memory is used to store computer programs;

[0024] The processor is used to execute the computer program stored in the memory, so that the terminal executes the above-described single-core integrated full protocol stack emulation method.

[0025] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a terminal, implements the above-described single-core integrated full protocol stack simulation method.

[0026] As described above, the single-core integrated full protocol stack simulation method, system, storage medium, and terminal described in this application have the following beneficial effects:

[0027] (1) The single-core integrated full protocol stack simulation method of this application has extremely high simulation fidelity. Since the protocol stack runs directly on the virtual single-core processor and all layers share the same computing resources, it truly reproduces the operating environment of the protocol stack inside the terminal chip. In particular, the simulation of resource competition and timing behavior of each protocol layer on a single core has achieved unprecedented accuracy.

[0028] (2) The single-core integrated full protocol stack simulation method of this application has excellent debugging and transparency. Thanks to QEMU's full system simulation capabilities, developers can use standard debugging tools such as GDB to perform instruction-level single-step tracing, memory viewing and status monitoring on the running protocol stack. The operation of the entire protocol stack is completely transparent, which greatly facilitates in-depth development and problem localization.

[0029] (3) The single-core integrated full protocol stack simulation method of this application has efficient resource utilization and real-time guarantee. By introducing a coprocessor to handle high-overhead operations such as network data encapsulation / decapsulation, the main processor resources are reserved to the protocol stack logic itself to the maximum extent. This architecture effectively reduces the latency jitter of protocol stack processing and ensures the determinism of tasks with high real-time requirements (such as MAC scheduling and HARQ).

[0030] (4) The single-core integrated full protocol stack simulation method of this application has significant cost advantages and flexibility. The entire scheme is built on open source software (QEMU, open source software simulator base station), avoiding reliance on expensive dedicated test instruments or hardware prototypes. At the same time, the protocol stack code can be flexibly modified, which is convenient for algorithm research, customized function development and forward-looking technology verification. Attached Figure Description

[0031] Figure 1 The flowchart shown is an embodiment of the single-core integrated full protocol stack simulation method of this application;

[0032] Figure 2 The diagram shown is an architectural schematic of one embodiment of the single-core integrated full protocol stack simulation method of this application.

[0033] Figure 3 The diagram shown is a structural schematic of a single-core integrated full protocol stack simulation system according to an embodiment of this application.

[0034] Figure 4 The diagram shown is a structural schematic of the electronic device of this application in one embodiment. Detailed Implementation

[0035] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0036] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0037] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0038] Before providing a further detailed description of this application, the nouns and terms used in the embodiments of this application are explained, and the nouns and terms used in the embodiments of this application shall be interpreted as follows:

[0039] QEMU: Quick Emulator, an open-source full-system emulator capable of simulating a complete computer system (including processor, memory, peripherals, etc.), allowing one operating system (guest operating system) to run on top of another operating system (external network emulator).

[0040] LTE Cat.1bis: A type of LTE terminal category (User Equipment Category) defined in the 3GPP standard, specifically referring to LTE Cat.1 terminals that support single-antenna reception, with uplink speeds of 5Mbps and downlink speeds of 10Mbps, mainly targeting low-to-medium speed IoT applications.

[0041] PHY: Physical Layer, is the lowest layer of the communication protocol stack, responsible for signal modulation and demodulation, channel coding and decoding, radio frequency processing, etc.

[0042] MAC: Medium Access Control Layer, responsible for logical channel mapping, scheduling, Hybrid Automatic Repeat Request (HARQ), etc.

[0043] RLC: Radio Link Control Layer, responsible for packet segmentation / reassembly, error correction (ARQ), etc.

[0044] PDCP: Packet Data Convergence Protocol Layer, responsible for encryption / decryption of user data, IP header compression, etc.

[0045] RRC: Radio Resource Control Layer, responsible for control plane functions such as connection management, mobility management, and system information broadcasting.

[0046] NAS: Non-Access Stratum, responsible for signaling interaction between terminals and the core network, such as authentication and session management.

[0047] PHY-HAC: Physical Layer Hardware Accelerator Core.

[0048] IQ data: In-phase and Quadrature data, is complex sampled data used in digital communication to represent the baseband form of radio frequency signals.

[0049] Coprocessor: In this application, it refers to a functional module that is independent of the main virtual processor and is specifically responsible for handling specific high-overhead tasks (such as network encapsulation and decapsulation of IQ data) to reduce the load on the main processor and improve system efficiency and real-time performance.

[0050] Shared memory: an efficient inter-process or inter-module communication mechanism that allows multiple processors or processes to access the same physical memory area, thereby enabling fast data sharing.

[0051] like Figure 1 As shown, in one embodiment, the single-core integrated full protocol stack simulation method of this application includes steps S1-S4.

[0052] Step S1: Construct a virtual single-core processor.

[0053] Specifically, this application constructs a virtual single-core processor based on the QEMU virtual machine. The QEMU virtual machine uses software to simulate a processor (such as a CPU) with only a single core, making the internal system of the virtual machine believe it is running on a single-core computer.

[0054] Step S2: Integrate a full protocol stack on the virtual single-core processor.

[0055] Specifically, the virtual single-core processor's embedded system environment integrates the full protocol stack. The full protocol stack refers to a complete set of network communication protocols and implementations covering the physical layer, data link layer, network layer, transport layer, and application layer, capable of independently completing end-to-end communication from electrical signals to application data without relying on external protocol modules.

[0056] In one embodiment, the full protocol stack adopts the LTE Cat.1bis protocol stack, the NB-IoT full protocol stack, or the 5G NR full protocol stack. For example... Figure 2As shown, the virtual single-core processor employs a virtual single-core CPU. The LTE Cat.1bis protocol stack includes the Physical layer (PHY layer), Medium Access Control layer (MAC layer), Radio Link Control layer (RLC layer), Packet Data Convergence Protocol layer (PDCP layer), Radio Resource Control layer (RRC layer), Non-Access Stratum layer (NAS layer), and Internet Protocol layer (IP layer), enabling the scheduling and execution of physical layer signal processing functions and higher-level protocol processing functions on the virtual single-core CPU. All protocol layers in the full protocol stack share the computing resources of the same virtual single-core CPU, accurately simulating the hardware constraints of a real Cat.1 terminal chip (typically a single-core or main control single-core). In addition, the protocol layers within the full protocol stack interact with each other through an efficient internal bus or function calls, avoiding the overhead of inter-process communication (IPC), making the simulation timing closer to the real device. This is especially beneficial for studying and optimizing the collaborative working characteristics between protocol layers (such as the high-intensity computing of the physical layer and the real-time scheduling of the MAC layer) under single-core resource contention.

[0057] Step S3: Construct a coprocessor, wherein the coprocessor is configured with shared memory.

[0058] Specifically, in this application, the coprocessor is a dedicated virtual processor that assists the virtual single-core processor in its operation. The coprocessor includes shared memory. This shared memory is used for subsequent baseband IQ data exchange between the physical layer of the full protocol stack and an external network simulator.

[0059] In one embodiment, the coprocessor is implemented in the following two ways:

[0060] (1) The coprocessor is built based on the QEMU virtual machine, that is, the coprocessor is implemented as a software thread in the QEMU virtual machine.

[0061] (2) The coprocessor is set on the external network simulator as an independent user-mode process, and shares memory with the full protocol stack in the QEMU virtual machine through a specific interface (such as ivshmem) provided by the QEMU virtual machine.

[0062] Step S4: The physical layer of the full protocol stack exchanges baseband IQ data with an external network simulator via the shared memory.

[0063] Specifically, this application utilizes shared memory technology to achieve baseband IQ data exchange between the physical layer of the full protocol stack and an external network simulator, ensuring the efficiency and determinism of data exchange. Specifically, the physical layer exchanges baseband IQ data with the shared memory via a physical layer solid-core accelerator.

[0064] In this configuration, the physical layer of the full protocol stack exchanges baseband IQ data with the coprocessor via the shared memory, rather than performing network protocol stack operations itself, thereby allowing the full protocol stack on the virtual single-core processor to focus on simulating full protocol stack scheduling.

[0065] like Figure 2 As shown, the coprocessor also includes a network protocol stack. The shared memory directly exchanges baseband IQ data with the physical layer, and the network protocol stack encapsulates / decapsulates the baseband IQ data before exchanging data with the external network simulator. The external network simulator is a host machine equipped with an external network simulator base station. Therefore, the coprocessor completes the encapsulation, decapsulation, and transmission of baseband IQ data based on the network, achieving decoupling between data processing and network communication. This not only ensures the real-time performance and determinism of the entire protocol stack processing but also more accurately simulates common data flow architectures in embedded systems.

[0066] In one embodiment, the physical layer of the full protocol stack can also exchange baseband IQ data with the external network simulator via a virtual direct memory access (DMA) controller. The coprocessor can be configured with the virtual DMA controller to directly read or write baseband IQ data from the memory address specified by the physical layer of the full protocol stack, thereby further reducing the data handling overhead of the virtual single-core processor.

[0067] It should be noted that although the full protocol stack in this application uses the LTE Cat.1bis protocol stack as an example, it is also applicable to the NB-IoT full protocol stack or the 5G NR full protocol stack. Therefore, the same architecture in this application is fully applicable to corresponding communication terminals that require high-fidelity simulation, such as NB-IoT terminals and even simplified versions of 5G RedCap terminals.

[0068] The scope of protection of the single-core integrated full protocol stack simulation method described in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the scope of protection of this application.

[0069] This application also provides a single-core integrated full protocol stack simulation system. The single-core integrated full protocol stack simulation system can implement the single-core integrated full protocol stack simulation method described in this application. However, the implementation device of the single-core integrated full protocol stack simulation system described in this application includes, but is not limited to, the structure of the single-core integrated full protocol stack simulation system listed in this embodiment. All structural modifications and substitutions of the prior art made based on the principles of this application are included within the protection scope of this application.

[0070] like Figure 3 As shown, in one embodiment, the single-core integrated full protocol stack simulation system of this application includes a first building module 31, an integration module 32, a second building module 33, and a switching module 34.

[0071] The first building module 31 is used to build a virtual single-core processor.

[0072] The integration module 32 is connected to the construction module 31 and is used to integrate a full protocol stack on the virtual single-core processor.

[0073] The second building module 33 is used to build a coprocessor, wherein the coprocessor is provided with shared memory.

[0074] The switching module 34 is connected to the integration module 32 and the second construction module 33, and is used to enable the physical layer of the full protocol stack to exchange baseband IQ data with an external network simulator via the shared memory.

[0075] The structure and principle of the first building module 31, the integration module 32, the second building module 33 and the switching module 34 correspond one-to-one with the steps in the above-mentioned single-core integrated full protocol stack simulation method, so they will not be described again here.

[0076] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0077] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules / units in the various embodiments of this application may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0078] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0079] This application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing a processor. The program can be stored in a computer-readable storage medium, which is a non-transitory medium, such as random access memory, read-only memory, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof. The storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., solid-state drive (SSD)).

[0080] This application also provides a terminal. The terminal includes a processor and a memory.

[0081] The memory is used to store computer programs.

[0082] The memory includes various media capable of storing program code, such as ROM, RAM, magnetic disk, USB flash drive, memory card, or optical disk.

[0083] The processor is connected to the memory and is used to execute the computer program stored in the memory, so that the terminal executes the above-described single-core integrated full protocol stack simulation method.

[0084] Preferably, the processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0085] like Figure 4 As shown, the terminal of this application is presented in the form of a general-purpose computing device. The components of the terminal may include, but are not limited to: one or more processors or processing units 41, memory 42, and bus 43 connecting different system components (including memory 42 and processing unit 41).

[0086] Bus 43 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0087] Terminals typically include various computer system-readable media. These media can be any available media that can be accessed by the terminal, including volatile and non-volatile media, and removable and non-removable media.

[0088] Memory 42 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 421 and / or cache memory 422. The terminal may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 423 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 4 Not shown; usually referred to as a "hard drive"). Although Figure 4As not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 43 via one or more data media interfaces. Memory 42 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this application.

[0089] A program / utility 424 having a set (at least one) of program modules 4241 may be stored, for example, in memory 42. Such program modules 4241 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 4241 typically perform the functions and / or methods described in the embodiments of this application.

[0090] The terminal can also communicate with one or more external devices (e.g., keyboard, pointing device, display, etc.), one or more devices that enable user interaction with the terminal, and / or any device that enables the terminal to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). This communication can be performed through input / output (I / O) interface 44. Furthermore, the terminal can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 45. Figure 4 As shown, network adapter 45 communicates with other modules of the terminal via bus 43. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the terminal, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0091] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A single-core integrated full protocol stack simulation method, characterized by, The method includes the following steps: Construct a virtual single-core processor; A full protocol stack is integrated on the virtual single-core processor; Construct a coprocessor, wherein the coprocessor has shared memory; The physical layer of the full protocol stack exchanges baseband IQ data with an external network simulator via the shared memory.

2. The single core integrated full protocol stack emulation method of claim 1, wherein, The virtual single-core processor and the coprocessor are constructed based on the QEMU virtual machine.

3. The single core integrated full protocol stack emulation method of claim 1, wherein, The full protocol stack adopts the LTE Cat.1bis protocol stack, the NB-IoT full protocol stack, or the 5G NR full protocol stack.

4. The single core integrated full protocol stack emulation method of claim 1, wherein, The physical layer exchanges baseband IQ data with the shared memory via the physical layer solid core accelerator.

5. The single core integrated full protocol stack emulation method of claim 1, wherein, The coprocessor also includes a network protocol stack; the shared memory directly exchanges the baseband IQ data with the physical layer, and the network protocol stack encapsulates / decapsulates the baseband IQ data before exchanging it with the external network simulator.

6. The single core integrated full protocol stack emulation method of claim 1, wherein, The coprocessor is set on the external network simulator.

7. The single core integrated full protocol stack emulation method of claim 1, wherein, The physical layer of the full protocol stack exchanges baseband IQ data with the external network simulator via a virtual DMA controller.

8. A single core integrated full protocol stack emulation system, characterized by, The system includes a first building module, an integration module, a second building module, and a switching module; The first building module is used to build a virtual single-core processor; The integration module is used to integrate a full protocol stack on the virtual single-core processor; The second building module is used to build a coprocessor, wherein the coprocessor has shared memory; The switching module is used to enable the physical layer of the full protocol stack to exchange baseband IQ data with an external network simulator via the shared memory.

9. A terminal, characterized by comprising: The terminal includes: a processor and a memory; The memory is used to store computer programs; The processor is used to execute the computer program stored in the memory, so that the terminal executes the single-core integrated full protocol stack simulation method according to any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the program is executed by the terminal, it implements the single-core integrated full protocol stack simulation method as described in any one of claims 1 to 7.

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