An auto-evolution method, device and storage medium for specification-to-schematic PCB design

Abstract

The present application belongs to the technical field of integrated circuits, and relates to a self-evolution method and device for a specification-to-schematic PCB design and a storage medium. The present application aims to solve the problems of low design process efficiency, insufficient verification reliability and difficulty in realizing end-to-end automation caused by the large design space, difficulty in extracting multi-modal knowledge and lack of a verifiable simulation closed-loop optimization mechanism in the existing PCB design automation. The present application includes: receiving a PCB design specification containing constraints; retrieving compatible design elements based on a PCB knowledge graph of storage chips, topologies, pins and parameter entities and associated relationships; constructing a structured intermediate representation integrating the specification and the elements; generating an initial netlist using a large language model with parameter freezing; verifying the netlist through SPICE simulation; when the verification fails, adopting a training-free group relative strategy optimization mechanism to retrieve a high-reward editing mode from an experience library to optimize the netlist and store the successful editing in the experience library; and outputting the schematic after the verification passes.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and provides a self-evolving method, apparatus, and storage medium for specification-to-schematic PCB design. Background Technology

[0002] With the rapid proliferation of artificial intelligence (AI) systems, printed circuit board (PCB) design faces challenges of higher integration density and stricter electrical constraints [6,8,11,23,33,36]. However, current board-level circuit design workflows still rely heavily on manual and sequential operations, heavily dependent on iterative simulation feedback [20,22,31]. Industry practice shows that perfecting a single BUCK / LDO design can take days to weeks

[13] , which creates a significant barrier to early feasibility assessment and limits scalability to heterogeneous board designs.

[0003] Existing methods for accelerating PCB design workflows mainly fall into two categories:

[0004] The first category is template-based methods, which utilize structured repositories, predefined topologies, and constraint solvers to produce predictable designs within well-defined domains [5,14,17,21,28]. However, these methods exhibit significant performance degradation when faced with unseen topologies, unstructured data tables, or cross-vendor combinations of controllers and passive components.

[0005] The second category comprises learning-based methods, including machine learning (ML), reinforcement learning (RL), large language models (LLMs) and their multi-agent or simulated guided variants. These methods efficiently explore large topology-parameter spaces and utilize design rules for synthesis [1,7,9,12,16,21,31,34]. However, most of these methods only accelerate isolated stages in the design flow, failing to establish a unified and verifiable specification-to-schema workflow, making true closed-loop automation an unresolved challenge.

[0006] The first challenge is the large discrete design space. The board-level specification to netlist design is inherently combinatory, with discrete decision variables involved at each stage. Even within a single family of DC-DC converters, controller options (approximately...) (type), passive configuration (approximately 1) The design space resulting from combinations of types, control strategies, package types, and cross-vendor device variants can exceed [a certain limit]. The number of possible combinations makes exhaustive exploration based on SPICE computationally unsustainable [9,10]. Existing template-based methods primarily prune candidates during topology selection, but tightly couple specific devices to a fixed template and still rely on manual verification. Learning-based methods restrict the parameter subspace of the predetermined topology, but fail to significantly reduce the global design space to a manageable size.

[0007] To address this issue, we decouple the chip from peripheral circuitry using a functional pin-to-component module library. Combining Retrieval-Enhanced Generation (RAG), constraint filtering, and LLM-SPICE collaborative pruning loops, our hierarchical framework expands the effective search space from... Reduced to the baseline case One candidate.

[0008] The second challenge is extracting knowledge from multimodal data tables. Data tables remain the authoritative source for defining control modes, pin functions, electrical limits, and reference circuits, but this information is scattered across text, tables, and graphs. In a corpus of over 3000 documents, more than 70% requires cross-contextual reasoning because key design rules are fragmented and easily overlooked. Previous work on domain-specific knowledge graphs (KGs) and retrieval-enhanced generation (RAG) [1,7,21,26,27,32] has improved structure awareness but typically assumes semi-structured data or relies on manual annotation.

[0009] To overcome these limitations, we constructed a structured PCB knowledge graph (PCB-KG) and a unified intermediate representation (IR). This IR links the contents of multimodal data tables into a consistent instance-relational form, enabling stable schematic synthesis rather than purely text-based reasoning.

[0010] The third challenge is the lack of verifiable schematic designs. Most LLM-assisted workflows focus on generating syntactically valid netlists or coarse connections, with limited integration of SPICE feedback for parameter optimization [2,18,19,21]. Existing simulation closed-loop techniques [21,28,35] incorporate SPICE analysis, but rely on formula-based or manual tuning, lacking versatility across multi-objective design constraints.

[0011] To address this gap, we introduce a self-evolutionary parameter tuning mechanism based on a training-free group optimization strategy (TF-GRPO) [4,37]. Without updating the LLM weights, our framework uses a performance metric derived from SPICE as a reward signal. High-scoring edits are distilled into a reusable experience pool, progressively improving design quality while keeping the model frozen. Throughout the process, all edits must align with predefined circuit modules and satisfy Design Rule Check (DRC) constraints, thus completing a verifiable specification-to-schematic automated loop.

[0012] As shown in Table 1 (Note: This table should be included in the actual patent), existing research such as Toposizing

[30] , Spec2topo[9] and SPICEAssistant

[21] have only partially solved the above three challenges. There is no method that can comprehensively address these challenges in a unified workflow, especially to achieve a verifiable specification to schematic system for closed-loop synthesis and verification without fine-tuning large models.

[0013] Table 1: Comparison of previous work with PCBgen in terms of challenge coverage.

[0014] Summary of the Invention

[0015] The purpose of this invention is to solve the problem of excessively large combination design space (up to approximately 10 candidate solutions) in existing printed circuit board design automation technology. 20 The problems include: large scale, difficulty in extracting knowledge from multimodal data tables (fragmented key design rules with over 70% requiring cross-context reasoning), and lack of verifiable SPICE simulation closed-loop optimization mechanisms, resulting in low efficiency in the specification-to-schematic design process (a single BUCK / LDO design can take several days to weeks), insufficient design verification reliability, and the inability to achieve end-to-end verifiable closed-loop automation without fine-tuning large models.

[0016] To achieve the above objectives, the present invention employs the following technical means:

[0017] This invention provides a self-evolving method for specification-to-schematic PCB design, comprising the following steps:

[0018] Step 1: Receive the PCB design specifications containing numerical and classification constraints;

[0019] Step 2: Retrieve design elements compatible with the specifications based on the PCB knowledge graph. The PCB knowledge graph stores chip, topology, pin and parameter entities and their relationships, including parameter association, connection relationship and compatibility relationship.

[0020] Step 3: Construct a structured intermediate representation, integrating the PCB design specifications and retrieved design elements. The structured intermediate representation includes specification data, device attributes, topology information, pin roles, functional modules, and design rules.

[0021] Step 4: Generate an initial netlist based on the structured intermediate representation using a large language model with frozen parameters. The initial netlist conforms to the basic syntax and connection rules.

[0022] Step 5: Verify whether the initial netlist meets the electrical performance and design rule constraints using a SPICE simulator;

[0023] Step 6: When the verification fails, the initial netlist is optimized by the training-free group relative policy optimization mechanism. The training-free group relative policy optimization mechanism retrieves high-reward editing methods from the experience base, applies the high-reward editing methods to the current netlist, re-verifies the modified netlist, and stores the successful editing in the experience base when the verification passes, without updating the parameters of the large language model.

[0024] Step 7: Output the final schematic diagram that has passed verification;

[0025] The method described above compresses the original design space to a verifiable scale by performing layered filtering before and after simulation, thus solving the technical problems of searching large discrete design spaces and generating verifiable schematics.

[0026] In the above scheme, step 1 includes:

[0027] Step 1.1: Collect the set of numerical constraints This includes output voltage, load current, ripple boundary, efficiency target, and transient behavior;

[0028] Step 1.2: Encoding the set of classification constraints This includes topology families, control modes, packaging types, isolation requirements, and device families;

[0029] Step 1.3: Express the PCB design specifications as follows .

[0030] In the above scheme, step 2 includes:

[0031] Step 2.1: Using constraint-based fractions Retrieve feasible chip-topology pairs to form a set:

[0032]

[0033] Step 2.2: For the set The results are deduplicated according to the {chip, topology, package} tuple to form a set of feasible design elements;

[0034] in, For the PCB design specifications, Indicates the first One candidate chip, Indicates the first Candidate topologies, To combine the hard compatibility check with the soft matching between the data table descriptors in the PCB knowledge graph, a score function is used. This is a preset threshold.

[0035] In the above scheme, step 3 includes:

[0036] Step 3.1: Normalize the contents of the multimodal data table into a structured intermediate representation:

[0037] ;

[0038] Step 3.2: Record the information source anchor points in the structured intermediate representation. This includes page, table, and chart identifiers;

[0039] Step 3.3: Separate device attributes, pin roles, functional modules, and design rules to , , and In explicit fields, deterministic pin mapping and module instantiation are implemented across heterogeneous suppliers and product lines;

[0040] in, Indicates PCB design specifications. Indicates device attributes. Represents topology information. Indicates the pin role. Represents a functional module library. This indicates that electrical rules check constraints. Indicates the anchor point of the information source.

[0041] In the above scheme, step 4 includes:

[0042] Step 4.1: Freeze the parameters of the large language model according to the conditional probability distribution. Generate initial netlist ;

[0043] Step 4.2: The generated initial netlist satisfy ,in This represents a set of netlists that are structurally valid under schematic syntax and basic connection rules.

[0044] in, For the PCB design specifications, This refers to the structured intermediate representation. For the retrieved feasible context, This refers to a subset of relevant experiences retrieved from the experience base. Indicates parameters The frozen large-scale language model strategy, whose basic connection rules include pin role constraints and module pattern constraints.

[0045] In the above scheme, step 5 includes:

[0046] Step 5.1: Compile the initial netlist into a SPICE netlist and perform a pre-simulation check, which includes syntax checking, electrical rule checking, and classification consistency verification. ;

[0047] Step 5.2: For the netlist that passes the pre-simulation check, perform transient and / or steady-state circuit analysis using the SPICE simulator to generate a set of performance metrics. ;

[0048] Step 5.3: Based on the aforementioned set of performance metrics and the numerical constraints in the PCB design specifications Calculate the feasibility function value ;

[0049] Step 5.4: Verify whether the feasibility function value satisfies the requirements. To determine whether the initial netlist meets all numerical requirements;

[0050] in, Represents transient / steady-state analysis operators. For the initial netlist, For classification consistency function and , This is the feasibility function (also known as the violation score). This refers to the set of classification constraints in the PCB design specifications. This refers to the set of numerical constraints in the PCB design specifications.

[0051] In the above scheme, step 6 includes:

[0052] Step 6.1: Before exhausting the preset SPICE simulation budget Under the condition of relevant experience subsets from the experience base Select the current netlist Matching the best editing mode ,in ;

[0053] Step 6.2: Extract the optimal editing mode. Editing actions in and the editing action Apply to the current netlist Generate the modified netlist ,in Furthermore, the editing actions ensure module consistency and design rule compatibility checks. Indicates adding, deleting, modifying, and keeping;

[0054] Step 6.3: Apply the modified netlist Re-execute circuit simulation verification to generate an updated set of performance metrics. And calculate the feasibility function value. ;

[0055] Step 6.4: If satisfied Then, the successful edits will be selectively stored in the experience base. In, and the modified netlist As an optimized netlist; if it does not satisfy and the SPICE simulation budget has not been exhausted. Then the modified netlist As the current netlist Then return to step 6.1 to continue the iteration;

[0056] in, This is the preset maximum number of SPICE simulation calls. To extract from the experience base A subset of highly rewarded editing experiences relevant to the current design, retrieved from [the database]. The netlist currently to be optimized. For the selected editing mode, For transient / steady-state analysis operators, For feasibility functions, This refers to the set of numerical constraints in the PCB design specifications.

[0057] In the above scheme, step 7 includes:

[0058] Step 7.1: Generate a valid SPICE schematic;

[0059] Step 7.2: Generate a design audit workflow. The design audit workflow fully records the design process from PCB design specifications to the final schematic, including retrieved design elements, structured intermediate representations, generated netlists, simulation verification results, and editing records during parameter tuning, and includes information source anchors.

[0060] Step 7.3: Output the valid SPICE schematic and the design audit workflow.

[0061] The present invention also provides a self-evolving device for specification-to-schematic PCB design, comprising a processor and a memory, the memory containing computer-executable instructions that, when executed by the processor, cause the device to implement the method described.

[0062] The present invention also provides a storage medium in which the method is implemented when the processor executes a program in the storage medium.

[0063] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects:

[0064] 1. This invention solves the technical problem of large-scale discrete design space search through steps 2 (retrieving design elements compatible with the specifications based on the PCB knowledge graph) and 3 (constructing a structured intermediate representation), achieving the effect of compressing the original design space to a verifiable scale. Specifically, the PCB knowledge graph stores chip, topology, pin, and parameter entities and their relationships, making design element retrieval targeted and constrained; the structured intermediate representation standardizes the content of multimodal data tables, making the expression of design knowledge more definite and unified, thereby avoiding invalid calculations in invalid design areas and significantly improving the efficiency and feasibility of the design process.

[0065] 2. This invention, through step 3 (constructing a structured intermediate representation), solves the technical problem of difficult knowledge extraction from multimodal data tables, achieving the effect of unifying and standardizing design knowledge. The structured intermediate representation clearly separates device attributes, pin roles, functional modules, and design rules into different fields and records information source anchors. This enables deterministic pin mapping and module instantiation across suppliers and product lines, making the extraction and application of design knowledge more reliable and consistent. It avoids errors and omissions caused by fragmented design rules in traditional methods, improving the accuracy and auditability of the design.

[0066] 3. This invention solves the technical problem of lacking verifiable schematic generation through steps 4 (generating an initial netlist based on the structured intermediate representation using a parameter-frozen large language model) and 5 (verifying the initial netlist using a SPICE simulator), achieving the effect of ensuring that the generated schematic conforms to basic syntax and electrical performance. The parameter-frozen large language model generates the initial netlist conditionally based on the structured intermediate representation, guaranteeing the correctness of the initial netlist in terms of syntax and connection rules. Subsequent SPICE simulation verification ensures that the netlist meets electrical performance and design rule constraints, forming a verifiable design flow. This avoids the problem of repeated manual verification and modification required in traditional methods, improving the reliability and automation of the design.

[0067] 4. This invention, through step 6 (optimizing the initial netlist using a training-free group relative policy optimization mechanism), solves the technical problem of low netlist optimization efficiency after verification failure, achieving efficient netlist optimization within a limited simulation budget. The training-free group relative policy optimization mechanism retrieves high-reward editing patterns from the experience base and applies them to the current netlist without updating large language model parameters, enabling rapid iterative optimization. Simultaneously, this mechanism accumulates successful editing experience, gradually improving design quality and avoiding the problems of extensive simulation iterations and manual intervention required in traditional methods, thus improving design quality while maintaining model stability.

[0068] 5. This invention combines PCB knowledge graph retrieval (step 2), structured intermediate representation construction (step 3), parameter-frozen large language model generation (step 4), and training-free group relative strategy optimization (step 6) to achieve a synergistic effect of hierarchical filtering and verification closed-loop, solving the problems of low efficiency and insufficient reliability in specification-to-schematic PCB design. PCB knowledge graph retrieval performs constraint-based filtering at the front end, structured intermediate representation ensures the accurate expression and transmission of design knowledge, parameter-frozen large language model guarantees the structural validity of the initial netlist, and the training-free group relative strategy optimization mechanism achieves efficient closed-loop optimization. This synergistic mechanism of hierarchical filtering and verification closed-loop enables the entire design process to achieve end-to-end verifiable specification-to-schematic automation without updating the parameters of the large language model, significantly improving the efficiency and reliability of PCB design. Attached Figure Description

[0069] Figure 1 The process of schematic design and simulation.

[0070] Figure 2 PCBgen Framework. A: Specification to schematic workflow; B: SPICE-guided constraint filtering; C: Knowledge base through PCB-KG and IR; D: Self-evolutionary optimization through TF-GRPO (where circuit diagrams, knowledge graphs, intermediate representation files, etc. are only for illustration and have no specific substantive content to express, so there is no need to focus on their clear details).

[0071] Figure 3 TF-GRPO framework. Notation: S for specification, C for candidate, r for reward, s for summary. It is to verify experience.

[0072] Figure 4: Relationship between solution rate and number of iterations (DS: DeepSeek-V3, GPT: ChatGPT-5). PCBgen is compared with LLM-based (green: LLM I / O, orange: LLM CoT, blue: SPICEAssistant

[21] ) and ML baseline (red) under the same validation budget.

[0073] Figure 5 The impact of PCBgen component ablation on model accuracy and computational cost. Detailed Implementation

[0074] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0075] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0076] This invention provides a self-evolving method for specification-to-schematic PCB design, referred to as PCBgen, which is an end-to-end automated framework that receives text specifications and generates valid SPICE schematics with fully auditable design traces. To our knowledge, PCBgen is the first verifiable specification-to-schematic system that achieves closed-loop synthesis and verification without fine-tuning large models. As summarized in Table 1, previous research only addressed one or two of the three main challenges, while PCBgen integrates all challenges in a unified workflow. The main contributions of this invention are as follows:

[0077] Space: Design space compression is achieved through knowledge graph (KG) filtering and training-free optimization. We decouple devices from topology using a functional pin-to-component module library, retrieve chip-topology pairs from the PCB-KG (PCB Knowledge Graph), and filter using electrical, package, and DRC constraints. Combined with self-evolutionary optimization, this hierarchical process will... The combined search space is reduced to approximately [value missing] under the baseline specification. A feasible and simulable candidate.

[0078] Structured Intermediate Representation (IR): A unified intermediate representation for multimodal data tables. This invention develops a structured IR that normalizes textual, tabular, and graphical evidence with explicit sources (pages, charts, and table anchors). Integrated with PCB-KG retrieval, IR improves control pattern extraction, pin mapping, and parameter grounding, ensuring consistency in rule checking and schematic conversion across heterogeneous vendors.

[0079] Simulation Loop (SimLoop): LLM–RL–SPICE Closed-Loop Optimization. PCBgen integrates an LLM-based policy model with SPICE closed-loop evaluation, where numerical metrics are aggregated into a gated hybrid reward. This reward enforces module legitimacy and DRC error-free behavior, while RL-guided tuning jointly optimizes the topology and parameters, improving semantic consistency, reducing iteration count, and increasing Pass@k on representative specifications.

[0080] Self-evolving loop: for faster, verifiable designs. In power design benchmarks, PCBgen accelerates convergence and improves design quality, reducing actual time by 55.4%, SPICE calls from 37 to 14, and Pass@5 from 41% to 74%.

[0081] 1. Problem formulaization

[0082] Board-level power management module (PMM) design is a search problem in a combined netlist space, where only a few candidates satisfy structural and electrical constraints. This represents the set of netlists that are structurally valid under schematic syntax and basic connection rules (such as pin roles and module modes). When considering controller selection, power stage configuration, feedback and compensation networks, and peripheral passive components, The base number is easy to reach – This makes exhaustive exploration impractical within a realistic SPICE budget.

[0083] 1.1 Specifications and LLM-based generation

[0084] The design specifications are expressed as follows:

[0085] (1)

[0086] in Collect numerical requirements (such as output voltage, load current, ripple boundary, efficiency target, and transient behavior). Encoding classification constraints, such as topology families, control modes, encapsulation, isolation, and device families. The design goal is to construct a netlist consistent with both parts of the specification. .

[0087] In PCBgen, LLM is used as a condition generator in the structured design space. Given specifications... And auxiliary context (data table, design rules, topology prior), LLM-induced distribution

[0088] (2)

[0089] in This represents the (frozen) parameters of the LLM. The distribution serves as... The above strategy

[0090] (3)

[0091] Select a specific netlist candidate by choosing the controller, assigning pins, and connecting the power stage and feedback module in a syntax-valid manner.

[0092] 1.2 Constraints and Objectives

[0093] Each generated candidate is evaluated using the SPICE simulator.

[0094] (4)

[0095] in Represents transient / steady-state analysis operators. Collect performance metrics derived from the waveform, such as Ripple, load response, current stress, and efficiency.

[0096] Feasibility is checked through classification and numerical constraints. Classification consistency is verified.

[0097] (5)

[0098] Enforcement ensures compatibility with the requested topology family, control mode, device class, and encapsulation constraints. Numerical performance is determined by the feasibility function.

[0099] (6)

[0100] Summarize, This indicates that all numerical requirements are met. Combining the components mentioned above, the specification-to-schematic problem of the LLM driver is formulated as follows:

[0101]

[0102] (7)

[0103] PCBgen: A self-evolving LLM agent for specification-to-schematic PCB design with parameter tuning capabilities. The core idea is that LLM provides a semantically rich generated distribution, while physical and rule-based constraints project this distribution onto the feasible region, enabling the search to efficiently converge to a netlist that is both highly probable under prior knowledge and electrically realizable.

[0104] 2. PCBgen: From specifications to schematic framework

[0105] 2.1 Overall Framework

[0106] Figure 2 The example in section A showcases PCBgen, our specification-to-schematic framework. Each step, including knowledge base building, constraint candidate generation, SPICE closed-loop evaluation, and self-evolutionary optimization, is all within a unified closed loop. Given a PCB design specification, PCBgen first normalizes it to a structured IR and performs topology selection, ranking feasible (chip, topology, package) tuples that satisfy type-level constraints. Next, during netlist generation, a frozen LLM strategy generates schematic-compatible drafts instead of manually connecting pins. These drafts are processed by a toolchain handling IR-to-SPICE compilation, rule checking, and transient simulation, producing the evaluation metrics required for feasibility criteria. Finally, the parameter tuning phase optimizes topology selection and component values ​​within a constrained SPICE budget, generating a SPICE-efficient and manufacturable schematic along with a complete audit methodology. The following subsections describe each stage of this process in detail.

[0107] 2.2 Constraint-Aware Design Space Compression

[0108] like Figure 2 As shown in Figure B, PCBgen applies layered filtering before and after simulation to actively prune the design space. In the pre-SPICE stage, the IR-level draft is compiled into a SPICE netlist and undergoes syntax checking, electrical rule checking (ERCs), and type-level gates. Candidates with invalid structures or incompatible types are eliminated without invoking SPICE; only the surviving netlists are simulated to obtain the desired results. In the post-SPICE stage, PCBgen uses violation scores. Evaluate multi-objective performance. Designs with minor positive violations were marked as resolved; designs with minor positive violations were considered fixable and passed to the TF-GRPO editor, while candidates with major violations were discarded to save SPICE budget. Feasible and fixable designs were then ranked using a hybrid score that combined [various factors]. Based on the ERC / DRC status and gate satisfaction conditions, the highest-ranked schematic will be returned.

[0109] Empirically, this process compresses the original combined controller-topology-parameter search space to approximately [size missing] per specification. A draft that can be simulated and manufactured.

[0110] 2.3 Knowledge Base: PCB-KG and IR

[0111] To perform basic generation in a verifiable context, PCBgen relies on two complementary layers (such as...). Figure 2 (As shown in C): A structured PCB-KG for fact retrieval and filtering, and a lightweight IR system for standardized handover between retrieval, generation, and inspection. The PCB-KG is built from datasheets, simulation models, and reference designs. It uses a pattern-based parser and LLM-assisted extraction for semi-automatic building, followed by lightweight manual soundness checks. The graph encodes entity types (such as chips, topologies, pins, and parameters) and typified relationships (including has-parameter, connects-to, and is-compatible-with). Each entity stores normalized attributes, allowing traversal along electrical, structural, and functional dimensions.

[0112] Given specifications PCBgen uses constraint-based scores. Retrieve feasible chip-topology pairs:

[0113] (8)

[0114] in It's a fixed threshold. (Score) Combines hardware compatibility checks and Soft matching between data table descriptors in the PCB-KG. Retrieval hyperparameters (such as top-k, ...). The values ​​remain constant during the experiment, and the results are deduplicated based on tuples (chip, topology, package). (Set) It is then integrated into IR as a foundational factual context.

[0115] All retrieved and parsed information is normalized into structured IR:

[0116] (9)

[0117] The module library decouples device selection from specific topologies, rules store ERC-related constraints, and the `src` attribute records pages, tables, and chart anchors for auditability. By separating device attributes, pin roles, modules, and rules into explicit fields, IR enables deterministic pin mapping and module instantiation across heterogeneous vendors and product lines, which is difficult to guarantee solely through free-form hints. IR thus acts as a stability contract: LLM strategies read from it to build complete drafts of modules, while the inspector writes violations back to guide subsequent optimizations.

[0118] 2.4, TF-GRPO and self-evolutionary tuning

[0119] To improve feasibility under a tight SPICE budget, PCBgen uses a training-free GRPO scheme to separate experience mining and experience replay, such as Figure 2 As shown in D. In the offline phase ( Figure 3 ), PCBgen from the freezing strategy The mid-sampled netlist candidate groups are evaluated using SPICE and based on... The rewards are mixed with the rewards for rule violations. For each group, the controller compares the rewards and proposes a modularly consistent, DRC-compatible edit on a local subgraph. The editing that enhances gating rewards is distilled into a compact text experience. Record the condition-edit-result triples with IR and PCB-KG sources. This process builds an experience base without updating any model parameters. .

[0120] During inference, as shown in Algorithm 1, PCBgen keeps the LLM parameters frozen and does not perform any gradient-based parameter updates or fine-tuning. Given specifications... It first retrieves feasible context. Then select the top K relevant experiences. and make by Generate an initial draft based on the conditions. If the SPICE evaluation satisfies all feasibility gates ( If the draft fails, it is accepted. Otherwise, PCBgen enters the self-evolutionary tuning phase: it directly replays the failed draft. High-reward edits in the process no longer invoke LLM and re-simulate the modified netlist until constraints are met or the SPICE budget is exhausted. Newly successful edits can be selectively logged. In this process, the experience base is enriched over time. This replay-only mechanism enables parameterless optimization of topology selection and component values, providing fast convergence and a significantly higher pass@k rate.

[0121] Algorithm 1: Self-evolutionary parameter tuning in PCBgen

[0122] Input: Specifications IR, Retrieval Freeze LLM strategy experience buffer SPICE budget

[0123] Output: Valid SPICE schematic

[0124] 1: Initialize SPICE call counter

[0125] 2:

[0126] 3:

[0127] 4:

[0128] 5: Evaluation of the SPICE network table

[0129] 6: if then

[0130] 7: return

[0131] 8: end if

[0132] 9: while do

[0133] 10:

[0134] 11:

[0135] 12: Re-evaluate the edited netlist

[0136] 13: if then

[0137] 14: return

[0138] 15: end if

[0139] 16: end while

[0140] 17: return Return to the final candidate after budget completion.

[0141] 3. Experiment

[0142] 3.1 Experimental Setup

[0143] Benchmarking: PCBgen in the presence of

[0144] (i) Single-stage and vendor-integrated buck / linear designs (152 cases);

[0145] (ii) Controller-based non-isolated converters with medium peripheral devices (110 cases);

[0146] (iii) Multiphase, isolated, or multi-output designs with tighter electrical and package constraints (74 cases). All methods use the same SPICE backend and have the same transient settings. ms), maximum step size ( (ns) and the budget for each case (maximum iterations) Maximum SPICE call Rollout size ).

[0147] Models and tools: PCBgen uses two inference LLMs for evaluation: ChatGPT-5 and DeepSeek-V3-reasoner, accessed through their respective Assistants APIs, both of which have function calls enabled for consistent tool coordination. Sampling parameters are adjusted based on the model: ChatGPT-5 uses temperature=0.7 and top-p=1.0, while DeepSeek-V3 uses temperature=0.5 and top-p=1.0. For fairness, both models run on the same instruction data table, API bindings, and SPICE backend—PSpice[3].

[0148] Baseline: Since only a few existing methods were originally designed for end-to-end PCB power supply design, we tailor representative circuit design methods to a board-level setting. Therefore, we compare ourselves to three representative families, all implemented on the same simulator, time budget, and document pool:

[0149] (i) ML, a lightweight ML-based predictor that encodes component type, voltage level and pin role on graph nodes and performs message passing for topology completion and parameter prediction, following [15, 24, 25];

[0150] (ii) LLM I / O, instruction-only generation without explicit tools [2, 14];

[0151] (iii) LLM CoT, the same LLM with structured chain of thought (CoT) reasoning, for topology selection and size determination [18, 29]. In addition, we adapted a simulation-guided LLM baseline inspired by the SPICE-guided assistant

[21] , which repeatedly calls SPICE but uses formula-based parameter updates.

[0152] Metrics: We use four metrics to evaluate schematic-level correctness and task-level success:

[0153] (i) Topology Adaptation (TA) — The generated converter must be electrically compliant with specifications and compatible with type-level constraints;

[0154] (ii) Netlist Syntax (NS) and ERC – The draft must be syntactically valid and satisfy pin role and electrical rule validity;

[0155] (iii) Parameter Tuning (PT) - The final netlist must meet all numerical and electrical constraints. PT=1 is granted only if each requirement is within the predefined tolerance (default 5%).

[0156] (iv) Solution rate Pass@k — Whether at least one of the top k generated candidates satisfies all thresholds. All metrics are calculated over a shared steady-state measurement window, and the same feasibility gate is applied to all methods.

[0157] 3.2 End-to-end design effectiveness across circuit complexity

[0158] Across all three circuit regimes, PCBgen delivers the highest end-to-end schematic quality, as shown in Table 2, outperforming both ChatGPT-5 and DeepSeek-V3 backends in TA, NS, ERC, PT, and Pass@5. TA and PT are key metrics for PCB power supply design. As shown in Table 2, PCBgen improves TA by 59%, which in turn translates to 69%, 67%, and 55% PT gains across the three regimes, respectively, compared to the best baseline. These gains stem from two main factors:

[0159] 1) Higher TA places the initial draft within the feasible design domain, avoiding the need to fix invalid "no-startup" topologies;

[0160] 2) Systematic NS / ERC correction preserves legitimate editing space, making parameter tuning effective rather than oscillating around structurally invalid drafts.

[0161] Leveraging the TF-GRPO experience base, PCBgen improved Pass@5 by approximately 54% within the same iteration budget. These gains stemmed from three key components:

[0162] (i) Constraint-first search: PCB-KG eliminates incompatible chip-topology pairs before generation, reducing the combination space to a SPICE-verifiable size.

[0163] (ii) Semantic Preservation IR: Pin roles, module templates, and rule anchors are used throughout retrieval and inspection to improve NS / ERC and prevent dead-end drafts. (iii) TF-GRPO Experience Loop: Policy weights are kept frozen while SPICE-shaped rewards drive consistent module editing; validated edits are distilled into the experience library to improve early solution rates and reduce wasted SPICE calls.

[0164] Figure 4 The solution rate was reported as a function of controller iteration. All methods improved with additional iterations and essentially plateaued after 5-6 steps, but PCBgen consistently started and ended at a higher level. At iteration 0, PCBgen had reached a solution rate of approximately 18%, while the best baseline was below 8%, reflecting the reliability of constraint-priority search and semantically preserved IR in generating verifiable initial drafts for SPICE. By iteration 6, PCBgen converged to a solution rate of 84%, 30 percentage points (pp) higher than SPICEAssistant

[21] (54%), although both used SPICE closure. This suggests that experience reuse and consistent module editing make each simulation call more efficient.

[0165] The baseline curves further highlight the impact of different design choices. ML and LLM I / O saturate around 10% solution rate after about 3 iterations due to the lack of design space compression and weak topology verification in their flow. LLM CoT and SPICEAssistant

[21] benefit from partial structure checks, with SPICE feedback enabling them to achieve solution rates of about 44% and 54%, respectively, for the latter. However, LLM CoT does not include SPICE feedback, while SPICEAssistant relies on formula-based parameter updates, which provides moderate gains but lacks the flexibility and generalization ability of TF-GRPO empirically driven optimization.

[0166] Table 2: End-to-end schematic fidelity and adaptability under various design challenges.

[0167]

[0168] 3.3 Comparison with human and supplier baselines

[0169] To evaluate the actual efficiency of PCBgen, we benchmarked it against experienced designers and representative vendor-assisted tools (TI Workbench

[13] and CELUS[5]) on 24 PMM cases, which are within the functional coverage of commercial tools. We evaluated two phases of the workflow: topology selection and schematic verification, and reported runtime improvements relative to human designers (1.00 × baseline), as well as Pass@1 solver rate and overall return on investment (ROI).

[0170] As summarized in Table 3, PCBgen accelerates two stages while maintaining comparable human reliability: topology selection is 3.70x faster, schematic verification is 4.74x faster, and Pass@1 rates are 0.83 and 0.75 respectively, resulting in an overall ROI of 4.39x. These results highlight the effectiveness of PCB-KG and IR in guiding topology selection and demonstrate that TF-GRPO's experience-driven optimization significantly improves Pass@1 during parameter tuning. Vendor tools also provide meaningful acceleration through curated templates. TI Workbench achieves speedups of 2.07x and 1.79x in topology selection and schematic verification, respectively, while CELUS achieves 1.56x and 1.95x, respectively. However, both require significant manual work and re-checking, which in some cases results in Pass@1 rates lower than those of human experts. Overall, PCBgen automates the entire specification-to-schematic cycle and achieves a higher ROI than manual design and vendor-assisted workflows.

[0171] Table 3: Comparison with Developer and Vendor Tools: Speed ​​Improvement and Pass@1 in 24 PMM Cases

[0172]

[0173] Table 4: Comparison of efficiency and solution rate with GPT-5 I / O baseline

[0174]

[0175] 3.4 Comparison of computational costs with the basic model

[0176] We compared the raw computational footprint of the basic inference LLM (DeepSeek-V3 / ChatGPT-5) with and without PCBgen, reporting token usage, wall clock time, SPICE calls, and Pass@5 for each case, as shown in Table 4. Compared to the ChatGPT-5 I / O baseline, DeepSeek-V3 (PCBgen) achieved up to a token reduction of 53.1%, while GPT–5–mini (PCBgen) provided the best wall clock time and iteration reduction (55.4% ↓ to 21.5 minutes; 62.2% ↓ to 14 iterations) and improved Pass@5 by +33.0 percentage points (from 41% to 74%). PCBgen reduces token and time overhead by generating KG filtering, IR-based candidates, and reusing IR fields in consecutive edits. It further reduces SPICE calls through pre-SPICE feasibility gates and consistent local edits in post-SPICE modules, while TF-GRPO enables early solutions within the same iteration budget. These results indicate that most of the efficiency and quality gains come from reconstructing the generation-simulation loop, rather than modifying the underlying LLM itself.

[0177] 3.5 Ablation Research

[0178] We ablated four key components of PCBgen: (1) PCB-KG-based pre-filtering; (2) Structured IR; (3) TF-GRPO editing stage; and (4) Module consistency constraints. All experiments used the same settings as in Section 4.1. Figure 5 The report presents the solver rate, SPICE calls per case, and token cost per case. Removing the PCB-KG primarily impacts front-end pruning: Pass@5 decreases, SPICE calls increase as simulation is wasted on incompatible chip-topology pairs. Dropping structured IR primarily reduces semantic routing: even with correct high-level topology, netlist syntax and ERC correctness decrease, leading to a significant drop in Pass@5, which explicitly defines pin roles and module contracts crucial for stable connections. Disabling TF-GRPO reduces early solver rate and SPICE efficiency: Pass@k decreases, SPICE calls increase as edits are no longer guided to high-leverage subgraphs by group relative rewards. Removing module consistency constraints directly impacts electrical legality: ERC and syntax errors surge, Pass@1 deteriorates, and more runs are rejected as illegal rather than repaired. Overall, ablation reveals a clear division of labor: PCB-KG suppresses noisy candidates, IR preserves structural semantics, TF-GRPO converts SPICE feedback into target editing, and module constraints provide hard safety protection; PCBgen can only achieve the highest solution rate under strict SPICE and token budgets when all four components are present.

[0179] 4. Conclusion

[0180] This invention proposes PCBgen, a verifiable end-to-end framework for automating specification-to-schematic PCB power supply design. By integrating PCB-KG-based retrieval, constraint-aware pruning, multimodal IR and SPICE loop closure, and training-free GRPO optimization, PCBgen expands the design space from... Compress to PCBgen provides several viable candidates while maintaining semantic and electrical correctness. On a 336-case benchmark, PCBgen improves topology adaptation by 57%, Pass@5 by 74% from 41%, and reduces token usage and wall clock time by over 50%. Compared to human designer and vendor tools, it achieves speedups of 3.70x and 4.74x respectively at comparable Pass@1, resulting in a 4.39x ROI. These results demonstrate that a self-evolving LLM agent based on structured knowledge and reinforced by SPICE feedback can significantly accelerate and enhance board-level power design.

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Claims

1. A self-evolving method for specification-to-schematic PCB design, comprising the following steps: Step 1: Receive the PCB design specifications containing numerical and classification constraints; Step 2: Retrieve design elements compatible with the specifications based on the PCB knowledge graph. The PCB knowledge graph stores chip, topology, pin and parameter entities and their relationships, including parameter association, connection relationship and compatibility relationship. Step 3: Construct a structured intermediate representation, integrating the PCB design specifications and retrieved design elements. The structured intermediate representation includes specification data, device attributes, topology information, pin roles, functional modules, and design rules. Step 4: Generate an initial netlist based on the structured intermediate representation using a large language model with frozen parameters. The initial netlist conforms to the basic syntax and connection rules. Step 5: Verify whether the initial netlist meets the electrical performance and design rule constraints using a SPICE simulator; Step 6: When the verification fails, the initial netlist is optimized by the training-free group relative policy optimization mechanism. The training-free group relative policy optimization mechanism retrieves high-reward editing methods from the experience base, applies the high-reward editing methods to the current netlist, re-verifies the modified netlist, and stores the successful editing in the experience base when the verification passes, without updating the parameters of the large language model. Step 7: Output the final schematic diagram that has passed verification.

2. The method according to claim 1, wherein step 1 comprises: Step 1.1: Collecting the set of numerical constraints including output voltage, load current, ripple boundary, efficiency target, and transient behavior; Step 1.2: Encoding the set of classification constraints including topology family, control mode, encapsulation type, isolation requirements and device family; Step 1.3: Representing the PCB design specification as .

3. The method according to claim 1, wherein step 2 comprises: Step 2.1: Using constraint-based scores Retrieving feasible chip-topology pairs, forming a set: Step 2.2: For the set The results are deduplicated according to the {chip, topology, package} tuple to form a set of feasible design elements; in, For the PCB design specifications, Indicates the first One candidate chip, Indicates the first Candidate topologies, To combine the hard compatibility check with the soft matching between the data table descriptors in the PCB knowledge graph, a score function is used. This is a preset threshold.

4. The method according to claim 1, wherein step 3 comprises: Step 3.1: Normalize the contents of the multimodal data table into a structured intermediate representation: ； Step 3.2: Record information source anchors in the structured intermediate representation including page, table and chart identification; Step 3.3: Separate device attributes, pin roles, functional modules, and design rules to , , and In explicit fields, deterministic pin mapping and module instantiation are implemented across vendors and product lines; in, Indicates PCB design specifications. Indicates device attributes. Represents topology information. Indicates the pin role. Represents a functional module library. This indicates that electrical rules check constraints. Indicates the anchor point of the information source.

5. The method of claim 1, wherein step 4 comprises: Step 4.1: Freeze the parameters of the large language model according to the conditional probability distribution. Generate initial netlist ; Step 4.2: Generating the initial netlist satisfies wherein denotes the set of netlists that are structurally valid under the schematic syntax and basic connectivity rules; wherein, is the PCB design specification, is the structured intermediate representation, is the retrieved feasible context, is the relevant experience subset retrieved from the experience base, denotes parameters frozen large language model strategy, the basic connection rules including pin role constraints and module pattern constraints.

6. The method of claim 1, wherein step 5 comprises: Step 5.1 : Compiling the initial netlist into a SPICE netlist and performing pre- simulation checks, including syntax checks, electrical rule checks, and classification consistency verification ; Step 5.2: For the netlist that passes the pre-simulation check, perform transient and / or steady-state circuit analysis using the SPICE simulator to generate a set of performance metrics. ; Step 5.3: Based on the aforementioned set of performance metrics and the numerical constraints in the PCB design specifications Calculate the feasibility function value ; Step 5.4: verifying whether the feasibility function value satisfies to determine whether the initial netlist satisfies all numerical requirements; in, Represents transient / steady-state analysis operators. For the initial netlist, For classification consistency function and , This is the feasibility function (also known as the violation score). This refers to the set of classification constraints in the PCB design specifications. This refers to the set of numerical constraints in the PCB design specifications.

7. The method of claim 1, wherein step 6 comprises: Step 6.1: Before exhausting the preset SPICE simulation budget Under the condition of relevant experience subsets from the experience base Select the current netlist Matching the best editing mode ,in ; Step 6.2: Extract the optimal editing mode. Editing actions in and the editing action Apply to the current netlist Generate the modified netlist ,in Furthermore, the editing actions ensure module consistency and design rule compatibility checks. Indicates adding, deleting, modifying, and keeping; Step 6.3: Apply the modified netlist Re-execute circuit simulation verification to generate an updated set of performance metrics. And calculate the feasibility function value. ; Step 6.4: If satisfied Then, the successful edits will be selectively stored in the experience base. In, and the modified netlist As an optimized netlist; if it does not satisfy and the SPICE simulation budget has not been exhausted. Then the modified netlist As the current netlist Then return to step 6.1 to continue the iteration; in, This is the preset maximum number of SPICE simulation calls. To extract from the experience base A subset of highly rewarded editing experiences relevant to the current design, retrieved from [the database]. The netlist currently to be optimized. For the selected editing mode, For transient / steady-state analysis operators, For feasibility functions, This refers to the set of numerical constraints in the PCB design specifications.

8. The method of claim 1, wherein step 7 comprises: Step 7.1: Generate a valid SPICE schematic; Step 7.2: Generate a design audit trail. The design audit trail fully records the design process from PCB design specifications to the final schematic, including retrieved design elements, structured intermediate representations, generated netlists, simulation verification results, and editing records during parameter tuning, and includes information source anchors. Step 7.3: Output the valid SPICE schematic and the design audit trail.

9. A self-evolving device for specification-to-schematic PCB design, comprising a processor and a memory, characterized in that, The memory contains computer-executable instructions that, when executed by a processor, cause the apparatus to perform the method as described in any one of claims 1 to 8.

10. A storage medium, characterized by When the processor executes a program in the storage medium, it implements the method as described in any one of claims 1 to 8.

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