Simulation optimization design method of electrostatic protection circuit

Abstract

This invention discloses a simulation optimization design method for electrostatic discharge (ESD) protection circuits, relating to the field of integrated circuit protection design technology. It can quantify and compensate for the asynchronous dynamic activation problem of multi-branch ESD protection circuits caused by differences in layout parasitic parameters. The method includes: acquiring the electrical parameters corresponding to each parallel discharge branch in the ESD protection circuit; obtaining the dynamic response characteristics of the ESD protection circuit under a preset fast pulse excitation through a preset circuit simulation based on the electrical parameters of each discharge branch; determining the compensation requirement index of each parallel discharge branch relative to a reference branch based on the dynamic response characteristics; calculating the required series balancing resistor value for each parallel discharge branch based on the compensation requirement index of each parallel discharge branch and a preset target synchronous discharge current value; and generating a correction instruction based on the required series balancing resistor value for each parallel discharge branch. The correction instruction is used to adjust the physical structure of the parallel discharge branches in the ESD protection circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit protection design technology, and specifically to a simulation optimization design method for electrostatic discharge (ESD) protection circuits. Background Technology

[0002] In integrated circuits using deep submicron and more advanced processes, electrostatic discharge (ESD) protection circuits are critical modules for ensuring chip reliability. They need to respond quickly and discharge large currents in extremely fast ESD events (such as charge device model CDM) on the nanosecond scale to prevent damage to internal precision circuits. To cope with such fast pulse impacts, multiple gate-grounded NMOS transistors are often connected in parallel to form a low-impedance discharge path.

[0003] However, in actual chip layout implementation, due to area and layout limitations, the metal interconnects from each parallel branch to the common pad cannot be perfectly symmetrical in length and shape. This asymmetry in physical layout results in inherent differences in the parasitic parameters contained in each branch, especially the parasitic inductance of the metal traces.

[0004] Existing design and analysis methods for multi-finger ESD protection circuits typically focus on considering static resistance parameters or using uniform ballast resistors to attempt to balance the current in each branch. These methods fail to adequately account for the significant impact of transient induced voltages generated by parasitic inductance on branch turn-on timing under extremely fast-rising CDM pulses. This results in inaccurate assessments of the circuit's dynamic performance under actual stress, and the uniformity compensation measures often worsen the circuit's clamping capability while improving uniformity, making it difficult to optimize the overall robustness of the ESD protection circuit. Summary of the Invention

[0005] To address the current technical challenge of quantifying and compensating for the asynchronous dynamic activation of multiple ESD protection circuits caused by differences in layout parasitic parameters, this invention aims to provide a simulation optimization design method for electrostatic protection circuits. The specific technical solution adopted is as follows:

[0006] In a first aspect, the present invention provides a simulation optimization design method for an electrostatic discharge (ESD) protection circuit, comprising: acquiring the electrical parameters corresponding to each parallel discharge branch in the ESD protection circuit; wherein the electrical parameters include at least the branch trace inductance and branch trace resistance characterizing the induced effect of each parallel discharge branch during transient response; acquiring the dynamic response characteristics of the ESD protection circuit under a preset fast pulse excitation through a preset circuit simulation based on the electrical parameters of each discharge branch; determining the compensation requirement index of each parallel discharge branch relative to a reference branch based on the dynamic response characteristics, and calculating the required series balancing resistance value of each parallel discharge branch according to the compensation requirement index of each parallel discharge branch and a preset target synchronous discharge current value; generating a correction instruction according to the required series balancing resistance value of each parallel discharge branch; wherein the correction instruction is used to adjust the physical structure of the parallel discharge branches in the ESD protection circuit.

[0007] Secondly, the present invention provides a simulation optimization design system for an electrostatic discharge (ESD) protection circuit, comprising: a parameter acquisition module for acquiring electrical parameters corresponding to each parallel discharge branch in the ESD protection circuit; wherein the electrical parameters include at least the branch trace inductance characterizing the induced effect of each parallel discharge branch during transient response; a simulation analysis module for acquiring the dynamic response characteristics of the ESD protection circuit under a preset fast pulse excitation through a preset circuit simulation based on the electrical parameters of each discharge branch; a compensation calculation module for determining the compensation requirement index of each parallel discharge branch relative to a reference branch based on the dynamic response characteristics, and calculating the required series balancing resistance value of each parallel discharge branch based on the compensation requirement index of each parallel discharge branch and a preset target synchronous discharge current value; and an instruction generation module for generating a correction instruction based on the required series balancing resistance value of each parallel discharge branch; wherein the correction instruction is used to adjust the physical structure of the parallel discharge branches in the ESD protection circuit.

[0008] Thirdly, the present invention provides an electronic device, comprising: a processor and a memory; wherein the memory is used to store one or more programs, the one or more programs including computer-executable instructions, and when the electronic device is running, the processor executes the computer-executable instructions stored in the memory to cause the electronic device to perform the simulation optimization design method for an electrostatic protection circuit as described in the first aspect and any possible implementation thereof.

[0009] This invention offers the following advantages: By constructing a high-fidelity simulation model that accurately reflects the spatial distribution of parasitic inductance in each parallel branch, and applying fast pulse excitation to quantify and capture the dynamic switching asynchronous characteristics caused by inductance differences, the dynamic response hysteresis is innovatively mapped into a calculable compensation requirement index. Furthermore, a non-uniform micro-ohm level balancing resistor value is designed in reverse based on a high-current reference. Finally, through engineering safety verification, this electrical compensation value is converted into directly executable layout geometry adjustment instructions, thereby achieving precise suppression of "easy-to-start branches" and preservation of "difficult-to-start branches" at the physical level. Ultimately, this ensures that the multi-finger parallel ESD protection circuit can achieve highly synchronized and uniform switching under nanosecond-level fast pulses, significantly improving the overall failure current level while strictly guaranteeing the circuit's low clamping voltage characteristics. This solves the problem of traditional methods struggling to balance improving uniformity and maintaining performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is one of the schematic flowcharts for the simulation optimization design of an electrostatic protection circuit according to an embodiment of the present invention;

[0012] Figure 2 This is a second schematic diagram of the simulation optimization design of an electrostatic protection circuit provided in one embodiment of the present invention;

[0013] Figure 3 This is one of the schematic diagrams of the architecture of a simulation optimization design system for an electrostatic protection circuit provided in an embodiment of the present invention;

[0014] Figure 4 This is a second schematic diagram of the architecture of a simulation optimization design system for an electrostatic protection circuit provided in one embodiment of the present invention. Detailed Implementation

[0015] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the specific implementation methods, structures, features, and effects of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0017] The following description, in conjunction with the accompanying drawings, details the specific scheme of the simulation optimization design method for an electrostatic protection circuit provided by this invention.

[0018] For example, such as Figure 1 The diagram shown is a flowchart illustrating a simulation optimization design method for an electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention, comprising the following steps:

[0019] S101. Obtain the electrical parameters corresponding to each parallel discharge branch in the electrostatic protection circuit. Among them, the electrical parameters include at least the branch trace inductance and branch trace resistance, which characterize the induced effect of each parallel discharge branch during the transient response.

[0020] In this embodiment of the invention, the electrical parameters mainly include parasitic parameters extracted from the physical structure of the layout, including branch trace inductance and branch trace resistance. Branch trace inductance refers to the parasitic inductance introduced by the metal interconnect connecting each parallel discharge unit (such as the drain of an NMOS transistor) to the common output node. Under the action of rapidly changing ESD current at the nanosecond level, it will generate an induced voltage, which directly affects the turn-on threshold and speed of the branch device.

[0021] Optionally, obtaining the aforementioned electrical parameters may specifically include the following steps:

[0022] (1) Perform parasitic parameter extraction operation on the physical layout of the electrostatic protection circuit to obtain the branch trace inductance and branch trace resistance of each parallel discharge branch respectively.

[0023] This step aims to quantify the unique parasitic parameters of each parallel discharge branch from the actual chip layout geometry. Specifically, the layout data of the ESD protection circuit to be analyzed (such as a GDSII format file) is first imported. To ensure the extraction tool can identify and retain the independent paths of each branch, the layout connection relationships need to be processed before extraction: in the rule file or settings of the parasitic parameter extraction tool (such as Calibre xRC or StarRC), it is explicitly configured to retain the connection node between the drain active region of each discharge branch and the common bus as an independent port; if the tool does not support automatic retention, it is necessary to manually break the connection at the metal bus point of each branch in the layout editor and assign independent port labels to each. Afterwards, a joint extraction operation of resistors and inductors is performed, and the extraction frequency is set to a high-frequency mode (e.g., 100MHz) to accurately capture the inductive effect under nanosecond-level transient currents.

[0024] After extraction, the tool will output the corresponding branch trace resistance and branch trace inductance for each parallel discharge branch identified by a unique index (k). The branch trace resistance represents the total resistance of all metal traces and vias along the current path of that branch, while the branch trace inductance represents the partial self-inductance exhibited by that specific trace shape at high frequencies. This operation yields a set of independent parasitic parameters bound to each physical branch, laying the foundation for building a high-fidelity simulation model.

[0025] Optionally, the parasitic parameter extraction tool can also be used to obtain the geometry, thickness, spacing, and dielectric properties of the metal layers in the electrostatic protection circuit.

[0026] (2) Obtain the intrinsic circuit model of each parallel discharge branch.

[0027] It should be noted that the single-branch intrinsic circuit model is a nonlinear equivalent circuit model used to describe the avalanche breakdown and conduction characteristics of a single discharge unit (such as a GGNMOS transistor) under ESD stress. It is typically represented by a voltage-controlled current source or a piecewise linear model. Its determination process is as follows:

[0028] First, transmission line pulse (VLP) tests were performed on an independent test structure manufactured using the same process as the electrostatic discharge (ESD) protection circuit to obtain nonlinear conductivity parameters. These nonlinear conductivity parameters, including trigger voltage, sustaining voltage, and on-resistance, are key parameters characterizing the IV (inductively coupled plasma) performance of the device under fast pulse conditions.

[0029] Specifically, a transmission line pulse test system is used to apply a series of current pulses with fixed rise times and pulse widths to a single GGNMOS test structure that is manufactured independently, while accurately measuring the transient voltage response across the device. This allows the plotting of its IV characteristic curve under high current, and the extraction of nonlinear conductivity parameters from the curve.

[0030] Furthermore, based on the nonlinear conductivity parameters, a single-branch intrinsic circuit model is constructed. Specifically, in circuit simulation software, a circuit element is created using a behavioral-level model or a macro-model fitted based on measured data, ensuring that its IV characteristics match the parameters extracted from the TLP test. This element represents the core conductivity characteristics of a single discharge branch.

[0031] (3) Based on the branch line inductance, branch line resistance and single branch intrinsic circuit model, construct a distributed multi-branch parallel circuit netlist.

[0032] After determining the intrinsic circuit model of a single branch, in the circuit simulation environment, an independent branch is created for each discharge branch with index k (k=1, 2, ..., N, where N is the total number of parallel branches). In this branch, the branch trace resistance and branch trace inductance extracted in step (1) are sequentially connected in series with the drain terminal of the corresponding intrinsic circuit model of the single branch. Then, one end of all N such branches (i.e., the far end of the series connection of parasitic resistance and inductance) is connected to a common excitation node (such as a pad) for simulating ESD stress input, and the other end (i.e., the source end of each intrinsic circuit model of the single branch) is connected to the reference ground node.

[0033] The circuit netlist constructed in this way is no longer an ideal parallel model with completely identical parameters for each branch, but a "distributed" network that explicitly includes the spatial distribution information of parasitic parameters of each branch caused by differences in layout traces. This netlist can reproduce with high fidelity the asynchronous competition effect of dynamic voltage establishment in each branch under fast pulses caused by differences in trace inductance in actual chips.

[0034] S102. Based on the electrical parameters of each discharge branch, obtain the dynamic response characteristics of the electrostatic protection circuit under preset fast pulse excitation through preset circuit simulation.

[0035] This step aims to reveal the spatiotemporal asynchrony of the activation behavior of parallel branches under a fast ESD pulse due to differences in parasitic parameters through transient circuit simulation. Specifically, the distributed multi-branch parallel circuit netlist constructed in S101 is imported into the simulator, and a preset fast pulse excitation source simulating a CDM event is applied to it. This excitation source typically has a sub-nanosecond rise time and a peak current of tens of amperes. By performing transient simulation, the waveforms of current and voltage changes of each branch over time can be observed and recorded, thereby obtaining the dynamic response characteristics. It should be noted that the specific procedures in the aforementioned sub-steps can be found in S201-S203 below, and will not be repeated here.

[0036] For example, in specific implementations, the aforementioned preset fast pulse excitation source is used to simulate electrostatic discharge events in a Charged Device Model (CDM) type. Its waveform is typically configured with an extremely fast rise time in the sub-nanosecond range (e.g., 0.1 ns to 1.0 ns) to fully excite the parasitic inductance effects of each branch caused by layout trace differences, thereby reproducing the dynamic competition process leading to asynchronous startup in the simulation. Simultaneously, its peak current is set to the order of tens of amperes to ensure that the circuit can enter a sufficiently high-current discharge state after being triggered from the off state, thus providing accurate test conditions for subsequent calculation of the balancing resistance based on the target discharge current value.

[0037] Therefore, this step allows for the quantitative acquisition of key dynamic response characteristics such as the dynamic turn-on timing, pin voltage at the moment of turn-on, and voltage rise rate of each branch, providing a data foundation for subsequent differential analysis and compensation.

[0038] S103. Based on the dynamic response characteristics, determine the compensation requirement index of each parallel discharge branch relative to the reference branch, and calculate the required series balance resistance value of each parallel discharge branch according to the compensation requirement index of each parallel discharge branch and the preset target synchronous discharge current value.

[0039] Specifically, the compensation requirement index for each parallel discharge branch relative to the reference branch is a scalar value that integrates the static voltage difference and dynamic response weights. This value quantifies the "gap" in triggering difficulty between this branch and the most difficult branch to activate (the reference branch). Furthermore, the calculated balancing resistance value is a small resistance value recommended to be connected in series in this branch. Its function is to compensate for the aforementioned "gap" by introducing an appropriate ohmic voltage drop, thereby causing all branches to tend to activate synchronously.

[0040] It should be noted that the aforementioned benchmark branch is the parallel discharge branch with the largest compensation requirement in the dynamic response characteristics, i.e., the branch that is most difficult to start. The preset target synchronous discharge current value is a preset large current value used to characterize the current that each branch should carry when the circuit is expected to discharge the total ESD current divided by the number of branches when all branches are ideally started synchronously. For example, it can be set to 1A to 5A. The rule for its value is: it must be greater than the holding current of a single branch device to ensure effective start-up, while not exceeding the maximum safe discharge current allowed by the process. It is usually determined based on the process design manual and TLP test data.

[0041] The purpose of this step is to convert the differences in dynamic response into physically achievable resistance compensation values. Specifically, firstly, based on the difference between the intrinsic trigger voltage and the actual voltage experienced at the moment of activation (static voltage difference) of each branch obtained from simulation, and the dynamic weight reflecting the rate of voltage rise, the compensation requirement index for each branch is calculated. Then, using the index of the branch most difficult to activate as a benchmark, the "surplus" of other branches relative to this benchmark is calculated, and this surplus is divided by the preset target synchronous discharge current, thereby initially obtaining the required balancing resistance value for each branch. It should be noted that the specific procedures for calculating the compensation requirement index and balancing resistance value in the aforementioned sub-steps can be found in S301-S305 below, and will not be repeated here.

[0042] Therefore, this step outputs a series of customized, non-uniform balancing resistor recommendations. The core idea is to "use more resistors in series for branches that are easy to open, and fewer or no resistors in series for branches that are difficult to open" in order to achieve a balance in dynamic performance.

[0043] S104. Generate a correction instruction based on the required series balancing resistor value for each parallel discharge branch. The correction instruction is used to adjust the physical structure of the parallel discharge branches in the electrostatic protection circuit.

[0044] Specifically, the correction instructions are data files or script instructions containing the balancing resistor values ​​required to be connected in series for each parallel discharge branch, and optionally, further converted layout resistor geometry adjustment amounts.

[0045] This step aims to map the calculated theoretical compensation resistance value, after verification against engineering safety boundaries, into physical design instructions that can directly guide layout modifications. Optionally, the specific execution flow of this step is as follows:

[0046] (1) Obtain the preset maximum allowable resistance value.

[0047] The preset maximum allowable resistance value is an upper limit of resistance predetermined according to process design rules or circuit system voltage tolerance. This ensures that the introduced compensation resistor does not generate excessive additional voltage drop during the high-current ESD discharge phase, thereby guaranteeing the clamping voltage performance of the protection circuit. The system can retrieve this parameter from a database storing preset maximum allowable resistance values.

[0048] For example, this value can be set from 1 ohm to 5 ohms. The rule for its selection is that it must be determined based on the range of ballast resistors allowed by the semiconductor process, the maximum additional clamping voltage increment that the protected circuit can withstand, and the target current of the ESD design. Typically, it must be ensured that the voltage drop generated by this resistor is much lower than the safety margin of the circuit under the target discharge current.

[0049] (2) For each parallel discharge branch, when the corresponding balance resistance value is greater than the preset maximum allowable resistance value, the balance resistance value is corrected to the preset maximum allowable resistance value.

[0050] Specifically, this step is an engineering safety cutoff verification. In this step, the system iterates through all the original balanced resistance values ​​calculated for each branch and compares them one by one with the preset maximum allowable resistance value. If the original resistance value of a branch does not exceed the upper limit, it is retained; if it exceeds the upper limit, the final effective resistance value of that branch is forcibly set to the upper limit value.

[0051] The mechanism corresponding to this step prevents the calculation of unreasonably large resistance values ​​under extreme layout conditions, and is a key safety measure to ensure that the optimization scheme does not degrade the core performance of the circuit.

[0052] (3) Generate correction instructions based on the corrected balance resistance value of each parallel discharge branch.

[0053] First, for each parallel discharge branch, the layout resistor geometry adjustment amount is calculated based on the corrected balancing resistance value, the resistor process parameters, and the geometric parameters of the ESD protection circuit. Specifically, the resistor process parameters and geometric parameters include the sheet resistance of the conductive material layer (such as polysilicon) used to manufacture the resistor, and the stripe width set for the ballast resistor in the layout design. Layout resistor geometry adjustment amount. The required length of the resistance bar is calculated as follows: .in, This represents the adjustment amount of the layout resistor length for the k-th parallel discharge branch. This is the corrected balance resistance value for the k-th parallel discharge branch. The preset resistor strip width, Sheet resistors are the conductive material layers (such as polycrystalline silicon) used to manufacture resistors.

[0054] Subsequently, based on the layout resistor geometry adjustment amounts corresponding to all parallel discharge branches, correction instructions are generated to adjust the physical structure of each branch. Specifically, the system outputs a list of calculated length adjustments in the order of branch index k as a structured data file (such as CSV or JSON format) or a script (such as a SKILL script) that can be directly executed by layout editing software (such as Virtuoso). This instruction explicitly specifies the exact length value of the polysilicon resistor required to be connected in series at each physical branch location, guiding designers to make non-uniform modifications to the original layout: for branches requiring compensation, draw or stretch the polysilicon pattern of the corresponding length; for branches that do not require compensation (with a balance resistance value of zero or near zero), it may indicate direct connection with a low-resistance metal.

[0055] Thus, this step completes the final conversion from the theoretical value of electrical compensation to the manufacturable physical design instructions, outputting a precise and executable layout modification scheme, ensuring that by adjusting the physical dimensions of the series resistors of each branch, a dynamic synchronization effect of "suppressing the fast and supporting the slow" is achieved on the silicon chip.

[0056] Based on the above technical solution, this invention constructs a high-fidelity simulation model that accurately reflects the spatial distribution of parasitic inductance in each parallel branch, and applies fast pulse excitation to quantify and capture the dynamic start-up asynchronous characteristics caused by inductance differences. It then innovatively maps dynamic response hysteresis into a calculable compensation requirement index, and reverse-engineers a non-uniform micro-ohm level balancing resistor value based on a high-current reference. Finally, through engineering safety verification, this electrical compensation value is converted into directly executable layout geometry adjustment instructions, thereby achieving precise suppression of "easy-to-start branches" and preservation of "difficult-to-start branches" at the physical level. Ultimately, this ensures that the multi-finger parallel ESD protection circuit can achieve highly synchronized and uniform start-up under nanosecond-level fast pulses, significantly improving the overall failure current level while strictly guaranteeing the low clamping voltage characteristics of the circuit. This solves the problem of traditional methods struggling to balance improving uniformity and maintaining performance.

[0057] For example, such as Figure 2 As shown, in another simulation optimization design method for an electrostatic discharge protection circuit provided by an embodiment of the present invention, after generating a correction instruction based on the required series balancing resistor value for each parallel discharge branch, the method further includes the following steps:

[0058] S105. Adjust the physical layout of the electrostatic protection circuit according to the correction instructions to generate an optimized layout.

[0059] This step aims to implement the correction instructions generated by S104 (i.e., the instruction set containing the adjustment of the geometric dimensions of the layout resistors of each branch) into the actual chip layout design, so as to physically realize the non-uniform resistance compensation network calculated above.

[0060] The specific operations are performed in an integrated circuit layout editing tool (such as CadenceVirtuoso). Specifically, import the original ESD protection circuit layout file (such as GDSII format), and according to the correction instructions, modify each index... The parallel discharge branch performs the corresponding physical modification: for the length adjustment amount in the instruction For the branch, on the connection path between its drain active region and the metal interconnect, draw or modify a section of polysilicon layer pattern so that its length is strictly equal to... This forms a series ballast resistor with the target resistance value; for For the branch circuits, low-resistance metal direct connections are maintained.

[0061] After all branch modifications are completed, a Design Rule Check (DRC) is performed on the new layout to ensure it meets manufacturing process requirements. Finally, it is saved as a new, independent layout data file, i.e., the optimized layout. This layout has a non-uniform resistive network embedded in its physical structure to balance the dynamic response.

[0062] S106. Perform circuit simulation on the optimized layout to determine the synchronicity of the opening of each parallel discharge branch in the optimized layout under the preset fast pulse excitation.

[0063] This step aims to verify the design's effectiveness after physical implementation, evaluating through simulation whether the optimized layout truly improves the dynamic on-time behavior of multiple branches. First, a parasitic parameter extraction operation similar to that in S101 is performed on the optimized layout. The extracted netlist will then include the newly added physical resistive elements and their parasitic effects. Next, a distributed multi-branch parallel netlist containing the new parasitic parameters is constructed.

[0064] Following this, the same preset fast pulse excitation (i.e., the same CDM pulse waveform with the same rise time, pulse width, and amplitude) as in S201 is applied to the netlist, and transient simulation is performed. The core objective of the simulation is to determine the synchronicity of the activation of each branch. To this end, it is necessary to monitor and record the optimized current waveform of each parallel discharge branch during the simulation. Synchronization is quantified here as the degree of dispersion of the triggering time of each branch.

[0065] Specifically, when the current in a certain branch reaches the preset trigger threshold for the first time... Record that moment as the trigger moment for that branch. In obtaining all Triggering time of each branch Then, the improvement in synchronicity is quantitatively evaluated by calculating its statistical dispersion. For example, the standard deviation of the trigger time can be used. As a quantitative indicator for enabling synchronization.

[0066] Therefore, by comparing the standard deviation of the triggering time obtained from the simulations before and after optimization... (or direct observation) If the value is below an acceptable threshold (e.g., 1 ps), it can be clearly determined whether the activation synchronization of the optimized layout has achieved the expected design goal, thus completing the final verification of the entire simulation optimization design process.

[0067] For example, in another simulation optimization design method for an electrostatic discharge (ESD) protection circuit provided in one embodiment of the present invention, the dynamic response characteristics of the ESD protection circuit under a preset fast pulse excitation are obtained through preset circuit simulation based on the electrical parameters of each discharge branch. Specifically, this includes the following steps:

[0068] S201. During the circuit simulation of the distributed multi-branch parallel circuit netlist containing electrical parameters, the moment corresponding to the first parallel discharge branch whose current reaches the preset trigger threshold is determined as the trigger moment of the first branch.

[0069] As can be understood, circuit simulation is the process of applying transient excitation to a distributed multi-branch parallel circuit netlist constructed by S101 and solving its electrical response. Specifically, in circuit simulation software, a current pulse source simulating a fast ESD event (such as a CDM model) is applied to the netlist as excitation. The waveform of this excitation source is typically configured as a pulse with an extremely fast rise time (e.g., 0.1 ns to 1.0 ns) to fully excite the transient effects of the parasitic inductance of each branch.

[0070] During the simulation, the system continuously monitors the branch current flowing through its intrinsic device model in each parallel discharge branch. Simultaneously, a preset current threshold is established to determine whether the device has experienced avalanche breakdown (turn-on), i.e., a preset trigger threshold. For example, A possible value is 20mA. The rule for its selection is: this threshold should be greater than the leakage current of the circuit in steady state, but much smaller than the large current in the ESD discharge state. It is typically selected at the point where the device's IV characteristic curve just exceeds the trigger voltage. The current value corresponding to the entry into the negative resistance region, depending on the process and device size, typically falls within a reasonable range of 10mA to 50mA. During the simulation, the system compares the current of each branch with... The first in the entire network table to meet the requirements ≥ The branch that meets the condition is determined to be the first to be triggered, and the time when this event occurs is recorded as the first branch trigger time. This serves as a time reference for assessing the status of other branches.

[0071] S202. At the triggering time of the first branch, record the voltage at both ends of each parallel discharge branch as the first voltage value, and obtain the intrinsic trigger voltage corresponding to each parallel discharge branch.

[0072] In this step, in the determined At that moment, the system "freezes" the simulation state and iterates through all indices. For the parallel discharge branches, the real-time voltage value across the intrinsic device model of each branch at that moment is read, and this voltage value is recorded as the first voltage value. It represents the actual voltage level established in the remaining branches at the instant the fastest branch is turned on.

[0073] Simultaneously, the inherent intrinsic trigger voltage is extracted from the intrinsic circuit model of each branch obtained from S101. This voltage is a device-level parameter representing the critical voltage required for the discharge cell to undergo avalanche breakdown from a high-resistivity state. This value is the same for parallel branches with the same process and size.

[0074] S203. Determine the voltage rise rate of each parallel discharge branch based on the voltage change of each parallel discharge branch before the triggering time of the first branch.

[0075] Furthermore, to quantify the dynamic speed of voltage establishment in each branch, this step obtains the voltage rise rate by calculating the voltage change rate. The purpose of this step is to use the voltage gradient over time as a core indicator characterizing the "inertia" or "agility" of the branch's dynamic response. Specifically, a short backtracking time window is set. (For example, take 50ps). For each branch To obtain their respective in Time and Voltage value at time and The voltage rise rate is calculated using the following formula:

[0076]

[0077] in, Indicates the first The voltage rise rate of a parallel discharge branch directly reflects how quickly the voltage of that branch builds up in the short period before the first branch is triggered. The unit is usually V / s or V / ns. Indicates the first A branch road The first voltage value at that moment. Indicates the first A branch road The voltage value at a given moment. This indicates the preset backtracking time window width, which is a small positive value much smaller than the ESD pulse rise time, such as 50ps.

[0078] The above formula calculates in The average rate of change of branch voltage (i.e., the rate of voltage rise) over the time interval. Result The larger the value, the faster the voltage builds up in that branch, and the more agile the dynamic response; conversely, the smaller the value, the slower the voltage builds up, and the more significantly affected by delay effects such as parasitic inductance. This rate is the direct input for subsequent calculations of dynamic weights.

[0079] Therefore, the voltage rise rate of each branch calculated in this step is... This constitutes the dynamic response characteristics. From the perspective of the rate of change, the dynamic response characteristics accurately characterize the transient behavior differences of each parallel discharge branch under nanosecond-level fast pulse excitation, providing crucial dynamic quantitative basis for subsequent steps to comprehensively analyze the start-up difficulty and achieve differentiated compensation.

[0080] For example, in another simulation optimization design method for electrostatic discharge circuit provided in one embodiment of the present invention, based on dynamic response characteristics, the compensation requirement index of each parallel discharge branch relative to the reference branch is determined, and the required series balancing resistor value of each parallel discharge branch is calculated according to the compensation requirement index of each parallel discharge branch and the preset target synchronous discharge current value. Specifically, the method includes the following steps:

[0081] S301. Determine the static voltage difference based on the intrinsic trigger voltage and the first voltage value corresponding to each parallel discharge branch.

[0082] The intrinsic trigger voltage is the critical voltage at which the device experiences avalanche breakdown. The first voltage value is the triggering time of the first branch of the parallel discharge branch. The first voltage value recorded.

[0083] This step aims to quantify the static difference between the voltage actually established in each parallel discharge branch and its own avalanche breakdown threshold voltage at the instant the first branch is triggered. For each parallel discharge branch with index k, the static voltage difference is the intrinsic trigger voltage minus the first voltage value, that is: .in, Indicates the first The static voltage difference of the parallel discharge branches. If the value is positive, it means that the voltage of the branch has not yet reached the trigger threshold; if it is negative, it means that voltage overshoot has occurred due to the extremely fast response. The first branch is extracted from the single-branch intrinsic circuit model. The intrinsic trigger voltage of each branch. Indicates the first The first voltage value of each branch.

[0084] Therefore, the result is This intuitively reflects how far each branch is from the trigger voltage at the initial moment of competition initiation (i.e., when the fastest branch just starts). This value provides a static benchmark for subsequent weighted compensation based on comprehensive dynamic factors.

[0085] S302. Determine the dynamic response weight of each parallel discharge branch based on the voltage rise rate of all parallel discharge branches.

[0086] The purpose of this step is to normalize and compare the voltage rise rates of each branch obtained in S203, generating a weighting coefficient to amplify the "disadvantage" of slow-responding branches in the overall evaluation, thus giving them more attention in subsequent compensation. First, from the voltage rise rates of all branches... Find the maximum value in To prevent calculation errors caused by the speed of a certain branch approaching zero, a very small positive constant is introduced. (For example Next, the dynamic response weights of each branch are determined according to the following logic. :

[0087] like ≤ If the dynamic response speeds of all branches are not significantly different, then let =1 (for all k).

[0088] Otherwise, calculate according to the following formula:

[0089]

[0090] in, Indicates the first The dynamic response weight of a parallel discharge branch is a dimensionless ratio. This represents the maximum voltage rise rate among all parallel discharge branches. Indicates the first The rate of voltage rise in each branch. This represents a preset, extremely small positive number used for numerical protection.

[0091] The above calculation process first compares the calculated maximum voltage rise rate. With the preset minimum positive number .like ≤ This indicates that the response rates of all branches are negligible, meaning they are either "equally slow" or "not started," and there is no meaningful difference in dynamic response speed between branches. In this case, all branches are uniformly assigned dynamic response weights. =1 means that in subsequent calculations, the compensation requirements of each branch will be determined solely by its static voltage difference, and dynamic factors will not have a differentiating effect.

[0092] And if Greater than This indicates that at least one branch has experienced a significant voltage build-up, and there are distinguishable differences in dynamic response between the branches. In this case, the calculation is performed according to the above formula: the maximum rate of rise... Divide by the current branch's own rate of ascent (To prevent the denominator from being zero, the actual calculation should be rounded to zero.) and The larger of the two values ​​is used to determine the dynamic response weight of the branch. The slower the response ( The smaller the branch (the smaller the value), the larger this weight value, thus amplifying it during subsequent synthesis and compensation. This weight transforms the dynamic characteristic of "slow speed" into an amplification factor that can be multiplied.

[0093] S303. Determine the compensation requirement index based on the static voltage difference and dynamic response weight corresponding to each parallel discharge branch.

[0094] The purpose of this step is to integrate the static voltage information obtained in S301 with the dynamic response information obtained in S302 into a unified, scalarized engineering evaluation index, namely, the compensation demand index. This indicator comprehensively reflects how far each branch is from the finish line and how slowly it is progressing, thus providing a complete and quantitative representation of the difficulty relative to simultaneous operation. The compensation demand indicator is calculated using the following formula:

[0095]

[0096] in, Indicates the first The larger the value of the compensation requirement index for each parallel discharge branch, the more difficult it is to achieve synchronous opening of the branch. Indicates the first The static voltage difference of each branch. Indicates the first Dynamic response weights of each branch. This represents an engineering adjustment factor, with a default value of 1.0, which can be used to fine-tune the amplification of dynamic weights under specific designs.

[0097] The above formula combines the static voltage difference with the dynamic response weight. For a voltage that is "far from the trigger threshold (...)" Large, and slow to respond ( The compensation demand index of the "large" branch road The value will be significantly amplified, thus numerically highlighting its status as the most difficult "weak link" in the system to activate. This indicator is the direct input for subsequent resistance compensation calculations.

[0098] S304. Determine the maximum compensation requirement from all the compensation requirement indicators of the parallel discharge branches.

[0099] In this step, the compensation demand indicators for all branches are obtained. Next, this step identifies the maximum value and defines it as the maximum compensation demand index. .

[0100] have The branch in question represents the most difficult to initiate and the one most in need of special attention in the entire network; it will be established as the alignment benchmark for subsequent resistor compensation designs. Other branches will introduce compensation resistors with the goal of "filling" the gap between themselves and this largest gap.

[0101] S305. Calculate the balance resistance value of each parallel discharge branch based on the maximum compensation demand index, the compensation demand index corresponding to each parallel discharge branch, and the preset target synchronous discharge current value.

[0102] This step aims to transform the differences in turn-on difficulty quantified in the previous steps into specific, physically achievable impedance compensation values. Its core is "suppressing the fast and supporting the slow": introducing appropriate series resistances into branches that respond too quickly and are easy to turn on to delay their conduction, thereby making all branches tend to be synchronized.

[0103] Among them, the preset target synchronous discharge current value This is a key parameter representing the expected current carried by each branch when the ESD protection circuit is fully activated and in a high-current discharge state. For example, A value of 1.0A is acceptable. The rule for determining its value is as follows: it needs to be determined based on the single-point device safety discharge capability (It2) of the semiconductor process and the overall protection level of the circuit. Typically, a current value greater than the holding current is chosen that ensures the device is fully turned on and in the low-resistance discharge region, generally ranging from 0.5A to 2.0A. Using a large current as the calculation basis ensures that the calculated resistance value is in the micro-ohm range, meeting the design requirements of the ballast resistor and avoiding the introduction of excessive voltage drop.

[0104] For example, the required series balancing resistor value for each branch Calculated using the following formula:

[0105]

[0106] in, Indicates the first The balancing resistor value required for each parallel discharge branch is in ohms. . This represents the maximum compensation demand indicator. Indicates the first Compensation demand indicators for each branch road. This indicates the preset target synchronous discharge current value. This indicates taking the larger value between the result calculated within the parentheses and 0.

[0107] In the above formula, the first step is to calculate the molecule. Its physical meaning is the first The "difficulty surplus" or "advantage" of each branch relative to the most difficult branch to open. For the most difficult branch to open... This value is 0. The second step is to divide this "advantage amount" by the target discharge current. This yields the theoretical resistance value required to offset this advantage (i.e., to counteract its tendency to trigger more easily through ohmic voltage drop). Finally, through... The function applies a non-negative constraint to ensure that the resistance value is not negative. For the reference branch that is most difficult to open, the calculation result is automatically 0, which means that no additional resistance is needed.

[0108] Based on the above technical solution, this embodiment of the invention quantifies the voltage state of each branch at the competition initiation point by determining the static voltage difference; then, by introducing the voltage rise rate and calculating the dynamic response weight, the nanosecond-level time response speed difference is transformed into a weight coefficient that can be mathematically calculated; furthermore, by multiplying the static voltage difference with the dynamic response weight, a comprehensive engineering scalar of compensation requirement index is synthesized. This index successfully maps "time response lag" to "calculable gap in the voltage domain," thereby clearly identifying the "shortest board" (most difficult to turn on) and "long board" (easiest to turn on) branches in the system; finally, using the maximum compensation requirement index as a unified benchmark and the target current value representing the large current discharge state as the denominator, the non-uniform balance resistance value required for each branch is calculated in reverse. Thus, a precise compensation logic of "suppressing fast and supporting slow" is realized. The final effect is to generate a set of micro-ohm-level, customized resistance values, providing direct input for subsequent layout modifications, thereby ensuring that all parallel branches tend to turn on synchronously at the circuit design level, while strictly avoiding the risk of deteriorating the core clamping performance of the circuit due to excessive compensation resistance.

[0109] For example, such as Figure 3 The diagram shown is an architectural schematic of a simulation optimization design system for an electrostatic discharge (ESD) circuit (hereinafter referred to as the optimization design system) according to an embodiment of the present invention. The optimization design system 30 includes: a parameter acquisition module 31, a simulation analysis module 32, a compensation calculation module 33, and an instruction generation module 34. The modules are described in detail below:

[0110] The parameter acquisition module 31 is used to acquire the electrical parameters corresponding to each parallel discharge branch in the electrostatic discharge protection circuit. These electrical parameters include at least the branch trace inductance and branch trace resistance, which characterize the induced effect of each parallel discharge branch during transient response. For detailed procedures, please refer to S101 above.

[0111] The simulation analysis module 32 is used to obtain the dynamic response characteristics of the electrostatic protection circuit under a preset fast pulse excitation by using preset circuit simulation based on the electrical parameters of each discharge branch. For details of the process, please refer to S102 above.

[0112] The compensation calculation module 33 is used to determine the compensation requirement index of each parallel discharge branch relative to the reference branch based on the dynamic response characteristics, and to calculate the required series balancing resistor value for each parallel discharge branch according to the compensation requirement index of each parallel discharge branch and the preset target synchronous discharge current value. For details of the process, please refer to S103 above.

[0113] The instruction generation module 34 is used to generate correction instructions based on the required series balancing resistor value for each parallel discharge branch. These correction instructions are used to adjust the physical structure of the parallel discharge branches in the electrostatic protection circuit. For details, please refer to S104 above.

[0114] For example, such as Figure 4 As shown, in another embodiment of the present invention, the simulation optimization design system for an electrostatic protection circuit also includes an optimization verification module 35.

[0115] The optimized verification module 35 is used to perform parasitic parameter extraction operations on the physical layout of the electrostatic discharge circuit to obtain the branch trace inductance and branch trace resistance of each parallel discharge branch. It is also used to obtain the intrinsic circuit model of each single branch corresponding to each parallel discharge branch, and to construct a distributed multi-branch parallel circuit netlist based on the branch trace inductance, branch trace resistance, and the single-branch intrinsic circuit model. For detailed procedures, please refer to S105-106 above.

[0116] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0117] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

Claims

1. A simulation optimization design method for an electrostatic discharge (ESD) protection circuit, characterized in that, The method includes: Obtain the electrical parameters corresponding to each parallel discharge branch in the electrostatic protection circuit; wherein, the electrical parameters include at least the branch trace inductance and branch trace resistance characterizing the induced effect of each parallel discharge branch during the transient response process; Based on the electrical parameters of each discharge branch, the dynamic response characteristics of the electrostatic protection circuit under a preset fast pulse excitation are obtained through preset circuit simulation. Based on the dynamic response characteristics, the compensation requirement index of each parallel discharge branch relative to the reference branch is determined, and the required series balance resistance value of each parallel discharge branch is calculated according to the compensation requirement index of each parallel discharge branch and the preset target synchronous discharge current value. A correction instruction is generated based on the required series balancing resistor value for each of the parallel discharge branches; wherein the correction instruction is used to adjust the physical structure of the parallel discharge branches in the electrostatic protection circuit.

2. The simulation optimization design method for electrostatic protection circuit according to claim 1, characterized in that, Based on the electrical parameters of each discharge branch, the dynamic response characteristics of the electrostatic protection circuit under a preset fast pulse excitation are obtained through preset circuit simulation, specifically including: During the circuit simulation of the distributed multi-branch parallel circuit netlist containing the electrical parameters, the moment corresponding to the first parallel discharge branch whose current reaches the preset trigger threshold is determined as the first branch trigger moment. At the triggering time of the first branch, the voltage across each of the parallel discharge branches is recorded as the first voltage value, and the intrinsic trigger voltage corresponding to each of the parallel discharge branches is obtained; The voltage rise rate of each of the parallel discharge branches is determined based on the voltage change of each of the parallel discharge branches before the triggering time of the first branch.

3. The simulation optimization design method for electrostatic protection circuit according to claim 2, characterized in that, Based on the dynamic response characteristics, the compensation requirement index for each parallel discharge branch relative to the reference branch is determined, specifically including: The static voltage difference is determined based on the intrinsic trigger voltage corresponding to each of the parallel discharge branches and the first voltage value; The dynamic response weight of each of the parallel discharge branches is determined based on the voltage rise rate of all parallel discharge branches. The compensation requirement index is determined based on the static voltage difference and dynamic response weight corresponding to each of the parallel discharge branches.

4. The method of claim 3, wherein the method further comprises: Based on the compensation requirement index and preset target synchronous discharge current value of each parallel discharge branch, the required series balancing resistor value for each parallel discharge branch is calculated, specifically including: From the compensation demand indices of all parallel discharge branches, determine the maximum compensation demand index; The balance resistance value of each parallel discharge branch is calculated based on the maximum compensation requirement index, the compensation requirement index corresponding to each parallel discharge branch, and the preset target synchronous discharge current value.

5. The method of claim 4, wherein the method further comprises: Based on the required series balancing resistor value for each of the parallel discharge branches, a correction instruction is generated, specifically including: Get the preset maximum allowable resistance value; For each of the parallel discharge branches, when the corresponding balance resistance value is greater than the preset maximum allowable resistance value, the balance resistance value is corrected to the preset maximum allowable resistance value; The correction instruction is generated based on the corrected balance resistance value of each of the parallel discharge branches.

6. The method of simulation-based design optimization of electrostatic discharge protection circuits of claim 5, wherein, The correction instruction is generated based on the corrected balance resistance value of each of the parallel discharge branches, specifically including: For each of the parallel discharge branches, the layout resistor geometry adjustment amount of the parallel discharge branch is calculated based on the corrected balance resistor value, the resistor process parameters and geometric parameters of the electrostatic protection circuit. Based on the layout resistor geometry adjustment amount corresponding to all parallel discharge branches, the correction instruction for adjusting the physical structure of each branch is generated.

7. The method of claim 1, wherein the static protection circuit is a circuit for protecting a semiconductor device from electrostatic discharge. After generating a correction instruction based on the required series balancing resistor value for each of the parallel discharge branches, the method further includes: The physical layout of the electrostatic protection circuit is adjusted according to the correction instructions to generate an optimized layout; Perform circuit simulation on the optimized layout to determine the activation synchronicity of each parallel discharge branch in the optimized layout under the preset fast pulse excitation.

8. The method of simulation-based design optimization of electrostatic protection circuits according to any of claims 1 to 7, characterized in that, Obtaining the electrical parameters corresponding to each parallel discharge branch in the electrostatic protection circuit specifically includes: Parasitic parameter extraction is performed on the physical layout of the electrostatic protection circuit to obtain the branch trace inductance and branch trace resistance of each of the parallel discharge branches. Obtain the intrinsic circuit model of each parallel discharge branch, and construct a distributed multi-branch parallel circuit netlist based on the branch trace inductance, the branch trace resistance, and the intrinsic circuit model of the single branch.

9. The method of simulation-based design optimization of electrostatic protection circuits according to claim 8, characterized in that, Obtaining the single-branch intrinsic circuit model corresponding to each of the parallel discharge branches specifically includes: A transmission line pulse test was performed on an independent test structure with the same process as the electrostatic protection circuit to obtain nonlinear conductivity parameters. Based on the nonlinear conductivity parameters, the single-branch intrinsic circuit model is constructed.

10. An electrostatic protection circuit simulation and optimization design system, comprising: The system includes: The parameter acquisition module is used to acquire the electrical parameters corresponding to each parallel discharge branch in the electrostatic protection circuit; wherein, the electrical parameters include at least the branch trace inductance and branch trace resistance characterizing the induced effect of each parallel discharge branch during the transient response. The simulation analysis module is used to obtain the dynamic response characteristics of the electrostatic protection circuit under a preset fast pulse excitation by using preset circuit simulation based on the electrical parameters of each discharge branch. The compensation calculation module is used to determine the compensation requirement index of each parallel discharge branch relative to the reference branch based on the dynamic response characteristics, and to calculate the required series balance resistance value of each parallel discharge branch according to the compensation requirement index of each parallel discharge branch and the preset target synchronous discharge current value. The instruction generation module is used to generate a correction instruction based on the required series balance resistor value for each of the parallel discharge branches; wherein the correction instruction is used to adjust the physical structure of the parallel discharge branches in the electrostatic protection circuit.

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