A data loading optimization method and device for circuit layout wiring

Abstract

The application provides a data loading optimization method and device for circuit layout and wiring, which is applied to a layout and wiring tool used for layout and wiring of a target circuit, and includes the following steps: in response to the layout and wiring tool receiving an initialization loading signal, a plurality of design input files are acquired, and modular data clustering processing is performed on the design input files to determine a plurality of data partitions corresponding to the design input files and file data corresponding to each data partition; in response to the layout and wiring tool receiving layout and wiring requirement information input by a user for the target circuit, a corresponding target data partition is determined; and the corresponding target file data is loaded in the target data partition by using a multiplexing mechanism, so that the target circuit is designed and laid out and wired based on the target file data. By using the above method, the memory occupation of the layout and wiring is reduced, and the efficiency, flexibility and debuggability of the circuit layout and wiring are improved.

Description

Technical Field

[0001] This application relates to the field of circuit layout and routing technology, and in particular to a data loading optimization method and apparatus for circuit layout and routing. Background Technology

[0002] Currently, in the circuit design process of digital chips, a single design often contains numerous subsystems and modules. Placement and routing tools load all the data of the entire design at once during initialization. This full loading method can ensure the integrity of the data required in subsequent design stages. However, the redundant data loading in this method not only affects the performance of the tool, but also increases the memory overhead.

[0003] For a specific subsystem, only a portion of the relevant data is actually needed, but the placement and routing tool loads a large amount of irrelevant information, resulting in a significant increase in memory usage and loading time. In addition, if problems occur in the back-end stage of the design (e.g., timing violations and routing congestion), the large amount of data generated by placement and routing makes it difficult to accurately locate the root cause of the problem. The lack of hierarchical boundaries makes problem tracing extremely complex, reducing the efficiency of circuit placement and routing, and consequently reducing the flexibility and debuggability of circuit placement and routing. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a data loading optimization method and apparatus for circuit placement and routing. By performing modular data clustering processing on the design input file during the initial loading of the placement and routing tool, the loaded data is stored in a structured and standardized manner to avoid the introduction of irrelevant data. When receiving the user's placement and routing requirement information, the target data partition corresponding to the placement and routing requirement information is determined, and the corresponding target file data is loaded in the target data partition using a reuse mechanism, so as to use the target file data to perform circuit placement and routing design. This reduces the memory occupation of placement and routing while improving the interoperability between modules in the placement and routing tool, and improves the efficiency, flexibility and debuggability of circuit placement and routing.

[0005] This application provides a data loading optimization method for circuit placement and routing. The method is applied to a placement and routing tool used to place and route a target circuit. The method includes: In response to the placement and routing tool receiving an initialization loading signal, it acquires multiple preset design input files, performs modular data clustering processing on the design input files, and determines multiple data partitions corresponding to the design input files and file data corresponding to each data partition; In response to the placement and routing tool receiving placement and routing requirement information input by the user for the target circuit, the target data partition corresponding to the placement and routing requirement information is determined; The corresponding target file data is loaded into the target data partition using a preset reuse mechanism, so that the target circuit can be designed based on the target file data in accordance with the layout and routing requirements.

[0006] Furthermore, the modular data clustering processing of the design input file to determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition includes: The design input file is identified to determine the top-level module in the design input file, and the modules to be decomposed and the target module are determined in the top-level module to construct a queue of modules to be decomposed composed of the modules to be decomposed. The module queue to be decomposed is traversed to determine the modules to be merged and the target module in the modules to be decomposed, so as to construct a module queue to be merged composed of the modules to be merged; The modules to be merged in the queue of modules to be merged are merged using a preset hypergraph segmentation method to obtain the target module; Construct a target clustering network table composed of the target modules, and based on the target clustering network table, determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition.

[0007] Furthermore, the step of determining the modules to be decomposed and the target module in the top-level module to construct a queue of modules to be decomposed, consisting of the modules to be decomposed, includes: The set of top-level modules corresponding to the top-level module is placed into a preset clustering table, and the first data volume corresponding to each top-level module is compared with a preset constraint threshold in the clustering table to obtain the constraint comparison result; Based on the constraint comparison results, the top-level module whose first data volume is greater than the preset constraint threshold is determined as the module to be decomposed, and the top-level module whose first data volume is less than or equal to the preset constraint threshold is determined as the target module. The modules to be decomposed are extracted from the clustering network table, and a queue of modules to be decomposed is constructed.

[0008] Furthermore, the step of traversing the queue of modules to be decomposed to determine the modules to be merged and the target module in the queue of modules to be decomposed, so as to construct a queue of modules to be merged composed of the modules to be merged, includes: Perform a first traversal of the queue of modules to be decomposed to determine the modules to be compared among the modules to be decomposed. A second traversal is performed on the queue of modules to be compared corresponding to the module to be compared, to determine the sub-modules to be compared in the module to be compared. The second data volume corresponding to the sub-module to be compared is compared with the first preset specification threshold and the second preset specification threshold respectively to obtain the specification comparison result; wherein, the first preset specification threshold is greater than the second preset specification threshold; Based on the specification comparison results, the sub-modules to be compared with the second data volume being greater than the first preset specification threshold are determined as sub-modules to be decomposed, the sub-modules to be compared with the second data volume being less than the second preset specification threshold are determined as modules to be merged, and the sub-modules to be compared with the second data volume being less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold are determined as the target modules. For the sub-module to be decomposed, the sub-module to be decomposed is placed in the queue of modules to be decomposed, so as to split the sub-module to be decomposed in the queue of modules to be decomposed until the second data volume corresponding to the split module is less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold, so as to determine the target module corresponding to the sub-module to be decomposed; For the modules to be merged, a queue of modules to be merged is constructed.

[0009] Furthermore, the step of merging the modules to be merged in the queue of modules to be merged using a preset hypergraph segmentation method to obtain the target module includes: Based on the connection relationships between the modules to be merged in the queue of modules to be merged, the superedges corresponding to the modules to be merged are determined, and based on the connection strength between the modules to be merged in the queue of modules to be merged, the weights of the superedges corresponding to the modules to be merged are determined. Using the modules to be merged as nodes of the hypergraph, a hypergraph corresponding to the modules to be merged is constructed based on the nodes, the hyperedges, and the hyperedge weights. Based on preset segmentation conditions, the hypergraph is segmented to obtain the merging result corresponding to the module to be merged, and the target module is obtained based on the merging result.

[0010] Furthermore, the step of loading the corresponding target file data into the target data partition using a preset reuse mechanism includes: Determine whether serialized file data exists in the target data partition; If the serialized file data exists in the target data partition, the file data is deserialized to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0011] Furthermore, the step of loading the corresponding target file data into the target data partition using a preset reuse mechanism also includes: If the serialized file data is not stored in the target data partition, the file data is serialized and stored to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0012] This application embodiment also provides a circuit layout and routing data loading optimization device, the data loading optimization device comprising: The data clustering processing module is used to respond to the placement and routing tool receiving the initialization loading signal, acquire multiple preset design input files, perform modular data clustering processing on the design input files, and determine multiple data partitions corresponding to the design input files and file data corresponding to each data partition; The data partition determination module is used to determine the target data partition corresponding to the layout and routing requirement information received by the layout and routing tool from the user for the target circuit. The data loading module is used to load the corresponding target file data in the target data partition using a preset reuse mechanism, so as to perform the layout and routing design work corresponding to the layout and routing requirements information of the target circuit based on the target file data.

[0013] Furthermore, when the data clustering processing module performs modular data clustering processing on the design input file to determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition, the data clustering processing module is used to: The design input file is identified to determine the top-level module in the design input file, and the modules to be decomposed and the target module are determined in the top-level module to construct a queue of modules to be decomposed composed of the modules to be decomposed. The module queue to be decomposed is traversed to determine the modules to be merged and the target module in the modules to be decomposed, so as to construct a module queue to be merged composed of the modules to be merged; The modules to be merged in the queue of modules to be merged are merged using a preset hypergraph segmentation method to obtain the target module; Construct a target clustering network table composed of the target modules, and based on the target clustering network table, determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition.

[0014] Furthermore, when the data clustering processing module determines the modules to be decomposed and the target modules in the top-level module to construct a queue of modules to be decomposed, the data clustering processing module is used to: The set of top-level modules corresponding to the top-level module is placed into a preset clustering table, and the first data volume corresponding to each top-level module is compared with a preset constraint threshold in the clustering table to obtain the constraint comparison result; Based on the constraint comparison results, the top-level module whose first data volume is greater than the preset constraint threshold is determined as the module to be decomposed, and the top-level module whose first data volume is less than or equal to the preset constraint threshold is determined as the target module. The modules to be decomposed are extracted from the clustering network table, and a queue of modules to be decomposed is constructed.

[0015] Furthermore, when the data clustering processing module performs module traversal on the queue of modules to be decomposed, determines the modules to be merged and the target module in the queue of modules to be decomposed, in order to construct a queue of modules to be merged composed of the modules to be merged, the data clustering processing module is used to: Perform a first traversal of the queue of modules to be decomposed to determine the modules to be compared among the modules to be decomposed. A second traversal is performed on the queue of modules to be compared corresponding to the module to be compared, to determine the sub-modules to be compared in the module to be compared. The second data volume corresponding to the sub-module to be compared is compared with the first preset specification threshold and the second preset specification threshold respectively to obtain the specification comparison result; wherein, the first preset specification threshold is greater than the second preset specification threshold; Based on the specification comparison results, the sub-modules to be compared with the second data volume being greater than the first preset specification threshold are determined as sub-modules to be decomposed, the sub-modules to be compared with the second data volume being less than the second preset specification threshold are determined as modules to be merged, and the sub-modules to be compared with the second data volume being less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold are determined as the target modules. For the sub-module to be decomposed, the sub-module to be decomposed is placed in the queue of modules to be decomposed, so as to split the sub-module to be decomposed in the queue of modules to be decomposed until the second data volume corresponding to the split module is less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold, so as to determine the target module corresponding to the sub-module to be decomposed; For the modules to be merged, a queue of modules to be merged is constructed.

[0016] Furthermore, when the data clustering processing module merges the modules to be merged in the queue of modules to be merged using a preset hypergraph segmentation method to obtain the target module, the data clustering processing module is used to: Based on the connection relationships between the modules to be merged in the queue of modules to be merged, the superedges corresponding to the modules to be merged are determined, and based on the connection strength between the modules to be merged in the queue of modules to be merged, the weights of the superedges corresponding to the modules to be merged are determined. Using the modules to be merged as nodes of the hypergraph, a hypergraph corresponding to the modules to be merged is constructed based on the nodes, the hyperedges, and the hyperedge weights. Based on preset segmentation conditions, the hypergraph is segmented to obtain the merging result corresponding to the module to be merged, and the target module is obtained based on the merging result.

[0017] Furthermore, when the data loading module loads the corresponding target file data in the target data partition using a preset reuse mechanism, the data loading module is used to: Determine whether serialized file data exists in the target data partition; If the serialized file data exists in the target data partition, the file data is deserialized to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0018] Furthermore, when the data loading module loads the corresponding target file data in the target data partition using a preset reuse mechanism, the data loading module is also used to: If the serialized file data is not stored in the target data partition, the file data is serialized and stored to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0019] This application embodiment also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the data loading optimization method for circuit layout and routing as described above are performed.

[0020] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the data loading optimization method for circuit layout and routing as described above.

[0021] The circuit layout and routing data loading optimization method and apparatus provided in this application embodiment are applied to a layout and routing tool used for placing and routing a target circuit. The method includes: in response to the layout and routing tool receiving an initialization loading signal, acquiring multiple preset design input files, and performing modular data clustering processing on the design input files to determine multiple data partitions corresponding to the design input files and file data corresponding to each data partition; in response to the layout and routing tool receiving layout and routing requirement information input by a user for the target circuit, determining the target data partition corresponding to the layout and routing requirement information; and loading the corresponding target file data in the target data partition using a preset reuse mechanism, so as to perform layout and routing design work for the target circuit corresponding to the layout and routing requirement information based on the target file data.

[0022] Compared to existing placement and routing tools that load all the data of the entire design at once during initialization, this method performs modular data clustering on the design input file during initialization. This allows for structured and standardized storage of the loaded data, avoiding the introduction of irrelevant data. Upon receiving the user's placement and routing requirements, the method determines the target data partition corresponding to the requirements and loads the corresponding target file data into the target data partition using a reuse mechanism. This enables the placement and routing design of the circuit using the target file data. This reduces the memory footprint of placement and routing while improving the interoperability between modules in the placement and routing tool, thus enhancing the efficiency, flexibility, and debuggability of circuit placement and routing.

[0023] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a data loading optimization method for circuit layout and routing provided in an embodiment of this application; Figure 2 A schematic diagram of a data loading optimization device for circuit layout and routing provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0027] Research has found that in the current circuit design process of digital chips, a single design often contains many subsystems and modules. Placement and routing tools load all the data of the entire design at once during initialization. This full loading method can ensure the integrity of the data required in subsequent design stages. However, the redundant data loading in this method not only affects the performance of the tool, but also increases the memory overhead.

[0028] For a specific subsystem, only a portion of the relevant data is actually needed, but the placement and routing tool loads a large amount of irrelevant information, resulting in a significant increase in memory usage and loading time. In addition, if problems occur in the back-end stage of the design (e.g., timing violations and routing congestion), the large amount of data generated by placement and routing makes it difficult to accurately locate the root cause of the problem. The lack of hierarchical boundaries makes problem tracing extremely complex, reducing the efficiency of circuit placement and routing, and consequently reducing the flexibility and debuggability of circuit placement and routing.

[0029] Based on this, this application provides a data loading optimization method for circuit placement and routing. By performing modular data clustering on the design input file during the initial loading of the placement and routing tool, the loaded data is stored in a structured and standardized manner, avoiding the introduction of irrelevant data. When receiving the user's placement and routing requirement information, the target data partition corresponding to the placement and routing requirement information is determined, and the corresponding target file data is loaded in the target data partition using a reuse mechanism, so as to use the target file data to perform circuit placement and routing design. This reduces the memory occupation of placement and routing while improving the interoperability between modules in the placement and routing tool, thereby improving the efficiency, flexibility and debuggability of circuit placement and routing.

[0030] Please see Figure 1 , Figure 1 This is a flowchart illustrating a data loading optimization method for circuit layout and routing provided in an embodiment of this application. Figure 1 As shown in the illustration, the circuit layout and routing data loading optimization method provided in this application embodiment is typically applied to layout and routing tools used for placing and routing target circuits. The method includes: S101. In response to the placement and routing tool receiving an initialization loading signal, it acquires multiple preset design input files, performs modular data clustering processing on the design input files, and determines multiple data partitions corresponding to the design input files and file data corresponding to each data partition.

[0031] It should be noted that place and route tools are a key component of the electronic design automation (EDA) process. They are mainly used to convert the synthesized netlist into a physical layout for chip manufacturing or FPGA implementation. These tools are widely used in the design of integrated circuits (ICs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

[0032] Here, placement refers to placing standard cells (such as logic gates, flip-flops, etc.) or macrocells (such as memory, IP cores) in the physical area of ​​a chip or FPGA; the goal is to optimize timing, power consumption, and area (PPA, Power-Performance-Area) while meeting design rules.

[0033] For example, placement and routing tools may include Synopsys' IC Compiler II, Cadence's Innovus, and Siemens' Calibre physical verification tool.

[0034] Routing is the process of connecting metal wires between existing units to achieve logical connections. It is divided into global routing and detailed routing, and must meet electrical rules (such as minimum wire width and spacing), timing constraints, and signal integrity requirements.

[0035] In this embodiment of the application, the design input files include at least physical layout files, physical library files, timing function files, and design constraint files.

[0036] The physical layout file (Design Exchange Format, DEF) describes the physical layout of the design, such as cell locations, pins, routing, and area constraints. The physical library file (Library Exchange Format, LEF) describes the physical information of the standard cell library, such as cell size, pin shape, metal layer rules, and obstacles. The timing function file (Liberty Timing Library, LIB) describes the timing, power consumption, and functional model of the standard cells, such as delay, drive capability, and power consumption table. The design constraint file (Synopsys DesignConstraints, SDC) describes the timing and physical constraints of the design, such as clock definitions, input / output delays, maximum / minimum delays, and multi-cycle paths.

[0037] Here, the design input files also include technical documents, parasitic parameter files, and power consumption model files.

[0038] In one possible implementation of this application, in specific implementation, the step S101 of performing modular data clustering processing on the design input file to determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition may include: S1011. Identify the design input file, determine the top-level module in the design input file, and determine the module to be decomposed and the target module in the top-level module to construct a module queue to be decomposed composed of the module to be decomposed.

[0039] In one possible implementation of this application, in specific implementation, the step S1011 of determining the modules to be decomposed and the target modules in the top-level module to construct a queue of modules to be decomposed consisting of the modules to be decomposed may include: S10111. Place the set of top-level modules corresponding to the top-level module into a preset clustering table, and compare the first data volume corresponding to each top-level module with a preset constraint threshold in the clustering table to obtain the constraint comparison result.

[0040] In this embodiment, the preset constraint threshold can be specifically calibrated according to the actual parameters of the placement and routing tool and the actual situation of the target circuit.

[0041] S10112. Based on the constraint comparison results, the top-level module whose first data volume is greater than the preset constraint threshold is determined as the module to be decomposed, and the top-level module whose first data volume is less than or equal to the preset constraint threshold is determined as the target module.

[0042] S10113. Extract the modules to be decomposed from the clustering network table and construct a queue of modules to be decomposed consisting of the modules to be decomposed.

[0043] For example, the top-level module set (top_clusters) corresponding to the top-level module (top_module) is created and placed into the preset clustering list (cluster_list). The number of modules to be decomposed that exceeds the preset constraint threshold is taken from the clustering list (cluster_list) and added to the module queue to be decomposed (break_cluster_queue).

[0044] S1012. Perform module traversal on the queue of modules to be decomposed, determine the modules to be merged and the target module in the modules to be decomposed, so as to construct a queue of modules to be merged composed of the modules to be merged.

[0045] In one possible implementation of this application, step S1012 may include: S10121. Perform a first traversal of the queue of modules to be decomposed to determine the modules to be compared among the modules to be decomposed.

[0046] S10122. Perform a second traversal on the queue of modules to be compared corresponding to the module to be compared, and determine the sub-modules to be compared in the module to be compared.

[0047] S10123. The second data volume corresponding to the sub-module to be compared is compared with the first preset specification threshold and the second preset specification threshold respectively to obtain the specification comparison result.

[0048] Wherein, the first preset specification threshold is greater than the second preset specification threshold.

[0049] In this embodiment, the first preset specification threshold and the second preset specification threshold can be specifically calibrated according to the actual parameters of the layout and routing tool and the actual situation of the target circuit.

[0050] S10124. Based on the specification comparison results, the sub-modules to be compared with the second data volume being greater than the first preset specification threshold are determined as sub-modules to be decomposed, the sub-modules to be compared with the second data volume being less than the second preset specification threshold are determined as modules to be merged, and the sub-modules to be compared with the second data volume being less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold are determined as the target module.

[0051] S10125. For the sub-module to be decomposed, the sub-module to be decomposed is placed in the queue of modules to be decomposed, so as to split the sub-module to be decomposed in the queue of modules to be decomposed until the second data volume corresponding to the split module is less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold, so as to determine the target module corresponding to the sub-module to be decomposed.

[0052] S10126. For the modules to be merged, construct a queue of modules to be merged consisting of the modules to be merged.

[0053] For example, the queue of modules to be decomposed (break_cluster_queue) is traversed, the module to be compared (big_module) is retrieved, the queue of modules to be compared corresponding to the module to be compared (big_module.child_modules) is traversed, the sub-module to be compared (child_module) is retrieved, and the sub-module to be compared with the second data volume being less than the second preset specification threshold is determined as the module to be merged and added to the constructed queue of modules to be merged (merge_cluster_list).

[0054] S1013. Merge the modules to be merged in the queue of modules to be merged using a preset hypergraph segmentation method to obtain the target module.

[0055] In one possible implementation of this application, step S1013 may include: S10131. Based on the connection relationship between the modules to be merged in the queue of modules to be merged, determine the superedge corresponding to the module to be merged, and based on the connection strength between the modules to be merged in the queue of modules to be merged, determine the superedge weight corresponding to the module to be merged.

[0056] S10132. Using the modules to be merged as nodes of the hypergraph, construct the hypergraph corresponding to the modules to be merged based on the nodes, the hyperedges, and the hyperedge weights.

[0057] S10133. Based on preset segmentation conditions, the hypergraph is segmented to obtain the merging result corresponding to the module to be merged, and the target module is obtained based on the merging result.

[0058] Furthermore, for the leaf units in the modules to be merged, corresponding target modules are created and added to the corresponding clustering netlist.

[0059] S1014. Construct a target clustering network table composed of the target modules, and based on the target clustering network table, determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition.

[0060] S102. In response to the placement and routing tool receiving placement and routing requirement information input by the user for the target circuit, the target data partition corresponding to the placement and routing requirement information is determined.

[0061] For example, when the layout and routing requirement information is due to circuit modification or optimization of some modules (subsystems), such as ECO placement, incremental placement, ECO routing, and incremental routing, the user can determine the target data partition corresponding to the layout and routing requirement information by checking the layout instances or networks that need to be optimized through the target clustering netlist, so as to obtain the design input file corresponding to the layout and routing requirement information in the target data partition.

[0062] S103. Using a preset reuse mechanism, load the corresponding target file data into the target data partition, and based on the target file data, perform layout and routing design work for the target circuit corresponding to the layout and routing requirement information.

[0063] In this application embodiment, the reuse mechanism runs through the entire chip back-end design flow of the target circuit, such as place, route and physical verification. The stored target file data can be reused in different design stages. For example, the cell library information loaded in the global layout stage can be used directly in the incremental layout stage. Data can be read directly through deserialization or partial data can be loaded to avoid redundancy and repeated parsing.

[0064] In one possible implementation of this application, in specific implementation, the step S103 of loading the corresponding target file data in the target data partition using a preset reuse mechanism may include: S1031. Determine whether serialized file data exists in the target data partition.

[0065] S1032. If the serialized file data exists in the target data partition, the file data is deserialized to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0066] Furthermore, step S103, which involves loading the corresponding target file data into the target data partition using a preset reuse mechanism, further includes: S1033. If the serialized file data is not stored in the target data partition, the file data is serialized and stored to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0067] Furthermore, since the design input files meet the standard format of the electronic design automation industry, the deserialized format of the target file data in the target data partition can be directly read through cross-vendor tools, thus enabling data sharing.

[0068] As an example of the data loading optimization method for circuit layout and routing described in this application, for example, when designing a chip circuit containing three subsystems: CPU, GPU, and DSP, if the user only performs layout and routing for the GPU subsystem, the target data partition to which the GPU belongs is determined through the target clustering netlist included in the GPU, and then the target file data in the target data partition is loaded. Only the input design files such as library files and constraint files related to the GPU are loaded, without loading CPU and DSP related data. This significantly shortens the initialization time while making the development of the back-end chip circuit more flexible and convenient, and reducing redundant loading time.

[0069] The circuit placement and routing data loading optimization method provided in this application performs modular data clustering processing on the design input file during the initial loading of the placement and routing tool. This allows for structured and standardized storage of the loaded data, avoiding the introduction of irrelevant data. Upon receiving the user's placement and routing requirements, the method determines the target data partition corresponding to the requirements and loads the corresponding target file data into the target data partition using a reuse mechanism. This enables the placement and routing design of the circuit using the target file data. This reduces the memory footprint of placement and routing while improving the interoperability between modules in the placement and routing tool, thereby enhancing the efficiency, flexibility, and debuggability of circuit placement and routing.

[0070] Please see Figure 2 , Figure 2This is a schematic diagram of a data loading optimization device for circuit layout and routing provided in an embodiment of this application. Figure 2 As shown, the data loading optimization device 200 includes: The data clustering processing module 210 is used to respond to the placement and routing tool receiving the initialization loading signal, acquire multiple preset design input files, perform modular data clustering processing on the design input files, and determine multiple data partitions corresponding to the design input files and file data corresponding to each data partition; The data partition determination module 220 is used to determine the target data partition corresponding to the layout and routing requirement information received by the layout and routing tool from the user for the target circuit. The data loading module 230 is used to load the corresponding target file data in the target data partition using a preset reuse mechanism, so as to perform the layout and routing design work corresponding to the layout and routing requirements information of the target circuit based on the target file data.

[0071] Furthermore, when the data clustering processing module 210 performs modular data clustering processing on the design input file to determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition, the data clustering processing module 210 is used to: The design input file is identified to determine the top-level module in the design input file, and the modules to be decomposed and the target module are determined in the top-level module to construct a queue of modules to be decomposed composed of the modules to be decomposed. The module queue to be decomposed is traversed to determine the modules to be merged and the target module in the modules to be decomposed, so as to construct a module queue to be merged composed of the modules to be merged; The modules to be merged in the queue of modules to be merged are merged using a preset hypergraph segmentation method to obtain the target module; Construct a target clustering network table composed of the target modules, and based on the target clustering network table, determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition.

[0072] Furthermore, when the data clustering processing module 210 is used to determine the modules to be decomposed and the target modules in the top-level module to construct a queue of modules to be decomposed composed of the modules to be decomposed, the data clustering processing module 210 is used to: The set of top-level modules corresponding to the top-level module is placed into a preset clustering table, and the first data volume corresponding to each top-level module is compared with a preset constraint threshold in the clustering table to obtain the constraint comparison result; Based on the constraint comparison results, the top-level module whose first data volume is greater than the preset constraint threshold is determined as the module to be decomposed, and the top-level module whose first data volume is less than or equal to the preset constraint threshold is determined as the target module. The modules to be decomposed are extracted from the clustering network table, and a queue of modules to be decomposed is constructed.

[0073] Furthermore, when the data clustering processing module 210 performs module traversal on the queue of modules to be decomposed, determines the modules to be merged and the target modules in the queue of modules to be decomposed, and constructs a queue of modules to be merged composed of the modules to be merged, the data clustering processing module 210 is used to: Perform a first traversal of the queue of modules to be decomposed to determine the modules to be compared among the modules to be decomposed. A second traversal is performed on the queue of modules to be compared corresponding to the module to be compared, to determine the sub-modules to be compared in the module to be compared. The second data volume corresponding to the sub-module to be compared is compared with the first preset specification threshold and the second preset specification threshold respectively to obtain the specification comparison result; wherein, the first preset specification threshold is greater than the second preset specification threshold; Based on the specification comparison results, the sub-modules to be compared with the second data volume being greater than the first preset specification threshold are determined as sub-modules to be decomposed, the sub-modules to be compared with the second data volume being less than the second preset specification threshold are determined as modules to be merged, and the sub-modules to be compared with the second data volume being less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold are determined as the target modules. For the sub-module to be decomposed, the sub-module to be decomposed is placed in the queue of modules to be decomposed, so as to split the sub-module to be decomposed in the queue of modules to be decomposed until the second data volume corresponding to the split module is less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold, so as to determine the target module corresponding to the sub-module to be decomposed; For the modules to be merged, a queue of modules to be merged is constructed.

[0074] Furthermore, when the data clustering processing module 210 merges the modules to be merged in the queue of modules to be merged using a preset hypergraph segmentation method to obtain the target module, the data clustering processing module 210 is used to: Based on the connection relationships between the modules to be merged in the queue of modules to be merged, the superedges corresponding to the modules to be merged are determined, and based on the connection strength between the modules to be merged in the queue of modules to be merged, the weights of the superedges corresponding to the modules to be merged are determined. Using the modules to be merged as nodes of the hypergraph, a hypergraph corresponding to the modules to be merged is constructed based on the nodes, the hyperedges, and the hyperedge weights. Based on preset segmentation conditions, the hypergraph is segmented to obtain the merging result corresponding to the module to be merged, and the target module is obtained based on the merging result.

[0075] Furthermore, when the data loading module 230 loads the corresponding target file data in the target data partition using a preset reuse mechanism, the data loading module 230 is used to: Determine whether serialized file data exists in the target data partition; If the serialized file data exists in the target data partition, the file data is deserialized to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0076] Furthermore, when loading the corresponding target file data into the target data partition using a preset reuse mechanism, the data loading module 230 is also used to: If the serialized file data is not stored in the target data partition, the file data is serialized and stored to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

[0077] The circuit layout and routing data loading optimization device provided in this application performs modular data clustering processing on the design input file during the initial loading of the layout and routing tool. This allows for structured and standardized storage of the loaded data, avoiding the introduction of irrelevant data. Upon receiving the user's layout and routing requirement information, the device determines the target data partition corresponding to the requirement information and loads the corresponding target file data into the target data partition using a reuse mechanism. This enables the device to perform circuit layout and routing design using the target file data. This reduces the memory footprint of layout and routing while improving the interoperability between modules in the layout and routing tool, thereby enhancing the efficiency, flexibility, and debuggability of circuit layout and routing.

[0078] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 3As shown, the electronic device 300 includes a processor 310, a memory 320, and a bus 330.

[0079] The memory 320 stores machine-readable instructions executable by the processor 310. When the electronic device 300 is running, the processor 310 and the memory 320 communicate via the bus 330. When the machine-readable instructions are executed by the processor 310, they can perform the operations described above. Figure 1 The steps of the data loading optimization method for circuit layout and routing in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0080] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The steps of the data loading optimization method for circuit layout and routing in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0081] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0085] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of data load optimization for circuit layout routing, characterized by, The method is applied to a placement and routing tool used for placing and routing a target circuit, and the method includes: In response to the placement and routing tool receiving an initialization loading signal, it acquires multiple preset design input files, performs modular data clustering processing on the design input files, and determines multiple data partitions corresponding to the design input files and file data corresponding to each data partition; In response to the placement and routing tool receiving placement and routing requirement information input by the user for the target circuit, the target data partition corresponding to the placement and routing requirement information is determined; The corresponding target file data is loaded into the target data partition using a preset reuse mechanism, so that the target circuit can be designed based on the target file data in accordance with the layout and routing requirements.

2. The method of claim 1, wherein, The modular data clustering process of the design input file, which determines multiple data partitions corresponding to the design input file and the file data corresponding to each data partition, includes: The design input file is identified to determine the top-level module in the design input file, and the modules to be decomposed and the target module are determined in the top-level module to construct a queue of modules to be decomposed consisting of the modules to be decomposed. The module queue to be decomposed is traversed to determine the modules to be merged and the target module in the modules to be decomposed, so as to construct a module queue to be merged composed of the modules to be merged; The modules to be merged in the queue of modules to be merged are merged using a preset hypergraph segmentation method to obtain the target module; Construct a target clustering network table composed of the target modules, and based on the target clustering network table, determine multiple data partitions corresponding to the design input file and the file data corresponding to each data partition.

3. The method of claim 2, wherein, The step of determining the modules to be decomposed and the target module in the top-level module to construct a queue of modules to be decomposed, consisting of the modules to be decomposed, includes: The set of top-level modules corresponding to the top-level module is placed into a preset clustering table, and the first data volume corresponding to each top-level module is compared with a preset constraint threshold in the clustering table to obtain the constraint comparison result; Based on the constraint comparison results, the top-level module whose first data volume is greater than the preset constraint threshold is determined as the module to be decomposed, and the top-level module whose first data volume is less than or equal to the preset constraint threshold is determined as the target module. The modules to be decomposed are extracted from the clustering network table, and a queue of modules to be decomposed is constructed.

4. The method of claim 2, wherein, The step of traversing the queue of modules to be decomposed to determine the modules to be merged and the target module in the queue of modules to be decomposed, so as to construct a queue of modules to be merged composed of the modules to be merged, includes: Perform a first traversal of the queue of modules to be decomposed to determine the modules to be compared among the modules to be decomposed. A second traversal is performed on the queue of modules to be compared corresponding to the module to be compared, to determine the sub-modules to be compared in the module to be compared. The second data volume corresponding to the sub-module to be compared is compared with the first preset specification threshold and the second preset specification threshold respectively to obtain the specification comparison result; wherein, the first preset specification threshold is greater than the second preset specification threshold; Based on the specification comparison results, the sub-modules to be compared with the second data volume being greater than the first preset specification threshold are determined as sub-modules to be decomposed, the sub-modules to be compared with the second data volume being less than the second preset specification threshold are determined as modules to be merged, and the sub-modules to be compared with the second data volume being less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold are determined as the target modules. For the sub-module to be decomposed, the sub-module to be decomposed is placed in the queue of modules to be decomposed, so as to split the sub-module to be decomposed in the queue of modules to be decomposed until the second data volume corresponding to the split module is less than or equal to the first preset specification threshold and greater than or equal to the second preset specification threshold, so as to determine the target module corresponding to the sub-module to be decomposed; For the modules to be merged, a queue of modules to be merged is constructed.

5. The method of claim 2, wherein, The process of merging the modules to be merged in the queue of modules to be merged using a preset hypergraph segmentation method to obtain the target module includes: Based on the connection relationship between the modules to be merged in the queue of modules to be merged, the superedge corresponding to the module to be merged is determined, and based on the connection strength between the modules to be merged in the queue of modules to be merged, the weight of the superedge corresponding to the module to be merged is determined. Using the modules to be merged as nodes of the hypergraph, a hypergraph corresponding to the modules to be merged is constructed based on the nodes, the hyperedges, and the hyperedge weights. Based on preset segmentation conditions, the hypergraph is segmented to obtain the merging result corresponding to the module to be merged, and the target module is obtained based on the merging result.

6. The method of claim 1, wherein, The step of loading the corresponding target file data into the target data partition using a preset reuse mechanism includes: Determine whether serialized file data exists in the target data partition; If the serialized file data exists in the target data partition, the file data is deserialized to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

7. The method according to claim 6, characterized in that, The method of loading the corresponding target file data into the target data partition using a preset reuse mechanism further includes: If the serialized file data is not stored in the target data partition, the file data is serialized and stored to determine the target file data, so as to load the target file data corresponding to the target data partition into the target data partition.

8. A data loading optimization device for circuit layout and routing, characterized in that, The data loading optimization device includes: The data clustering processing module is used to respond to the placement and routing tool receiving the initialization loading signal, acquire multiple preset design input files, perform modular data clustering processing on the design input files, and determine multiple data partitions corresponding to the design input files and file data corresponding to each data partition; The data partition determination module is used to determine the target data partition corresponding to the layout and routing requirement information received by the layout and routing tool from the user for the target circuit. The data loading module is used to load the corresponding target file data in the target data partition using a preset reuse mechanism, so as to perform the layout and routing design work corresponding to the layout and routing requirements information of the target circuit based on the target file data.

9. An electronic device, comprising: include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the data loading optimization method for circuit layout and routing as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the data loading optimization method for circuit layout and routing as described in any one of claims 1 to 7.

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