Macrocell layout optimization method, product and device based on monte carlo graph search

Abstract

This invention belongs to the field of integrated circuit design, specifically relating to a macrocell layout optimization method, product, and device based on Monte Carlo graph search. The scheme represents each complete legal macro-layout as a graph node. Then, high-potential parent nodes are identified from the retained historical graph nodes using the Graph-UCB mechanism. Guided scores are calculated for each macrocell within the parent node, selecting several macrocells with greater optimization value. Next, the spatial layout of these cells is locally optimized and reconstructed to generate child nodes representing the new macro-layout, thereby achieving progressive local optimization of the macro-layout. This invention can more efficiently optimize the scheme that achieves optimal half-circle length, line length, and congestion proxy indicators while satisfying legality constraints, overcoming problems such as the accumulation of sequential generation errors, lack of guidance in local reconstruction, and easy stagnation in the later stages of the search in traditional schemes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a macrocell layout optimization method based on Monte Carlo map search, and its corresponding computer program product, computer storage medium, and circuit design optimization equipment. Background Technology

[0002] With the continuous increase in the complexity of VLSI design, the physical design phase faces increasingly severe layout optimization problems. The layout result not only determines the spatial distribution of standard cells and macrocells within the chip area, but also further affects subsequent global routing, detailed routing, timing closure, power optimization, and the final PPA (Power, Performance, and Area). In mixed-size layout tasks, macrocells typically have a much larger area than standard cells and often correspond to memory, compute arrays, or critical functional modules. Their location significantly alters the available area of ​​standard cells, global interconnect length, and local routing resource distribution. Therefore, macrocell layout is generally considered a key pre-design issue in modern chip physical design flows. The core objective of macrocell layout is to minimize interconnect costs and improve routerability while satisfying chip boundary constraints and macrocell non-overlap constraints. Half-perimeter wirelength (HPWL) is widely used as a primary optimization metric in the macro-layout stage due to its computational efficiency, ease of incremental updates, and ability to approximate subsequent routing lengths well.

[0003] Existing macrocell placement methods can be broadly categorized into analytical methods, learning-based methods, and search optimization methods. Analytical placement methods, such as DREAMPlace, RePlAce, ePlace / ePlace-MS, NTUplace3, SimPL, and FastPlace, typically transform the placement problem into a continuous optimization problem. They drive cell movement jointly through line length and density terms, and achieve relatively fast solutions using efficient numerical optimization or GPU acceleration. These methods are highly efficient in large-scale placement tasks, but their flexibility is relatively limited when dealing with discrete macrocell placement, non-overlapping constraints, and local structure reconstruction. In contrast, reinforcement learning and deep learning methods model macrocell placement as a sequential decision-making process, gradually generating macrocell positions through policy networks. For example, Graph Placement uses graph neural networks to encode netlist structures and completes macro placement based on reinforcement learning; MaskPlace introduces position masks, wiremasks, and viewmasks to improve the ability to filter legal positions and estimate line length increments; ChiPFormer further employs an offline decision-making Transformer to learn existing placement trajectories to improve cross-circuit transfer capabilities. These methods have driven the development of learning-based macro placement, but they still generally face problems such as high training costs, insufficient sample efficiency, unstable generalization across designs, and accumulation of sequential generation errors.

[0004] Besides learning-based methods, black-box optimization, genetic algorithms, and Monte Carlo search have also been used for macro-layout optimization. WireMask-BBO encodes the macro-layout as a coordinate vector and uses a wire-mask-guided greedy decoder to map candidate solutions to valid layouts, thus combining black-box optimization with layout domain knowledge. EfficientPlace uses a reinforcement learning embedding tree search framework to improve search efficiency by managing potentially viable partial layout states. RollPlace further points out that generating macro positions sequentially in one go can easily lead to early errors being amplified in subsequent decisions. Therefore, it uses Monte Carlo rollout search to locally adjust and replay existing complete layouts to improve layout quality. This idea illustrates that macro-unit layout is not just a single-sequence generation problem starting from a blank canvas, but is more suitable as a combinatorial optimization process that can be iteratively adjusted, locally reconstructed, and continuously refined.

[0005] Despite the positive results achieved by the aforementioned methods, macrocell placement still has several shortcomings. First, many reinforcement learning or learned placement methods rely on a fixed macrocell order for one-time generation. If the early macrocell positions are unreasonable, subsequent macrocells can only be placed within a limited space, easily leading to error accumulation. Second, existing tree search or rollout methods typically optimize around partial placement paths or a single complete placement, making it difficult to fully reuse the same complete placement state appearing under different search paths, resulting in redundant expansion and wasted search statistics. Finally, if local reconstruction regions lack effective guidance, the algorithm may repeatedly consume search budget in low-yield areas, especially in the later stages of the search, where it is more likely to enter a stable period, making further effective improvement difficult. Summary of the Invention

[0006] To address the problem of insufficient optimization efficiency in existing macro-cell layout optimization schemes due to the aforementioned reasons, this invention provides a macro-cell layout optimization method based on Monte Carlo map search, along with corresponding computer program products, computer storage media, and circuit design optimization equipment.

[0007] This invention is achieved using the following technical solution: A macrocell layout optimization method based on Monte Carlo map search, comprising: Obtain the design parameters of the chip to be optimized, mesh the layout area, and generate a list of macrocells representing the arrangement order based on preset indicators.

[0008] A preset layout strategy is adopted to sequentially lay out each macro cell according to the macro cell list, thereby generating several initial layout solutions that satisfy the legality constraints.

[0009] Each initial layout solution is used as a candidate node to generate a search graph. The search graph uses each valid layout solution as a node, and the edges between nodes represent the source relationships for performing local reconstruction. Iterative optimization is then performed based on the search graph as follows: (i) Design a node selection function with the goal of balancing layout quality, exploration needs, frontier potential and rollout feasibility, calculate the selection score of all candidate nodes, and select the node with the highest score as the parent node of this round.

[0010] (ii) Based on the adaptive selection strategy set in the search phase, select several macro units with more optimization value as releasable macro units to form the macro set Ω to be reconstructed.

[0011] (iii) Based on the parent node, a preset layout strategy is adopted to reconstruct the layout of each macrocell in Ω according to the macrocell list, thereby generating several feasible solutions that satisfy the legality constraints.

[0012] (iv) Calculate the half-perimeter length HPWL of each feasible solution and select a specified number of better solutions as child nodes of the parent node.

[0013] (v) Transpose and merge child nodes to eliminate duplicate solutions, update the search graph and its node attributes, and select some or all nodes in the search graph as new candidate nodes for the next iteration based on the search stage.

[0014] After the iteration stops, the globally optimal node is output as the optimized macro layout.

[0015] As a further improvement of the present invention, the macrocell area is used as the optimal index, the total area of ​​connected macrocells is used as the second-optimal index, and the number of the associated Nets is used as the third-optimal index. The macrocells are sorted in a multi-level manner to generate the required macrocell list.

[0016] As a further improvement of the present invention, the legality constraints include boundary constraints and non-overlapping constraints.

[0017] As a further improvement of the present invention, the preset layout strategy includes: firstly, randomly generating the initial positions of all macrocells within the layout area, and then using a greedy strategy to adjust the positions of each macrocell in turn according to the macrocell list to obtain a global layout diagram that satisfies the legality constraints.

[0018] As a further improvement of the present invention, the method of transposing and merging child nodes to eliminate duplicate solutions includes: calculating the node key value according to the global layout graph corresponding to the node, with each global layout graph corresponding to a unique key value; when the newly added child node has the same key value as any node, the child node is deleted.

[0019] As a further improvement to this invention, the calculation formula for the node selection function is as follows: ; In the above formula, Score(v) represents the selection score of node v; HPWL best B represents the current globally optimal HPWL; v HPWL is the best way to represent the history of node v. It is a preset constant to prevent division by zero; N total N represents the total number of visits to each node in the graph. v The number of times node v is visited is represented by c; the exploration coefficient is represented by F(v); the frontier reward is represented by r. v f represents the rollout feasibility of node v; v Indicates the number of consecutive failures; f max This indicates the preset maximum number of failures; and These are the combined weights of the rollout feasibility rate and the number of failures in the penalty item.

[0020] As a further improvement of the present invention, the generation strategy for the macro set Ω to be reconstructed includes: (1) Calculate the guiding score based on the net span contribution, local density, boundary pressure and macro cell area of ​​each macro cell in the macro layout corresponding to the parent node.

[0021] (2) Based on the current search phase, generate an adaptive number of sampling anchors and a sampling window size.

[0022] (3) Select a specified number of macrocells from each macrocell as sampling anchors based on the guided score.

[0023] (4) Select each macrocell within a sampling window of a specified size, centered on the sampling anchor, as a releasable macrocell, and thus form the macro set Ω to be reconstructed.

[0024] As a further improvement of the present invention, an upper limit and a lower limit are preset for the size of the macro set Ω to be reconstructed. When the size of Ω is higher than the upper limit, macro cells with higher guiding scores, closer connection with the sampling anchor, or greater local density contribution are preferentially retained. When the size of Ω is lower than the upper limit, candidate macro cells are supplemented from macro cells near the sampling anchor or in the same mesh as releasable macro cells.

[0025] As a further improvement of the present invention, in the parent node, any macrounit m i The guiding fraction G(m) i The calculation formula for ) is as follows: ; In the above formula, C net (m i ) represents the contribution of the network span; C density (m i ) represents the local density term; C boundary (m i ) represents the boundary pressure term; C area (m i ) represents the area term of the macro unit; These are the weight coefficients for the corresponding items.

[0026] As a further improvement of this invention, let T be the interval between the current round and the last global optimal update. plateau According to T plateau The following strategy is used to adaptively adjust the size of Ω:

[0027] In the above formula, and They are the preset T plateau Mild and severe thresholds; Ωsmall Ω mid Ω large These represent the minimum, medium, and maximum ranges of the size of Ω, respectively.

[0028] As a further improvement of the present invention, in each round of iterative optimization, if the parent node successfully generates at least one valid sub-solution in the current search, the parent node's rollout success count and access count are updated; if the parent node fails to generate a valid sub-solution, the parent node's failure count is updated.

[0029] When the number of consecutive failures reaches the preset cooling threshold, the node is placed in a cooling state; when the number of consecutive failures continues to increase and reaches the failure threshold, the node is marked as a failed node.

[0030] Cooling nodes will not be included in the candidate node selection range for a specified number of subsequent iterations; failed nodes will not be included in the candidate node selection range for all subsequent iterations.

[0031] As a further improvement of this invention, the initial layout solution is subjected to elite node screening and archiving to generate an initial elite solution set. ; After each iteration, the retained nodes are selected and archived as elite nodes, and the elite solution set is updated. ; Elite solution sets are periodically used to replace candidate nodes in order to generate the required parent nodes.

[0032] The present invention also includes a computer storage medium storing a computer program. When the computer program is executed by a processor, it implements the macrocell layout optimization method based on Monte Carlo map search as described above, thereby obtaining the design parameters of the chip to be designed and generating an optimal layout that satisfies the legality constraints.

[0033] The present invention also includes a computer program product comprising a computer program that, when executed by a processor, implements the aforementioned macrocell layout optimization method based on Monte Carlo map search, thereby obtaining the design parameters of the chip to be designed and generating an optimal layout that satisfies the legality constraints.

[0034] The present invention also includes a circuit design optimization device, which includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the macrocell layout optimization method based on Monte Carlo map search as described above, thereby obtaining the design parameters of the chip to be designed and generating an optimal layout that satisfies the legality constraints.

[0035] The technical solution provided by this invention has the following beneficial effects: This invention provides a novel macro-cell layout optimization method based on Monte Carlo Graph Search (MCGS). This method represents each complete and legal macro-layout as a graph node, and selects high-potential parent nodes from the various retained historical graph nodes to locally optimize and reconstruct the spatial layout of several macro-cells with more optimization value contained therein, generating child nodes that represent the new macro-layout, thereby achieving progressive local optimization of the macro-layout.

[0036] Compared with traditional tree search-based optimization schemes, the MCGS scheme of this invention can repeatedly verify the complete macro layout corresponding to the newly added child nodes in each iteration, thereby reusing search information such as access count, historical optimal cost and feasibility statistics, and avoiding wasting search resources on the same optimization results.

[0037] In the iterative optimization process, the MCGS scheme employs a parent node selection strategy with feasibility penalties to balance layout quality, exploration needs, and update success rate, preventing the search from being confined to the vicinity of a single current optimal solution for an extended period. During the local reconstruction phase of the macro-layout, the MCGS scheme generates a guiding score for each macrocell by integrating factors such as net span, local density, boundary pressure, and macrocell area. This allows for the priority selection of macrocell sets more likely to affect line length and congestion, followed by legitimate spatial layout replay and fine-tuning.

[0038] Furthermore, this invention introduces mechanisms such as elite solution archiving, phase awareness, stable period escape, and failure node pruning into the solution. These strategies can improve the stability of the later stages of the search and the ability to escape local optima, thereby enhancing the effectiveness and robustness of macrocell layout search. Attached Figure Description

[0039] Figure 1 This is a flowchart of the steps of the macrocell layout optimization method based on Monte Carlo map search provided in Embodiment 1 of the present invention.

[0040] Figure 2 This is a schematic diagram of guided relocation in Embodiment 1 of the present invention.

[0041] Figure 3 This is a schematic diagram of macrocell layout fine-tuning based on position mask and field mask in Embodiment 1 of the present invention.

[0042] Figure 4 This is a schematic diagram of a newly added child node and other nodes having the same macro layout in the search graph in Embodiment 1 of the present invention.

[0043] Figure 5Visual images of the layout schemes of Wiremask_EA, EfficiencePlace, RollPlace, and the present invention on adaptec2 in the test experiment.

[0044] Figure 6 To compare the convergence curves of the optimization process of the present invention and the control group on adaptec1, adaptec2, adaptec3 and adaptec4 in the test experiment.

[0045] Figure 7 To test the convergence curves of the optimization process of the present invention and the control group on bigblue1, bigblue2, bigblue3 and bigblue4 in the experiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0047] Example 1

[0048] To address the common problems in existing macro-layout optimization methods based on analytical, learning, and search optimization approaches, such as insufficient state reuse, accumulation of sequential generation errors, lack of guidance in local reconstruction, low efficiency in handling legality constraints, and easy stagnation in the later stages of the search, this embodiment provides a macro-unit layout optimization method based on Monte Carlo graph search. Unlike traditional tree search, which only organizes search states along a single path, the Monte Carlo graph search method provided in this embodiment represents each complete legal macro-layout as a graph node. By selecting high-potential parent nodes from each retained historical graph node, it performs local optimization and reconstruction on the spatial layout of several macro-units with greater optimization value contained therein, generating child nodes representing the new macro-layout, thereby achieving progressive local optimization of the macro-layout.

[0049] Specifically, this scheme sorts the macrocells to be placed based on information such as macrocell area and network connectivity, and generates several legal initial layout solutions using a randomized guided and greedy placement strategy, serving as the initial nodes for the MCGS search. Next, in the search phase, each complete macro layout is represented as a node in the graph, and a parent node is selected based on the node's historical visit count, optimal HPWL (Half-Perimeter Wirelength), feasibility, and exploration items. After selecting the parent node, this embodiment combines key macrocell scoring, network expansion, and local region sampling to generate multiple candidate reconstruction schemes. While maintaining the positions of some macrocells unchanged, guided local rearrangement of macrocells within key sub-regions is performed. Each reconstruction scheme constrains the placement position through a position mask and a wire length mask, and multiple fine-tuning operations can be performed in parallel to obtain multiple feasible solutions. Next, this embodiment evaluates each generated feasible solution based on HPWL, retaining only the top-k child nodes with better quality and adding them to the search graph, while updating the parent node value, visit count, edge information, and global optimum. Finally, a transpose merging mechanism is used to exclude duplicate nodes, and duplicate nodes are merged to avoid repeatedly searching for the same layout state. Furthermore, this embodiment can prune long-term invalid or low-quality nodes and utilize an elite archive to maintain high-quality and diverse layout solutions, allowing for exiting the search when it stalls.

[0050] In detail, such as Figure 1 As shown, the macrocell layout optimization method based on Monte Carlo map search provided in this embodiment includes the following steps: 1. Obtain the design parameters of the chip to be optimized, mesh the layout area, and generate a list of macrocells representing the arrangement order based on preset indicators.

[0051] In this embodiment, the design parameters of the chip to be optimized can be read through the netlist file. The information in the design parameters includes macrocell size information, net connection relationships, pin offset information, fixed object coordinate information, and chip layout boundary information. Therefore, the macro layout optimization problem to be solved in this embodiment is essentially to scientifically place each macrocell within the layout area, and then, under the premise of satisfying legal constraints such as boundary constraints and non-overlapping constraints, obtain the optimization problem that optimizes congestion proxy indicators such as half-perimeter wire length HPWL and RUDY (Rectangular Uniform wire DensityY).

[0052] In this embodiment, the chip layout area is divided into a G×G discrete grid, and the number of grids can be set according to the circuit scale, the number of macrocells, and the chip area size. The placement result of each macrocell is represented as the position of the macrocell reference point in the grid. Through gridding, the continuous layout space is transformed into a finite set of discrete candidate positions, which facilitates the construction of position masks and line length masks.

[0053] In actual circuit netlists, the length of a net is not directly determined by the center point of the macrocell, but by the actual physical coordinates of the pins connected to that net. Therefore, in this embodiment, the system adopts a pin-aware net length calculation method. Let any macrocell... The coordinates of the lower left corner are macrocell pins on The offset relative to the lower left corner of this macrocell is Then the pin The absolute coordinates are represented as:

[0054]

[0055] in, Pin indication The actual physical coordinates in the chip layout area.

[0056] In this way, this embodiment uses the actual coordinates of the pins when calculating the half-circuit length and the wiring congestion proxy index, instead of simply using the coordinates of the macrocell center. This allows for a more accurate reflection of the impact of different macrocell placement positions on the actual interconnection cost.

[0057] For any macrounit Its discrete placement position can be represented as grid coordinates: ,in: To facilitate state encoding during the subsequent search process, this embodiment maps two-dimensional grid coordinates to one-dimensional discrete placement actions: .

[0058] in, Represents macro unit The corresponding discrete placement action.

[0059] Therefore, a complete macrocell layout solution S can be expressed as: .in, Indicates the number of macrocells to be optimized. Indicates the first macro units The discrete placement action. This embodiment can reconstruct the actual placement coordinates of each macrocell in the chip layout area based on the complete layout solution S.

[0060] For a chip containing multiple macrocells, the order in which each macrocell is placed during macro-layout generation affects the final layout result. Both generating the initial layout solution and fine-tuning local regions during iterative optimization involve placing multiple macrocells. Therefore, this embodiment pre-generates a macrocell list based on the importance of each macrocell. The order of each macrocell in the list determines its placement order in the initial layout solution and sub-feasible solution generation nodes. In practical applications, this embodiment uses macrocell area as the optimal metric, the total area of ​​connected macrocells as the second-optimal metric, and the number of their respective Nets as the third-optimal metric to perform multi-level sorting of each macrocell, thereby generating the required macrocell list. Each macrocell is first sorted by area, with larger areas having higher priority. For macrocells with similar areas, the macrocell with the larger sum of the areas of all macrocells within the same Net (the second-optimal metric) has higher priority, and so on.

[0061] Second, a preset layout strategy is adopted to lay out each macro cell in sequence according to the macro cell list, thereby generating several initial layout solutions that satisfy the legality constraints.

[0062] In this embodiment, when generating a macro layout, the placement of any macro cell must satisfy two basic legality constraints: boundary constraints and non-overlapping constraints. That is, the spatial position of any macro cell cannot exceed the layout area, and the spatial positions of any two macro cells cannot overlap. In practical applications, methods for checking whether the layout position of any macro cell satisfies the legality constraints include: Let the width and height of the chip layout area be W and H, respectively, then the grid coordinates... Can be converted into macrounits Actual placement coordinates If macro unit The width and height are respectively and Then the boundary validity constraint of the macrocell is expressed as:

[0063] The above constraints are used to ensure that each macrocell is placed inside the chip layout boundary. If any constraint is not satisfied, the corresponding candidate placement position is determined to be an illegal position.

[0064] In addition to boundary constraints, any two macrocells must also satisfy non-overlapping constraints. Let macrocells... and macro unit The coordinates of the lower left corner are respectively and The width and height are respectively and The condition under which the two do not overlap is:

[0065] If any of the above conditions are met, then the macrocell With macro units No overlap occurs; if none of the above conditions are met, then there is an overlap, and the current layout solution does not meet the legality requirements.

[0066] In this embodiment, to enhance the exploration of the solution space while ensuring that the feasible solution of the generated macro-layout satisfies the legality constraints, a layout strategy combining random sampling and a greedy strategy is adopted. The greedy strategy helps to quickly reduce HPWL (Highest Power Wage Limit), while the random sampling strategy helps to maintain search diversity. The layout strategy is implemented as follows: first, the initial positions of all macrocells within the layout region are randomly generated; then, when any macrocell violates the aforementioned legality constraints, the greedy strategy is used to adjust the positions of each macrocell sequentially according to the macrocell list, ultimately obtaining a global layout graph that satisfies the legality constraints.

[0067] Third, each initial layout solution is used as a candidate node to generate a search graph. The search graph uses each valid layout solution as a node, and the edges between nodes are used to represent the source relationship for performing local reconstruction.

[0068] In this embodiment, the set M of macrocells of any chip is represented as: , where m1~m N These are the N macrounits contained in set M.

[0069] Based on this, this embodiment represents a complete macro layout solution as:

[0070] in, Represents macro unit The discrete grid positions.

[0071] Therefore, in this embodiment, when each node corresponds to a complete layout solution, the macro-layout optimization problem can be characterized by a search graph. In this embodiment, the search graph can be defined as:

[0072] in, Let E represent the set of nodes for the complete layout solution, and let E represent the set of edges corresponding to the tracing relationships for which local reconstruction is performed. In simpler terms, for a parent and child node connected by a directed edge in the search graph, the edge between the nodes indicates that the layout solution corresponding to the child node is obtained by locally fine-tuning the layout solution corresponding to the parent node.

[0073] Furthermore, in the search graph, for any node , The corresponding layout solution can be denoted as To facilitate iterative optimization and gradually generate child nodes at different levels, this embodiment also maintains the following statistical information in each node:

[0074] in, This indicates the current optimal HPWL for this node. Indicates the number of visits. This represents the best possible price in history. Represents the set of parent nodes. This indicates rollout feasibility statistics, including the number of successes, failures, and cooldown status. These statistics will serve as the basis for selecting parent nodes and the macro set to be refactored in each iteration.

[0075] In this embodiment, the initial search graph consists of candidate nodes corresponding to several pre-generated initial layout solutions. Since parent nodes have not yet been selected and their child nodes generated at this stage, the initial search graph is actually composed of multiple isolated nodes. Based on this, this embodiment will perform iterative optimization based on the initial search graph, so as to gradually fine-tune the selected parent nodes in each round, generate a series of new child nodes, and thus obtain an optimized new layout solution.

[0076] IV. Implement iterative search based on search graph to optimize macro layout.

[0077] The iterative optimization process in this embodiment mainly includes the following steps: (i) Design a node selection function with the goal of balancing layout quality, exploration needs, frontier potential and rollout feasibility, calculate the selection score of all candidate nodes, and select the node with the highest score as the parent node of this round.

[0078] In each round of the MCGS scheme in this embodiment, a parent node needs to be selected as the starting point for local reconstruction. All new feasible solutions generated in this round are fine-tuned based on this parent node. In practical applications, if the current optimal solution is always selected, the search is prone to getting stuck in local optima; if the parent node is randomly selected, a lot of overhead will be wasted. To balance layout quality, exploration requirements, frontier potential, and rollout feasibility, this embodiment designs a node selection function. This function scores each candidate node in the previous round of the search graph at the beginning of each iteration, and then selects the node with the highest score as the parent node for this round.

[0079] Specifically, in this embodiment, for nodes Define its selection score as And satisfy the following formula:

[0080] in, For quality items, For exploration purposes, As a cutting-edge reward item, This is a feasibility penalty item.

[0081] The quality term measures the quality of the node layout. Since the objective is to minimize HPWL, the quality term... It can be defined as follows:

[0082] In the above formula, It is the current globally optimal HPWL. It is a node HPWL is the best in history. It is a small constant to prevent division by zero. The lower the node HPWL, the better. The larger.

[0083] Exploration Item The following UCB form is adopted:

[0084] in, This represents the total number of visits in the graph. Indicates the number of times a node is accessed. This is for exploring coefficients. This option encourages searching for nodes that have fewer visits but may have potential.

[0085] Cutting-edge reward items Used to encourage nodes that have not yet been fully expanded, and calculated by the following formula:

[0086] In the above formula, This represents the unit reward value.

[0087] Feasibility penalty items Used to suppress the repeated generation of illegal or invalid child nodes. Let node... rollout feasibility for:

[0088] The number of consecutive failures is The penalty term is then defined as:

[0089] In summary, the complete form of the node selection function designed in this embodiment is:

[0090] Based on the node selection function, this embodiment selects the node with the highest score from the candidate nodes as the parent node in each round of search. :

[0091] In the above formula, This represents the set of all candidate nodes included in the previous search graph.

[0092] (ii) Based on the adaptive selection strategy set in the search phase, select several macro units with more optimization value as releasable macro units to form the macro set Ω to be reconstructed.

[0093] In each round of the search, after selecting the parent node, the MCGS method also needs to determine the macro set Ω to be reconstructed in this round of local reconstruction. Where M represents the entire set of macrocells to be optimized. For macrocells not belonging to Ω, their positions remain unchanged in this round of local reconstruction; only macrocells within Ω undergo subsequent legitimacy-aware replay. In each round of iterative optimization, if macrocells are randomly released, a large amount of budget may be consumed in regions with little impact on HPWL or RUDY. To overcome this drawback, the MCGS scheme in this embodiment uses a guided proposal mechanism to select macrocells with greater optimization value based on their line length contribution, local space pressure, and geometric features, and these macrocells are designated as the set of macrocells to be reconstructed, Ω.

[0094] Specifically, such as Figure 2 As shown, under the guided proposal mechanism, the generation strategy for the macro set Ω to be reconstructed includes the following steps: (1) Calculate the guiding score based on the net span contribution, local density, boundary pressure, and macrocell area of ​​each macrocell in the macro layout corresponding to the parent node. In this embodiment, any macrocell m i The guiding fraction G(m) i The calculation formula for ) is as follows: ; In the above formula, C net (m i ) represents the contribution of the network span; C density (m i ) represents the local density term; C boundary (m i ) represents the boundary pressure term; C area (m i ) represents the macrocell area term; the above terms can be set or normalized according to the actual circuit size, grid size and search stage. These are the weight coefficients for the corresponding items.

[0095] Network span contribution item C net (m i Used to measure macrocells The impact of the connected network on the overall HPWL. This embodiment can be configured with macrocells. The associated set of wire meshes is: , The contribution of the network span can then be expressed as: .

[0096] If the net span connected to a macrocell is large, it indicates that the position of the macrocell has a significant impact on the net bounding box. Releasing and reconstructing the macrocell is more likely to reduce the total HPWL.

[0097] Local density term C density (m i Used to measure macrocells The degree of spatial congestion in the surrounding area. This embodiment can be configured with macro units. Construct a local neighborhood window centered on the current position. The occupied area in this window is The total window area is Then the local density term can be expressed as:

[0098] when When the value is large, it indicates that the space around the macrocell is relatively crowded, and there may be problems such as unreasonable macrocell arrangement, insufficient movable space, or tight subsequent wiring resources in some areas. Therefore, this area has high reconstruction value.

[0099] Boundary pressure term C boundary (m i Used to measure macrocells The degree of limitation on movable range due to proximity to the chip boundary. Let the width and height of the chip area be respectively... and macrocell The coordinates of the lower left corner are The width and height are respectively and Then the minimum distance from the macrocell to the chip boundary can be expressed as: , The boundary pressure term can be expressed as:

[0100] Alternatively, a normalized form can be used:

[0101] in, This represents the maximum value among all the minimum distances from macrocells to the boundary. The closer a macrocell is to the chip boundary, the more limited its movable range is usually, and the more easily subsequent macrocell placement is affected. Therefore, the system uses a boundary pressure term to increase the probability that this type of macrocell will be selected as a reconstruction sampling anchor.

[0102] Macro-unit area term C area (m i This is used to measure the impact of macrocells on layout space. For macrocells... Its area term can be expressed as Larger macrocells have a more significant impact on chip layout space allocation, and changes in their position may alter the distribution of available space over a larger area. Therefore, they should be given some attention in local reconstruction.

[0103] (2) Based on the current search phase, generate an adaptive number of sampling anchors and a sampling window size.

[0104] In this embodiment, the selection of the macro set to be reconstructed can be defined as selecting one or more macro units from the layout solution of the original parent node, denoting these units as sampling anchors, and then selecting a candidate region centered on the sampling anchors according to a preset sampling window. Each macro unit within the candidate region is then selected as the macro unit to be reconstructed. In this embodiment, the number of sampling anchors and the size of the sampling window have a significant impact on the final selected macro units and are key parameters for generating Ω. To explore the solution space more efficiently, this embodiment sets these two parameters to be dynamically adjustable during the search phase.

[0105] (3) Select a specified number of macrocells from each macrocell as sampling anchors based on the guided score.

[0106] In this embodiment, if the number of sampling anchors is set to 2, then the two macrocells with higher guiding scores are selected as sampling anchors from the macrocells of the parent node, and so on.

[0107] (4) Select each macrocell within a sampling window of a specified size, centered on the sampling anchor, as a releasable macrocell, and thus form the macro set Ω to be reconstructed.

[0108] In this embodiment, after determining the sampling anchor, a local reconstruction region is constructed centered on the sampling anchor according to the sampling window. For any sampling anchor... Let its center coordinates be: This embodiment uses Construct a rectangular or square sampling window centered on the sampler. in, and These represent the sampling widths of the window in the horizontal and vertical directions, respectively. Based on this, this embodiment adds all macrocells located within the sampling window to the set to be reconstructed.

[0109] In practical applications, to avoid difficulties in finding legitimate feasible solutions due to an excessive number of released macrocells, this embodiment can also preset an upper and lower limit on the size of the macro set Ω to be reconstructed. When the size of Ω is higher than the upper limit, macrocells with higher guiding scores, closer connections to the sampling anchor, or greater local density contributions are preferentially retained; when the size of Ω is lower than the upper limit, candidate macrocells are supplemented from macrocells near the sampling anchor or in the same mesh as released macrocells.

[0110] Furthermore, in this embodiment, the size of the preset macro set Ω to be reconstructed can be dynamically adjusted during the search process. The adjustment strategy is as follows: Let T be the interval between the current round and the last round of global optimal update. plateau In this embodiment, T plateauAs an indicator used to evaluate the search phase, a larger value indicates that the search process has not achieved new global improvements for a longer period of time, and the current search may have entered a stable or plateau phase. Therefore, this embodiment is based on T plateau The following strategy is used to adaptively adjust the size of Ω:

[0111] In the above formula, and They are the preset T plateau Mild and severe thresholds; Ω small Ω mid Ω large These represent the minimum, medium, and maximum ranges of the size of Ω, respectively.

[0112] Among them, when The time-representation search process is in the normal phase, where the goal is to make fine adjustments near the current optimal parent node. Therefore, the number of macrocells released and the number of reconstructed regions are relatively small. At this time, the size of the set to be reconstructed should be appropriately reduced to avoid excessive perturbation that could damage the existing optimal layout structure. The time signature indicates entry into the plateau stage. This stage signifies that the search has gone through several rounds without updating the global optimum, and continuing with only small-scale local adjustments may not be enough to escape the current local optimum. Therefore, this embodiment increases the number of macrocells to be released, increases the number of local sampling regions, and increases the number of reconstruction attempts. At this time, the size of the set to be reconstructed is as large as possible. By increasing the reconstruction range, the spatial relationships of macrocells within a larger range can be readjusted, thereby increasing the probability of generating a new layout structure. At this point, the characterization search has continued for a certain number of rounds, triggering the stable-period escape mechanism. The stable-period escape mechanism generates a range of releasable macrocells with a larger perturbation range or stronger randomness. Its set of macrocells to be reconstructed is larger, thus allowing for the use of larger local sampling windows, the selection of multiple sampling anchors to construct multi-region reconstruction sets, and an increase in the sampling ratio. This enables the search to break free from the current local structure and explore layout states with greater differences.

[0113] (iii) Based on the parent node, a preset layout strategy is adopted to reconstruct the layout of each macrocell in Ω according to the macrocell list, thereby generating several feasible solutions that satisfy the legality constraints.

[0114] In this embodiment, the number of feasible solutions generated in each round can be predetermined. Then, based on the macro layout of the original parent node, each macrocell belonging to the macro set Ω to be reconstructed is reset multiple times to obtain the specified number of feasible solutions. For each macrocell to be reconstructed, the reset method includes: Figure 3As shown, the system first generates a position mask to determine whether each candidate mesh would cause boundary overflow or overlap; then it generates a line length mask to calculate the HPWL increment caused when a macrocell is placed on each valid candidate mesh. The system selects the position with the lowest line length increment from the valid candidate positions for placement. After placing each macrocell, the system updates the occupancy matrix and the bounding box of the associated mesh.

[0115] (iv) Calculate the half-perimeter length HPWL of each feasible solution and select a specified number of better solutions as child nodes of the parent node.

[0116] In this embodiment, a parallel mechanism can be used to generate various feasible solutions simultaneously. After completing the local reconstruction, this embodiment filters out illegal sub-solutions and sub-solutions that failed to be reconstructed; then, the legal sub-solutions are sorted according to HPWL. In practical applications, this embodiment not only retains the optimal solution, but also uses a Top-k mechanism to retain a specified number of legal feasible solutions ranked at the top as the required child nodes, so that high-quality candidate layouts with different structures have the opportunity to be further expanded in subsequent rounds.

[0117] This embodiment uses HPWL as an evaluation index to assess the quality of each macro layout; the calculation process of HPWL is as follows: For any net e, in this embodiment, the set of coordinates of all pins connected to the net is set as follows: : . For each pin, the coordinates are: The true coordinates are (x p y p This embodiment first determines the net bounding box based on the actual coordinates of all pins in the net. The width of the net bounding box... and height They are represented as follows:

[0118]

[0119] Then the network The semi-circumference length is defined as .Right now: ; The total half-circuit length of the entire circuit netlist is the sum of the half-circuit lengths of all nets, that is: ; Where E represents the set of nets in the circuit netlist, This represents the total half-circle length corresponding to the complete layout solution S. This metric is used to evaluate the interconnection cost of the current macrocell layout.

[0120] (v) Transpose and merge child nodes to eliminate duplicate solutions, update the search graph and its node attributes, and select some or all nodes in the search graph as new candidate nodes for the next iteration based on the search stage.

[0121] In this embodiment, when generating multiple valid child nodes, each child node corresponds to a complete macro layout. For example... Figure 4 As shown, since each iteration only performs partial reconstruction on a portion of the macrocells within a specified parent node, it is possible that the macro layouts of the partially reconstructed child nodes are identical, or that the generated child nodes have the same macro layout as the candidate nodes retained in previous rounds. To address this issue, this embodiment eliminates duplicate solutions by transposing and merging the child nodes.

[0122] Specifically, assuming a layout solution includes M macrocells, this embodiment organizes the discrete positions of each macrocell into a sequence according to a fixed macrocell numbering order, and can convert this sequence into a corresponding key value. For each retained feasible solution, this embodiment generates a unique key value based on the complete position sequence of its corresponding macro layout. If two layout solutions have the same key value, it means that they correspond to the same complete layout state. That is, the key value assigned to each node in this embodiment can actually be regarded as the "category label" of each node.

[0123] Therefore, if no historical candidate node with the same key value as the newly added feasible solution exists in the original search graph, the macro layout corresponding to the feasible solution is determined to be a completely new scheme. In this case, a new node should be created in the search graph. Conversely, if a historical candidate node with the same key value already exists in the search graph, the feasible solution should be merged into the existing node, and the statistical information of the existing node should be updated. In this way, multiple search paths can share statistical information when reaching the same complete layout state. Through the above transpose merging mechanism, this embodiment enables the same layout state under different search paths to share historical information. This reduces the number of duplicate nodes and makes the guiding score calculated based on the number of node visits, quality estimation, and feasibility statistics more accurate, thereby improving the reliability of parent node selection.

[0124] In this embodiment, after adding new nodes to the search graph based on the search results of each round, the search graph and the node attributes of each node it contains are updated. Based on the updated search graph, this embodiment redetermines candidate nodes and proceeds to the next iteration.

[0125] In a further optimized scheme of this embodiment, during each round of iterative optimization, a stable-period escape and elite archiving mechanism is introduced. The implementation of the stable-period escape mechanism includes: If a parent node successfully generates at least one valid sub-solution in this round of search, its rollout success count and access count are updated; if the parent node fails to generate a valid sub-solution, its failure count is updated. Based on this, when a parent node's consecutive failure count reaches a preset cooling threshold, the node is placed in a cooling state; when the consecutive failure count continues to increase and reaches a failure threshold, the node is marked as a failed node. Cooled nodes are not included in the candidate node selection range for a specified number of subsequent iterations (i.e., they cannot be selected as parent nodes again); failed nodes are not included in the candidate node selection range for all subsequent iterations.

[0126] The implementation methods of the elite archiving mechanism include: Elite nodes are selected and archived from the initial layout solutions to generate an initial set of elite solutions. After each iteration, the retained nodes are selected and archived as elite nodes, and the elite solution set is updated. In this embodiment, the elite solutions in the archive need to simultaneously satisfy a low HPWL and a certain degree of structural diversity.

[0127] Among them, for the two layout solutions and The degree of discrete position difference is defined as :

[0128] In the above formula, and respectively layout solution and The discrete grid position of the i-th macrocell.

[0129] Then when a new feasible solution When a candidate is added to the archive, if its minimum distance from an existing archived solution is greater than a threshold... If a solution's HPWL is significantly better than a worse solution in the archive, then it is added to the archive.

[0130] This embodiment can also preset the size of the elite solution set. When any feasible solution triggers the archiving size to exceed the maximum capacity during archiving, the archiving is rebuilt according to HPWL and diversity, and solutions with low HPWL and large differences from each other are preferentially retained.

[0131] In this embodiment, the purpose of setting up an elite solution set is to periodically use the elite solution set instead of candidate nodes to generate the required parent nodes. Specifically, assuming the elite solution set is activated every 9 rounds, the adjustment cycle for the parent node selection range is 10 rounds. In every 10 iterations, the first 9 rounds select parent nodes from the candidate node set consisting of nodes from the previous round's search graph and newly added child nodes, while in the 10th round, the parent nodes for this round are selected from the elite solution set.

[0132] By employing a stable-period escape and elite archiving mechanism, this embodiment can prioritize fine-grained optimization in the early and middle stages of the search, utilizing key macrocell regions with large network span contributions, high local density, strong boundary pressure, or large areas. When the search fails to produce global improvement for an extended period, the system can automatically increase the perturbation range and periodically introduce stronger randomness, thereby enhancing its ability to escape local optima. Furthermore, compared to local reconstruction methods that release macrocells completely randomly, this mechanism can concentrate the search budget on regions more likely to reduce HPWL and improve local layout structure. Compared to local search methods with fixed perturbation intensity, this mechanism can adaptively adjust the reconstruction scale based on the degree of search stagnation, enabling the complete solution search to maintain continuous optimization capabilities even in later stages.

[0133] Finally, after the iteration terminates, the globally optimal node is output as the optimized macro layout. In this embodiment, the iteration termination condition can be set from three dimensions: the number of iterations, the search time, or the quality of the globally optimal solution. For example, the iteration termination condition can be set to reaching a preset number of search rounds, reaching a time limit, or satisfying a convergence condition. After the iteration terminates, this embodiment will output the macro cell layout file corresponding to the current globally optimal node. If necessary, it can also output search logs, round-by-round index files, and intermediate checkpoint files that characterize the search process.

[0134] Example 2

[0135] The macrocell layout optimization method based on Monte Carlo map search provided in Example 1 is essentially a data processing method. In order to better apply this scheme, this example further provides related computer storage media, computer program products and circuit design optimization equipment.

[0136] The computer storage medium provided in this embodiment stores a computer program. When the computer program is executed by the processor, it implements the macrocell layout optimization method based on Monte Carlo map search as in Embodiment 1, thereby obtaining the design parameters of the chip to be designed and generating the optimal layout that satisfies the legality constraints.

[0137] The computer program product provided in this embodiment includes a computer program. When the computer program is executed by the processor, it implements the macrocell layout optimization method based on Monte Carlo map search as in Embodiment 1, thereby obtaining the design parameters of the chip to be designed and generating the optimal layout that satisfies the legality constraints.

[0138] The circuit design optimization device provided in this embodiment includes a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements the macrocell layout optimization method based on Monte Carlo map search as in Embodiment 1, thereby obtaining the design parameters of the chip to be designed and generating an optimal layout that satisfies the legality constraints.

[0139] In practical applications, the circuit design optimization device provided in this embodiment is essentially a computer device. This computer device can employ embedded chips or a computing terminal capable of executing programs. Examples include: smartphones, tablets, laptops, desktop computers, rack servers, blade servers, tower servers, or cabinet servers (including standalone servers or server clusters composed of multiple servers), etc.

[0140] The computer device in this embodiment includes, but is not limited to, a memory and a processor that can be interconnected via a system bus. In this embodiment, the memory (i.e., the readable storage medium) includes flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory can be an internal storage unit of the computer device, such as the hard disk or RAM of the computer device. In other embodiments, the memory can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc. Of course, the memory can also include both internal storage units and external storage devices of the computer device. In this embodiment, the memory is typically used to store the operating system and various application software installed on the computer device. Furthermore, the memory can also be used to temporarily store various types of data that have been output or will be output. In some embodiments, the processor may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. The processor is typically used to control the overall operation of a computer device.

[0141] Simulation test

[0142] To verify the macrocell layout optimization method based on Monte Carlo map search provided by this invention, technicians simulated relevant schemes and compared the performance of this invention with some existing typical schemes on some typical circuits. The process and results of the test experiments are as follows: (a) Experimental conditions The experimental platform for this study was a server equipped with an Intel(R) Xeon(R) Gold 6226 CPU @ 2.70GHz (24 cores) and an NVIDIA RTX 3090 GPU. Macrounit experiments were conducted using the ISPD2005 dataset, including eight circuits: adaptec1, adaptec2, adaptec3, adaptec4, bigblue1, bigblue2, bigblue3, and bigblue4. Each benchmark used five random seeds. The primary evaluation metric was macro HPWL, and the values ​​needed to be calculated... A lower value indicates a lower interconnection cost between macrocells. Comparison methods include DREAMPlace, DeepPlace, MaskPlace, WireMask-EA, EfficientPlace, and RollPlace.

[0143] (II) HPWL Comparison

[0144] Visualizations of partial results of the layout optimization schemes of the present invention and the comparative scheme on various circuits are shown below. Figure 5 As shown in the table below, the macro HPWL performance of different schemes on various circuits is further statistically analyzed: Table 1: HPWL performance comparison between the present invention and different schemes in the control group

[0145] Analyzing the data in the table above reveals the following: From the perspective of method categories, analytical methods such as DREAMPlace are fast on some circuits, but their continuous optimization process has limited expressive power for discrete macro-level reconstruction; learning methods such as MaskPlace and EfficientPlace can quickly generate better layouts, but are still limited by sequential generation and local exploration range; WireMask-EA and RollPlace improve layouts through local replay, but lack cross-path state reuse at the complete solution level.

[0146] The MCGS scheme of this invention achieves optimal performance on multiple circuits. Compared with previously disclosed optimal or near-optimal comparative methods, MCGS reduces HPWL by approximately 4.33%, 8.92%, 4.12%, 21.45%, 3.34%, 15.81%, 16.11%, and 12.65% on adaptec1, adaptec2, adaptec3, adaptec4, bigblue1, bigblue2, bigblue3, and bigblue4, respectively, with an average reduction of approximately 10.84%. The improvements on adaptec4, bigblue2, bigblue3, and bigblue4 are particularly significant, indicating that complete solution graph search and guided rebuild have stronger late-stage optimization capabilities in complex macro-layout spaces. Its advantages stem from the combination of complete-solution graph, Transposition Merge, Graph-UCB, and guided proposal, enabling it to explore different local reconstruction paths while preserving high-quality solutions.

[0147] (III) Comparison of cabling congestion

[0148] Reporting only HPWL does not fully illustrate the routerbability of the layout; this experiment also verifies whether the MCGS scheme introduces local congestion while reducing wire length. Based on the previous experiments, the average RUDY demand of the top-10% most congested meshes in each layout was further calculated, and the minimum mean value on each benchmark was normalized to 1. The experimental results are shown in Table 2. Table 2: Comparison of RUDY performance between the present invention and the control group of different schemes

[0149] Analysis of the data in the table above shows that: Except for the bigblue1 circuit, the solution of this invention achieved the best performance on all other circuits. This is related to the guiding mechanism used in MCGS when generating the set of macros to be reconstructed. Based on this mechanism, this invention tends to release long-line related macros in each round of reconstruction, pay attention to local crowded regions, and help identify macro cells that are restricted by boundaries.

[0150] 4. Convergence Curve

[0151] This experiment further plotted the convergence curves of the macroHPWL index for the layout optimization process of the present invention and the control group scheme on 8 circuits. The results are as follows: Figure 6 and Figure 7 As shown in the figure. Analyzing the data in the figure reveals that: As can be observed from the convergence curves, MCGS exhibits a more stable mid-to-late-stage decline trend on most circuits. Compared to single-chain search, the optimization strategy based on complete layout solutions in this invention can retain multiple high-quality candidate states; compared to strategies that only retain the optimal child node, the Top-k sub-solution retention of this invention can provide more entry points for subsequent improvements; compared to a fixed-strength macroset to be reconstructed, the plateau escape of this invention can expand the perturbation range when the search stagnates. Therefore, MCGS not only achieves a lower final result but also retains strong continuous optimization capabilities in the later stages.

[0152] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A macrocell layout optimization method based on Monte Carlo map search, characterized in that, It includes: Obtain the design parameters of the chip to be optimized, mesh the layout area, and generate a list of macrocells representing the arrangement order based on preset indicators; A preset layout strategy is adopted to sequentially lay out each macro cell according to the macro cell list, thereby generating several initial layout solutions that satisfy the legality constraints. Each initial layout solution is used as a candidate node to generate a search graph, where each valid layout solution is used as a node, and the edges between nodes are used to represent the source relationships for performing local reconstruction; and the following iterative optimization is performed based on the search graph: (i) Design a node selection function with the goal of balancing layout quality, exploration needs, frontier potential and rollout feasibility, calculate the selection score of all candidate nodes, and select the node with the highest score as the parent node of this round; (ii) Based on the adaptive selection strategy set in the search phase, select several macro units with more optimization value as releasable macro units to form the macro set Ω to be reconstructed; (iii) Based on the parent node, a preset layout strategy is adopted to reconstruct the layout of each macrocell in Ω according to the macrocell list, thereby generating several feasible solutions that satisfy the legality constraints. (iv) Calculate the half-perimeter length HPWL of each feasible solution and select a specified number of better solutions as child nodes of the parent node. (v) Transpose and merge child nodes to eliminate duplicate solutions, update the search graph and its node attributes, and select some or all nodes in the search graph as new candidate nodes for the next iteration based on the search stage. After the iteration stops, the globally optimal node is output as the optimized macro layout.

2. The macrocell layout optimization method based on Monte Carlo map search as described in claim 1, characterized in that: The macrocell area is used as the optimal indicator, the total area of ​​connected macrocells is used as the second-optimal indicator, and the number of associated Nets is used as the third-optimal indicator. The macrocells are sorted in a multi-level manner to generate the macrocell list. And / or, the legality constraints include boundary constraints and non-overlapping constraints; And / or, the preset layout strategy includes: first, randomly generating the initial positions of all macro cells within the layout area, and then using a greedy strategy to adjust the positions of each macro cell in turn according to the macro cell list to obtain a global layout diagram that satisfies the legality constraints; And / or, methods for transposing and merging child nodes to exclude duplicate solutions include: calculating the node key value based on the global layout graph corresponding to the node, with each global layout graph having a unique key value; and deleting the child node if the newly added child node has the same key value as any other node.

3. The macrocell layout optimization method based on Monte Carlo map search as described in claim 2, characterized in that: The calculation formula for the node selection function is as follows: ； In the above formula, Score(v) represents the selection score of node v; HPWL best B represents the current globally optimal HPWL; v HPWL is the best way to represent the history of node v. It is a preset constant to prevent division by zero; N total N represents the total number of visits to each node in the graph. v The number of times node v is visited is represented by c; the exploration coefficient is represented by F(v); the frontier reward is represented by r. v f represents the rollout feasibility of node v; v Indicates the number of consecutive failures; f max This indicates the preset maximum number of failures; and These are the combined weights of the rollout feasibility rate and the number of failures in the penalty item.

4. The macrocell layout optimization method based on Monte Carlo map search as described in claim 1, characterized in that: The generation strategy for the macro set Ω to be reconstructed includes: (1) Calculate the guiding score based on the net span contribution, local density, boundary pressure and macro cell area of ​​each macro cell in the macro layout corresponding to the parent node; (2) Based on the current search stage, generate an adaptive number of sampling anchors and a sampling window size; (3) Select a specified number of macrocells as sampling anchors from each macrocell based on the guided score; (4) Select each macrocell within a sampling window of a specified size centered on the sampling anchor as a releasable macrocell, thereby forming the macro set Ω to be reconstructed; And / or, preset an upper and lower limit for the size of the macro set Ω to be reconstructed. When the size of Ω is higher than the upper limit, prioritize retaining macro cells with higher guiding scores, closer connections to the sampling anchor, or greater local density contributions. When the size of Ω is lower than the upper limit, supplement a specified number of candidate macro cells from macro cells near the sampling anchor or in the same mesh as releasable macro cells.

5. The macrocell layout optimization method based on Monte Carlo map search as described in claim 4, characterized in that: In the parent node, any macrounit m i The guiding fraction G(m) i The calculation formula for ) is as follows: ； In the above formula, C net (m i ) represents the contribution of the network span; C density (m i ) represents the local density term; C boundary (m i ) represents the boundary pressure term; C area (m i ) represents the area term of the macro unit; These are the weight coefficients for the corresponding items; And / or, let T be the interval between the current round and the last round of global optimal update. plateau According to T plateau The following strategy is used to adaptively adjust the size of Ω: In the above formula, and They are the preset T plateau Mild and severe thresholds; Ω small Ω mid Ω large These represent the minimum, medium, and maximum ranges of the size of Ω, respectively.

6. The macrocell layout optimization method based on Monte Carlo map search as described in claim 5, characterized in that: In each round of iterative optimization, if the parent node successfully generates at least one valid sub-solution in this round of search, then the parent node's rollout success count and access count are updated; if the parent node fails to generate a valid sub-solution, then the parent node's failure count is updated. When the number of consecutive failures reaches the preset cooling threshold, the node is placed in a cooling state; when the number of consecutive failures continues to increase and reaches the failure threshold, the node is marked as a failed node. Cooling nodes will not be included in the candidate node selection range for a specified number of subsequent iterations; failed nodes will not be included in the candidate node selection range for all subsequent iterations.

7. The macrocell layout optimization method based on Monte Carlo map search as described in claim 6, characterized in that: And / or, perform elite node selection and archiving on the initial layout solution to generate an initial elite solution set. ; After each iteration, the retained nodes are selected and archived as elite nodes, and the elite solution set is updated. ; Elite solution sets are periodically used to replace candidate nodes in order to generate the required parent nodes.

8. A computer storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the macrocell layout optimization method based on Monte Carlo map search as described in any one of claims 1-7, thereby obtaining the design parameters of the chip to be designed and generating the optimal layout that satisfies the legality constraints.

9. A computer program product comprising a computer program, characterized in that: When the computer program is executed by the processor, it implements the macrocell layout optimization method based on Monte Carlo map search as described in any one of claims 1-7, thereby obtaining the design parameters of the chip to be designed and generating the optimal layout that satisfies the legality constraints.

10. A circuit design optimization device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the computer program, it implements the macrocell layout optimization method based on Monte Carlo map search as described in any one of claims 1-7, thereby obtaining the design parameters of the chip to be designed and generating an optimal layout that satisfies the legality constraints.

Images