Chip verification methods, apparatus, computing devices, and machine-readable storage media

Abstract

This application discloses a chip verification method, apparatus, computing device, and machine-readable storage medium, belonging to the field of device testing. The chip verification method includes: constructing a verification state transition graph composed of nodes and edges based on the transaction execution stage, stage transition relationship, and constraint attributes corresponding to the target chip; updating the heat value of each node in the verification state transition graph based on the coverage item hit information corresponding to the node, obtaining an updated verification state transition graph; performing path planning based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain; outputting verification stimuli through the abstract state transition chain and constraint attributes constraining a preset large language model; and iteratively verifying the target chip based on the verification stimuli. By constructing a collaborative architecture of logical planning and code generation, and based on the rigor of temporal logic, it is possible to accurately verify verification blind spots, improving chip verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of equipment testing, and more specifically to a chip verification method, apparatus, computing device, and machine-readable storage medium. Background Technology

[0002] With the continuous advancement and development of integrated circuit manufacturing processes, the scale of SoC (System on Chip) design has exceeded tens of billions of transistors, and its complexity is increasing exponentially. In the chip design flow, chip verification accounts for approximately 70% of the R&D cycle. Currently, traditional Constrained Random Verification (CRV) techniques and verification stimulus generation techniques such as static formalization and graph search all have significant technical bottlenecks. How to efficiently generate high-quality test stimuli to cover all boundary cases and potential defects in the design is a major challenge facing the field of electronic design automation.

[0003] Traditional constrained stochastic verification techniques essentially involve blind random exploration. In the later stages of chip verification, to fill remaining coverage blind spots, the solver often needs to make a massive number of invalid attempts just to encounter an uncovered state. This results in significant waste of computational resources and slow convergence speed in the later stages of chip verification. Furthermore, for complex cross-clock domain or long-sequence protocol interactions, traditional constrained stochastic verification techniques struggle to construct legitimate timing scenarios using simple random constraints. Engineers often need to manually write targeted tests, leading to high labor costs and low chip verification efficiency. Static formalization and graph search techniques are typically static and one-off, unable to detect changes in functional coverage during simulation. Even after seeing blind spots in the coverage report, verification engineers still need to manually analyze the graph and adjust test strategies, failing to achieve true automated closed-loop processing and further contributing to low chip verification efficiency. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the present invention aims to provide a chip verification method, apparatus, computing device and machine-readable storage medium to solve the problem of low chip verification efficiency.

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a chip verification method, apparatus, computing device and machine-readable storage medium to solve the problem of low chip verification efficiency.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: Firstly, this application provides a chip verification method, the chip verification method comprising:

[0007] Based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip, construct a verification state transition graph composed of nodes and edges;

[0008] Based on the coverage item hit information corresponding to the node, the heat value of each node in the verification state transition graph is updated to obtain the updated verification state transition graph. The coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node.

[0009] Path planning is performed based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain.

[0010] The validation stimulus is output by pre-setting a large language model through abstract state transition chains and constraint attributes;

[0011] The target chip is iteratively verified based on verification stimuli.

[0012] In the embodiments of this application, a verification state transition graph consisting of nodes and edges is constructed based on the transaction execution stage, stage transition relationship, and constraint attributes corresponding to the target chip, including:

[0013] Information is extracted from the interface specification of the target chip to obtain the constraints, all transaction execution stages, and the stage transition relationships corresponding to each transaction execution stage during the interface transaction execution process of the target chip.

[0014] Based on constraints and preset verification constraint information, generate constraint attributes corresponding to each transaction execution stage.

[0015] A verification state transition graph consisting of nodes and edges is constructed by representing the transaction execution phases and constraint attributes through nodes and the phase transition relationships through edges.

[0016] In the embodiments of this application, the heat value of each node in the verification state transition graph is updated according to the coverage item hit information corresponding to the node, resulting in an updated verification state transition graph, including:

[0017] If the current verification round is not the first round, the heat value of each node in the verification state transition graph is updated based on the coverage hit information, hit threshold and historical heat value of the node in the current verification round. The updated verification state transition graph is obtained, where the historical verification round is the previous verification round of the current verification round.

[0018] In the embodiments of this application, path planning is performed based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain, including:

[0019] Based on the node heat value distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint.

[0020] For each edge of the updated verification state transition graph, the passage cost of each edge is defined based on the heat value of the node corresponding to each edge;

[0021] Based on the travel cost of each edge, calculate the minimum travel cost path to the end point in the updated verification state transition graph, and determine the minimum travel cost path as the abstract state transition chain.

[0022] In the embodiments of this application, based on the node heat value distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint, including:

[0023] Based on the node popularity value distribution of the updated verification state transition graph, a target node set is selected, wherein the popularity value of all nodes in the target node set is less than the preset popularity threshold.

[0024] If the target node set is not empty, any node in the target node set will be used as the path endpoint.

[0025] If the target node set is empty, any node in the updated verification state transition graph will be used as the path endpoint.

[0026] In the embodiments of this application, the output verification stimulus of the preset large language model is constrained by the abstract state transition chain and constraint attribute constraints, including:

[0027] Convert abstract state transition chains and constraint attributes into structured cue words;

[0028] The structured prompts are input into a pre-defined large language model, and the pre-defined large language model is constrained to output validation stimuli.

[0029] In the embodiments of this application, iterative verification of the target chip based on verification stimuli includes:

[0030] The target chip is simulated and tested based on the verification stimulus, and the simulation test results are obtained.

[0031] Based on the simulation test results, determine whether at least one critical node fails to meet the verification requirements. A critical node is any node in the verification state transition diagram.

[0032] If at least one critical node fails to meet the verification requirements, the following steps are performed: update the heat value of each node in the verification state transition graph based on the coverage item hit information corresponding to the node, and obtain the updated verification state transition graph.

[0033] Once all critical nodes meet the verification requirements, the verification results for the target chip are generated.

[0034] Secondly, this application provides a chip verification apparatus, comprising:

[0035] The verification state transition graph construction module is used to construct a verification state transition graph consisting of nodes and edges based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip.

[0036] The node heat value update module is used to update the heat value of each node in the verification state transition graph according to the coverage item hit information corresponding to the node, so as to obtain the updated verification state transition graph. The coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node.

[0037] The path planning module is used to perform path planning based on the node heat value distribution of the updated verification state transition graph, and obtain the abstract state transition chain.

[0038] The verification stimulus output module is used to output verification stimuli by constraining the preset large language model through the abstract state transition chain and constraint attributes.

[0039] The iterative verification module is used to perform iterative verification of the target chip based on verification stimuli.

[0040] Thirdly, this application provides a computing device, comprising:

[0041] The memory is configured to store instructions;

[0042] The processor is configured to retrieve instructions from memory and, when executing instructions, to implement the aforementioned chip verification method.

[0043] Fourthly, this application provides a machine-readable storage medium storing instructions that cause a machine to perform the chip verification method described above.

[0044] Therefore, this application provides a chip verification method, comprising: constructing a verification state transition graph composed of nodes and edges according to the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip; updating the heat value of each node in the verification state transition graph according to the coverage item hit information corresponding to the node, thereby obtaining an updated verification state transition graph, wherein the coverage item hit information is attached to the corresponding node according to the mapping relationship between the coverage item and the node; performing path planning based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain; outputting verification stimuli by constraining a preset large language model through the abstract state transition chain and constraint attributes; and iteratively verifying the target chip based on the verification stimuli.

[0045] Compared with the prior art, the beneficial effects of the present invention are:

[0046] This application provides a large language model collaborative generation incentive mechanism based on verification state transition graph constraints, decoupling incentive generation into macroscopic logical planning and microscopic code implementation. By leveraging the topological structure of the verification state transition graph to enforce temporal locking, and using only the large language model for restricted code instantiation, the temporal illusion of the large language model in long sequence generation is eliminated while preserving its generation efficiency.

[0047] By introducing coverage heat values, verification blind spots are visualized as node heat values ​​in the verification state transition graph. Path planning based on node heat values ​​can proactively avoid areas that are tested multiple times, reducing the generation of redundant test cases. This transforms the verification mode from blind random exploration to goal-oriented targeted generation, significantly improving the convergence speed of functional coverage and thus enhancing chip verification efficiency.

[0048] Furthermore, the constructed verification state transition graph can simultaneously represent the stage transition relationships and constraint attributes corresponding to the transaction execution stages. It can not only handle timing jumps but also adapt to complex data constraints such as address alignment and burst length limits. The verification stimuli generated by the large language model can adapt to chip verification scenarios of varying complexity, realizing a fully automated closed loop from verification planning to verification stimulus generation. This reduces the cost of manually writing targeted test cases, improving chip verification efficiency and demonstrating strong universality and engineering applicability. Attached Figure Description

[0049] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0050] Figure 1 This is a flowchart of a chip verification method according to an embodiment of the present invention;

[0051] Figure 2 This is an example diagram of the data structure of a node according to an embodiment of the present invention;

[0052] Figure 3 This is an example diagram of the mapping relationship and node heat values ​​according to an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram illustrating the principle of path planning according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the structure of a chip verification device according to an embodiment of the present invention. Detailed Implementation

[0055] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the present invention.

[0056] The components of the embodiments of the invention described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0057] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of the invention, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0058] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0059] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the invention pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of the invention.

[0060] With the rapid development of large language model technology, pre-trained large language models possess a certain logical thinking chain and contextual understanding ability, making it feasible to generate test code using large language models. However, when dealing with extremely stringent hardware protocols, the autoregressive generation mode based on probability distribution of large language models cannot guarantee the consistency of timing logic. If large language models are directly applied to chip verification scenarios to handle complex chip bus protocols such as AXI (Advanced eXtensible Interface) and PCIE (Peripheral Component Interconnect Express), the test code generated by the large language model may exhibit logical illusions, meaning that the code generated by the large language model is syntactically correct but functionally invalid. For example, when the chip's interface specification is typically input into the large language model, which then dominates the logical decisions of the test sequence, the large language model may generate code that violates the protocol's timing rules, causing the code to fail compilation or simulation and crash. Furthermore, since large language models lack real-time interactive feedback with the dynamic simulation environment during generation, they exhibit a pre-defined generation state. During multiple rounds of verification, the generation focus cannot be automatically adjusted according to the actual coverage progress, which may result in a large amount of blind repetitive work in the verification process, leading to low chip verification efficiency.

[0061] Example 1

[0062] Please see Figure 1 , Figure 1 This is a flowchart of a chip verification method according to an embodiment of the present invention. Figure 1 The chip verification methods include:

[0063] S110: Based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip, construct a verification state transition graph composed of nodes and edges.

[0064] Before generating chip verification stimuli, the set of transaction execution stages, stage transition relationships, and constraint attributes used for verification guidance are obtained. The type of target chip is set according to actual needs and can be any chip that needs to be verified; there is no limitation here. After obtaining each transaction execution stage of the target chip, as well as the corresponding stage transition relationships and constraint attributes, the transaction execution stages and stage transition relationships are abstracted into nodes, and the constraint attributes are abstracted into edges, constructing a verification state transition graph composed of nodes and edges. The constructed verification state transition graph is the initial static topology graph, serving as the basic search space for subsequent path planning and stimulus generation.

[0065] S120, based on the coverage item hit information corresponding to the node, update the heat value of each node in the verification state transition graph to obtain the updated verification state transition graph, wherein the coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node.

[0066] Coverage items refer to specific, measurable coverage targets defined during the verification process to ensure that the functional requirements of the chip design are fully tested. Chip verification scenarios typically require multiple rounds of simulation testing, obtaining coverage item hit information from the simulation tool output. Based on the mapping relationship between coverage items and nodes, the hit information of functional coverage items is attached to the corresponding nodes. Based on the coverage item hit information corresponding to a node, the hit count of the functional coverage items attached to the node is converted into a node heat value attribute, thereby updating the heat value of each node in the verification state transition graph, resulting in an updated verification state transition graph. This transforms the discrete simulation results into a weight distribution on the nodes of the verification state transition graph.

[0067] S130, Path planning is performed based on the node heat value distribution of the updated verification state transition graph to obtain the abstract state transition chain.

[0068] After updating the popularity value of each node in the validation state transition graph, the coverage is quickly determined by the distribution of node popularity values ​​in the validation state transition graph. Path planning is then performed based on the updated node popularity value distribution in the validation state transition graph to obtain an abstract state transition chain. Specifically, based on the updated node popularity value distribution in the validation state transition graph, nodes with low popularity values ​​are selected as target nodes. Path planning is then performed using these target nodes, and the calculated abstract test path, i.e., the abstract state transition chain, is used to transform the coverage feedback into a concrete test path.

[0069] S140 outputs verification stimuli by using abstract state transition chains and constraint attribute constraints to pre-set large language models.

[0070] The node information and constraint attributes on the abstract state transition chain are input into a preset large language model. Structured generated prompts serve as contextual constraints, and the test sequence output by the preset large language model is then constrained by the abstract state transition chain, thus constraining the validation stimulus. It is important to understand that the type of preset large language model is set according to actual needs and is not limited here.

[0071] The previous approach, which directly input the chip's interface specification into a large language model to generate verification stimuli, relies entirely on the language model to control the logical decisions of the test sequence, representing an end-to-end black-box generation model. This application provides a chip verification method that differs from this end-to-end black-box generation model. Instead of relying on a large language model for logical decision-making in the test sequence, this method strictly reduces the functionality of the large language model to a constrained code synthesis engine. An abstract state transition chain, acting as a context constraint, forces the large language model to instantiate each abstract node on the path into concrete test code. This verification stimulus generation process leverages the powerful coding capabilities of the large language model while eliminating the randomness of the language model's temporal logic through strict path planning constraints.

[0072] S150 performs iterative verification of the target chip based on verification stimuli.

[0073] The verification stimuli are output to the simulation environment for automatic compilation, loading, and execution, and then iterative verification of the target chip is performed based on the verification stimuli. If the output verification stimuli reach blind nodes with low heat values, the hit count of the coverage items attached to the nodes will increase. By generating verification stimuli multiple times, iterative verification of the target chip based on the verification stimuli is performed, thereby realizing an automated closed loop of the verification process.

[0074] This application provides a large language model collaborative generation incentive mechanism based on verification state transition graph constraints, decoupling incentive generation into macroscopic logical planning and microscopic code implementation. By leveraging the topological structure of the verification state transition graph to enforce temporal locking, and using only the large language model for restricted code instantiation, the temporal illusion of the large language model in long sequence generation is eliminated while preserving its generation efficiency.

[0075] By introducing coverage heat values, verification blind spots are visualized as node heat values ​​in the verification state transition graph. Path planning based on node heat values ​​can proactively avoid areas that are tested multiple times, reducing the generation of redundant test cases. This transforms the verification mode from blind random exploration to goal-oriented targeted generation, significantly improving the convergence speed of functional coverage and thus enhancing chip verification efficiency.

[0076] Furthermore, the constructed verification state transition graph can simultaneously represent the stage transition relationships and constraint attributes corresponding to the transaction execution stages. It can not only handle timing jumps but also adapt to complex data constraints such as address alignment and burst length limits. The verification stimuli generated by the large language model can adapt to chip verification scenarios of varying complexity, realizing a fully automated closed loop from verification planning to verification stimulus generation. This reduces the cost of manually writing targeted test cases, improving chip verification efficiency and demonstrating strong universality and engineering applicability.

[0077] In the embodiments of this application, a verification state transition graph consisting of nodes and edges is constructed based on the transaction execution stage, stage transition relationship, and constraint attributes corresponding to the target chip, including:

[0078] Information is extracted from the interface specification of the target chip to obtain the constraints, all transaction execution stages, and the stage transition relationships corresponding to each transaction execution stage during the interface transaction execution process of the target chip.

[0079] Based on constraints and preset verification constraint information, generate constraint attributes corresponding to each transaction execution stage.

[0080] A verification state transition graph consisting of nodes and edges is constructed by representing the transaction execution phases and constraint attributes through nodes and the phase transition relationships through edges.

[0081] After identifying the target chip to be verified, the interface specification document of the target chip is obtained, along with preset verification constraint information. In this embodiment, information extraction is performed using a large language model. Specifically, the interface specification document is converted into a parsable text format. Based on a preset information extraction template, the large language model is invoked to parse and extract structured information from the converted interface specification document text, obtaining the constraints of the target chip during interface transaction execution, all transaction execution stages, and the stage transition relationships corresponding to each transaction execution stage. The information extraction template is predefined for the interface specification document parsing task and is used to constrain the large language model to output constraints, all transaction execution stages, and stage transition relationships in a unified format, thereby enabling the extracted information to be further structured and written into the verification state transition diagram.

[0082] For ease of understanding, this embodiment uses AXI write transactions and takes a full FIFO (First Input First Output) queue as an example to extract information from the target chip's interface specification to obtain the transaction execution stages with a time sequence. The transaction execution stages identified in this embodiment include the idle stage, write address stage, write data stage, and write response stage. For ease of understanding, in this embodiment, the idle stage is abbreviated as Idle, the write address stage as AW, the write data node as W, and the response stage as B.

[0083] Contextual analysis is performed on the descriptions related to each transaction execution stage to extract data validity rules and stage transition triggering conditions related to the transaction execution stage, and these are written into the constraint attribute fields of the nodes. For example, for the idle stage, the burst length constraint can be extracted as Burst_Length≤16 and the address alignment constraint as Address_Align_4KB. For stage transition relationships, the establishment of the VALID / READY handshake can be extracted as the stage advancement condition in the stage transition relationship. In the embodiments of this application, externally preset verification constraint information is also received. The verification constraint information is set according to actual needs and can be user-input constraints or target constraints specified by the verification plan, which are not limited here. The verification constraint information is used as supplementary constraints. Based on the constraint conditions and the preset verification constraint information, constraint attributes corresponding to each transaction execution stage are generated. For example, the constraint attributes can be specified as at least one of FIFO full state, write enable restriction Write_Enable=0, and requirement to maintain the blocking state for Hold_Cycles=3 clock cycles.

[0084] In the embodiments of this application, let node v be, directed edge e be, all node set be V, all directed edge set be E, and the constructed verification state transition graph be G, then G=(V,E). Each transaction execution stage corresponds to a node v∈V, and each stage transition relationship corresponds to a directed edge e=(u→v)∈E.

[0085] Please see Figure 2 , Figure 2 This is an example diagram of the data structure of a node according to an embodiment of the present invention.

[0086] As shown in the figure, the constraints extracted from the interface specification and the externally preset verification constraints are jointly written into the node's data structure. The node's data structure includes, but is not limited to, a stage identifier field, constraint attribute fields, and extended attribute fields. The stage identifier field indicates the transaction execution stage corresponding to the node; the constraint attribute fields record the data constraints and control conditions under the transaction execution stage; and the extended attribute fields store information such as the obtained heat value and associated coverage item identifier. The node not only represents the current transaction execution stage but also the control conditions and data constraints that must be satisfied under the current transaction execution stage.

[0087] An edge set is established based on the legal sequence of events during interface interactions. For example, directed edges could be Idle→AW, AW→W, and W→B, etc., without limitation. Nodes represent the transaction execution stages and constraint attributes, and edges represent stage transition relationships, constructing an initial static topology for the verification state transition graph. This initial static topology provides a set of feasible transition paths for path planning and is used to prevent illegal stage jumps during the stimulus generation process.

[0088] In the embodiments of this application, the heat value of each node in the verification state transition graph is updated according to the coverage item hit information corresponding to the node, resulting in an updated verification state transition graph, including:

[0089] If the current verification round is not the first round, the heat value of each node in the verification state transition graph is updated based on the coverage hit information, hit threshold and historical heat value of the node in the current verification round. The updated verification state transition graph is obtained, where the historical verification round is the previous verification round of the current verification round.

[0090] If the current verification round is not the first round, the coverage item hit information is obtained from the coverage statistics output by the simulation tool, and all coverage item hit information is organized into a coverage database. A hierarchical path matching algorithm based on regular expressions is used to establish the mapping relationship between coverage items and nodes. Specifically, the mapping relationship between coverage items and nodes is determined by comprehensively considering information such as coverage item name, hierarchical path, associated signal identifier, and transaction execution stage label, and coverage items are merged into one or more corresponding nodes.

[0091] Based on the coverage item hit information, hit threshold, and historical heat values ​​of nodes in the current verification round, the heat value of each node in the verification state transition graph is updated to obtain the updated verification state transition graph. Specifically, after the simulation of each historical verification round is completed, the sum of the hit counts of the coverage item corresponding to each node in the historical verification rounds is calculated, and a hit threshold is set. The coverage item hit count in the current verification round is normalized to a coverage ratio, and the heat value of the node is updated using a weighted smoothing method.

[0092] Formula (1)

[0093] Formula (2)

[0094] Where t is the current verification round, t-1 is the historical verification round, and h i (t) N represents the coverage ratio. i (t) K is the sum of the number of hits in the historical verification rounds. i H is the hit threshold. i (t-1) For historical verification rounds, the historical heat value obtained from each iteration, H i (t) α represents the heat value of the node after the current verification round update, where α is the smoothing coefficient and 0 ≤ α ≤ 1.

[0095] In embodiments of this application, the chip verification method further includes:

[0096] Given that the current verification round is the first round, the heat value of each node in the verification state transition graph is set to zero.

[0097] Please see Figure 3 , Figure 3 This is an example diagram of the mapping relationship and node heat value according to an embodiment of the present invention.

[0098] In the current cold start scenario (first round of verification), lacking coverage hit information, the heat value of each node in the verification state transition graph is set to zero. As shown in the figure, based on the mapping relationship between coverage items and nodes, the hit information of functional coverage items is attached to the corresponding nodes. In the figure, red nodes represent measured areas with high heat values, such as nodes in the write address stage with heat values ​​approaching 0.9. Dark blue nodes represent verification blind spots with heat values ​​close to 0, such as nodes corresponding to the FIFO full state. By mapping coverage hit information to heat values, discrete coverage statistics are converted into weight distributions attached to nodes, thus forming a visualized and computable heat topology and providing a cost basis for path planning.

[0099] In this embodiment, a weighted smoothing method is used to verify the heat value of each node in the state transition graph. This method can simultaneously reflect the coverage of the node in the current verification round and retain verification information from previous rounds, thereby avoiding excessive disturbance to path planning caused by fluctuations in a single simulation round. If the heat value of a node approaches 1, it is determined that the node has been fully verified; if the heat value of a node approaches 0, it is determined that the region corresponding to the node is still in a low-coverage state. Nodes with low heat values ​​can be used as priority targets for path planning and stimulus generation.

[0100] In the embodiments of this application, path planning is performed based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain, including:

[0101] Based on the node heat value distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint.

[0102] For each edge of the updated verification state transition graph, the passage cost of each edge is defined based on the heat value of the node corresponding to each edge;

[0103] Based on the travel cost of each edge, calculate the minimum travel cost path to the end point in the updated verification state transition graph, and determine the minimum travel cost path as the abstract state transition chain.

[0104] To avoid repetitive and blind exploration, this embodiment uses the node popularity distribution of the updated verification state transition graph and selects any node with a low popularity value as the path endpoint. This embodiment employs Dijkstra's shortest path algorithm for weighted pathfinding. For ease of understanding, this embodiment uses the first and second nodes corresponding to the edges as examples. For each edge in the updated verification state transition graph, the travel cost of each edge is defined based on the popularity value of the node corresponding to that edge:

[0105] Formula (3)

[0106] Where e is an edge, u is the first node, v is the second node, i.e., e = (u → v), β is the weight coefficient, γ is a non-negative constant bias used to avoid path degradation caused by zero cost, and H v This is the heat value of the second node.

[0107] The defined travel cost makes nodes with higher popularity less likely to be selected for a path. Based on the travel cost of each edge, the minimum travel cost path to the destination in the updated verification state transition graph is calculated:

[0108] Formula (4)

[0109] Where P* is the minimum cost path, i.e., the output abstract state transition chain, v is a node, and v start As the starting node, v goal This is the node corresponding to the end point of the path.

[0110] The minimum passage cost path is defined as an abstract state transition chain. For ease of understanding, this embodiment uses the node corresponding to the idle phase as the starting node and verifies that the node corresponding to the FIFO full state covering the target in the state transition diagram is the path endpoint. The output abstract state transition chain can then be Idle→AW→W→FIFO_FULL, where Idle is the node corresponding to the idle phase, AW is the node corresponding to the write address phase, W is the node corresponding to the write data node, and FIFO_FULL is the node corresponding to the FIFO full state covering the target.

[0111] Please see Figure 4 , Figure 4 This is a schematic diagram illustrating the principle of path planning according to an embodiment of the present invention.

[0112] As shown in the figure, the node heat value formed by simulation coverage feedback is converted into a passage cost. During path planning, multiple candidate paths are constructed starting from the initial node. The cost of multiple candidate transition paths is evaluated, prioritizing the avoidance of high-passage-cost paths to already covered high-heat nodes and selecting lower-cost paths to low-heat nodes. This forms the minimum passage cost path, i.e., the abstract state transition chain, oriented towards the verification blind zone. The abstract state transition chain serves as a path constraint for generating verification stimuli, constraining the large language model to generate verification stimuli along the path, thereby improving the ability to explore low-coverage areas in a targeted manner. Since the edges in the verification state transition graph consist of valid stage transition relationships, the output abstract state transition chain is a path that naturally satisfies temporal validity. By calculating the minimum passage cost path through the defined passage cost, the path of the abstract state transition chain avoids high-heat node areas and prioritizes passing through low-heat uncovered areas, avoiding repeated blind exploration, thus achieving coverage-guided targeted incentive planning.

[0113] In the embodiments of this application, based on the node heat value distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint, including:

[0114] Based on the node popularity value distribution of the updated verification state transition graph, a target node set is selected, wherein the popularity value of all nodes in the target node set is less than the preset popularity threshold.

[0115] If the target node set is not empty, any node in the target node set will be used as the path endpoint.

[0116] If the target node set is empty, any node in the updated verification state transition graph will be used as the path endpoint.

[0117] Based on the updated node popularity distribution in the verification state transition graph, it is determined whether there are nodes whose popularity values ​​are all below a preset popularity threshold, thus filtering out the target node set. The preset popularity threshold is set according to actual needs and is not limited here. If the target node set is not empty, all nodes in the target node set are considered blind spots, and one node in the target node set is selected as the path endpoint. Specifically, the node with the lowest popularity value in the target node set can be used as the path endpoint, or a node can be randomly sampled from the target node set; details are omitted here.

[0118] If the target node set is not empty, meaning there are no blind spots where all nodes have a popularity value less than the preset popularity threshold, then any node in the target node set can be used as the path endpoint. Specifically, this can be done by selecting the node with the lowest popularity value, or by specifying a particular node as the path endpoint according to the verification plan; details will not be elaborated here.

[0119] In the embodiments of this application, the output verification stimulus of the preset large language model is constrained by the abstract state transition chain and constraint attribute constraints, including:

[0120] Convert abstract state transition chains and constraint attributes into structured cue words;

[0121] The structured prompts are input into a pre-defined large language model, and the pre-defined large language model is constrained to output validation stimuli.

[0122] The abstract state transition chain and constraint attributes are transformed into structured prompts to constrain the output verification stimulus of the pre-defined large language model. Specifically, the static attribute Constraints is read for each node in the path of the abstract state transition chain, and the path sequence of the abstract state transition chain and the constraint attributes corresponding to each node are filled into the generated pre-defined template. In this embodiment, the pre-defined template includes the protocol name, target path, signal constraints and data constraints corresponding to each node, and code format requirements for the verification stimulus output by the large language model. The pre-defined template is filled according to the abstract state transition chain and constraint attributes to transform the abstract state transition chain and constraint attributes into structured prompts. In the scenario of AXI write transactions, the Prompt in the generated pre-defined template will contain a highly structured comprehensive constraint instruction. The instructions in the pre-defined template macroscopically define the path guidance, forcing the test sequence to flow strictly in chronological order. The instructions in the preset template inject precise boundary conditions into each node at the micro level. For example, the Burst_Length of the specific address phase is limited to 16, the address is aligned to 4KB and the AWVALID and AWREADY bidirectional handshakes are satisfied. It requires that 16 valid data cycles be sent continuously during the write data phase and that the handshake be verified for each cycle. It also explicitly instructs that the slave be driven to inject back pressure stimulus during the FIFO full state phase to trigger the FIFO full state and maintain the blocked state for 3 clock cycles.

[0123] Compared to directly inputting the interface specification into a large language model and having the large language model dominate the logical decision-making of the test sequence, this embodiment inputs structured prompts into a preset large language model. Upon receiving highly deterministic abstract state transition chains and constraint attributes as instructions, the preset large language model no longer performs divergent logical predictions but strictly follows the temporal skeleton and data constraints to instantiate specific test code. In the AXI write transaction scenario, structured generation prompts are input into the preset large language model, and the model outputs verification stimuli as UVM (Universal Verification Methodology) sequence code, causing the driver layer to generate signals that satisfy the constraints. The preset large language model is confined to the scope of code instantiation within the given path of the abstract state transition chain, thereby reducing illegal temporal outputs caused by divergent reasoning and improving the executability and consistency of the generated code.

[0124] In the embodiments of this application, iterative verification of the target chip based on verification stimuli includes:

[0125] The target chip is simulated and tested based on the verification stimulus, and the simulation test results are obtained.

[0126] Based on the simulation test results, determine whether at least one critical node fails to meet the verification requirements. A critical node is any node in the verification state transition diagram.

[0127] If at least one critical node fails to meet the verification requirements, the following steps are performed: update the heat value of each node in the verification state transition graph based on the coverage item hit information corresponding to the node, and obtain the updated verification state transition graph.

[0128] Once all critical nodes meet the verification requirements, the verification results for the target chip are generated.

[0129] Iterative verification of the target chip based on verification stimuli includes:

[0130] The target chip is simulated and tested based on the verification stimulus, and the simulation test results are obtained.

[0131] Based on the simulation test results, determine whether at least one critical node fails to meet the verification requirements. A critical node is any node in the verification state transition diagram.

[0132] If at least one critical node fails to meet the verification requirements, the following steps are performed: update the heat value of each node in the verification state transition graph based on the coverage item hit information corresponding to the node, and obtain the updated verification state transition graph.

[0133] Once all critical nodes meet the verification requirements, the verification results for the target chip are generated.

[0134] In this embodiment, the verification stimulus is UVM test sequence code. The obtained UVM test sequence code is output to the simulation environment, and compilation, loading, and execution are performed automatically. Simulation testing is conducted on the target chip based on the verification stimulus. After the simulation, simulation test results are obtained. Based on the simulation test results, it is determined whether there is at least one critical node that does not meet the verification requirements. A critical node is any node in the verification state transition graph; in this embodiment, a critical node is a node that fully covers the target state. The verification requirements are set according to actual needs; they can be a requirement for the critical node's heat value or a requirement for the number of hits of the coverage item attached to the critical node, and are not limited here. If all critical nodes meet the verification requirements, the verification of the target chip is considered complete, and the verification results for the target chip are generated.

[0135] The key nodes are set according to actual needs and can be predetermined through the verification plan; no limitation is made here. Furthermore, the number of predetermined key nodes is set according to actual needs and is not limited here. For ease of understanding, in the embodiments of this application, key nodes are nodes that fully cover the target in the FIFO state. If at least one key node does not meet the verification requirements, the step of updating the heat value of each node in the verification state transition diagram based on the coverage item hit information corresponding to the node is executed, resulting in an updated verification state transition diagram; that is, S120 is executed to update the heat value of each node.

[0136] For ease of understanding, the embodiments of this application take the current node as a blind zone node as an example. In the process of obtaining the abstract state transition chain, the current node will be given priority as the exploration target. If the verification stimulus generated in the current verification round reaches the current node, the hit count of the coverage items attached to the current node will increase, thereby increasing the current node's popularity value. Subsequently, path planning is performed based on the node popularity value distribution of the updated verification state transition graph. In the process of obtaining the abstract state transition chain, the current node becomes a high-passage-cost path due to the increased popularity value. The path planning process can reduce repeated exploration of the current node and select other blind zone nodes with low popularity values ​​as new exploration targets to avoid repeated exploration. By generating multiple rounds of verification stimulus, the target chip is iteratively verified until all key nodes meet the verification requirements, thereby realizing the automated closed loop of the verification process.

[0137] Example 2

[0138] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a chip verification device according to an embodiment of the present invention. Figure 5 The chip verification device 200 includes:

[0139] The verification state transition graph construction module 210 is used to construct a verification state transition graph consisting of nodes and edges based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip.

[0140] The node heat value update module 220 is used to update the heat value of each node in the verification state transition graph according to the coverage item hit information corresponding to the node, so as to obtain the updated verification state transition graph. The coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node.

[0141] The path planning module 230 is used to perform path planning based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain.

[0142] The verification stimulus output module 240 is used to output verification stimuli by constraining the preset large language model through the abstract state transition chain and constraint attribute constraints.

[0143] The iterative verification module 250 is used to perform iterative verification of the target chip based on verification stimuli.

[0144] In embodiments of this application, the verification state transition graph construction module 210 includes:

[0145] The information extraction submodule is used to extract information from the interface specification of the target chip to obtain the constraints of the target chip in the interface transaction execution process, all transaction execution stages, and the stage transition relationship corresponding to each transaction execution stage.

[0146] The constraint attribute generation submodule is used to generate constraint attributes corresponding to each transaction execution stage based on constraint conditions and preset verification constraint information.

[0147] The state transition graph construction submodule is used to construct a verification state transition graph composed of nodes and edges, which represents the transaction execution phase and constraint attributes through nodes and the phase transition relationship through edges.

[0148] In the embodiments of this application, the node heat value update module 220 is further configured to update the heat value of each node in the verification state transition graph according to the coverage item hit information, hit threshold and historical heat value of the node in the historical verification round when the current verification round is not the first round, so as to obtain the updated verification state transition graph, wherein the historical verification round is the previous verification round of the current verification round.

[0149] In embodiments of this application, the path planning module 230 includes:

[0150] The path endpoint determination submodule is used to determine any node in the updated verification state transition graph as the path endpoint based on the node heat value distribution of the updated verification state transition graph.

[0151] The passage cost definition submodule is used to define the passage cost of each edge in the updated verification state transition graph based on the heat value of the node corresponding to each edge.

[0152] The abstract state transition chain determination submodule is used to calculate the minimum travel cost path to the end point of the updated verification state transition graph based on the travel cost of each edge, and determine the minimum travel cost path as the abstract state transition chain.

[0153] In the embodiments of this application, the path endpoint determination submodule is further used to filter out a target node set based on the node heat value distribution of the updated verification state transition graph, wherein the heat value of all nodes in the target node set is less than a preset heat threshold.

[0154] If the target node set is not empty, any node in the target node set will be used as the path endpoint.

[0155] If the target node set is empty, any node in the updated verification state transition graph will be used as the path endpoint.

[0156] In embodiments of this application, the verification stimulus output module 240 further includes:

[0157] The prompt conversion submodule is used to convert abstract state transition chains and constraint attributes into structured prompts;

[0158] The stimulus output submodule is used to input structured prompt words into a preset large language model and constrain the preset large language model to output validation stimuli.

[0159] In the embodiments of this application, the iterative verification module 250 includes:

[0160] The simulation test submodule is used to perform simulation tests on the target chip based on verification stimuli and obtain simulation test results.

[0161] The critical node determination submodule is used to determine, based on the simulation test results, whether at least one critical node fails to meet the verification requirements. Here, a critical node is any node in the verification state transition diagram.

[0162] The critical node verification submodule is used to perform the following steps when at least one critical node fails to meet the verification requirements: update the heat value of each node in the verification state transition graph based on the coverage item hit information corresponding to the node, and obtain the updated verification state transition graph.

[0163] The verification result generation submodule is used to generate the verification results of the target chip when all key nodes meet the verification requirements.

[0164] This application embodiment also provides a computing device, including:

[0165] The memory is configured to store instructions;

[0166] The processor is configured to retrieve instructions from memory and, when executing instructions, to implement the aforementioned chip verification method.

[0167] In this embodiment, the verification state transition graph construction module 210, the node heat value update module 220, the path planning module 230, the verification stimulus output module 240, and the iterative verification module 250 are all stored in the memory as program units, and the processor executes the above program units stored in the memory to realize the corresponding functions.

[0168] The processor contains a kernel, which retrieves the corresponding program units from memory. One or more kernels can be configured, and the chip verification method described above can be implemented by adjusting the kernel parameters.

[0169] The memory may include non-permanent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0170] This application also provides a machine-readable storage medium storing instructions that cause a machine to perform the chip verification method described above.

[0171] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0172] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0173] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0174] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0175] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0176] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0177] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0178] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0179] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A chip verification method, characterized in that, include: Based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip, construct a verification state transition graph composed of nodes and edges; Based on the coverage item hit information corresponding to the node, the heat value of each node in the verification state transition graph is updated to obtain the updated verification state transition graph. The coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node. Based on the node heat value distribution of the updated verification state transition graph, path planning is performed to obtain an abstract state transition chain. The validation stimulus is output by the pre-defined large language model constrained by the abstract state transition chain and the constraint attributes. The target chip is iteratively verified based on the verification stimulus.

2. The chip verification method according to claim 1, characterized in that, Based on the transaction execution stage, stage transition relationship, and constraint attributes corresponding to the target chip, a verification state transition graph consisting of nodes and edges is constructed, including: Information is extracted from the interface specification of the target chip to obtain the constraints of the target chip in the interface transaction execution process, all transaction execution stages, and the stage transition relationship corresponding to each transaction execution stage; Based on the constraints and preset verification constraint information, generate constraint attributes corresponding to each transaction execution stage; A verification state transition graph consisting of nodes and edges is constructed by representing the transaction execution phase and the constraint attributes through nodes and the phase transition relationship through edges.

3. The chip verification method according to claim 1, characterized in that, Based on the coverage item hit information corresponding to the node, the heat value of each node in the verification state transition graph is updated to obtain the updated verification state transition graph, including: If the current verification round is not the first round, the heat value of each node in the verification state transition graph is updated according to the coverage item hit information, hit threshold and historical heat value of the node in the current verification round. The updated verification state transition graph is obtained, wherein the historical verification round is the previous verification round of the current verification round.

4. The chip verification method according to claim 1, characterized in that, Based on the node heat value distribution of the updated verification state transition graph, path planning is performed to obtain an abstract state transition chain, including: Based on the node heat value distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint. For each edge of the updated verification state transition graph, the passage cost of each edge is defined based on the heat value of the node corresponding to each edge; Based on the travel cost of each edge, calculate the minimum travel cost path to the endpoint of the path in the updated verification state transition graph, and determine the minimum travel cost path as the abstract state transition chain.

5. The chip verification method according to claim 4, characterized in that, Based on the node heat distribution of the updated verification state transition graph, any node in the updated verification state transition graph is taken as the path endpoint, including: Based on the node heat value distribution of the updated verification state transition graph, a target node set is selected, wherein the heat value of all nodes in the target node set is less than a preset heat threshold. If the target node set is not empty, any node in the target node set shall be taken as the path endpoint. If the target node set is empty, any node in the updated verification state transition graph is taken as the path endpoint.

6. The chip verification method according to claim 1, characterized in that, The validation stimulus is output through the abstract state transition chain and the constraint attribute constraints of the preset large language model, including: Convert the abstract state transition chain and the constraint attributes into structured prompt words; The structured prompt words are input into a preset large language model, and the preset large language model is constrained to output verification stimuli.

7. The chip verification method according to claim 1, characterized in that, Iterative verification of the target chip based on the verification stimulus includes: The target chip is simulated and tested based on the verification stimulus to obtain simulation test results. Based on the simulation test results, determine whether at least one key node fails to meet the verification requirements, wherein the key node is any node in the verification state transition diagram; If at least one of the key nodes does not meet the verification requirements, the step of updating the heat value of each node in the verification state transition graph according to the coverage item hit information corresponding to the node is performed to obtain an updated verification state transition graph. If all the key nodes meet the verification requirements, the verification result of the target chip is generated.

8. A chip verification device, characterized in that, include: The verification state transition graph construction module is used to construct a verification state transition graph consisting of nodes and edges based on the transaction execution stage, stage transition relationship and constraint attributes corresponding to the target chip. The node heat value update module is used to update the heat value of each node in the verification state transition graph according to the coverage item hit information corresponding to the node, so as to obtain the updated verification state transition graph. The coverage item hit information is mounted to the corresponding node according to the mapping relationship between the coverage item and the node. The path planning module is used to perform path planning based on the node heat value distribution of the updated verification state transition graph to obtain an abstract state transition chain. The verification stimulus output module is used to output verification stimuli through the abstract state transition chain and the constraint attribute constraint preset large language model; An iterative verification module is used to perform iterative verification on the target chip based on the verification stimulus.

9. A computing device, characterized in that, include: The memory is configured to store instructions; A processor is configured to retrieve the instructions from the memory and, when executing the instructions, to implement the chip verification method according to any one of claims 1 to 7.

10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores instructions for causing the machine to perform the chip verification method according to any one of claims 1 to 7.

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