System-on-chip system-level functional verification system and method

Abstract

The application discloses a kind of SoC system-level function verification system and method, system includes: SoC chip, at least two PCIe controllers integrated in SoC chip, configuration module, link training and enumeration module, system-level function verification module, result comparison module;Each PCIe controller supports dynamic configuration as RC mode or EP mode, two PCIe controllers include first, second PCIe controller, the sending end of first PCIe controller is connected with the receiving end of second PCIe controller by external differential trace, the sending end of second PCIe controller is connected with the receiving end of first PCIe controller, to form physical layer interconnection loop outside chip;Configuration module, link training and enumeration module, system-level function verification module and result comparison module cooperate and verify and output verification conclusion.Using the application, avoid the simulation environment bloated and regression efficiency decline caused by introducing external VIP, improve verification coverage, test confidence and research and development efficiency.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and embedded system technology, and in particular to a SoC system-level functional verification system and method. Background Technology

[0002] As the core high-speed interconnect interface of a System on Chip (SoC), PCI Express (PCIe) has become an indispensable key component for various high-performance chips due to its high bandwidth, low latency, and excellent scalability. In modern SoC chip design, the PCIe controller is deeply coupled with various on-chip system-level functional modules. Therefore, ensuring the functional correctness and protocol consistency of the PCIe controller and its collaboration with various system-level functional modules is of paramount importance.

[0003] In existing technologies, the mainstream method for functional verification of PCIe controllers in the industry is to introduce a third-party commercial PCIe verification IP (VIP). Specifically, on an electronic design automation (EDA) simulation platform, the PCIe controller to be verified is treated as a device under test (DUT) and connected to the commercial VIP. This commercial VIP can be configured in Root Complex (RC) mode or Endpoint (EP) mode to simulate a real PCIe topology. Verification engineers write test sequences to drive the VIP to send standard Transaction Layer Packets (TLPs) to the DUT, including configuration read / write, memory read / write, and completion messages, while simultaneously sending Data Link Layer Packets (DLLPs) to simulate the interaction behavior between real PCIe devices. Based on this, the correctness of the DUT's Link Training and State Machine (LTSSM), data link layer, and transaction layer processing logic is verified. However, this verification scheme has the following drawbacks:

[0004] First, the commercial PCIe VIP architecture is complex, and the interface adaptation (wrapping) between it and the internal logic of the SoC chip requires a significant investment of development and debugging time, resulting in high manpower and time costs for setting up the verification environment. Second, introducing a large VIP model significantly increases the amount of code and compilation time in the simulation environment, leading to a substantial decrease in the overall efficiency of regression verification and extending the chip verification iteration cycle. Third, commercial VIPs are primarily used to verify the compliance of the PCIe protocol itself. However, for system-level functions within the SoC chip, such as data transport in the HDMA engine's PCIe path, the actual mapping of the ATU address translation unit, the encapsulation and decapsulation of the MCTP protocol on the PCIe link, the correct routing of MSI / MSI-X interrupts, and the actual configuration access to the base address register (BAR) space, they often cannot provide efficient verification methods directly. Verification engineers still need to write a large number of complex test sequences for indirect verification, increasing the complexity of the verification work. Fourth, commercial VIPs belong to third-party intellectual property cores, and their internal logic is usually encrypted. If a test case fails to execute, verification engineers will find it difficult to perform breakpoint debugging or waveform analysis within the VIP, making problem localization extremely difficult and thus prolonging the debugging cycle.

[0005] Therefore, existing PCIe verification solutions based on external commercial VIPs suffer from technical problems such as high cost, low efficiency, insufficient system-level functional coverage, and difficulty in debugging, and there is an urgent need for a more efficient and low-cost verification solution. Summary of the Invention

[0006] This application provides a SoC system-level functional verification system. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0007] In a first aspect, embodiments of this application provide a SoC system-level functional verification system, the system comprising: The system-on-a-chip (SoC), at least two PCIe controllers integrated within the SoC, a configuration module, a link training and enumeration module, a system-level functional verification module, and a result comparison module; among which... Each PCIe controller supports dynamic configuration to RC or EP mode. At least two PCIe controllers are included, comprising a first PCIe controller and a second PCIe controller. The transmitter of the first PCIe controller is connected to the receiver of the second PCIe controller via external differential traces, and the transmitter of the second PCIe controller is connected to the receiver of the first PCIe controller, forming a physical layer interconnect loop outside the SoC chip. The configuration module, link training and enumeration module, system-level function verification module, and result comparison module work together in sequence to configure the two PCIe controllers to EP mode and RC mode respectively, establish PCIe communication links and complete enumeration, perform a variety of preset system-level function verification steps under the physical layer interconnection loop, and automatically compare the readback data or interrupt status of the PCIe controller configured in EP mode with the preset expected values ​​before outputting the verification conclusion.

[0008] Optionally, a configuration module is provided for writing the configuration space of each PCIe controller into the control register and configuring one PCIe controller in RC mode and the other PCIe controller in EP mode. The link training and enumeration module is used to initiate link training by the PCIe controller configured in RC mode after the internal power and clock of the SOC chip are turned on, establish a PCIe communication link with the PCIe controller configured in EP mode, and execute the PCIe enumeration process by the PCIe controller configured in RC mode, read the configuration space of the PCIe controller configured in EP mode and perform address allocation and space configuration on its base address register. The system-level functional verification module is used to perform a variety of preset system-level functional verification steps under the physical layer interconnection loop; The result comparison module is used to collect readback data or interrupt status from the PCIe controller side configured in EP mode, automatically compare it with the preset expected value, and generate and output the verification conclusion.

[0009] Optionally, multiple system-level functional verification steps are preset, including TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification. At least one of the X interruption verification methods; wherein... TLP and BAR verification are used to directly read and write the BAR mapping space of a PCIe controller configured in EP mode via PIO through a PCIe controller configured in RC mode, in order to verify the routing and data integrity of TLP. HDMA verification is used to start the HDMA engine inside the SoC chip, configure its source address to the local memory on the RC mode side and the destination address to the BAR space on the EP mode side, initiate DMA transfer, and verify the continuous streaming transmission capability of PCIe as a data path.

[0010] Optional, ATU verification is used to configure the address translation unit inside the SoC chip to verify the correctness of the address mapping after ATU translation of the Outbound request issued by the RC mode side and the Inbound completion message returned by the EP mode side. MCTP verification is used to trigger the MCTP module inside the SoC chip, encapsulate MCTP over PCIe messages, send and receive them through the closed-loop path from the RC mode side to the EP mode side, and verify the layer 2 decapsulation and routing logic of the messages. MSI / MSI X interrupt verification is used to trigger an interrupt request on the PCIe controller side configured in EP mode to verify whether the PCIe controller side configured in RC mode can correctly receive MSI or MSI. X interrupt signal, and resolve interrupt vector number.

[0011] Optionally, collect readback data from the PCIe controller side configured in EP mode and automatically compare it with preset expected values, including: In the TLP and BAR verification process, the first read data is obtained by reading the BAR mapping space of the PCIe controller configured in EP mode using PIO through the PCIe controller configured in RC mode. The first read data is then compared with the original data written at the time of writing. In the HDMA verification process, the data after DMA transfer is read from the target storage space on the PCIe controller side configured in EP mode to obtain the second readback data, and the second readback data is compared with the source data in the local memory on the RC mode side. In the ATU verification process, the PCIe controller configured in RC mode reads the data in the target address space after ATU conversion to obtain the third readback data, and compares the third readback data with the expected address mapping data.

[0012] Optionally, the interrupt status is collected and automatically compared with preset expected values, including: At MSI / MSI In the X interrupt verification process, the status of the interrupt signal and the interrupt vector number received by the PCIe controller configured in RC mode are collected. Compare the interrupt signal status with the expected interrupt trigger status; The parsed interrupt vector number is compared with the preset expected interrupt vector number.

[0013] Optionally, automatic comparison with preset expected values ​​may be performed, including: In the MCTP verification process, the content of the MCTP message received and decapsulated via the closed-loop path is obtained. The decapsulated MCTP message content is compared field by field with the original MCTP message content before encapsulation to verify the correctness of the encapsulation and decapsulation process of MCTP over PCIe messages.

[0014] Optionally, generate and output verification conclusions, including: When TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI If the comparison results of each verification step in the X-interrupt verification are consistent, a verification conclusion indicating that the PCIe and related internal IP functions have passed verification is generated and output; or, When TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI If the comparison result of any verification step in the X interruption verification is inconsistent, the abnormal verification step with inconsistent comparison result is determined. Generate a verification conclusion that includes failure flags and abnormal data information for the abnormal verification process, and output the verification conclusion.

[0015] Optionally, write the configuration space of each PCIe controller to the control register, including: The mode selection registers are written to the configuration spaces of the first PCIe controller and the second PCIe controller via the internal configuration bus of the SoC chip. The first PCIe controller can be configured in RC mode and the second PCIe controller in EP mode; or, After completing the mode configuration, the link training enable register is written to the configuration space of each PCIe controller via the internal configuration bus to start the link training state machine of each PCIe controller.

[0016] Secondly, a SoC system-level functional verification method, the method comprising: The SoC chip integrates at least two PCIe controllers; the at least two PCIe controllers include a first PCIe controller and a second PCIe controller, and each PCIe controller supports dynamic configuration to RC mode or EP mode; The transmitter of the first PCIe controller is connected to the receiver of the second PCIe controller through external differential traces, and the transmitter of the second PCIe controller is connected to the receiver of the first PCIe controller to form a physical layer interconnect loop outside the SoC chip. Configure the two PCIe controllers to RC mode and EP mode respectively; The link training is initiated by the PCIe controller configured in RC mode, a PCIe communication link is established with the PCIe controller configured in EP mode, and the PCIe enumeration process is executed. Perform multiple preset system-level functional verification steps under the physical layer interconnection loop; Collect readback data or interrupt status from the PCIe controller side configured in EP mode, automatically compare it with the preset expected value, and output the verification conclusion.

[0017] In this embodiment, by utilizing at least two PCIe controllers integrated within the SoC chip that support dynamic configuration to RC or EP modes, and cross-interconnecting their transceiver channels to form a physical layer interconnect loop, a self-closing verification architecture completely independent of external commercial PCIe Verification IP is achieved. This system can directly and efficiently verify the chip's internal HDMA engine, ATU address translation unit, MCTP protocol encapsulation / decapsulation, and MSI / MSI... The real-world interaction scenarios of system-level functions such as X interrupt routing and BAR space configuration access significantly reduce the cost and integration cycle of setting up the verification environment. It avoids the problems of bloated simulation environment and decreased regression efficiency caused by the introduction of external VIPs. At the same time, since all verification components are natively designed inside the chip, they have good debuggability, thereby greatly improving verification coverage, test confidence and R&D efficiency.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram of the system architecture of a SoC system-level functional verification system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the system architecture of a SoC system-level functional verification system provided in an embodiment of this application; Figure 3 This is a diagram of an external PCIe loopback verification architecture for a SoC chip provided in an embodiment of this application; Figure 4 This is an implementation architecture and data flow diagram provided in an embodiment of this application; Figure 5This is a flowchart illustrating a SoC system-level functional verification method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the configuration process of a configuration module provided in an embodiment of this application; Figure 7 This is a schematic diagram of a verification conclusion output process provided in an embodiment of this application. Detailed Implementation

[0021] The following description and accompanying drawings fully illustrate specific embodiments of this application to enable those skilled in the art to practice them.

[0022] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0023] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of systems and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0025] Currently, the mainstream method in the industry for functional verification of PCIe controllers is to introduce third-party commercial PCIe verification IP (VIP). For example... Figure 1As shown, on an Electronic Design Automation (EDA) simulation platform, the PCIe controller to be verified is used as a Device Under Test (DUT) and connected to a commercial VIP. This commercial VIP can be configured in Root Complex (RC) mode or Endpoint (EP) mode to simulate a real PCIe topology. Verification engineers write test sequences to drive the VIP to send standard Transaction Layer Packets (TLPs) to the DUT, including configuration read / write, memory read / write, and completion messages, while simultaneously sending Data Link Layer Packets (DLLPs) to simulate the interaction behavior between real PCIe devices. Based on this, the correctness of the DUT's Link Training and State Machine (LTSSM), data link layer, and transaction layer processing logic is verified.

[0026] The inventors recognized the following drawbacks of the verification scheme: First, the commercial PCIe VIP architecture is complex, and its interface adaptation (wrapper) with the internal logic of the SoC chip requires a significant investment of development and debugging time, resulting in high manpower and time costs for setting up the verification environment. Second, introducing a large VIP model significantly increases the amount of code and compilation time in the simulation environment, leading to a substantial reduction in the overall efficiency of regression verification and extending the chip verification iteration cycle. Third, commercial VIPs are mainly used to verify the compliance of the PCIe protocol itself. However, for system-level functions within the SoC chip, such as PCIe path data transfer in the HDMA engine, the actual mapping of the ATU address translation unit, the encapsulation and decapsulation of the MCTP protocol on the PCIe link, the correct routing of MSI / MSI-X interrupts, and the actual configuration access of the base address register (BAR) space, they often cannot directly provide efficient verification methods. Verification engineers still need to write a large number of complex test sequences for indirect verification, increasing the complexity of the verification work. Fourth, commercial VIPs belong to third-party intellectual property cores, and their internal logic is usually encrypted. If a test case fails to execute, verification engineers will find it difficult to perform breakpoint debugging or waveform analysis within the VIP, making problem localization extremely difficult and thus prolonging the debugging cycle.

[0027] In this embodiment, by utilizing at least two PCIe controllers integrated within the SoC chip that support dynamic configuration to RC or EP modes, and cross-interconnecting their transceiver channels to form a physical layer interconnect loop, a self-closing verification architecture completely independent of external commercial PCIe Verification IP is achieved. This system can directly and efficiently verify the chip's internal HDMA engine, ATU address translation unit, MCTP protocol encapsulation / decapsulation, and MSI / MSI... Real-world interaction scenarios for system-level functions such as X-interrupt routing and BAR space configuration access significantly reduce the cost and integration cycle of setting up the verification environment. This avoids the problems of bloated simulation environments and decreased regression efficiency caused by the introduction of external VIPs. Furthermore, because all verification components are natively designed within the chip, they possess excellent debuggability, thereby greatly improving verification coverage, test confidence, and R&D efficiency. The following detailed description uses exemplary embodiments.

[0028] Please see Figure 2 , Figure 2 This is a schematic diagram of the system architecture of a SoC system-level functional verification system provided in an embodiment of this application. The system includes: an SoC chip, at least two PCIe controllers integrated in the SoC chip, a configuration module, a link training and enumeration module, a system-level functional verification module, and a result comparison module. Each PCIe controller supports dynamic configuration to RC mode or EP mode. The at least two PCIe controllers include a first PCIe controller and a second PCIe controller. The transmitting end of the first PCIe controller and the receiving end of the second PCIe controller are connected through external differential traces. The transmitting end of the second PCIe controller is connected to the receiving end of the first PCIe controller to form a physical layer interconnect loop outside the SoC chip.

[0029] In this context, SoC (System-on-a-Chip) refers to an integrated circuit that integrates a central processing unit, memory, various interface controllers, and functional modules onto a single semiconductor substrate. In this application, the SoC serves as the carrier of all verification resources, internally integrating multiple PCIe controllers and other system-level functional modules. The PCIe controller is an interface controller compliant with the PCI Express protocol specification, used to manage and process the physical layer, data link layer, and transaction layer protocol logic on the PCIe link, enabling high-speed data transmission and control between external PCIe devices or other internal PCIe controllers. RC mode (Root Complex mode) is the root complex mode in the PCIe architecture. PCIe controllers configured in this mode assume the host role, responsible for initiating configuration transactions, memory transactions, and I / O transactions, executing link training and enumeration processes, and managing address allocation and resource configuration for downstream devices.

[0030] In the PCIe architecture, EP mode (Endpoint mode) is the endpoint mode. A PCIe controller configured in this mode acts as a peripheral, passively responding to transaction requests from the RC side, providing the BAR mapping space for the RC side to access, and initiating interrupt requests or DMA operations. The transmit end (TX) is the physical interface in the PCIe controller used to send serial data, including the transmit differential pair signal lines (TX+, TX-) and their driving circuitry. The receive end (RX) is the physical interface in the PCIe controller used to receive serial data from the outside, including the receive differential pair signal lines (RX+, RX-) and their receiving circuitry. External differential traces are differential signal transmission lines located outside the SoC chip package pins and laid out on the printed circuit board (PCB), used to physically connect the transmit end of the first PCIe controller to the receive end of the second PCIe controller, and vice versa. Physical layer interconnect loops are physical layer signal loops located outside the SoC chip, formed by cross-connecting the transmit and receive ends of the two PCIe controllers. This loop enables the two PCIe controllers to send and receive data through the real PCIe physical layer channel, thereby achieving a closed-loop PCIe communication within the chip without the need for external PCIe devices or commercial VIPs.

[0031] For example Figure 3 As shown, Figure 3This application presents an external PCIe loopback verification architecture for a SoC chip. It utilizes multiple PCIe controllers integrated within the SoC chip (pcie0, pcie1, and pcie2 in the figure), and interconnects the transmit (TX) and receive (RX) ends of two of these controllers via external physical SerDes differential traces, thus constructing a physical layer interconnect loop outside the chip. This architecture allows the two selected PCIe controllers (e.g., pcie0 and pcie1) to be dynamically configured in RC (Root Complex) mode and EP (Endpoint) mode, or vice versa. After establishing the PCIe communication link and completing enumeration, various system-level functional verifications can be performed within this closed-loop path, including but not limited to HDMA (Host DMA) data transfer, MCTP (Management Component Transport Protocol) message encapsulation and decapsulation, BAR (Base Address Register) space access, and interrupt (MSI / MSI-X) triggering and response. Furthermore, the red section in the diagram illustrates the scalability of the verification logic. Similarly, any two other PCIe controllers within the chip (such as pcie1 and pcie2) can be selected for the same external cross-connection verification, while the remaining third PCIe controller remains idle during this verification process. This self-closing-loop verification scheme, utilizing internal multi-controller cross-connection, effectively achieves comprehensive testing of PCIe-related internal IP and system-level functions.

[0032] In some embodiments of this application, the configuration module, the link training and enumeration module, the system-level function verification module, and the result comparison module cooperate sequentially to configure the two PCIe controllers to EP mode and RC mode respectively, establish a PCIe communication link and complete enumeration, perform a variety of preset system-level function verification steps under the physical layer interconnection loop, and automatically compare the readback data or interrupt status of the PCIe controller configured in EP mode with the preset expected value and output the verification conclusion.

[0033] In some embodiments of this application, a configuration module is used to write the configuration space of each PCIe controller into a control register, and configure one PCIe controller in RC mode and the other PCIe controller in EP mode; a link training and enumeration module is used to initiate link training by the PCIe controller configured in RC mode after the SOC chip's internal power supply and clock are turned on, establish a PCIe communication link with the PCIe controller configured in EP mode, and execute the PCIe enumeration process by the PCIe controller configured in RC mode, read the configuration space of the PCIe controller configured in EP mode and perform address allocation and space configuration on its base address register; a system-level function verification module is used to perform a variety of preset system-level function verification steps under the physical layer interconnection loop; and a result comparison module is used to collect the readback data or interrupt status of the PCIe controller configured in EP mode, automatically compare it with the preset expected value, and generate and output the verification conclusion.

[0034] In some embodiments of this application, the specific process of writing control registers to the configuration space of each PCIe controller includes: writing mode selection registers to the configuration spaces of the first PCIe controller and the second PCIe controller respectively through the internal configuration bus of the SoC chip, so as to configure the first PCIe controller as RC mode and the second PCIe controller as EP mode; or, after completing the mode configuration, writing link training enable registers to the configuration space of each PCIe controller through the internal configuration bus to start the link training state machine of each PCIe controller.

[0035] In some embodiments of this application, the specific process of executing the PCIe enumeration procedure includes: a PCIe controller configured in RC mode scans the PCIe bus through a configuration read / write TLP to discover a PCIe controller configured in EP mode mounted on the bus; reads the configuration space of the PCIe controller configured in EP mode to obtain its device identification information and the address space size and type indicated by the base address register; allocates a corresponding system physical address space for each base address register according to the address space size and type, and writes the allocated address value into the base address register to complete the address space mapping configuration on the EP mode side.

[0036] The system includes multiple pre-defined system-level functional verification steps, such as TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification. At least one of the X-interruption verification methods.

[0037] In some embodiments of this application, TLP and BAR verification are used to directly read and write the BAR mapping space of a PCIe controller configured in EP mode via PIO through a PCIe controller configured in RC mode, to verify the routing and data integrity of TLP; HDMA verification is used to start the HDMA engine inside the SoC chip, configure its source address to the local memory on the RC mode side and the destination address to the BAR space on the EP mode side, initiate DMA transfer, and verify the continuous streaming transmission capability of PCIe as a data path; ATU verification is used to configure the address translation unit inside the SoC chip to verify the correctness of the address mapping of the Outbound request issued by the RC mode side and the Inbound completion message returned by the EP mode side after ATU translation; MCTP verification is used to trigger the MCTP module inside the SoC chip, encapsulate the MCTP over PCIe message, send and receive it through the closed-loop path from the RC mode side to the EP mode side, and verify the layer 2 decapsulation and routing logic of the message; MSI / MSI X interrupt verification is used to trigger an interrupt request on the PCIe controller side configured in EP mode to verify whether the PCIe controller side configured in RC mode can correctly receive MSI or MSI. X interrupt signal, and resolve interrupt vector number.

[0038] In some embodiments of this application, the specific process of collecting readback data from the PCIe controller configured in EP mode and automatically comparing it with a preset expected value includes: in the TLP and BAR verification stages, the PCIe controller configured in RC mode reads the BAR mapping space of the PCIe controller configured in EP mode using PIO to obtain first readback data, and compares the first readback data with the original data at the time of writing; in the HDMA verification stage, the PCIe controller configured in EP mode reads the data after DMA transfer from the target storage space to obtain second readback data, and compares the second readback data with the source data in the local memory of the RC mode side; in the ATU verification stage, the PCIe controller configured in RC mode reads the data in the target address space after ATU conversion to obtain third readback data, and compares the third readback data with the expected address mapping data.

[0039] In some embodiments of this application, the specific process of collecting interruption status and automatically comparing it with a preset expected value includes: in MSI / MSI In the X interrupt verification process, the interrupt signal status and interrupt vector number received by the PCIe controller configured in RC mode are collected; the interrupt signal status is compared with the expected interrupt trigger status; and the parsed interrupt vector number is compared with the preset expected interrupt vector number.

[0040] In some embodiments of this application, the specific process of automatically comparing with a preset expected value includes: in the MCTP verification stage, obtaining the MCTP message content received and decapsulated through the closed-loop path; comparing the decapsulated MCTP message content with the original MCTP message content before encapsulation field by field to verify the correctness of the encapsulation and decapsulation process of the MCTP over PCIe message.

[0041] In some embodiments of this application, the specific process of generating and outputting verification conclusions includes: when TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI... When the comparison results of each verification step in the X interruption verification are consistent, a verification conclusion indicating that PCIe and related internal IP functions have passed is generated and output; or, when TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification are all consistent, a verification conclusion indicating that PCIe and related internal IP functions have passed is generated and output; If the comparison result of any verification step in the X interruption verification is inconsistent, the abnormal verification step with inconsistent comparison result is identified; a verification conclusion containing the failure identifier and abnormal data information of the abnormal verification step is generated and output.

[0042] For example Figure 4 As shown, Figure 4 This application provides an implementation architecture and data flow diagram. The core module first initializes the PCIe0 controller (configured in EP mode) and the PCIe1 controller (configured in RC mode) through the dBi interface, and enables the LTSSM link training state machine. Then, the core module writes the data to be verified to the BAR space of PCIe0 through the SLV bus. After the data is converted into an ATU outbound address inside PCIe0, it is encapsulated into a TLP message and sent to PCIe1 through the SerDes TX / RX pins connected externally to the chip. After receiving the TLP message, PCIe1 decapsulates it and converts it into an AXI write transaction, and finally writes the data into the on-chip SRAM inside the SoC. Finally, the core module reads the loopback data from the SRAM and compares it with the expected value (checking whether the data is consistent), thereby completing the closed-loop verification of the PCIe0 ATU function and the integrity of the entire PCIe data path.

[0043] The dBi interface is a dedicated slave bus interface for accessing the internal configuration registers of the PCIe controller. The SLV interface refers to the slave service data interface exposed by the PCIe controller to its upstream counterpart (usually pointing to the SoC's internal bus), most commonly the AXISlave interface (or AHB / APB Slave, depending on the SoC bus architecture). SRAM (Static Random Access Memory) is a high-speed on-chip memory unit commonly used within chips, where data is lost when power is off, and is used for temporary data storage. The core module includes a configuration module, a link training and enumeration module, a system-level functional verification module, and a result comparison module.

[0044] In this embodiment, by utilizing at least two PCIe controllers integrated within the SoC chip that support dynamic configuration to RC or EP modes, and cross-interconnecting their transceiver channels to form a physical layer interconnect loop, a self-closing verification architecture completely independent of external commercial PCIe Verification IP is achieved. This system can directly and efficiently verify the chip's internal HDMA engine, ATU address translation unit, MCTP protocol encapsulation / decapsulation, and MSI / MSI... The real-world interaction scenarios of system-level functions such as X interrupt routing and BAR space configuration access significantly reduce the cost and integration cycle of setting up the verification environment. It avoids the problems of bloated simulation environment and decreased regression efficiency caused by the introduction of external VIPs. At the same time, since all verification components are natively designed inside the chip, they have good debuggability, thereby greatly improving verification coverage, test confidence and R&D efficiency.

[0045] Please see Figure 5 This is a flowchart illustrating a SoC system-level functional verification method provided in this application embodiment. Figure 5 As shown, the detection method in this application embodiment may include the following steps: S101 integrates at least two PCIe controllers inside the SoC chip; the at least two PCIe controllers include a first PCIe controller and a second PCIe controller, and each PCIe controller supports dynamic configuration to RC mode or EP mode. S102, the transmitting end of the first PCIe controller is connected to the receiving end of the second PCIe controller through external differential traces, and the transmitting end of the second PCIe controller is connected to the receiving end of the first PCIe controller to form a physical layer interconnection loop outside the SoC chip. S103, configure the two PCIe controllers to RC mode and EP mode respectively; In some embodiments of this application, mode selection registers are written to the configuration spaces of the first PCIe controller and the second PCIe controller via the internal configuration bus of the SoC chip, respectively, to configure the first PCIe controller as RC mode and the second PCIe controller as EP mode; or, after completing the mode configuration, a link training enable register is written to the configuration space of each PCIe controller via the internal configuration bus to start the link training state machine of each PCIe controller.

[0046] For example Figure 6 As shown, Figure 6 This is a schematic diagram of the configuration process of a configuration module provided in this application. First, inside the SoC chip, the first PCIe controller and the second PCIe controller are cross-connected via their respective transmitter (TX) and receiver (RX) terminals through differential traces outside the chip (i.e., TX connects to RX, and RX connects to TX), thereby constructing a complete interconnection loop at the physical layer outside the chip. Based on this, the process moves down to the software / firmware configuration stage: the configuration module performs operations, specifically writing control register data to the register space of the PCIe controller, and finally configuring the two PCIe controllers into RC (Root Complex) mode or EP (Endpoint) mode respectively, completing the initialization of the hardware link and building the underlying communication channel for subsequent system-level functional verification (such as TLP transmission, DMA, ATU, etc.).

[0047] S104, the PCIe controller configured in RC mode initiates link training, establishes a PCIe communication link with the PCIe controller configured in EP mode, and executes the PCIe enumeration process. In some embodiments of this application, the specific process of executing the PCIe enumeration procedure includes: a PCIe controller configured in RC mode scans the PCIe bus through a configuration read / write TLP to discover a PCIe controller configured in EP mode mounted on the bus; reads the configuration space of the PCIe controller configured in EP mode to obtain its device identification information and the address space size and type indicated by the base address register; allocates a corresponding system physical address space for each base address register according to the address space size and type, and writes the allocated address value into the base address register to complete the address space mapping configuration on the EP mode side.

[0048] S105 performs multiple preset system-level functional verification steps under the physical layer interconnection loop; The system includes multiple pre-defined system-level functional verification steps, such as TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification. At least one of the X-interruption verification methods.

[0049] In some embodiments of this application, TLP and BAR verification are used to directly read and write the BAR mapping space of a PCIe controller configured in EP mode via PIO through a PCIe controller configured in RC mode, to verify the routing and data integrity of TLP; HDMA verification is used to start the HDMA engine inside the SoC chip, configure its source address to the local memory on the RC mode side and the destination address to the BAR space on the EP mode side, initiate DMA transfer, and verify the continuous streaming transmission capability of PCIe as a data path; ATU verification is used to configure the address translation unit inside the SoC chip to verify the correctness of the address mapping of the Outbound request issued by the RC mode side and the Inbound completion message returned by the EP mode side after ATU translation; MCTP verification is used to trigger the MCTP module inside the SoC chip, encapsulate the MCTP over PCIe message, send and receive it through the closed-loop path from the RC mode side to the EP mode side, and verify the layer 2 decapsulation and routing logic of the message; MSI / MSI X interrupt verification is used to trigger an interrupt request on the PCIe controller side configured in EP mode to verify whether the PCIe controller side configured in RC mode can correctly receive MSI or MSI. X interrupt signal, and resolve interrupt vector number.

[0050] S106 collects readback data or interrupt status from the PCIe controller side configured in EP mode, automatically compares it with the preset expected value, and outputs the verification conclusion.

[0051] In some embodiments of this application, the specific process of collecting readback data from the PCIe controller configured in EP mode and automatically comparing it with a preset expected value includes: in the TLP and BAR verification stages, the PCIe controller configured in RC mode reads the BAR mapping space of the PCIe controller configured in EP mode using PIO to obtain first readback data, and compares the first readback data with the original data at the time of writing; in the HDMA verification stage, the PCIe controller configured in EP mode reads the data after DMA transfer from the target storage space to obtain second readback data, and compares the second readback data with the source data in the local memory of the RC mode side; in the ATU verification stage, the PCIe controller configured in RC mode reads the data in the target address space after ATU conversion to obtain third readback data, and compares the third readback data with the expected address mapping data.

[0052] In some embodiments of this application, the specific process of collecting interruption status and automatically comparing it with a preset expected value includes: in MSI / MSI In the X interrupt verification process, the interrupt signal status and interrupt vector number received by the PCIe controller configured in RC mode are collected; the interrupt signal status is compared with the expected interrupt trigger status; and the parsed interrupt vector number is compared with the preset expected interrupt vector number.

[0053] In some embodiments of this application, the specific process of automatically comparing with a preset expected value includes: in the MCTP verification stage, obtaining the MCTP message content received and decapsulated through the closed-loop path; comparing the decapsulated MCTP message content with the original MCTP message content before encapsulation field by field to verify the correctness of the encapsulation and decapsulation process of the MCTP over PCIe message.

[0054] In some embodiments of this application, the specific process of generating and outputting verification conclusions includes: when TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI... When the comparison results of each verification step in the X interruption verification are consistent, a verification conclusion indicating that PCIe and related internal IP functions have passed is generated and output; or, when TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification are all consistent, a verification conclusion indicating that PCIe and related internal IP functions have passed is generated and output; If the comparison result of any verification step in the X interruption verification is inconsistent, the abnormal verification step with inconsistent comparison result is identified; a verification conclusion containing the failure identifier and abnormal data information of the abnormal verification step is generated and output.

[0055] For example Figure 7 As shown, Figure 7 This is a schematic diagram of a verification conclusion output process provided in this application. The system-level functional verification module executes specific test items and then transfers the generated actual running results to the result comparison module. The result comparison module first collects the business data or interruption status read back from the EP (Endpoint) mode side and automatically compares it with the preset expected value. Then, it judges whether the comparison result is consistent. If the comparison result is "yes" (i.e., data matches), the process moves to the left and directly outputs the conclusion that the verification is passed. If the comparison result is "no" (i.e., there is a deviation in the data), the process moves to the right, accurately locates and outputs a detailed error conclusion containing the abnormal link identifier and specific error data information, thereby completing the automated judgment and feedback of the entire verification closed loop.

[0056] In this embodiment, by utilizing at least two PCIe controllers integrated within the SoC chip that support dynamic configuration to RC or EP modes, and cross-interconnecting their transceiver channels to form a physical layer interconnect loop, a self-closing verification architecture completely independent of external commercial PCIe Verification IP is achieved. This system can directly and efficiently verify the chip's internal HDMA engine, ATU address translation unit, MCTP protocol encapsulation / decapsulation, and MSI / MSI... The real-world interaction scenarios of system-level functions such as X interrupt routing and BAR space configuration access significantly reduce the cost and integration cycle of setting up the verification environment. It avoids the problems of bloated simulation environment and decreased regression efficiency caused by the introduction of external VIPs. At the same time, since all verification components are natively designed inside the chip, they have good debuggability, thereby greatly improving verification coverage, test confidence and R&D efficiency.

[0057] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The SoC system-level functional verification program can be stored in a computer-readable storage medium. When executed, the program can include the processes of the embodiments of the above methods. The storage medium for SoC system-level functional verification can be a magnetic disk, optical disk, read-only memory, or random access memory, etc.

[0058] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A system-on-chip (SoC) system-level functional verification system, comprising: The system includes: The system-on-a-chip (SoC), at least two PCIe controllers integrated in the SoC, a configuration module, a link training and enumeration module, a system-level functional verification module, and a result comparison module; wherein... Each PCIe controller supports dynamic configuration to RC mode or EP mode. The at least two PCIe controllers include a first PCIe controller and a second PCIe controller. The transmitting end of the first PCIe controller and the receiving end of the second PCIe controller are connected via external differential traces. The transmitting end of the second PCIe controller is connected to the receiving end of the first PCIe controller to form a physical layer interconnect loop outside the SoC chip. The configuration module, link training and enumeration module, system-level function verification module, and result comparison module work together in sequence to configure the two PCIe controllers to EP mode and RC mode respectively, establish PCIe communication links and complete enumeration, perform a variety of preset system-level function verification steps under the physical layer interconnection loop, and automatically compare the readback data or interrupt status of the PCIe controller configured in EP mode with the preset expected values ​​before outputting the verification conclusion.

2. The system according to claim 1, characterized in that, The configuration module is used to write the configuration space of each PCIe controller into the control register, and configure one PCIe controller in RC mode and the other PCIe controller in EP mode. The link training and enumeration module is used to initiate link training by the PCIe controller configured in RC mode after the internal power supply and clock of the SOC chip are turned on, establish a PCIe communication link with the PCIe controller configured in EP mode, and execute the PCIe enumeration process by the PCIe controller configured in RC mode, read the configuration space of the PCIe controller configured in EP mode and perform address allocation and space configuration on its base address register. The system-level functional verification module is used to perform multiple preset system-level functional verification steps under the physical layer interconnection loop; The result comparison module is used to collect readback data or interrupt status from the PCIe controller side configured in EP mode, automatically compare it with the preset expected value, and generate and output the verification conclusion.

3. The system of claim 2, wherein, The pre-defined multiple system-level functional verification steps include TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI verification. At least one of the X interruption verification methods; wherein... The TLP and BAR verification are used to directly read and write the BAR mapping space of the PCIe controller configured in EP mode via PIO through the PCIe controller configured in RC mode, in order to verify the routing and data integrity of TLP. The HDMA verification is used to start the HDMA engine inside the SoC chip, configure its source address to the local memory on the RC mode side and its destination address to the BAR space on the EP mode side, initiate DMA transfer, and verify the continuous streaming transmission capability of PCIe as a data path.

4. The system according to claim 2, characterized in that, The ATU verification is used to configure the address translation unit inside the SoC chip to verify the correctness of the address mapping after ATU translation of the Outbound request issued by the RC mode side and the Inbound completion message returned by the EP mode side. The MCTP verification is used to trigger the MCTP module inside the SoC chip, encapsulate the MCTP over PCIe message, send and receive it through the closed-loop path from the RC mode side to the EP mode side, and verify the layer 2 decapsulation and routing logic of the message. The MSI / MSI X interrupt verification is used to trigger an interrupt request on the PCIe controller side configured in EP mode to verify whether the PCIe controller side configured in RC mode can correctly receive MSI or MSI. X interrupt signal, and resolve interrupt vector number.

5. The system of claim 3, wherein, Collect readback data from the PCIe controller configured in EP mode and automatically compare it with preset expected values, including: In the TLP and BAR verification process, the PCIe controller configured in RC mode reads the BAR mapping space of the PCIe controller configured in EP mode in PIO mode to obtain the first readback data, and compares the first readback data with the original data at the time of writing. In the HDMA verification process, the data after DMA transfer is read from the target storage space on the PCIe controller side configured in EP mode to obtain the second readback data, and the second readback data is compared with the source data in the local memory on the RC mode side. In the ATU verification process, the PCIe controller configured in RC mode reads the data in the target address space after ATU conversion to obtain the third readback data, and compares the third readback data with the expected address mapping data.

6. The system of claim 3, wherein, Collect interruption status and automatically compare it with preset expected values, including: In the MSI / MSI In the X-interrupt verification link, the collection is configured to receive the interrupt signal state and the interrupt vector number of the PCIe controller side in the RC mode. The interrupt signal status is compared with the expected interrupt trigger status; The parsed interrupt vector number is compared with the preset expected interrupt vector number.

7. The system of claim 3, wherein, Automatically compare with preset expected values, including: In the MCTP verification process, the content of the MCTP message received and decapsulated through the closed-loop path is obtained; The decapsulated MCTP message content is compared field by field with the original MCTP message content before encapsulation to verify the correctness of the encapsulation and decapsulation process of MCTP over PCIe messages.

8. The system of claim 3, wherein, The generation and output of verification conclusions include: When the TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI When the comparison results of each verification link in the X interrupt verification are consistent, a verification conclusion that the PCIe and related internal IP function verification is passed is generated and output; or, When the TLP and BAR verification, HDMA verification, ATU verification, MCTP verification, and MSI / MSI are performed... If the comparison result of any verification step in the X interruption verification is inconsistent, the abnormal verification step with inconsistent comparison result is determined. Generate a verification conclusion that includes the failure identifier and abnormal data information of the aforementioned abnormal verification step, and output the verification conclusion.

9. The system of claim 2, wherein, The step of writing the configuration space of each PCIe controller into the control register includes: The mode selection registers are written to the configuration spaces of the first PCIe controller and the second PCIe controller via the internal configuration bus of the SoC chip. The first PCIe controller can be configured in RC mode and the second PCIe controller in EP mode; or, After completing the mode configuration, the link training enable register is written to the configuration space of each PCIe controller through the internal configuration bus to start the link training state machine of each PCIe controller.

10. A method for SoC system level functional verification implemented using the system of any of claims 1-9, wherein, The method includes: At least two PCIe controllers are integrated inside the SoC chip; the at least two PCIe controllers include a first PCIe controller and a second PCIe controller, and each PCIe controller supports dynamic configuration to RC mode or EP mode; The transmitter of the first PCIe controller is connected to the receiver of the second PCIe controller via external differential traces, and the transmitter of the second PCIe controller is connected to the receiver of the first PCIe controller to form a physical layer interconnect loop outside the SoC chip. Configure the two PCIe controllers to RC mode and EP mode respectively; The PCIe controller configured in RC mode initiates link training, establishes a PCIe communication link with the PCIe controller configured in EP mode, and executes the PCIe enumeration process. Multiple preset system-level functional verification steps are performed under the physical layer interconnection loop; Collect readback data or interrupt status from the PCIe controller side configured in the EP mode, automatically compare it with the preset expected value, and output the verification conclusion.

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