Memristive circuit of pavlovian associative memory with high-order conditional reflexes

Abstract

This invention belongs to the field of neuromorphic computing and brain-like hardware technology, and discloses a memristor circuit with Pavlovian associative memory featuring high-order conditioned reflexes. It includes N level processing modules, N-1 control circuit modules, a synaptic circuit module, and an output circuit module. The level processing modules perform noise reduction on the input signals, which are then processed by the corresponding control circuit modules to output learning and active forgetting signals. This changes the resistance value of the memristor in the corresponding synaptic circuit module, thereby generating a judgment signal indicating whether a conditioned reflex can be generated. The judgment signal output by the synaptic circuit module is then processed by the output circuit module to generate a result indicating whether a salivary response can be generated under N stimuli. This invention supports the flexible construction of multi-level stimulus relationships and takes into account the synergistic regulation of the learning and forgetting processes, more closely resembling the real learning behavior of biological nervous systems, and meeting the practical needs of neuromorphic computing and brain-like intelligent hardware development.

Description

Technical Field

[0001] This invention belongs to the field of neuromorphic computing and brain-like hardware technology, and more specifically, relates to a memristor circuit with Pavlovian associative memory that has higher-order conditioned reflexes. Background Technology

[0002] With the rapid development of artificial intelligence, neuromorphic computing, and new computing architectures, traditional computing systems based on the von Neumann architecture, due to the separation of computing and storage units, experience significant energy consumption and latency during data transfer. This makes them increasingly unable to meet the high energy efficiency, adaptability, and real-time requirements of next-generation intelligent sensing and cognitive computing. Especially in the post-Moore's Law era, with the continuous growth in computing power demand, traditional computing paradigms face significant bottlenecks in terms of energy efficiency and scalability.

[0003] Neuromorphic computing, a novel computing paradigm inspired by biological nervous systems, simulates the collaborative computing mechanisms of neurons and synapses at the hardware level to achieve event-driven information processing. It effectively supports in-memory computing models and offers significant advantages in reducing power consumption, improving parallelism, and enhancing system robustness. Therefore, neuromorphic computing has become an important development direction for brain-like intelligence and novel computing architectures.

[0004] From the perspective of learning mechanisms, biological nervous systems not only possess non-associative learning abilities such as habituation and sensitization, but also can form higher-level cognitive functions such as conditioned reflexes and multimodal associations. Among these, associative learning, by establishing mapping relationships between different stimuli, enables organisms to adapt to complex environments and make effective decisions. Pavlovian conditioning, as a typical form of associative learning, has its core mechanism in achieving learning and memory through a stimulus-response-association process, and further developing second-order and even higher-order conditioned reflex abilities.

[0005] Among hardware devices for realizing neuromorphic associative learning, memristors have become ideal devices for simulating the plasticity of biological synapses due to their continuously adjustable conductance, non-volatile storage, low power consumption, and good scalability. The conductance state of a memristor can be used to characterize changes in synaptic weights, thereby realizing learning and memory functions at the circuit level. Currently, memristors have shown broad application potential in multiple fields such as non-volatile storage, reconfigurable logic, circuit nonlinear dynamics, and neuromorphic computing.

[0006] Memristor-based neural network circuits typically use memristors as synaptic units to achieve connections and weight adjustments between neurons. Memristor neural networks, built upon Pavlovian conditioning principles, have been able to achieve associative learning and conditioned reflex memory between conditioned and unconditioned stimuli to a certain extent. However, most existing memristor associative learning circuits only support first-order or finite-level conditioned reflexes; their stimulus order and hierarchical structure are usually predetermined, making it difficult to flexibly express complex stimulus relationships.

[0007] Furthermore, biological nervous systems possess forgetting mechanisms during the learning process, including natural forgetting (passive forgetting) that decays over time and active forgetting triggered by new stimuli. This is crucial for maintaining system stability and avoiding erroneous associations. However, existing memristor associative learning circuits provide relatively simple descriptions of the forgetting process and typically lack effective support for the synchronous forgetting mechanism of associated memories in multi-level conditioned reflexes, thus limiting their biological rationality and long-term reliability.

[0008] Therefore, existing technologies still urgently need a memristor circuit scheme that can realize high-order conditioned reflex associative learning at the hardware level to support the flexible construction of multi-level stimulus relationships and take into account the synergistic regulation of learning and forgetting processes, so as to more closely resemble the real learning behavior of biological nervous systems and meet the actual needs of neuromorphic computing and brain-like intelligent hardware development. Summary of the Invention

[0009] To address the above-mentioned deficiencies or improvement needs of existing technologies, this invention provides a memristor circuit with Pavlovian associative memory featuring higher-order conditioned reflexes. The purpose is to construct a memristor circuit scheme that realizes higher-order conditioned reflex associative learning at the hardware level, so as to support the flexible construction of multi-level stimulus relationships and take into account the synergistic regulation of the learning and forgetting processes, thereby more closely resembling the real learning behavior of biological nervous systems.

[0010] To achieve the above objectives, the present invention provides a memristor circuit with Pavlovian associative memory of higher-order conditioned reflexes, comprising: N level processing modules, N-1 control circuit modules, a first synaptic circuit module, N-1 second synaptic circuit modules, and an output circuit module; The input terminals of the N level processing modules are respectively connected to the N input signals to convert the N input signals into corresponding high or low levels; wherein, the N input signals include one input signal S0 representing a food stimulus and N-1 input signals {S} representing other neutral stimuli besides the food stimulus. i | i∈{1,2,…,N-1},N≥4},and the input signal is a voltage signal; All N-1 control circuit modules have the same structure, wherein the i-th control circuit module includes: The first AND gate array is used to convert S i The corresponding levels are respectively divided by S i The levels corresponding to the remaining N-1 input signals are ANDed to obtain N-1 AND results D. 1 0, D 1 1、…、D 1 (i-1) D 1 (i+1) ... D 1 (N-1) Wherein, the level refers to the high or low level output after the input signal has passed through the corresponding level processing module; D 1 0 represents S i The result of ANDing the corresponding level with the level corresponding to S0, D 1 j S represents i The corresponding level and S j The result of the AND operation on the corresponding level is j∈{1,2,…,N-1, and j≠i}; The second AND gate array is used to store the AND operation result D. 1 j Perform an AND operation with the output of the j-th second synaptic circuit module to obtain the AND result D. 2 j ; The first OR gate is used to perform a bitwise AND operation on the result D. 1 0 and the result of the AND operation D 2 j Perform an OR operation to obtain the first OR result; the first OR result serves as the learning signal. , When it is high, it indicates that in S i Learning is stimulated by [the environment / initiatives]. XOR gate array, used to convert S i The corresponding levels are respectively divided by S i The levels corresponding to the remaining N-1 input signals are XORed to obtain N-1 XOR results Y0, Y1, ..., Y... (i-1) Y (i+1) ..., Y (N-1) Where Y0 represents S i The result of XORing the corresponding level with the level corresponding to S0 is Y. j S represents i The corresponding level and S j The result of XORing the corresponding voltage levels; The third AND gate array is used to process the XOR operation result Y. j Perform an AND operation with the output of the j-th second synaptic circuit module to obtain the AND result D.3 j ; The second OR gate is used to combine the XOR result Y0 and the AND result D. 3 j Perform an OR operation to obtain the second OR result; NOT gate, used to convert the learning signal Perform a NOT operation to obtain the NOT result; The fourth AND gate is used to perform an AND operation between the NOT result and the second OR result, and the result of the AND operation is used as an active forgetting signal. , When it is high, it indicates that in S i Active forgetting occurs under the stimulation of [the stimulus]. The output of the level processing module, whose input is connected to S0, is connected to the input of the first synaptic circuit module. The first synaptic circuit module outputs a judgment signal on whether a conditioned reflex can be generated under the stimulation of S0. The N-1 second synaptic circuit modules have identical structures, and the i-th second synaptic circuit module includes a memristor for use based on the learning signal. and the active forgetting signal Adjust its resistance value to output at S i The signal used to determine whether a conditioned reflex can be produced under a stimulus; The output terminals of the first synaptic circuit module and the N-1 output terminals of the second synaptic circuit modules are all connected to the input terminal of the output circuit module. The output of the output circuit module is located at S0, S1, S2, ..., S... N-1 The result of whether a salivary response can be produced under stimulation.

[0011] Furthermore, the first AND gate array includes N-1 AND gates D 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D 1 L(N-1) The second AND gate array includes N-2 AND gates D. 2 L1 D 2 L2 ... D 2 L(i-1) D 2 L(i+1) ... D 2 L(N-1) The third AND gate array includes N-2 AND gates D. 3 L1 D 3L2 ... D 3 L(i-1) D 3 L(i+1) ... D 3 L(N-1) The fourth AND gate includes the AND gate D. 4 L1 The XOR gate array includes N-1 XOR gates D Y0 D Y1 ... D Y(i-1) D Y(i+1) ... D Y(N-1) The first OR gate includes OR gate D. H1 The second OR gate includes OR gate D. H2 NOT gates include NOT gate D. F1 ; N-1 AND gates D 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D 1 L(N-1) The signals at the first input terminal are all S i The corresponding levels, the signals at the second input terminal are respectively excluding S i The levels corresponding to the remaining N-1 input signals, excluding those from the AND gate D; where, 1 L0 The signal at the second input terminal is the level corresponding to S0, and the AND gate D... 1 Lj The signal at the second input terminal is S. j The corresponding level; AND gate D 1 Lj The output terminal is connected to gate D. 2 Lj The first input terminal, AND gate D 2 Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module; AND gate D 1 L1 The output terminal and AND gate D 2 Lj The outputs of all terminals are connected to an OR gate D. H1 The input terminal of the OR gate D H1 The learning signal is output from the output terminal. ; N-1 XOR gates D Y0 D Y1 ... D Y(i-1) DY(i+1) ... D Y(N-1) The signals at the first input terminal are all S i The corresponding levels, the signals at the second input terminal are respectively excluding S i The levels corresponding to the remaining N-1 input signals, excluding those from the XOR gate D; where, Y0 The signal at the second input terminal is the level corresponding to S0, XOR gate D Yj The signal at the second input terminal is S. j The corresponding level; XOR gate D Yj The output terminal is connected to gate D. 3 Lj The first input terminal, AND gate D 3 Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module; XOR gate D Y0 The output terminal and AND gate D 3 Lj The outputs of all terminals are connected to an OR gate D. H2 The input terminal; NOT gate D F1 The input terminal is connected to the OR gate D. 1 H1 The output of the NOT gate D F1 Output of AND-OR gate D H2 The output terminals are respectively connected to gate D. 4 L1 The first and second input terminals of the AND gate D 4 L1 The active forgetting signal is output from the output terminal. .

[0012] Furthermore, the i-th second synaptic circuit module also includes a signal processing circuit and a conditional reflex judgment signal generation circuit; The signal processing circuit includes a threshold switch S. s1 S s2 and adders; Threshold switch S s1 One end is connected to a preset negative voltage signal V1 representing active forgetting, and the other end is connected to the first input terminal of the adder, used to input the active forgetting signal. When the signal is high, it closes to pass V1 to the first input of the adder, and in the active forget signal... Disconnect when the signal is low; Threshold switch S s2 One end is connected to a preset positive voltage signal V2 representing the learning, and the other end is connected to the second input terminal of the adder, used to input the learning signal. When the signal is high, it closes to pass V2 to the second input of the adder, and in the learning signal... Disconnect when the signal is low; The adder performs addition operations on the signals at its first, second, and third input terminals, and transmits the result to the positive terminal of the memristor; wherein, the signal at the third input terminal of the adder is a preset negative voltage signal V3 representing passive forgetting, and its absolute value is... Greater than absolute value And V2 is greater than the preset positive threshold and absolute value of the memristor. The sum of; The conditional reflex judgment signal generation circuit is used to convert the resistance value of the memristor into a value in S. i A judgment signal for whether a conditioned reflex can be generated under a stimulus; wherein, when the judgment signal is low, it indicates that a conditioned reflex is generated under S. i When a conditioned reflex cannot be produced under stimulation, and the judgment signal is high, it indicates that a conditioned reflex is not produced under stimulation. i A conditioned reflex can be produced under stimulation.

[0013] Furthermore, the memristor is based on the learning signal and the active forgetting signal Adjust its resistance value, including In the learning signal When the level is high, the operation result transmitted from the output of the adder to the positive terminal of the memristor is greater than the preset positive threshold of the memristor, and the resistance of the memristor decreases. In the active forgetting signal When the level is high, the result of the operation transmitted from the output of the adder to the positive terminal of the memristor is less than the preset negative threshold of the memristor, and the resistance of the memristor decreases. In the learning signal and the active forgetting signal When both are at low levels, the result of the operation transmitted from the adder output to the positive terminal of the memristor is less than the preset negative threshold of the memristor, the resistance of the memristor decreases, and the rate of decrease is less than that of the active forgetting signal. The descent rate when the voltage level is high.

[0014] Furthermore, the conditional reflex judgment signal generation circuit includes: an inverting amplifier, an ABM1 device, and a comparator; The negative input terminal of the inverting amplifier is connected to the negative terminal of the memristor, the positive input terminal of the inverting amplifier is grounded, the output terminal of the inverting amplifier is connected to the first input port of the ABM1 device, the positive terminal of the memristor is connected to the second input port of the ABM1 device, and the output of the ABM1 device is connected to the comparator. The output of the ABM1 device The output voltage of the inverting amplifier is the quotient of the voltage at the positive terminal of the memristor, and the output voltage of the inverting amplifier is determined based on the resistance value of the memristor and the voltage at its positive terminal; the comparator is used to convert the output of the ABM1 device... Compared with a preset threshold, the result is obtained in S i The signal used to determine whether a conditioned reflex can be produced under a stimulus.

[0015] Furthermore, the first synaptic circuit module includes a resistor with a resistance value exceeding a preset threshold, used to convert the level corresponding to S0 into a judgment signal for whether a conditioned reflex can be generated; wherein, when the level corresponding to S0 is high, the first synaptic circuit module outputs a judgment result indicating that a conditioned reflex can be generated; otherwise, it outputs a judgment result indicating that a conditioned reflex cannot be generated.

[0016] Furthermore, the output circuit module includes: N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) , and OR gate D H3 ; AND gate D 5 L0 The first input terminal is connected to the output terminal of the first synaptic circuit module, and AND gate D. 5 L0 The second input signal is S0; AND gate D 5 Li The first input terminal is connected to the output terminal of the i-th second synaptic circuit module, AND gate D 5 Li The second input signal is S i ; N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) The outputs of all terminals are connected to an OR gate D. H3 The input terminal of the OR gate D H3 The output terminals are located at S0, S1, S2, ..., S N-1 The result of whether a salivary response is produced under stimulation; among which, OR gate D H3 When the output terminal outputs a high level, it indicates that a saliva reaction can be generated; otherwise, it indicates that a saliva reaction cannot be generated.

[0017] Furthermore, the N level processing modules all have the same structure, and each level processing module includes a comparator for comparing the corresponding input signal with a preset threshold to convert the corresponding input signal into a corresponding high level or low level.

[0018] Furthermore, each level processing module includes a comparator consisting of two PMOS transistors and two NMOS transistors.

[0019] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: (1) This invention designs a high-order conditioned reflex neural network architecture, overcoming the dependence of traditional circuits on fixed stimulus sequences. Specifically, the control circuit module designed in this invention uses a first AND gate array to perform a preliminary judgment on the signals of neutral stimuli other than food stimuli in conjunction with other input signals. Only when both are at a high level simultaneously, the preliminary association pairing is established. Subsequently, a second AND gate array is used to introduce a judgment signal (output result of the second synaptic circuit module) to determine whether the corresponding conditioned stimulus (input signal) can produce a conditioned reflex, and a second gating is performed. Only when the results of the two AND operations are both at a high level, the learning signal output by the control circuit module indicates that the current input signal is a valid multimodal learning event (i.e., the current input signal is in a learning state). Meanwhile, this circuit also considers the coordinated regulation of the learning and forgetting processes. In the generation of the active forgetting signal, the conditioned stimulus is first judged by an XOR gate array. When only one conditioned stimulus is applied (the XOR gate outputs a high level), the circuit identifies the "active extinction" condition. Then, a second gating judgment is performed by combining the corresponding conditioned stimulus with a third AND gate array to determine whether a conditioned reflex can be generated (the output of the second synaptic circuit module). A NOT gate is also used to ensure that the current state is not in a learning state before finally generating the active forgetting signal. The generation method of the learning signal and the active forgetting signal in this invention correlates and controls each stimulus, overcoming the dependence of traditional circuits on fixed stimulus sequences. This makes it closer to the real learning and active forgetting behavior of biological nervous systems and allows for flexible definition of stimulus hierarchy relationships. Furthermore, this control circuit module has excellent scalability, supporting three or more layers of conditioned reflexes through cascading (the order of the conditioned reflex is flexibly configured according to the number of input signals N, where the order of the conditioned reflex is equal to N-1), laying the foundation for the hardware implementation of advanced cognitive functions.

[0020] (2) Furthermore, the high-order conditioned reflex circuit proposed in this invention simultaneously introduces a natural forgetting mechanism and an active forgetting mechanism. The active forgetting mechanism achieves synchronous forgetting of conditioned reflexes based on historical association (the third AND gate array combines the judgment signal of whether the corresponding conditioned stimulus can produce a conditioned reflex for secondary gating judgment), making the forgetting process more in line with biological characteristics and improving the reliability of high-order learning.

[0021] In general, this invention is a high-order conditioned reflex bionic circuit based on memristors. This architecture realizes an associative learning mechanism for various input conditioned stimuli, such as unconditioned stimuli (e.g., food) and conditioned stimuli (e.g., ringing, light, smell). It can flexibly define the hierarchical relationship of stimuli and support the formation of high-order conditioned reflexes. Attached Figure Description

[0022] Figure 1 This is a diagram illustrating the basic formation principle of a third-order conditioned reflex.

[0023] Figure 2 This is a diagram of a memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes, as described in an embodiment of the present invention.

[0024] Figure 3 This is a structural diagram of the control circuit module in an embodiment of the present invention.

[0025] Figure 4 This is a structural diagram of the second synaptic circuit module in an embodiment of the present invention.

[0026] Figure 5 This is a diagram of a memristor circuit with Pavlovian associative memory having third-order conditioned reflexes in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In this invention, the terms "first," "second," etc., used in the invention and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] Higher-order associative learning refers to the process of linking multiple stimuli through associative chains. Different neutral stimuli are connected to salivary neurons via synaptic modules. In Pavlov's second-order associative learning experiment (where the input signals only included food, bell, and light signals), the primary circuit was responsible for establishing the association between the food and bell signals; in circuit design, this learning process is achieved through state changes of memristors within the synaptic modules. Subsequently, this state information is transmitted to the second-order associative learning module, thereby establishing a connection between the bell and light signals. Higher-order associative learning follows a similar process to second-order associative learning, allowing associative memories to be transferred to more levels.

[0030] Figure 1The basic formation process of a third-order conditioned reflex was simulated, with input signals including food, bell sounds, light, and odors. This third-order conditioned reflex model consists of four input neurons (N1, N2, N3, N4) and one output neuron (N5). The input neurons are connected to the output neuron via synapses, where W... 15 W 25 W 35 and W 45 The figure represents synaptic weights. The three sets of arrows in the diagram indicate that the synaptic weight between each neutral stimulus and salivation affects the synaptic weights corresponding to other stimuli. Preliminary experimental results show that food can trigger salivation; this innate stimulus-response relationship is an unconditioned reflex, therefore the synaptic weight W... 15 It was initially assigned a high value.

[0031] Meanwhile, N2, N3, and N4 represent neutral stimuli such as ringing, light, and odor, respectively. Since these stimuli initially fail to induce salivation, their corresponding synaptic weights W... 25 W 35 and W 45 The value was set to a low value. In the existing simulation experiment, the bell stimulus and the food stimulus were presented simultaneously at the beginning. After repeated training, the synaptic weight W... 25 The connection is gradually strengthened, thus establishing a link between N2 and N5. After a period of time, the mere presentation of a bell stimulus can activate the output neuron N5, triggering salivation, and thus a classical conditioned reflex is formed.

[0032] Subsequently, a combined stimulus of light and ringing was introduced. Since the ringing already had an activating effect, during the combined stimulus training phase, the synaptic weight W corresponding to the light stimulus... 35 Gradually increasing, while W 25 During this process, the intensity decreases slightly. Through repeated training, light stimulation gradually acquires the ability to induce saliva secretion, and even without direct association with food, it can activate neuron N5, thereby forming a secondary conditioned reflex.

[0033] Next, when light stimulation and odor stimulation work together, the synaptic weight W corresponding to the odor stimulation... 45 Further enhancements were made. Ultimately, the experiment achieved a tertiary conditioned reflex—the output neuron was activated simply by presenting an odor stimulus.

[0034] As can be seen, in the process of establishing a three-level conditioned reflex, the stimulus sequence and hierarchical structure are fixed. The stimulus sequence follows a fixed sequence of food, bell, light, and smell to train the corresponding synaptic weights, and the hierarchical structure is also a fixed three levels, which makes it difficult to flexibly express complex stimulus relationships.

[0035] Based on this, such as Figure 2 As shown, this embodiment of the invention provides a memristor circuit for Pavlovian associative memory with higher-order conditioned reflexes. The circuit's input signals are N input signals representing neutral stimuli, where N≥4, forming an N-1 order conditioned reflex Pavlovian associative memory memristor circuit. The number of N can be flexibly set according to actual needs. Among the N input signals, one input signal is a voltage signal representing a food stimulus, denoted as S0; the other N-1 input signals are voltage signals representing other neutral stimuli besides the food stimulus. The set of input signals representing other neutral stimuli besides the food stimulus is denoted as S={S1,S2,……,S...}. N-1}.like Figure 3 As shown, Figure 3 The number of input signals N=4, and the input signal S0 representing the food stimulus is V. food The other three input signals S1, S2, and S3 represent the input signals V for ringing, light, and odor stimuli, respectively. ring V light and V odor That is, S1, S2, and S3 correspond to V. ring V light and V odor .

[0036] The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes in this embodiment of the invention includes: N level processing modules, N-1 control circuit modules, a first synaptic circuit module, N-1 second synaptic circuit modules, and an output circuit module; wherein, Figure 2 control circuit 1 to control circuit N-1 This represents N-1 control circuit modules, where synapse0 represents the first synapse circuit module, and synapse1 to synapse... N-1 This represents N-1 second synaptic circuit modules, where N salivation This indicates the output circuit module.

[0037] The input terminals of the N level processing modules are respectively connected to the N input signals. Each level processing module is used to perform logic level conversion on the corresponding input signal, converting it into a corresponding high level or low level. In this embodiment of the invention, the level processing module is a comparator, which converts the corresponding input signal into a high level or low level by comparing each input signal with a preset threshold voltage.

[0038] The i-th control circuit module is used to process the i-th input signal S in set S. i (S) i The level corresponding to ∈S is processed to obtain the learning signal corresponding to the i-th input signal in set S. and active forgetting signals ; The output of the i-th control circuit module is connected to the input of the i-th second synaptic circuit module in the N-1 second synaptic circuit modules. The i-th second synaptic circuit module outputs a judgment signal in set S to determine whether the i-th input signal can generate a conditioned reflex. The input terminal of the first synaptic circuit module is connected to the level corresponding to the input signal representing the food stimulus output by the level processing module, and the output terminal of the first synaptic circuit module outputs a judgment signal representing whether the input signal representing the food stimulus can produce a conditioned reflex. The output of the first synaptic circuit module and the outputs of the N-1 second synaptic circuit modules are all connected to the input of the output circuit module. The output circuit module outputs the result of whether the current N input signals produce a saliva response.

[0039] As a specific implementation, the N-1 control circuit modules have the same structure. The i-th control circuit module includes a first AND gate array, a second AND gate array, a third AND gate array, a fourth AND gate, a first OR gate, a second OR gate, an XOR gate array, and a NOT gate.

[0040] The first AND gate array is used to perform AND operations on the level corresponding to the i-th input signal in set S with the levels corresponding to the remaining N-1 input signals (excluding the i-th input signal), obtaining the corresponding N-1 AND operation results D. 1 0, D 1 1、…、D 1 (i-1) D 1 (i+1) ... D 1 (N-1) , i∈{1,2,…,N-1}; where, D 1 0 represents the result of a bitwise AND operation between the level of the i-th input signal and the level of the input signal representing the food stimulus, D 1 j Let represent the result of AND operation between the level corresponding to the i-th input signal and the level corresponding to the j-th input signal in set S, where j∈{1,2,…,N-1, and j≠i}.

[0041] The second AND gate array is used to process the AND operation result D. 1 j Perform an AND operation with the output of the j-th second synaptic circuit module (the judgment signal for whether the j-th input signal can generate a conditioned reflex) to obtain the AND operation result D. 2 j ; The first OR gate is used to perform a bitwise AND operation on the result D. 1 0 and the result of the operation D 2 jPerform an OR operation to obtain the first OR result; where the first OR result is the learning signal. This is used to determine whether learning should occur under the stimulus of the i-th input signal in set S; the learning signal... When the signal is high, it indicates that learning is in progress; the learning signal... When the level is low, it indicates that no learning is performed.

[0042] An XOR gate array is used to perform an XOR operation on the level corresponding to the i-th input signal in set S with the levels corresponding to the remaining N-1 input signals (excluding the i-th input signal), resulting in N-1 XOR operation results Y0, Y1, ..., Y... (i-1) Y (i+1) ..., Y (N-1) , i∈{1,2,…,N-1}; where Y0 represents the result of XORing the level corresponding to the i-th input signal with the level corresponding to the input signal representing the food stimulus, Y j Let represent the result of XORing the level corresponding to the i-th input signal with the level corresponding to the j-th input signal in set S, where j∈{1,2,…,N-1, and j≠i}.

[0043] The third AND gate array is used to perform an XOR operation on the result Y. j Perform an AND operation with the output of the j-th second synaptic circuit module to obtain the AND result D. 3 j ; The second OR gate is used to combine the XOR operation result Y0 and the AND operation result D. 3 j Perform an OR operation to obtain the second OR result; The NOT gate is used to perform a NOT operation on the result of the first OR operation to obtain the NOT result; The fourth AND gate is used to perform an AND operation on the result of the NOT operation and the result of the second OR operation. The result of the AND operation is the active forgetting signal. This is used to determine whether active forgetting occurs under the stimulus of the i-th input signal in set S; the active forgetting signal... When the signal is high, it indicates active forgetting; active forgetting signal. When the level is low, it indicates that active forgetting is not performed.

[0044] Specifically, in the i-th control circuit module, the first AND gate array includes N-1 AND gates D. 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D1 L(N-1) The second AND gate array includes N-2 AND gates D. 2 L1 D 2 L2 ... D 2 L(i-1) D 2 L(i+1) ... D 2 L(N-1) The third AND gate array includes N-2 AND gates D. 3 L1 D 3 L2 ... D 3 L(i-1) D 3 L(i+1) ... D 3 L(N-1) The fourth AND gate includes AND gate D. 4 L1 The first OR gate includes OR gate D. H1 The second OR gate includes OR gate D. H2 The XOR gate array includes N-1 XOR gates D Y0 D Y1 ... D Y(i-1) D Y(i+1) ... D Y(N-1) NOT gates include NOT gate D. F1 The connection relationships are as follows: AND gate D 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D 1 L(N-1) The signals at the first input terminal are all the levels corresponding to the i-th input signal in set S, and the signals at the second input terminal are the levels corresponding to the remaining N-1 input signals excluding the i-th input signal; where, AND gate D 1 L0 The signal at the second input terminal is the level corresponding to the input signal representing the food stimulus, and is connected to the D gate. 1 Lj The signal at the second input terminal is the level corresponding to the j-th input signal in set S, where j∈{1,2,…,N-1, and j≠i}; AND gate D 1 Lj The output terminal and AND gate D 2 Lj The first input terminal is connected to the AND gate D. 2Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module (used to generate a judgment signal on whether the j-th input signal can produce a conditioned reflex); AND gate D 1 L1 The output terminal and AND gate D 2 Lj The output terminal is connected to the OR gate D. H1 The input terminal, where the OR gate D H1 It can be a multi-input OR gate, or a combination of multiple commonly used standard OR gates. OR gate D 1 H1 The output terminal outputs the learning signal. The learning signal Used to determine whether learning should occur under the stimulus of the i-th input signal in set S; learning signal When the signal is high, it indicates that learning is in progress; the learning signal... When the level is low, it indicates that no learning is performed.

[0045] XOR gate D Y0 D Y1 ... D Y(i-1) D Y(i+1) ... D Y(N-1) The signals at the first input terminal are all the levels corresponding to the i-th input signal in set S, and the signals at the second input terminal are the levels corresponding to the remaining N-1 input signals excluding the i-th input signal; where, the XOR gate D Y0 The signal at the second input terminal is the level corresponding to the input signal representing the food stimulus, XOR gate D. Yj The signal at the second input terminal is the level corresponding to the j-th input signal in set S, where j∈{1,2,…,N-1, and j≠i}; XOR gate D Yj The output terminal and AND gate D 3 Lj The first input terminal is connected to the AND gate D. 3 Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module; XOR gate D Y0 The output terminal and AND gate D 3 Lj The output terminal is connected to the OR gate D. H2 The input terminal, where the OR gate D H2 It can be a multi-input OR gate, or a combination of multiple commonly used standard OR gates.

[0046] NOT gate D F1 The input terminal is connected to the OR gate D. 1H1 The output terminal is used to convert the OR gate D 1 H1 Output learning signal Invert the NOT gate D F1 The output terminal and OR gate D H2 The outputs of the gates are respectively connected to the AND gate D. 4 L1 The first and second input terminals are connected to the AND gate D. 4 L1 The output terminal outputs an active forgetting signal. Forgetting signals Used to determine whether active forgetting occurs under the stimulus of the i-th input signal in set S; active forgetting signal When the signal is high, it indicates active forgetting; active forgetting signal. When the level is low, it indicates that active forgetting is not performed.

[0047] The first synaptic circuit module includes a resistor with a resistance exceeding a preset threshold. It is used to convert the level corresponding to the input signal S0, which represents the food stimulus, output by the level processing module, into a judgment signal indicating whether a conditioned reflex can be generated. When the level corresponding to the input signal S0 is high, the first synaptic circuit module outputs a judgment result indicating that a conditioned reflex can be generated under the stimulation of the input signal S0. When the level corresponding to the input signal S0 is low, the first synaptic circuit module outputs a judgment result indicating that a conditioned reflex cannot be generated under the stimulation of the input signal S0.

[0048] All N-1 second synaptic circuit modules have the same structure. The i-th second synaptic circuit module includes a signal processing circuit, a memristor, and a conditional reflection judgment signal generation circuit.

[0049] The signal processing circuit, when the learning signal or active forgetting signal is high, adds a preset voltage signal representing learning or active forgetting to a preset voltage signal V3 representing passive forgetting (natural forgetting), and uses this sum as the positive input of the memristor. The signal processing circuit also adds the preset voltage signal V3 representing passive forgetting to 0 when both the learning signal and the active forgetting signal are low, and uses this sum as the positive input of the memristor. According to the design of the control circuit module described above, either the learning signal or the active forgetting signal can be high, or both can be low.

[0050] The memristor is used to dynamically change its resistance based on the positive input and a preset threshold. The resistance of the memristor is inversely proportional to the synaptic weight corresponding to the i-th input signal in the set S.

[0051] Specifically, the signal processing circuit includes a threshold switch S s1 S s2 And adders; threshold switch Ss1 Threshold switch S is used to close when the active forgetting signal is high, so as to transmit the negative voltage signal V1, which represents active forgetting, to the first input of the adder. s2 This is used to close the circuit when the learning signal is high, so as to pass the positive voltage signal V2, representing the learning, to the second input terminal of the adder; wherein, the absolute value of the voltage signal V1 is... Greater than the absolute value of the voltage signal V3, which characterizes passive forgetting. The passively forgotten voltage signal V3 is negative, and V2 is greater than the preset positive threshold and absolute value of the memristor. The sum of.

[0052] The adder is used to add the negative voltage signal V1 representing active forgetting or the positive voltage signal V2 representing learning to the negative voltage signal representing passive forgetting, and transmits the addition result to the positive terminal of the memristor.

[0053] Alternatively, the adder can be used to add the voltage signal V3, which represents passive forgetting, to 0 when both the active forgetting signal and the learning signal are low, and then use the result as the positive input of the memristor.

[0054] When the learning signal is high, V2 and V3 are added together (at this time, the active forgetting signal is low, and the voltage signal at the first input of the adder is 0). The result of the adder output is much greater than the positive threshold of the memristor, and the resistance of the memristor drops rapidly, indicating that the synaptic weight corresponding to the i-th input signal rises rapidly. When the active forgetting signal is high, V1 and V3 are added together (at this time the learning signal is low and the voltage signal at the second input of the adder is 0). The result of the adder output is much smaller than the negative threshold of the memristor, and the resistance of the memristor rises rapidly, indicating that the synaptic weight corresponding to the i-th input signal decreases rapidly. When both the active forgetting signal and the learning signal are low, after adding 0 and V3, the result of the adder output is just less than the negative threshold of the memristor. The resistance of the memristor rises slowly, indicating that the synaptic weight corresponding to the i-th input signal decreases slowly.

[0055] The conditional reflection judgment signal generation circuit is used to generate a judgment signal for whether the i-th input signal in set S can generate a conditional reflection based on the current resistance value of the memristor.

[0056] As a specific implementation, the output circuit module includes: N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) , and OR gate D H3 ; The output of the first synaptic circuit module is connected to gate D.5 L0 The first input terminal has a second input terminal signal that is an input signal S0 characterizing food stimulation; The output connection of the i-th second synaptic circuit module is D. 5 Li The first input terminal has a second input terminal signal that is the i-th input signal S in set S. i .

[0057] N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) The output terminal is connected to the OR gate D. H3 OR operation is performed on the input terminal of the OR gate D. H3 The output result serves as the result of whether the current N input signals produce a salivary response.

[0058] The following example, using N=4, further illustrates the structure of the memristor circuit for Pavlovian associative memory with multi-order conditioned reflexes designed in this embodiment of the invention. Figure 3 As shown, the four input signals S0, S1, S2, and S3 are V... food V ring V light and V odor Four level processing modules COMP1-COMP4 are used to process four input voltage signals V respectively. food V ring V light and V odor For noise reduction processing, each level processing module consists of a comparator composed of two PMOSFETs and two NMOSFETs. If the input voltage is lower than the preset threshold voltage of 2.5V, the comparator outputs 0V (low level); if the input voltage is higher than 2.5V, the comparator outputs 5V (high level).

[0059] The control circuit module determines the current state of the synapse (the memristor in the synapse circuit module) based on the input and output voltages—that is, whether it is in learning mode, active forgetting mode, or natural forgetting mode.

[0060] Taking ringing stimulation as an example, the structure of the control circuit module corresponding to the input signal Vring is explained. In this control circuit module, the first AND gate array contains three AND gates in sequence as follows: Figure 3 D in L1 D L2 D L3 The second AND gate array contains two AND gates, which are respectively: Figure 3 D inL4 D L5 The third AND gate array contains two AND gates, D, D, and D respectively. AF4 D AF5 The fourth AND gate contains the AND gate D. 4 L1 for Figure 3 D in AF8 First or gate D H1 for Figure 3 D in L6 Second OR gate D H2 for Figure 3 D in AF6 The XOR gate array contains three XOR gates, which are as follows: Figure 3 D in AF1 D AF2 and D AF3 NOT gate D F1 for Figure 3 D AF7 The connection relationships of each logic gate are as follows: Figure 3 As shown in Figure D. L6 Output V DL6 This is the learning signal. When D L6 When the output is high (V) DL6 (High level), ringtone stimulation initiates learning mode; D AF8 The output is the active forgetting signal. When D AF8 When the output is high (i.e.) If D is high, then the active forgetting state triggered by the ringing stimulus is activated. L6 and D AF8 At the same time, a low level is output, and the ringtone stimulation is converted into a state of natural forgetting. Figure 3 V in vision and V olfaction These represent the input signals V and V, respectively. light and V odor The corresponding second synaptic circuit module outputs a judgment signal to determine whether a conditioned reflex can be generated.

[0061] The other two input signals V light and V odor The corresponding control circuit module is designed similarly. Table 1 shows the truth table for different input signals.

[0062] Table 1 Truth table for different input signals

[0063] The core function of the synaptic module between input and output neurons is to transmit excitatory or inhibitory signals, and the strength of this connection is reflected by synaptic weights. As the core of biomimetic learning, the second synaptic circuit module uses memristors to simulate the dynamic changes in biological synaptic weights.

[0064] Regarding the design of the synaptic circuit module, since food stimulation is an unconditioned stimulus, the unconditioned reflex between food stimulation and salivation is stable. Therefore, for the input neuron N1 (voltage signal V... food The synapse between the input neurons N2, N3, and N4 (i.e., the first synaptic circuit module) and the output neuron N5 is directly replaced by a 45 kΩ resistor; ringing, light, and smell are all neutral stimuli, therefore the input neurons N2, N3, and N4 (input signal V) are directly replaced by a 45 kΩ resistor. ring V light and V odor The changes in synaptic weights between the output neuron N5 and the output neuron N6 are dynamically regulated by the corresponding second synaptic circuit modules. All three second synaptic circuit modules employ the following... Figure 3 The circuit structure shown represents the synaptic structure.

[0065] Figure 4 The voltage sources V1, V2, and V3 in the diagram represent the active forgetting voltage, the learning voltage, and the natural forgetting voltage, respectively, with corresponding values ​​of -5V, 6V, and -1.1V. s1 and S s2 It is a threshold switch, and its turn-on voltage V on Set to 4V, turn-off voltage V off Set to 0V. The switch closes when the voltage difference exceeds 4V (i.e., high-level input); otherwise, it opens. Operational amplifiers OP3 and OP4, along with resistors R7, R8, and R9, form an adder. The formula for calculating the output voltage of the adder is as follows: ; in, , , Resistors , , The node voltage connected to the negative input terminal of operational amplifier OP3.

[0066] The voltage at the positive terminal of the input memristor for: ; As an inverting amplifier, the OP5's output voltage The calculation formula is: ; in, This is the resistance value of the memristor.

[0067] The function of the ABM1 device is to divide the output voltage of OP5 by the positive terminal voltage of the memristor according to the formula: ; OP6 is a comparator whose function is defined by the following formula: ; The inverting amplifier OP5, ABM1, and comparator OP6 convert the resistance value of the memristor into a judgment signal to determine whether a conditioned reflection can be generated by the corresponding input signal. A high level indicates that a conditioned reflection can be generated, and a low level indicates that a conditioned reflection cannot be generated.

[0068] This synaptic module employs a synergistic design combining multi-voltage regulation and threshold switching, dynamically simulating synaptic plasticity through memristors. This allows the circuit to flexibly adjust synaptic weights under different stimulus conditions, becoming a key fundamental component for realizing multi-level conditioned reflexes. Through real-time weight modification, this module facilitates the realization of complex conditioned reflexes.

[0069] The output circuit module performs an AND operation between the unconditioned stimulus and the outputs of the three conditioned stimuli and their corresponding synaptic circuit modules, respectively, and then performs an OR operation between the results of each AND operation and an OR operation to determine whether there is a stimulus that can produce a salivary response.

[0070] The overall structure of the memristor circuit for Pavlovian associative memory in this third-order conditioned reflex is as follows: Figure 5 As shown.

[0071] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes, characterized in that, include: N level processing modules, N-1 control circuit modules, a first synapse circuit module, N-1 second synapse circuit modules, and an output circuit module; The input ends of the N-level processing modules are respectively connected with N input signals to convert the N input signals into corresponding high levels or low levels; wherein the N input signals include one input signal S0 representing food stimulation and N-1 input signals {S i | i∈{1,2,…,N-1},N≥4} and the input signals are voltage signals. All N-1 control circuit modules have the same structure, wherein the i-th control circuit module includes: The first AND gate array is used to convert S i The corresponding levels are respectively divided by S i The levels corresponding to the remaining N-1 input signals are ANDed to obtain N-1 AND operation results D. 1 0, D 1 1、…、D 1 (i-1) D 1 (i+1) ... D 1 (N-1) Wherein, the level refers to the high or low level output after the input signal has passed through the corresponding level processing module; D 1 0 represents S i The result of ANDing the corresponding level with the level corresponding to S0, D 1 j S represents i The corresponding level and S j The result of the AND operation on the corresponding level is j∈{1,2,…,N-1, and j≠i}; The second AND gate array is used to store the AND operation result D. 1 j Perform an AND operation with the output of the j-th second synaptic circuit module to obtain the AND result D. 2 j ; The first OR gate is used to perform a bitwise AND operation on the result D. 1 0 and the result of the AND operation D 2 j Perform an OR operation to obtain the first OR result; the first OR result serves as the learning signal. , When it is high, it indicates that in S i Learning is stimulated by [the environment / initiatives]. XOR gate array, used to convert S i The corresponding levels are respectively divided by S i The levels corresponding to the remaining N-1 input signals are XORed to obtain N-1 XOR results Y0, Y1, ..., Y... (i-1) Y (i+1) ..., Y (N-1) Where Y0 represents S i The result of XORing the corresponding level with the level corresponding to S0 is Y. j S represents i The corresponding level and S j The result of XORing the corresponding voltage levels; The third AND gate array is used to process the XOR operation result Y. j Perform an AND operation with the output of the j-th second synaptic circuit module to obtain the AND result D. 3 j ; The second OR gate is used to combine the XOR operation result Y0 and the AND operation result D. 3 j Perform an OR operation to obtain the second OR result; NOT gate, used to convert the learning signal Perform a NOT operation to obtain the NOT result; The fourth AND gate is used to perform an AND operation between the NOT result and the second OR result, and the result of the AND operation is used as an active forgetting signal. , When it is high, it indicates that in S i Active forgetting occurs under the stimulation of [the stimulus]. The output of the level processing module, whose input is connected to S0, is connected to the input of the first synaptic circuit module. The first synaptic circuit module outputs a judgment signal on whether a conditioned reflex can be generated under the stimulation of S0. The N-1 second synaptic circuit modules have identical structures, and the i-th second synaptic circuit module includes a memristor for use based on the learning signal. and the active forgetting signal Adjust its resistance value to output at S i The signal used to determine whether a conditioned reflex can be produced under a stimulus; The output terminals of the first synaptic circuit module and the N-1 output terminals of the second synaptic circuit modules are all connected to the input terminal of the output circuit module. The output of the output circuit module is located at S0, S1, S2, ..., S... N-1 The result of whether a salivary response can be produced under stimulation.

2. The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes as described in claim 1, characterized in that, The first AND gate array includes N-1 AND gates D. 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D 1 L(N-1) The second AND gate array includes N-2 AND gates D. 2 L1 D 2 L2 ... D 2 L(i-1) D 2 L(i+1) ... D 2 L(N-1) The third AND gate array includes N-2 AND gates D. 3 L1 D 3 L2 ... D 3 L(i-1) D 3 L(i+1) ... D 3 L(N-1) The fourth AND gate includes the AND gate D. 4 L1 The XOR gate array includes N-1 XOR gates D Y0 D Y1 ... D Y(i-1) D Y(i+1) ... D Y(N-1) The first OR gate includes OR gate D. H1 The second OR gate includes OR gate D. H2 NOT gates include NOT gate D. F1 ; N-1 AND gates D 1 L0 D 1 L1 ... D 1 L(i-1) D 1 L(i+1) ... D 1 L(N-1) The signals at the first input terminal are all S i The corresponding levels, the signals at the second input terminal are respectively excluding S i The levels corresponding to the remaining N-1 input signals, excluding those from the AND gate D; where, 1 L0 The signal at the second input terminal is the level corresponding to S0, and the AND gate D... 1 Lj The signal at the second input terminal is S. j The corresponding level; AND gate D 1 Lj The output terminal is connected to gate D. 2 Lj The first input terminal, AND gate D 2 Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module; AND gate D 1 L1 The output terminal and AND gate D 2 Lj The outputs of all terminals are connected to an OR gate D. H1 The input terminal of the OR gate D H1 The learning signal is output from the output terminal. ; N-1 XOR gates D Y0 D Y1 ... D Y(i-1) D Y(i+1) ... D Y(N-1) The signals at the first input terminal are all S i The corresponding levels, the signals at the second input terminal are respectively excluding S i The levels corresponding to the remaining N-1 input signals, excluding those from the XOR gate D; where, Y0 The signal at the second input terminal is the level corresponding to S0, XOR gate D Yj The signal at the second input terminal is S. j The corresponding level; XOR gate D Yj The output terminal is connected to gate D. 3 Lj The first input terminal, AND gate D 3 Lj The second input terminal is connected to the output terminal of the j-th second synaptic circuit module; XOR gate D Y0 The output terminal and AND gate D 3 Lj The outputs of all terminals are connected to an OR gate D. H2 The input terminal; NOT gate D F1 The input terminal is connected to the OR gate D. 1 H1 The output of the NOT gate D F1 Output of OR gate D H2 The output terminals are respectively connected to gate D. 4 L1 The first and second input terminals of the AND gate D 4 L1 The active forgetting signal is output from the output terminal. .

3. The memristor circuit with Pavlovian associative memory possessing higher-order conditioned reflexes according to claim 1 or 2, characterized in that, The i-th second synaptic circuit module also includes a signal processing circuit and a conditional reflex judgment signal generation circuit; The signal processing circuit includes a threshold switch S. s1 S s2 and adders; Threshold switch S s1 One end is connected to a preset negative voltage signal V1 representing active forgetting, and the other end is connected to the first input terminal of the adder, used to input the active forgetting signal. When the signal is high, it closes to pass V1 to the first input of the adder, and in the active forget signal... Disconnect when the signal is low; Threshold switch S s2 One end is connected to a preset positive voltage signal V2 representing the learning, and the other end is connected to the second input terminal of the adder, used to input the learning signal. When the signal is high, it closes to pass V2 to the second input of the adder, and in the learning signal... Disconnect when the signal is low; The adder performs addition operations on the signals at its first, second, and third input terminals, and transmits the result to the positive terminal of the memristor; wherein, the signal at the third input terminal of the adder is a preset negative voltage signal V3 representing passive forgetting, and its absolute value is... Greater than absolute value And V2 is greater than the preset positive threshold and absolute value of the memristor. The sum of; The conditional reflex judgment signal generation circuit is used to convert the resistance value of the memristor into a value in S. i A judgment signal for whether a conditioned reflex can be generated under a stimulus; wherein, when the judgment signal is low, it indicates that a conditioned reflex is generated under S. i When a conditioned reflex cannot be produced under stimulation, and the judgment signal is high, it indicates that a conditioned reflex is not produced under stimulation. i A conditioned reflex can be produced under stimulation.

4. The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes according to claim 3, characterized in that, The memristor is based on the learning signal and the active forgetting signal Adjust its resistance value, including In the learning signal When the level is high, the operation result transmitted from the output of the adder to the positive terminal of the memristor is greater than the preset positive threshold of the memristor, and the resistance of the memristor decreases. In the active forgetting signal When the level is high, the result of the operation transmitted from the output of the adder to the positive terminal of the memristor is less than the preset negative threshold of the memristor, and the resistance of the memristor decreases. In the learning signal and the active forgetting signal When both are at low levels, the result of the operation transmitted from the adder output to the positive terminal of the memristor is less than the preset negative threshold of the memristor, the resistance of the memristor decreases, and the rate of decrease is less than that of the active forgetting signal. The descent rate when the voltage level is high.

5. The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes according to claim 3, characterized in that, The conditional reflection judgment signal generation circuit includes: an inverting amplifier, an ABM1 device, and a comparator; The negative input terminal of the inverting amplifier is connected to the negative terminal of the memristor, the positive input terminal of the inverting amplifier is grounded, the output terminal of the inverting amplifier is connected to the first input port of the ABM1 device, the positive terminal of the memristor is connected to the second input port of the ABM1 device, and the output of the ABM1 device is connected to the comparator. The output of the ABM1 device The output voltage of the inverting amplifier is the quotient of the voltage at the positive terminal of the memristor, and the output voltage of the inverting amplifier is determined based on the resistance value of the memristor and the voltage at its positive terminal; the comparator is used to convert the output of the ABM1 device... Compared with a preset threshold, the result is obtained in S i The signal used to determine whether a conditioned reflex can be produced under a stimulus.

6. The memristor circuit with Pavlovian associative memory having higher-order conditioned reflexes according to claim 1 or 2, characterized in that, The first synaptic circuit module includes a resistor with a resistance value exceeding a preset threshold, used to convert the level corresponding to S0 into a judgment signal for whether a conditioned reflex can be generated; wherein, when the level corresponding to S0 is high, the first synaptic circuit module outputs a judgment result indicating that a conditioned reflex can be generated, otherwise, it outputs a judgment result indicating that a conditioned reflex cannot be generated.

7. The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes according to claim 2, characterized in that, The output circuit module includes: N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) and OR gate D H3 ; AND gate D 5 L0 The first input terminal is connected to the output terminal of the first synaptic circuit module, and AND gate D. 5 L0 The second input signal is S0; AND gate D 5 Li The first input terminal is connected to the output terminal of the i-th second synaptic circuit module, AND gate D 5 Li The second input signal is S i ; N AND gates D 5 L0 D 5 L1 ... D 5 L(N-1) The outputs of all terminals are connected to an OR gate D. H3 The input terminal of the OR gate D H3 The output terminals are located at S0, S1, S2, ..., S N-1 The result of whether a salivary response is produced under stimulation; among which, OR gate D H3 When the output terminal outputs a high level, it indicates that a saliva reaction can be generated; otherwise, it indicates that a saliva reaction cannot be generated.

8. The memristor circuit with Pavlovian associative memory having higher-order conditioned reflexes according to claim 1 or 2, characterized in that, The N level processing modules have the same structure. Each level processing module includes a comparator, which is used to compare the corresponding input signal with a preset threshold to convert the corresponding input signal into a corresponding high level or low level.

9. The memristor circuit with Pavlovian associative memory exhibiting higher-order conditioned reflexes according to claim 8, characterized in that, Each level processing module includes a comparator consisting of two PMOS transistors and two NMOS transistors.

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