A machine vision-based multi-chip package defect detection method and system

Abstract

This application relates to the field of chip inspection technology and discloses a multi-chip package defect detection method and system based on machine vision. This application combines the synergistic effect of a vision camera and a depth camera, which can accurately identify two core defects: surface depressions and protrusions. It can also locate the defect target area through depth information and depth change information, breaking through the limitations of traditional inspection and conventional vision inspection in accurately identifying defects. At the same time, by combining the heat dissipation path of the multi-chip package with the location comparison of the defect area, it realizes the accurate assessment of the potential risk of defects, and specifically associates the risk of thermal expansion and cracking of depression defects with the risk of heat dissipation obstruction of protrusion defects. This solves the problem that existing inspections cannot effectively assess the potential reliability of defects, greatly improves the accuracy and practicality of multi-chip package defect detection, and provides strong protection for the structural integrity and operational reliability of multi-chip packages.

Description

Technical Field

[0001] This invention relates to the field of chip inspection technology, and specifically to a method and system for detecting defects in multi-chip packaging based on machine vision. Background Technology

[0002] Multi-chip packaging (MCP) technology, with its core advantages of integrating multiple heterogeneous chips in a confined space, shortening signal transmission distances between chips, improving system performance, and optimizing package size, has been widely applied in high-end fields such as high-performance computing, artificial intelligence, 5G communication, and automotive electronics. It has become a key technology supporting the miniaturization, high computing power, and low power consumption of testing systems. However, the MCP process is complex, involving multiple steps such as wafer thinning, die mounting, wire bonding, and molding. It also requires adaptation to various heterogeneous materials, demanding extremely high material compatibility and process parameter matching. This makes it highly susceptible to various defects during packaging, with surface defects such as surface depressions and protrusions being particularly common, severely affecting the structural integrity and operational reliability of the package.

[0003] Surface defects in multi-chip packages not only disrupt the flatness of the package appearance, but may also lead to a series of subsequent reliability risks. Surface depressions may cause stress concentration in the package structure, which may lead to thermal expansion cracking due to thermal expansion coefficient mismatch during long-term thermal cycling of the device. Surface protrusions may hinder the effective contact between the package and the heat dissipation structure, disrupt the continuity of the heat dissipation path, and cause the heat generated by the chip in the package to be unable to dissipate in time, resulting in heat dissipation obstruction, chip overheating and aging, or even failure.

[0004] Currently, defect detection in multi-chip packaging still relies mainly on traditional detection methods and conventional visual inspection, which makes it difficult to quickly and accurately identify defect types and assess their potential risks. Summary of the Invention

[0005] The main objective of this invention is to provide a multi-chip packaging defect detection method and system based on machine vision, which aims to solve the technical problem that existing technologies are unable to quickly and accurately identify defect types and assess their potential risks.

[0006] To achieve the above objectives, in a first aspect, embodiments of this application provide a machine vision-based multi-chip packaging defect detection method, applied to an inspection system, the inspection system including a vision camera and a depth camera, the method comprising:

[0007] The surface defects of the multi-chip package are obtained by the vision camera and the depth camera, and the type of the surface defect is determined to be a surface depression defect or a surface protrusion defect, so as to obtain the target surface defect.

[0008] Obtain the defect parameters of the target surface defect, wherein the defect parameters include depth information and depth variation information;

[0009] Based on the depth information and depth change information, the target area of ​​the target surface defect on the multi-chip package is determined;

[0010] The heat dissipation path of the multi-chip package is determined based on its internal packaging structure and operating parameters.

[0011] The location information of the heat dissipation path is compared with that of the target area to determine whether the heat dissipation path passes through the target area;

[0012] When the heat dissipation path passes through the target area, the risk type corresponding to the multi-chip package is determined according to the type of the target surface defect; wherein, when the target surface defect is a surface depression defect, the risk type is thermal expansion cracking risk; when the target surface defect is a surface protrusion defect, the risk type is heat dissipation obstruction risk.

[0013] In one possible implementation, determining the target region of the target surface defect on the multi-chip package based on the depth information and the depth change information includes:

[0014] The target surface defect is divided into multiple consecutive candidate regions along the extension direction of the target surface defect;

[0015] For each candidate region, obtain its depth information and depth change information;

[0016] Candidate regions whose depth information and depth change information meet preset conditions are determined as the target regions.

[0017] In one possible implementation, determining the candidate region whose depth information and depth change information satisfy preset conditions as the target region includes:

[0018] When the target surface defect is a surface depression defect, the candidate region that meets any of the following conditions will be determined as the target region:

[0019] Along the length of the defect, the depth value gradually increases and the rate of change of depth is greater than or equal to a first rate of change threshold.

[0020] Along the width direction of the defect, the depth value gradually increases and the rate of change of depth is greater than or equal to a second rate of change threshold.

[0021] And / or, when the target surface defect is a surface protrusion defect, a candidate region that satisfies any of the following conditions is determined as the target region:

[0022] Along the length of the defect, the height value gradually increases and the height change rate is greater than or equal to the third change rate threshold;

[0023] Along the width direction of the defect, the height value gradually increases and the height change rate is greater than or equal to the fourth change rate threshold.

[0024] In one possible implementation, the defect parameters further include the contour complexity, defect area, and defect edge smoothness of the target surface defect; determining the target region of the target surface defect on the multi-chip package based on the depth information and depth change information includes:

[0025] The contour complexity, defect area, and defect edge smoothness of the target surface defect are calculated. The contour complexity is calculated by the ratio of the number of concave and convex points of the contour to the total number of points of the contour, and the edge smoothness is calculated by the average distance from the edge point to the contour fitting line.

[0026] When the contour complexity is determined to be greater than a preset complexity threshold, the defect area is greater than a preset area threshold, and the defect edge flatness is less than a preset flatness threshold, the region after extending the candidate region outward by a preset distance is determined as the target region.

[0027] In one possible implementation, determining the heat dissipation path of the multi-chip package based on its internal packaging structure and operating parameters includes:

[0028] A thermal simulation model is established in advance based on the internal chip layout, heat source power distribution, and thermal conductivity of the packaging material of the multi-chip package.

[0029] At least one main heat dissipation path is generated within the multi-chip package using the thermal simulation model, and the main heat dissipation path is used as the heat dissipation path.

[0030] In one possible implementation, if the heat dissipation path passes through the target area, the method further includes:

[0031] Determine the position of the target area on the heat dissipation path;

[0032] The risk level of the multi-chip package is determined based on the location of the target area on the heat dissipation path;

[0033] Specifically, when the first half of the heat dissipation path passes through the target area, the risk level corresponding to the multi-chip package is determined to be high risk; when the second half of the heat dissipation path passes through the target area, the risk level corresponding to the multi-chip package is determined to be low risk.

[0034] The first half is a path segment from the starting point of the heat dissipation path to a predetermined proportional position on the heat dissipation path, where the starting point of the heat dissipation path is the location of the heat source.

[0035] In one possible implementation, the method for determining the preset proportional position includes:

[0036] Obtain temperature distribution data along the heat dissipation path of the multi-chip package during historical operating cycles;

[0037] The path location corresponding to when the heat decays to a preset threshold is determined based on the temperature distribution data;

[0038] The ratio of the path position to the total length of the heat dissipation path is used as the preset ratio position.

[0039] In one possible implementation, if the heat dissipation path passes through the target area, the method further includes:

[0040] The target ratio is obtained by measuring the ratio of the overlap length of the target region on the heat dissipation path to the total length of the heat dissipation path.

[0041] The risk level of the multi-chip package is determined based on the target ratio.

[0042] Specifically, when the target ratio is greater than or equal to the ratio threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target ratio is less than the ratio threshold, the risk level corresponding to the multi-chip package is determined to be low risk.

[0043] In one possible implementation, if the heat dissipation path passes through the target area, the method further includes:

[0044] The depth change gradient direction of the target surface defect within the target area is obtained, wherein the depth change gradient direction is the direction in which the depth or height value increases the fastest;

[0045] Obtain the local path direction of the heat dissipation path as it passes through the target area;

[0046] Calculate the angle between the depth change gradient direction and the local path direction;

[0047] The risk level of the multi-chip package is determined based on the included angle and the type of the target surface defect;

[0048] Specifically, when the target surface defect is a surface depression defect and the included angle is less than a preset included angle threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target surface defect is a surface protrusion defect and the included angle is greater than or equal to 90 degrees, the risk level corresponding to the multi-chip package is determined to be high risk.

[0049] Secondly, embodiments of this application also provide a detection system, including a visual camera, a depth camera, and...

[0050] The memory is used to store program code;

[0051] A processor, the processor being configured to invoke the program code to execute the method as described in the first aspect.

[0052] Unlike existing technologies, the machine vision-based multi-chip package defect detection method provided in this application is applied to a detection system including a vision camera and a depth camera. First, the surface defects of the multi-chip package are acquired using the vision camera and depth camera, and the type of the surface defect is determined to be either a surface depression defect or a surface protrusion defect, thus obtaining the target surface defect. Next, defect parameters of the target surface defect are acquired, including depth information and depth variation information. Then, based on the depth information and depth variation information, the target area of ​​the target surface defect on the multi-chip package is determined. Subsequently, the heat dissipation path of the multi-chip package is determined based on its internal packaging structure and operating parameters. The heat dissipation path is then compared with the position information of the target area to determine whether the heat dissipation path passes through the target area. Finally, if the heat dissipation path passes through the target area, the risk type corresponding to the multi-chip package is determined based on the type of the target surface defect. Specifically, when the target surface defect is a surface depression defect, the risk type is thermal expansion cracking risk; when the target surface defect is a surface protrusion defect, the risk type is heat dissipation obstruction risk. Thus, this application combines the synergistic effect of a vision camera and a depth camera, enabling precise identification of two core defects: surface depressions and protrusions. It also allows for the location of defect target areas through depth information and depth change information, overcoming the limitations of traditional and conventional visual inspection methods in accurately identifying defects. Furthermore, by comparing the heat dissipation path of the multi-chip package with the location of the defect area, it achieves a precise assessment of potential defect risks. It specifically correlates the risk of thermal expansion and cracking of depression defects with the risk of heat dissipation obstruction of protrusion defects, solving the problem that existing inspection methods cannot effectively assess potential defects. This significantly improves the accuracy and practicality of multi-chip package defect detection, providing strong protection for the structural integrity and operational reliability of multi-chip packages. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the internal packaging structure and heat dissipation path of the multi-chip package in some embodiments of this application;

[0055] Figure 2 This is a flowchart illustrating a machine vision-based multi-chip packaging defect detection method in some embodiments of this application.

[0056] Figure 3 This is a schematic diagram of the heat dissipation path of a multi-chip package in some embodiments of this application;

[0057] Figure 4 This is a flowchart illustrating step S300 of the machine vision-based multi-chip packaging defect detection method in some embodiments of this application.

[0058] Figure 5 This is a schematic diagram of the hardware structure of the detection system in some embodiments of this application.

[0059] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0061] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0062] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the term "and / or" throughout the text includes three solutions; taking A and / or B as an example, it includes technical solution A, technical solution B, and a technical solution that simultaneously satisfies A and B. Furthermore, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0063] Multi-chip packaging (MCP) technology, with its core advantages of integrating multiple heterogeneous chips in a confined space, shortening signal transmission distances between chips, improving system performance, and optimizing package size, has been widely applied in high-end fields such as high-performance computing, artificial intelligence, 5G communication, and automotive electronics. It has become a key technology supporting the miniaturization, high computing power, and low power consumption of testing systems. However, the MCP process is complex, involving multiple steps such as wafer thinning, die mounting, wire bonding, and molding. It also requires adaptation to various heterogeneous materials, demanding extremely high material compatibility and process parameter matching. This makes it highly susceptible to various defects during packaging, with surface defects such as surface depressions and protrusions being particularly common, severely affecting the structural integrity and operational reliability of the package.

[0064] Surface defects in multi-chip packages not only damage the flatness of the package appearance, but may also lead to a series of subsequent reliability risks. Surface depressions may cause stress concentration in the package structure, and during the long-term thermal cycling process of the device, thermal expansion cracks may occur due to the mismatch of thermal expansion coefficients. Surface protrusions may hinder the effective contact between the package and the heat dissipation structure, disrupt the continuity of the heat dissipation path, and cause the heat generated by the chip in the package to be unable to dissipate in time, resulting in heat dissipation obstruction, chip overheating and aging, or even failure.

[0065] Currently, defect detection in multi-chip packaging mainly relies on traditional detection methods and conventional visual inspection, which makes it difficult to quickly and accurately identify defect types and assess their potential risks.

[0066] To address the aforementioned technical problems, this application provides a machine vision-based method for detecting defects in multi-chip packages. This method can be applied to an inspection system, which includes a vision camera and a depth camera, for detecting defects in multi-chip packages.

[0067] like Figure 1As shown, in one embodiment, the multi-chip package 100 includes a chip carrier 110, a first chip 120, and a second chip 130. The chip carrier 110 is provided with lead pins (not shown); the first chip 120 is disposed on the chip carrier in a flip-chip configuration and is electrically connected to the lead pins; the second chip 130 is disposed on top of the first chip 120 in a top-mount configuration and is also electrically connected to the lead pins.

[0068] It is understandable that, since the first chip 120 and the second chip 130 adopt different stacking methods, the overall heat dissipation path of the multi-chip package 100 also differs. Therefore, a thermal simulation model can be established by combining parameters such as the internal chip layout, heat source power distribution, and thermal conductivity of the packaging material of the multi-chip package to determine its heat dissipation path.

[0069] For example, Figure 1 The middle path S is the heat dissipation path of the multi-chip package 100 determined according to the thermal simulation model.

[0070] like Figures 1 to 4 As shown, the following explanation uses the execution of this machine vision-based multi-chip package defect detection method by the detection system as an example. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order. Please refer to the appendix. Figure 2 The method includes the following steps:

[0071] Step S100: Obtain surface defects of the multi-chip package through the vision camera and the depth camera, and determine whether the surface defects are surface depression defects or surface protrusion defects to obtain the target surface defects.

[0072] In this embodiment, the detection system can acquire two-dimensional grayscale images and texture information of the package surface using a vision camera, and simultaneously acquire three-dimensional point cloud and elevation data of the package surface using a depth camera (such as a structured light camera or a ToF camera), achieving a complete perception of the package surface morphology. Through defect identification algorithms such as image segmentation, edge detection, and elevation threshold judgment, the system can extract areas with surface anomalies from the acquired data and identify surface defects. Subsequently, based on the elevation difference of the defect area relative to the package reference plane, the defect type is classified: when the defect area elevation is lower than the reference plane, it is determined to be a surface depression defect; when the defect area elevation is higher than the reference plane, it is determined to be a surface protrusion defect, and this classified defect is recorded as the target surface defect. This step provides the basic detection object for subsequent defect parameter extraction and risk analysis, achieving accurate defect location and preliminary classification.

[0073] Step S200: Obtain the defect parameters of the target surface defect, wherein the defect parameters include depth information and depth variation information;

[0074] After identifying surface defects, the detection system can perform parametric extraction on the defect region based on the 3D data output by the depth camera. Depth information includes quantitative indicators characterizing the severity of the defect, such as the depth value of each pixel corresponding to the defect region, the maximum indentation depth, the maximum protrusion height, and the average depth of the defect. Depth variation information includes the depth gradient, depth curvature, edge steepness, and rate of depth change along the length / width direction of the defect region, reflecting the morphological distribution and trend of the defect. The system can calculate these parameters through point cloud fitting, regional elevation difference, and surface fitting, forming structured defect feature data to provide a quantitative basis for subsequent defect region localization.

[0075] Step S300: Based on the depth information and depth change information, determine the target area of ​​the target surface defect on the multi-chip package;

[0076] The purpose of this step is to accurately screen out the critical defect areas from the identified target surface defects that will affect the heat dissipation of the multi-chip package. This critical area is the target area, which is distinct from the overall defect coverage area and focuses only on the core parts that can interfere with the heat dissipation path and cause subsequent thermal risks. Specifically, the system can use the depth information and depth change information obtained in step S200 as a basis, combined with the preset coordinate system and region division rules of the multi-chip package surface, as well as the distribution of heat dissipation-related structures (such as areas near the heat sink, thermal interface, and heat dissipation pins), to accurately locate and screen the target surface defects, thereby obtaining the target area.

[0077] It can be understood that the target area is a heat dissipation interference area of ​​the target surface defect, that is, it affects the forward conduction of heat on the heat dissipation path.

[0078] For example, for surface depression defects, areas where the degree of depression reaches a certain threshold can be selected as target areas; for surface protrusion defects, areas where the height of protrusion reaches a certain threshold can be selected as target areas.

[0079] Step S400: Determine the heat dissipation path of the multi-chip package based on its internal packaging structure and operating parameters.

[0080] After locating the target area (the core defect area affecting heat dissipation), the detection system can calculate and determine the main heat dissipation path of the package under normal operating conditions based on the preset design information of the multi-chip package, including internal chip layout, bonding wire distribution, thermal adhesive / thermal via location, package substrate traces, and internal package structure such as the heat sink top cover and bottom heat dissipation structure. This is done in conjunction with operating parameters such as chip power consumption, operating current, junction temperature limit, and normal operating heat flux density, using a thermal simulation model or a preset heat dissipation path rule library. The heat dissipation path includes the main transfer channels and key heat conduction areas from the chip's heat-generating core to the package shell, substrate, heat sink pins, or external heat sink. Its spatial distribution directly determines whether the target area will actually interfere with heat dissipation. This step establishes an internal heat transfer model of the package, providing a baseline path for subsequent judgment on whether the target area interferes with heat dissipation.

[0081] For example, a thermal simulation model can be established in advance based on the internal chip layout, heat source power distribution and thermal conductivity of the packaging material of the multi-chip package; then, at least one main heat dissipation path in the multi-chip package can be generated through the thermal simulation model, and the main heat dissipation path can be used as the heat dissipation path.

[0082] Step S500: Compare the heat dissipation path with the location information of the target area to determine whether the heat dissipation path passes through the target area;

[0083] In this embodiment, the detection system can spatially match and compare the coordinates and contour range of the target area (the core defect area affecting heat dissipation) obtained in step S300 with the spatial distribution of the heat dissipation path determined in step S400. Through methods such as coordinate overlap judgment, region intersection detection, and distance threshold judgment, it identifies whether the target area and the heat dissipation path have a spatial overlap or coverage relationship: if the target area and the heat dissipation path intersect, cover, or are adjacent, it indicates that the core heat dissipation interference area of ​​the defect is located on a critical heat conduction channel, which will directly affect the heat dissipation efficiency of the package, and it is determined that the heat dissipation path passes through the target area; if the target area is far from all heat dissipation paths and does not affect the heat transfer channel, it indicates that the core interference area of ​​the defect does not touch the critical heat dissipation parts and will not have a substantial impact on heat dissipation, and it is determined that the heat dissipation path does not pass through the target area. This step achieves the correlation judgment between the target area and the thermally critical area, accurately screening out defects with potential thermal risks.

[0084] Step S600: When the heat dissipation path passes through the target area, determine the risk type corresponding to the multi-chip package according to the type of the target surface defect; wherein, when the target surface defect is a surface depression defect, the risk type is thermal expansion cracking risk; when the target surface defect is a surface protrusion defect, the risk type is heat dissipation obstruction risk.

[0085] In this embodiment of the application, when step S500 determines that the heat dissipation path passes through the target area, it indicates that the target area will directly affect the heat dissipation path, thereby affecting the thermal reliability of the package. Based on this, the detection system classifies risks according to the defect type:

[0086] If the target surface defect is a surface depression defect, it will cause the corresponding area of ​​the package to become thinner and generate stress concentration. When the chip generates heat during operation and conducts it along the heat dissipation path, the heat passes through this weak area and is prone to crack propagation due to thermal expansion. Therefore, the risk type is determined to be thermal expansion crack risk.

[0087] If the target surface defect is a surface protrusion defect, it will damage the flatness of the package surface, hinder or weaken the heat exchange efficiency between the package and the outside, causing heat to be poorly dissipated along the heat dissipation path and accumulate. Therefore, the risk type is determined to be heat dissipation obstruction risk.

[0088] For example, such as Figure 3 As shown in Figure A, region M is the aforementioned target region. Since the heat dissipation path S passes through this target region M, the heat transferred forward along the heat dissipation path S will be interfered with by the target region M, which may easily lead to risks such as thermal expansion cracking or heat dissipation obstruction. For example, when the target region M is a surface depression defect, and the chip generates heat during operation and conducts it along the heat dissipation path, thermal expansion cracking is likely to occur at this target region M.

[0089] like Figure 3 As shown in B, region N is a non-target region. Since the heat dissipation path S passes through the non-target region N but does not pass through the target region M, the heat is transferred normally along the heat dissipation path S and will not be affected by the defects in the target region. Therefore, there is no risk of thermal expansion cracking or heat dissipation obstruction.

[0090] Based on this, this application combines the synergistic effect of a vision camera and a depth camera, which can accurately identify two core defects: surface depressions and protrusions. It can also locate the defect target area through depth information and depth change information, breaking through the limitations of traditional inspection and conventional visual inspection in accurately identifying defects. At the same time, by combining the heat dissipation path of the multi-chip package with the location comparison of the defect area, it achieves accurate assessment of the potential risk of defects, and specifically associates the risk of thermal expansion and cracking of depression defects with the risk of heat dissipation obstruction of protrusion defects. This solves the problem that existing inspections cannot effectively assess the reliability risks of defects, greatly improves the accuracy and practicality of multi-chip package defect detection, and provides strong protection for the structural integrity and operational reliability of multi-chip packages.

[0091] In one embodiment, such as Figure 4 As shown, step S300: Based on the depth information and depth change information, determine the target region of the target surface defect on the multi-chip package, including:

[0092] S310. Divide the target surface defect into multiple consecutive candidate regions along the extension direction of the target surface defect;

[0093] S320. For each candidate region, obtain the depth information and depth change information of that candidate region;

[0094] S330. The candidate regions whose depth information and depth change information meet the preset conditions are determined as the target regions.

[0095] Specifically, this embodiment first divides the overall defect area into multiple continuous and non-overlapping candidate areas along the extension direction (which can be the length direction) of the target surface defect, achieving refined segmentation of the defect area and providing a foundation for subsequent accurate positioning of key defect areas. Then, for each candidate area, depth information and depth change information are collected and extracted. The depth information reflects the degree of concavity or convexity of the candidate area, while the depth change information characterizes the magnitude and distribution pattern of abrupt changes in depth within the area, thereby comprehensively quantifying the defect characteristics of each candidate area. Next, candidate areas whose depth information and depth change information simultaneously meet preset judgment conditions are selected as the target areas of the target surface defect on the multi-chip package. These preset conditions can be pre-set according to actual detection needs such as defect type and defect severity, thereby eliminating invalid areas with insignificant or non-critical defect features and accurately locating the core hazardous areas of the defect.

[0096] For example, when the target surface defect is a surface depression defect, a candidate region that meets any of the following conditions can be determined as the target region: along the length direction of the defect, the depth value gradually increases and the depth change rate is greater than or equal to a first change rate threshold; along the width direction of the defect, the depth value gradually increases and the depth change rate is greater than or equal to a second change rate threshold.

[0097] It is understandable that for depression-type defects, a gradual increase in depth value indicates that the area is continuously concave inward along the length or width direction, which is the key area for the formation and expansion of the defect core. When the depth change rate reaches or exceeds the set threshold, it indicates that the concavity trend at this location is obvious and the defect morphology changes drastically, which is different from slight and gentle surface fluctuations. This can effectively filter out non-hazardous slight undulations and accurately locate the depression core area that truly poses a structural risk.

[0098] For example, when the target surface defect is a surface protrusion defect, a candidate region that meets any of the following conditions can be determined as the target region: along the length direction of the defect, the height value gradually increases and the height change rate is greater than or equal to a third change rate threshold; along the width direction of the defect, the height value gradually increases and the height change rate is greater than or equal to a fourth change rate threshold.

[0099] It is understandable that for protrusion-type defects, a gradual increase in height value indicates that the area is continuously bulging outward along the length or width direction, which is the main formation section of the protrusion defect; if the height change rate meets the corresponding threshold, it indicates that the protrusion amplitude at that position changes significantly, which is different from the slight tolerance fluctuations of the normal packaging surface, avoiding misjudging slight protrusions within the process allowable range as defects, thereby ensuring the accuracy of the target area judgment.

[0100] It should be noted that the first, second, third, and fourth rate of change thresholds can be set to the same value, or they can be set to different values ​​depending on the actual detection scenario.

[0101] Thus, based on depth information and depth change information, the embodiments of this application can accurately screen the target area of ​​the target surface defect on the multi-chip package, providing a reliable basis for subsequent defect parameter calculation, defect level determination and defect detection analysis, thereby improving the accuracy and reliability of chip package surface defect detection.

[0102] In one embodiment, the defect parameters further include the contour complexity of the target surface defect, the defect area, and the defect edge smoothness. Step S300: Based on the depth information and the depth change information, determine the target region of the target surface defect on the multi-chip package, including:

[0103] The contour complexity, defect area, and defect edge smoothness of the target surface defect are calculated. The contour complexity is calculated by the ratio of the number of concave and convex points of the contour to the total number of points of the contour, and the edge smoothness is calculated by the average distance from the edge point to the contour fitting line.

[0104] When the contour complexity is determined to be greater than a preset complexity threshold, the defect area is greater than a preset area threshold, and the defect edge flatness is less than a preset flatness threshold, the region after extending the candidate region outward by a preset distance is determined as the target region.

[0105] Specifically, in this embodiment, the contour complexity, defect area, and defect edge smoothness of the target surface defect are first calculated. The contour complexity can be quantified by the ratio of the number of concave and convex points on the contour to the total number of points on the contour, thereby characterizing the irregularity of the defect contour. The more concave and convex points on the contour, the higher the complexity, indicating that the defect boundary contour is more complex. Complex boundary contours can disrupt the continuity of the multi-chip package surface, have a greater impact on the chip's heat dissipation path, and may lead to local heat accumulation, affecting the chip's operational stability. The defect edge smoothness is obtained by extracting the defect edge points and calculating the average distance from each edge point to the corresponding contour fitting line. The smaller the average distance, the smoother the edge; conversely, the larger the average distance, the greater the edge undulation. Defects with low edge smoothness are more likely to cause stress concentration and further exacerbate the problem of poor heat dissipation. The larger the defect area, the greater its impact on the chip's structural integrity and heat dissipation performance.

[0106] Subsequently, the calculated defect parameters are compared with the corresponding preset thresholds. When the defect contour complexity is greater than the preset complexity threshold, the defect area is greater than the preset area threshold, and the defect edge flatness is less than the preset flatness threshold, it indicates that the defect not only has a wide range of influence and poor edge condition, but also has a significant adverse impact on the heat dissipation path due to its complex boundary contour. It is a key defect that needs to be focused on. To ensure the comprehensiveness and accuracy of subsequent defect analysis or evaluation, the candidate area needs to be expanded. At this time, the area after extending the candidate area outward by a preset distance is determined as the target area of ​​the target surface defect on the multi-chip package, which can fully cover the defect and its surrounding related areas affected by heat dissipation.

[0107] Thus, this embodiment combines depth information, depth change information, and multiple parameters such as the contour complexity, area, and edge smoothness of the defect. In particular, considering the impact of contour complexity on the heat dissipation path, it can accurately screen and locate the target area corresponding to the defect that has a critical impact on chip performance, improve the accuracy and reliability of chip surface defect detection, and provide a more targeted basis for subsequent chip quality control.

[0108] Understandably, in step S600, when the heat dissipation path passes through the target area, the risk type corresponding to the multi-chip package has been determined based on the type of surface defects of the target. Therefore, subsequent defect warnings can be made based on the risk type. For example, when the risk type is thermal expansion cracking risk or heat dissipation obstruction risk, it will seriously affect the subsequent actual use of the multi-chip package. Therefore, the chip can be marked as a high-risk chip to be re-inspected and included in the key control batch, and subsequent packaging processes or whole machine assembly processes can be suspended to prevent defective chips from flowing into the next stage and causing greater production losses and quality risks.

[0109] Based on this, in order to further accurately control the defect risks of multi-chip packages, when the heat dissipation path passes through the target area, the multi-chip package defect detection method of this application further includes the following steps: First, determine the specific location of the target area on the heat dissipation path; then, determine the risk level of the multi-chip package based on the location of the target area on the heat dissipation path; wherein, the first half of the heat dissipation path is defined as the path segment from its starting point (i.e., the location of the heat source) to a preset proportion position on the heat dissipation path. When the first half of the heat dissipation path passes through the target area, the heat flux density is higher and the heat concentration is more significant, resulting in a greater impact on the target area. Therefore, the risk level corresponding to the multi-chip package is determined to be high risk. When the second half of the heat dissipation path passes through the target area, the heat transfer impact is relatively weak, and the impact on package reliability is limited. Therefore, the risk level corresponding to the multi-chip package is determined to be low risk. Through the dual judgment of risk type and risk level, accurate early warning, graded handling, and differentiated management of multi-chip package defects can be achieved.

[0110] It should be noted that the first half of the heat dissipation path is defined as the segment from its starting point (i.e., the location of the heat source) to a preset proportional position on the heat dissipation path. This preset proportional position can be set to 1 / 3, 1 / 2, or other suitable proportions.

[0111] In other embodiments, the aforementioned preset ratio value can also be dynamically determined based on the heat dissipation data of the multi-chip package during historical operating cycles. The method for determining the preset ratio position includes the following steps:

[0112] Obtain temperature distribution data along the heat dissipation path of the multi-chip package during historical operating cycles;

[0113] The path location corresponding to when the heat decays to a preset threshold is determined based on the temperature distribution data;

[0114] The ratio of the path position to the total length of the heat dissipation path is used as the preset ratio position.

[0115] Specifically, this embodiment first collects temperature distribution data of the multi-chip package at different locations along a preset heat dissipation path during its historical operating cycle. This data can be obtained through real-time sensor acquisition, simulation calculation, or aggregation of historical operating records, and can accurately reflect the heat transfer and distribution patterns of the package under operating conditions, providing a data foundation for subsequent key location determination. Then, based on the aforementioned temperature distribution data, the process of heat gradually transferring and attenuating along the heat dissipation path is analyzed, locating the specific path location corresponding to the temperature drop to a preset temperature threshold. This location is the dividing point where the heat conduction effect changes significantly and can serve as a key reference location for subsequent defect analysis or heat dissipation assessment. Next, the ratio of this key path location to the total length of the entire heat dissipation path is calculated, and the resulting ratio is the dynamically determined preset ratio location. Compared to a fixed setting value, this method can adaptively adjust based on the actual heat dissipation characteristics of the package, improving the accuracy and applicability of the location parameters.

[0116] Thus, the embodiments of this application dynamically determine the preset proportional position by using historical heat dissipation data, which can better match the actual heat dissipation characteristics of multi-chip packages, providing accurate positional basis for subsequent defect detection, thermal performance analysis and other processes, thereby improving detection accuracy and analysis reliability.

[0117] For example, let's take a specific example: Suppose that the preset heat dissipation path of a multi-chip package (such as a stacked package structure containing 2 core chips) is "chip core area → package substrate → heat dissipation pad → heat sink". The measured total length of the heat dissipation path is 10mm, and the preset temperature threshold is set to 50℃ (this threshold is preset according to the normal operating temperature range of the package and the heat dissipation safety standard, and is used to determine the critical state where the heat decays to a safe and meaningful level).

[0118] First, the heat dissipation data of the multi-chip package over the past 3 months (historical operating cycle) is obtained. By setting a temperature sensor every 0.5 mm along the heat dissipation path, the temperature data at each location under different operating conditions (such as full load operation and half load operation) is collected in real time. After summarizing, the complete temperature distribution data is obtained. For example, the temperature of the chip core area (0 mm position) is 85℃, the temperature of the package substrate at 2 mm position is 72℃, the temperature of the substrate and the heat dissipation pad at 5 mm position is 58℃, the temperature of the heat dissipation pad at 7 mm position is 50℃, and the temperature of the heat sink at 10 mm position is 42℃.

[0119] Subsequently, based on the temperature distribution data mentioned above, the heat decay process along the heat dissipation path was analyzed. It was found that the heat was gradually transferred outward from the core area of ​​the chip (85℃), and the temperature continued to decrease. When it reached the 7mm position of the heat dissipation path, the temperature just decayed to the preset threshold of 50℃. Therefore, it was determined that the 7mm position was the path position corresponding to when the heat decayed to the preset threshold.

[0120] Finally, the ratio of this path location to the total length of the heat dissipation path is calculated, i.e., the ratio of 7mm to 10mm is 0.7 (i.e., 70%). This 0.7 (70%) is the dynamically determined preset ratio position. When subsequently evaluating the heat dissipation performance or detecting defects in this multi-chip package, the 70% position of the heat dissipation path (7mm) can be used as a key reference position to determine the heat dissipation efficiency at that location and whether there are any abnormal thermal resistance issues. Compared to a fixed 50% ratio position, this dynamically determined ratio better reflects the actual heat dissipation characteristics of the package, effectively improving the accuracy of subsequent detection and analysis.

[0121] In another embodiment, when the heat dissipation path passes through the target area, the multi-chip package defect detection method of this application further includes:

[0122] The target ratio is obtained by measuring the ratio of the overlap length of the target region on the heat dissipation path to the total length of the heat dissipation path.

[0123] The risk level of the multi-chip package is determined based on the target ratio.

[0124] Specifically, when the target ratio is greater than or equal to the ratio threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target ratio is less than the ratio threshold, the risk level corresponding to the multi-chip package is determined to be low risk.

[0125] Specifically, in this embodiment, when the heat dissipation path is detected to pass through a target area with a defect, the length of the overlap between the target area and the heat dissipation path is calculated, and the overlap length is compared with the total length of the entire heat dissipation path to obtain a target ratio. This target ratio can quantify the degree of encroachment of the defective target area on the heat dissipation path, intuitively reflecting the magnitude of the defect's impact on the chip's heat dissipation performance, and providing a quantitative basis for subsequent risk assessment. Subsequently, the target ratio is compared with a preset ratio threshold, and the risk level is divided according to the comparison result: when the target ratio is greater than or equal to the ratio threshold, it indicates that the defect accounts for a large proportion of the heat dissipation path, which will significantly hinder heat conduction and easily cause chip overheating, performance degradation, or even failure. Therefore, the multi-chip package is determined to be of a high-risk level; when the target ratio is less than the ratio threshold, it indicates that the defect has a small impact on the heat dissipation path, the heat dissipation function can basically be realized normally, and it will not pose a serious threat to the reliability of the package. Therefore, it is determined to be of a low-risk level.

[0126] Thus, by quantitatively analyzing the overlap ratio between the heat dissipation path and the defect area, the risk level of the multi-chip package can be quickly and objectively determined, providing a reliable basis for defect screening, product classification and subsequent process improvement, thereby improving the efficiency of defect detection and quality control.

[0127] In one embodiment, when the heat dissipation path passes through the target area, the multi-chip package defect detection method of this application further includes:

[0128] The depth change gradient direction of the target surface defect within the target area is obtained, wherein the depth change gradient direction is the direction in which the depth or height value increases the fastest;

[0129] Obtain the local path direction of the heat dissipation path as it passes through the target area;

[0130] Calculate the angle between the depth change gradient direction and the local path direction;

[0131] The risk level of the multi-chip package is determined based on the included angle and the type of the target surface defect;

[0132] Specifically, when the target surface defect is a surface depression defect and the included angle is less than a preset included angle threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target surface defect is a surface protrusion defect and the included angle is greater than or equal to 90 degrees, the risk level corresponding to the multi-chip package is determined to be high risk.

[0133] Specifically, this embodiment first obtains the depth change gradient direction of the target surface defect within the target area, assuming the heat dissipation path passes through the defective target area. This direction represents the most significant change in depth or height within the defective area and can be obtained by gradient calculation of the elevation data of each point within the defective area. It can intuitively reflect the extension trend and structural orientation of the defect, providing geometric feature basis for subsequent risk assessment. Then, the local path direction of the heat dissipation path as it passes through the target area is obtained. This direction reflects the mainstream direction of heat transfer within the chip and the actual conduction path of heat near the defect. Next, the angle between the depth change gradient direction and the local heat dissipation path direction is calculated. This angle value can be accurately obtained through vector dot product and other methods, thereby quantifying the degree of matching between the defect extension direction and the heat transfer direction. Finally, considering the different types of target surface defects—concave or convex—the risk level of the multi-chip package is comprehensively determined, thereby distinguishing the degree of impact of defects on heat dissipation performance and structural reliability.

[0134] Differentiated judgment rules are set for different defect types: when the target surface defect is a surface depression defect and the angle between the two is less than the preset angle threshold, it means that the extension direction of the depression is highly coincident with the heat dissipation path. Heat is easily conducted along this path, which can easily cause thermal expansion and cracking in the depression area, and is judged as high risk; when the target surface defect is a surface protrusion defect and the angle between the two is greater than or equal to 90 degrees, it means that the protrusion structure is directly or perpendicularly blocking the heat dissipation path, which seriously disrupts the continuity of heat flow and aggravates local overheating, and is also judged as high risk.

[0135] Thus, by combining the defect depth gradient direction, heat dissipation path direction, and defect type, the risk level of multi-chip packaging defects can be accurately determined, improving the pertinence and reliability of defect detection and providing an effective basis for chip packaging quality screening.

[0136] In actual chip testing, the following measures can be used for tiered handling and differentiated control: High-risk chips with thermal expansion cracks or impaired heat dissipation are included in key control batches, and subsequent packaging processes and overall assembly processes are immediately suspended. Low-risk chips with thermal expansion cracks or impaired heat dissipation are subject to routine sampling inspection and control. Chips with common surface defects but no thermal expansion cracks or impaired heat dissipation are not subject to additional control, and packaging and assembly operations continue according to normal processes.

[0137] Thus, this application accurately identifies and determines the risk type and risk level of chips by performing defect detection on multi-chip packages. Based on this, it implements graded disposal and differentiated management, which can not only intercept high-risk chips at the source and avoid quality hazards and production losses, but also avoid excessive management of low-risk and non-critical risk chips. While ensuring the thermal reliability and structural safety of packaged products, it improves production continuity and overall quality control efficiency, and achieves a balance between quality safety and production efficiency.

[0138] like Figure 5 As shown, Figure 5 The diagram below shows the hardware structure of the detection system in some embodiments of this application. The detection system provided in the embodiments of this application further includes a memory 1000 and a processor 2000. The memory 1000 is used to store computer-readable instructions, and the processor 2000 is used to call the computer-readable instructions to execute the multi-chip packaging defect detection method based on machine vision as described above.

[0139] The processor 2000 provides computing and control capabilities to control the detection system to perform corresponding tasks, such as controlling the detection system to perform a machine vision-based multi-chip package defect detection method in any of the above method embodiments. The method includes: acquiring surface defects of the multi-chip package using the vision camera and the depth camera, and determining the type of the surface defect as a surface depression defect or a surface protrusion defect to obtain a target surface defect; acquiring defect parameters of the target surface defect, wherein the defect parameters include depth information and depth change information; determining a target area of ​​the target surface defect on the multi-chip package based on the depth information and depth change information; determining a heat dissipation path of the multi-chip package based on its internal packaging structure and operating parameters; comparing the heat dissipation path with the position information of the target area to determine whether the heat dissipation path passes through the target area; and, if the heat dissipation path passes through the target area, determining a risk type corresponding to the multi-chip package based on the type of the target surface defect; wherein, when the target surface defect is a surface depression defect, the risk type is thermal expansion cracking risk; and when the target surface defect is a surface protrusion defect, the risk type is heat dissipation obstruction risk.

[0140] The processor 2000 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0141] The memory 1000, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the machine vision-based multi-chip packaging defect detection method in the embodiments of this application. The processor 2000 can implement the machine vision-based multi-chip packaging defect detection method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in the memory 1000.

[0142] Specifically, memory 1000 may include volatile memory (VM), such as random access memory (RAM); memory 1000 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 1000 may also include combinations of the above types of memory.

[0143] In summary, the detection system of this application adopts the technical solution of any of the above-mentioned machine vision-based multi-chip packaging defect detection method embodiments. Therefore, it has at least the beneficial effects brought by the technical solutions of the above embodiments, which will not be elaborated here.

[0144] This application also provides a computer-readable storage medium, such as a memory including program code, which can be executed by a processor to complete the machine vision-based multi-chip packaging defect detection method described in the above embodiments. For example, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0145] This application also provides a computer program product comprising one or more lines of program code stored in a computer-readable storage medium. A processor reads the program code from the computer-readable storage medium and executes the program code to complete the steps of the machine vision-based multi-chip packaging defect detection method provided in the above embodiments.

[0146] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0147] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0148] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software and a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0149] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A machine vision-based method for detecting defects in multi-chip packaging, applied to an inspection system, the inspection system comprising a vision camera and a depth camera, characterized in that, The method includes: The surface defects of the multi-chip package are obtained by the vision camera and the depth camera, and the type of the surface defect is determined to be a surface depression defect or a surface protrusion defect, so as to obtain the target surface defect. Obtain the defect parameters of the target surface defect, wherein the defect parameters include depth information and depth variation information; Based on the depth information and depth change information, the target area of ​​the target surface defect on the multi-chip package is determined; The heat dissipation path of the multi-chip package is determined based on its internal packaging structure and operating parameters. The location information of the heat dissipation path is compared with that of the target area to determine whether the heat dissipation path passes through the target area; When the heat dissipation path passes through the target area, the risk type corresponding to the multi-chip package is determined according to the type of the target surface defect; wherein, when the target surface defect is a surface depression defect, the risk type is thermal expansion cracking risk; when the target surface defect is a surface protrusion defect, the risk type is heat dissipation obstruction risk.

2. The multi-chip packaging defect detection method based on machine vision as described in claim 1, characterized in that, The step of determining the target region of the target surface defect on the multi-chip package based on the depth information and depth change information includes: The target surface defect is divided into multiple consecutive candidate regions along the extension direction of the target surface defect; For each candidate region, obtain its depth information and depth change information; Candidate regions whose depth information and depth change information meet preset conditions are determined as the target regions.

3. The multi-chip packaging defect detection method based on machine vision as described in claim 2, characterized in that, The step of determining candidate regions whose depth information and depth change information meet preset conditions as target regions includes: When the target surface defect is a surface depression defect, the candidate region that meets any of the following conditions will be determined as the target region: Along the length of the defect, the depth value gradually increases and the rate of change of depth is greater than or equal to a first rate of change threshold. Along the width direction of the defect, the depth value gradually increases and the rate of change of depth is greater than or equal to a second rate of change threshold. And / or, when the target surface defect is a surface protrusion defect, a candidate region that satisfies any of the following conditions is determined as the target region: Along the length of the defect, the height value gradually increases and the height change rate is greater than or equal to the third change rate threshold; Along the width direction of the defect, the height value gradually increases and the height change rate is greater than or equal to the fourth change rate threshold.

4. The multi-chip packaging defect detection method based on machine vision as described in any one of claims 1-3, characterized in that, The defect parameters also include the contour complexity, defect area, and defect edge smoothness of the target surface defect. Determining the target region of the target surface defect on the multi-chip package based on the depth information and depth change information includes: The contour complexity, defect area, and defect edge smoothness of the target surface defect are calculated. The contour complexity is calculated by the ratio of the number of concave and convex points of the contour to the total number of points of the contour, and the edge smoothness is calculated by the average distance from the edge point to the contour fitting line. When the contour complexity is determined to be greater than a preset complexity threshold, the defect area is greater than a preset area threshold, and the defect edge flatness is less than a preset flatness threshold, the region after extending the candidate region outward by a preset distance is determined as the target region.

5. The multi-chip packaging defect detection method based on machine vision as described in claim 1, characterized in that, Determining the heat dissipation path of the multi-chip package based on its internal packaging structure and operating parameters includes: A thermal simulation model is established in advance based on the internal chip layout, heat source power distribution, and thermal conductivity of the packaging material of the multi-chip package. At least one main heat dissipation path is generated within the multi-chip package using the thermal simulation model, and the main heat dissipation path is used as the heat dissipation path.

6. The multi-chip packaging defect detection method based on machine vision as described in claim 1, characterized in that, When the heat dissipation path passes through the target area, the method further includes: Determine the position of the target area on the heat dissipation path; The risk level of the multi-chip package is determined based on the location of the target area on the heat dissipation path; Specifically, when the first half of the heat dissipation path passes through the target area, the risk level corresponding to the multi-chip package is determined to be high risk; when the second half of the heat dissipation path passes through the target area, the risk level corresponding to the multi-chip package is determined to be low risk. The first half is a path segment from the starting point of the heat dissipation path to a predetermined proportional position on the heat dissipation path, where the starting point of the heat dissipation path is the location of the heat source.

7. The multi-chip packaging defect detection method based on machine vision as described in claim 6, characterized in that, The method for determining the preset proportional position includes: Obtain temperature distribution data along the heat dissipation path of the multi-chip package during historical operating cycles; The path location corresponding to when the heat decays to a preset threshold is determined based on the temperature distribution data; The ratio of the path position to the total length of the heat dissipation path is used as the preset ratio position.

8. The multi-chip packaging defect detection method based on machine vision as described in claim 1, characterized in that, When the heat dissipation path passes through the target area, the method further includes: The target ratio is obtained by measuring the ratio of the overlap length of the target region on the heat dissipation path to the total length of the heat dissipation path. The risk level of the multi-chip package is determined based on the target ratio. Specifically, when the target ratio is greater than or equal to the ratio threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target ratio is less than the ratio threshold, the risk level corresponding to the multi-chip package is determined to be low risk.

9. The multi-chip packaging defect detection method based on machine vision as described in claim 1, characterized in that, When the heat dissipation path passes through the target area, the method further includes: The depth change gradient direction of the target surface defect within the target area is obtained, wherein the depth change gradient direction is the direction in which the depth or height value increases the fastest; Obtain the local path direction of the heat dissipation path as it passes through the target area; Calculate the angle between the depth change gradient direction and the local path direction; The risk level of the multi-chip package is determined based on the included angle and the type of the target surface defect; Specifically, when the target surface defect is a surface depression defect and the included angle is less than a preset included angle threshold, the risk level corresponding to the multi-chip package is determined to be high risk; when the target surface defect is a surface protrusion defect and the included angle is greater than or equal to 90 degrees, the risk level corresponding to the multi-chip package is determined to be high risk.

10. A detection system, characterized in that, Including visual cameras, depth cameras, and The memory is used to store program code; A processor, the processor being configured to invoke the program code to perform the method as described in any one of claims 1 to 9.

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