Indicator component control system

Abstract

This application provides an indicator component control system, including: a processor; and an isolation circuit corresponding to the processor; a controller for controlling the display state of the indicator component; the isolation circuit is configured to, when the processor is in a first state, cause the controller to receive a status indication signal of the indicator component, and control the display state of the indicator component according to the status indication signal.

Description

Technical Field

[0001] This application relates to control technology, and more particularly to an indicator component control system. Background Technology

[0002] In related technologies, when the processor in an electronic device is effectively short-circuited to ground, this short-circuit state will interfere with the controller's control of the indicator lights through the signal path, causing the indicator lights to display abnormally and affecting the user experience. Summary of the Invention

[0003] This application provides an indicator component control system.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides an indicator component control system, the system comprising: The processor; and the isolation circuit corresponding to the processor; The controller is used to control the display status of the indicator components; The isolation circuit is used to enable the controller to receive a status indication signal of the indicator component when the processor is in a first state, and to control the display state of the indicator component according to the status indication signal. Attached Figure Description

[0005] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0006] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0007] Figure 1 This is one of the structural schematic diagrams of an indicator component control system provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the structure of an indicator component control system provided in an embodiment of this application; Figure 3 This is the third schematic diagram of the structure of an indicator component control system provided in the embodiments of this application; Figure 4 This is the fourth schematic diagram of a control system for an indicator component provided in this application embodiment; Figure 5 This is the fifth schematic diagram of the structure of an indicator component control system provided in the embodiments of this application. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0009] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0010] In the following description, references to "some embodiments," "this embodiment," "this application embodiment," and examples, etc., describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subset of all possible embodiments and may be combined with each other without conflict.

[0011] The terms "first," "second," and "third" appearing in the embodiments of this application do not have a specific meaning (e.g., there is no order, nor does it indicate a special limitation on the number of devices in the embodiments of this application), but are merely for the purpose of clearly describing the embodiments of this application and do not constitute any limitation on the embodiments of this application. The term "multiple" appearing in the embodiments of this application refers to two or more integers.

[0012] In related technologies, for products on the ARM (Advanced RISC Machine) platform, the system-on-chip (SoC) has limitations due to the equivalent short circuit to ground on its general-purpose input / output (GPIO) pins in states such as power off, standby, and reset. This short circuit can directly interfere with the signal reception of the controller through the signal path, causing the embedded controller (EC) or microcontroller unit (MCU) to be unable to independently and reliably control the display behavior of the indicator lights in different operating states (e.g., abnormal flashing of indicator lights during restart or power-on, disordered indicator light status during system upgrade, and significant delay in the on / off response of indicator lights when charging while powered off), thus affecting the user experience.

[0013] To address at least one of the aforementioned problems in related technologies, embodiments of this application provide an indicator component control system. This system avoids signal interference from equivalent short circuits to ground on processor pins, enabling the controller to reliably receive status indication signals and control the display state of the indicator component. This achieves reliable control of the indicator component by the controller, preventing abnormal display states and improving the user experience. The indicator component control system provided in this application will be described in detail below with reference to the accompanying drawings.

[0014] Figure 1 This is one of the structural schematic diagrams of an indicator component control system provided in the embodiments of this application; as shown Figure 1 As shown, the system includes: Processor 101; and isolation circuit 102 corresponding to processor 101; The controller 103 is used to control the display status of the indicator component 104; The isolation circuit 102 is used to enable the controller 103 to receive a status indication signal of the indication component 104 when the processor 101 is in a first state, and to control the display state of the indication component 104 according to the status indication signal.

[0015] It should be noted that processor 101 is the main processor or central processing unit in an electronic device, including but not limited to ARM architecture system-on-a-chip (SOC), x86 architecture CPU, or other processing chips with general-purpose computing capabilities. When processor 101 is in states such as power off, standby, or reset, its general-purpose input / output (GPIO) pins may be effectively shorted to ground.

[0016] It should be noted that the isolation circuit 102 can electrically block or reduce the interference of the pin states of the processor 101 on the signal input path of the controller 103. Depending on the actual application requirements, the isolation circuit 102 can be a unidirectional isolation circuit or a bidirectional isolation circuit.

[0017] In some embodiments, when the system only needs to transmit status indication signals unidirectionally from upstream modules (such as charging chips or PD protocol chips) to controller 103, without processor 101 outputting signals to the signal receiving end of controller 103 through its GPIO pins, a unidirectional isolation circuit can be used. For example, a diode can be connected in series in the signal transmission path, utilizing its unidirectional conduction characteristic to block the reverse interference of short circuits to ground on the pins of processor 101; or an N-type metal-oxide-semiconductor field-effect transistor (NMOS) can be used, configured as a source follower, utilizing its voltage following characteristic to achieve signal transmission and isolation; or configured as a switch, turning off the path when processor 101 is in the first state to achieve isolation.

[0018] In some embodiments, when bidirectional signal transmission is required between the processor 101 and the controller 103 (e.g., the controller 103 reports the status indication signal reception status to the processor 101, and the processor 101 issues control commands to the controller 103), a bidirectional isolation circuit can be used. For example, an optocoupler can be used to achieve complete electrical isolation between the two circuits through optical signals, allowing signals to be transmitted bidirectionally without damaging each other; or magnetic couplers, capacitor isolators, bidirectional analog switches, and paired NMOS transistors can be used to achieve bidirectional signal transmission and electrical isolation.

[0019] It should be noted that the controller 103 can be an EC, MCU, or other control unit with logic control capabilities used to control the display status of the indicator component 104. The power supply of the controller 103 is independent of the power supply of the processor 101, and the controller 103 continues to operate normally even when the processor 101 is in a power-off, standby, or reset state.

[0020] It should be noted that the indicator component 104 may be an LED indicator, a digital tube, a display status icon, or other visual indicator elements used to present the device status to the user.

[0021] It should be noted that the first state is when the processor is in a non-working state (e.g., the corresponding electronic device is powered off, in standby, or in a reset state, or in other states that make its GPIO pins present an equivalent short circuit to ground). In this state, the processor is in a low-power mode of power-off or maintaining power supply. If the processor 101 is connected to the signal receiving end of the controller 103, it will cause electrical interference to the normal transmission of the status indication signal. To address this, this embodiment of the application sets up an isolation circuit 102 between the processor 101 and the transmission path of the status indication signal. When the processor 101 is in the first state, the isolation circuit 102 can block or reduce the electrical influence of the GPIO pin state of the processor 101 on the signal transmission path, ensuring that the controller 103 can reliably receive the status indication signal from the upstream functional module (e.g., charging chip, PD protocol chip, or power management chip). Furthermore, the controller 103 generates a corresponding drive signal according to the received status indication signal to control the indicator component 104 to present the corresponding display state, such as the power indicator light being on or the charging indicator light flashing.

[0022] It should be noted that the status indication signal can come from the status output signal of the charging chip, PD protocol chip, power management chip or other functional modules, and is used to indicate the power status, charging status or system operating status, etc.

[0023] In some embodiments, the isolation circuit 102 is coupled between the processor 101 and the transmission path of the status indication signal. It should be noted that coupling includes direct and indirect connections. For example, the isolation circuit 102 can be directly connected to the GPIO pin of the processor 101, i.e., directly connected via a wire or conductive medium without intermediate components. Alternatively, the isolation circuit 102 can be indirectly connected to the processor 101 via one or more intermediate components. Specifically, a current-limiting resistor can be connected in series between the processor 101 and the isolation circuit 102 to protect the circuit; or a capacitor can be connected in series to block DC and pass AC; or a diode can be connected in series to prevent reverse current. It is understood that any indirect connection method that does not change the basic function of the isolation circuit 102 falls within the scope of protection of this application.

[0024] In some embodiments, the controller 103 can be directly connected to the indicator component 104. For example, the GPIO pin of the controller 103 is directly connected to the anode of the LED indicator, and the cathode of the LED indicator is grounded. The controller 103 outputs a high or low level through its GPIO pin to directly drive the LED indicator to light up or turn off.

[0025] In some embodiments, the controller 103 can be indirectly connected to the indicator component 104 through one or more intermediate components. For example, a current-limiting resistor can be connected in series between the controller 103 and the LED indicator to limit the current flowing through the LED and prevent overcurrent damage; a transistor or MOSFET can be connected in series between the controller 103 and the LED indicator, and the controller 103 controls the switching of the transistor to indirectly drive the high-power indicator; a decoder or driver chip can be connected in series between the controller 103 and the digital tube or display screen, and the controller 103 outputs a control signal, which is converted by the decoder or driver chip to drive the indicator component 104 to display the corresponding status.

[0026] It should be noted that the controller 103 can determine the display state to be presented by the indicator component 104 based on the received status indication signal. This display state includes, but is not limited to: constantly on, constantly off, flashing at a specific frequency, breathing effect, color change, or displaying a specific icon. For example, when the controller 103 receives a good power signal from the charger, it controls the charging indicator light to remain constantly on; when it receives a charging in progress signal, it controls the charging indicator light to flash at a frequency of 1Hz; and when it receives a charging complete signal, it controls the charging indicator light to turn off or become solid green.

[0027] In some embodiments, taking temperature monitoring and overheat protection applications in electronic devices as an example, when the CPU or GPU temperature exceeds the extreme value, the electronic device may instantly trigger a hardware protection mechanism (such as a hard reset or direct power-off). The temperature sensor has a Thermal Critical pin, used to output a high-temperature alarm signal when an excessive temperature is detected. When the SOC triggers a hard reset or direct power-off due to overheating, its GPIO pin will go low (presenting an equivalent short circuit to ground). If the SOC's GPIO pin is directly connected to the transmission path of the high-temperature alarm signal, it will pull the alarm signal low, causing the controller to be unable to receive it. This embodiment, however, uses an isolation circuit to couple the SOC's GPIO pin to the transmission path, thereby blocking the electrical interference of the SOC's short circuit to ground on the high-temperature alarm signal. Therefore, the controller can still reliably receive the high-temperature alarm signal and control the LED strip to flash with specific yellow or orange light according to preset logic, indicating to the user that the electronic device has triggered a protective shutdown due to overheating and has entered a protection state.

[0028] In some embodiments, taking a Basic Input Output System (BIOS) or firmware update application scenario as an example, during the BIOS or firmware update process, the processor is in an abnormal operating state (e.g., bootloader mode or reset state). At this time, the processor cannot run complex User Interface (UI) control logic, and the level of its GPIO pins may exhibit an equivalent short circuit to ground. When the flashing circuit enters update mode, it outputs an activation signal (e.g., the Flash_Mode_Active signal) to indicate that it is currently in a firmware update state. If the processor's GPIO pins are directly connected to the transmission path of this activation signal, level fluctuations may pull the signal low or cause interference, preventing the controller from accurately identifying the firmware update state. This embodiment, however, uses an isolation circuit to couple the processor's GPIO pins to the transmission path of the activation signal, thereby blocking electrical interference from GPIO pin level fluctuations on the activation signal. Therefore, the controller can still reliably receive the activation signal from the flashing circuit and control the indicator light to flash at a specific frequency (e.g., a purple breathing flash) according to preset logic, intuitively showing the user that the electronic device is in the BIOS or firmware update process.

[0029] In some embodiments, taking a camera privacy protection application scenario as an example, when a hacker causes a processor (such as a SOC) to crash or enter a suspended state (reset state) through a virus attack, they may attempt to activate the camera without the user's knowledge. At this time, the processor's GPIO pins may be in an equivalent short-circuit state to ground. If the processor's GPIO pins are directly connected to the camera's hardware power-on signal line, this signal will be pulled low or interfered with, causing the controller to be unable to accurately detect the actual working state of the camera. This embodiment, however, sets up an isolation circuit to couple the processor's GPIO pins to the camera's hardware power-on signal line, thereby blocking electrical interference from the abnormal state of the processor on this signal line. Thus, the controller can directly capture the "powered on" physical signal from the camera hardware. When the controller detects that the camera is powered on, it forcibly illuminates a privacy indicator light (e.g., a red LED). The user can then know that the camera hardware has been activated simply by seeing the indicator light illuminate. Even if the main system is in a black screen, crashed, or powered off state at this time, the user can promptly detect the potential privacy leakage risk.

[0030] In this embodiment, an isolation circuit 102 is provided between the processor 101 and the signal transmission path. When the processor 101 is in a first state, the isolation circuit 102 can block the electrical interference of the GPIO pin of the processor 101 being short-circuited to ground to the status indication signal, ensuring that the status indication signal is reliably transmitted to the controller 103. Then, the controller 103 can reliably control the indication component 104 according to the received status indication signal, avoiding the indication component 104 from displaying abnormal status, thereby improving the user experience.

[0031] In some embodiments, such as Figure 2 As shown, the indicator component control system provided in this application embodiment further includes: At least one status indication port 105 is used to output a first status indication signal; the status indication port 105 is coupled to one end of the controller 103 to form a signal input path of the controller 103, and the status indication port 105 is coupled to one end of the isolation circuit 102.

[0032] It should be noted that the status indicator port 105 is a physical interface or pin used to output a first status indicator signal, which can come from a charging chip (Charger IC), PD protocol chip (PD Controller), power management chip (Power Management Integrated Circuit, PMIC), temperature sensor, flashing circuit, or other functional modules capable of generating a first status indicator signal. Status indicator port 105 may include a Type-C port, a power adapter interface, and a network interface, etc. The first status indicator signal is a raw signal characterizing the current operating state of the electronic device, such as a charger power good signal, charging status signal, PD negotiation status signal, temperature alarm signal, flashing mode activation signal, camera power-on signal, etc.

[0033] It should be noted that, in this embodiment, the status indicator port 105 is coupled to one end of the controller 103, and the status indicator port 105 is also coupled to one end of the isolation circuit 102. The coupling includes direct connection (direct connection via wires or conductive media) and indirect connection (connection via intermediate components such as resistors, capacitors, diodes, and MOSFETs). One end of the isolation circuit 102 refers to a connection terminal of the isolation circuit 102, which is coupled to the signal input path between the status indicator port 105 and the controller 103. The other end of the isolation circuit 102 is coupled to the GPIO pin of the processor 101.

[0034] It should be noted that, in this embodiment of the application, the signal input path of the controller 103 refers to the physical path through which the status indication signal is transmitted from the status indication port 105 to the controller 103. The integrity of the signal on this path directly affects the accuracy of the controller 103 in judging the status of the device.

[0035] In some embodiments, the status indication port 105 may be the Power Good pin of the charging chip. When the charger is plugged in and the input voltage is stable, this pin outputs a high level as a first status indication signal, indicating that "the charger is ready and can be charged normally".

[0036] In some embodiments, the status indication port 105 is coupled to the signal input terminal of the controller 103, thereby forming a signal input path from the status indication port 105 to the controller 103.

[0037] In some embodiments, the status indication port 105 can be directly connected to the controller 103 via a wire to achieve direct signal transmission.

[0038] In some embodiments, the status indication port 105 can be indirectly connected to the controller 103 via a current-limiting resistor, a DC blocking capacitor, or other protective components to prevent overcurrent or electrostatic damage.

[0039] In some embodiments, the status indication port 105 is also coupled to one end of the isolation circuit 102. Specifically, one connection end of the isolation circuit 102 is connected to the signal input path between the status indication port 105 and the controller 103, while the other connection end of the isolation circuit 102 is connected to the GPIO pin of the processor 101. Through this connection method, the processor 101 can indirectly obtain the first status indication signal through the isolation circuit 102. When the processor 101 is in the first state (e.g., power off, standby, or reset, which are equivalent to a short circuit to ground), the isolation circuit 102 can block the electrical interference of the processor 101 pin state to the signal input path, ensuring that the first status indication signal received by the controller 103 is not affected.

[0040] For example, when the processor 101 is powered off, its GPIO pins are effectively short-circuited to ground. Without the isolation circuit 102, this short circuit would pull the signal input path low, causing the controller 103 to fail to correctly recognize the charger's power-good signal. However, by setting the isolation circuit 102 (e.g., using an optocoupler or NMOS transistor), the short circuit to ground on the processor 101's GPIO pins does not affect the signal input path's level, and the controller 103 can still reliably receive the high-level power-good signal and control the charging indicator light to illuminate accordingly.

[0041] In some embodiments, the indicator component control system provided in this application may include multiple status indicator ports 105, each corresponding to a different functional module. For example, a first status indicator port is connected to the power-good pin of the charging chip to output a charging status signal; a second status indicator port is connected to the PD protocol chip to output a PD negotiation status signal; and a third status indicator port is connected to the over-temperature interrupt pin of the temperature sensor to output an overheat alarm signal. Each status indicator port 105 is simultaneously coupled to the controller 103 and the isolation circuit 102 in a similar manner to achieve reliable transmission and isolation protection of multiple status indicator signals.

[0042] It is understood that the first status indication signal output from the status indication port 105 needs to be reliably transmitted to the controller 103 via the signal input path so that the controller 103 can accurately control the display status of the indicator component 104. However, when the processor 101 is in a first state such as power off or reset, its GPIO pins are effectively short-circuited to ground, which will generate electrical interference to the signal input path through the coupling node, pulling down the first status indication signal. This causes the controller 103 to be unable to obtain the true status, resulting in abnormal flashing or response delay of the indicator light. To avoid the above interference, in this embodiment, the status indication port 105 is simultaneously coupled to one end of the isolation circuit 102, and the other end of the isolation circuit 102 is connected to the processor 101. When the processor 101 is in the first state, the isolation circuit 102 can block the interference of the processor 101's GPIO pin short-circuit to ground to the signal input path, ensuring that the first status indication signal is transmitted to the controller 103 completely and stably. The controller 103 obtains the true first state indication signal accordingly, and then independently and accurately controls the display state of the indicator component 104 to avoid abnormal display of the indicator component 104 and improve the user experience.

[0043] In some embodiments, when the processor 101 is in a first state, the controller 103 independently controls the display state of the indicator component 104 according to the first state indication signal.

[0044] In this embodiment, the first state includes, but is not limited to, the power-off state, standby state, and reset state of the processor 101. In these states, the GPIO pins of the processor 101 are subject to an equivalent short circuit to ground. If the processor 101 is relied upon to control the indicator component 104, the control signal will be abnormal due to the short circuit of the processor 101's GPIO pins. Therefore, in this embodiment, the controller 103 independently undertakes the control task of the indicator component 104. That is, the controller 103 does not rely on the participation or intervention of the processor 101; it autonomously generates drive signals to control the display state of the indicator component 104 based solely on the first state indication signal it receives.

[0045] In this embodiment, the controller 103 receives a first status indication signal from the status indication port 105 via a signal input path. Due to the presence of the isolation circuit 102, a short circuit to ground when the processor 101 is in the first state will not interfere with the normal transmission of this signal. After receiving the first status indication signal, the controller 103 does not need to wait for instructions or intervention from the processor 101, but directly generates the corresponding drive signal according to preset logic rules, controlling the indication component 104 to present a display effect corresponding to the current device state.

[0046] For example, in a charging indicator application scenario, when the controller 103 receives a Power Good signal from the charging chip, it determines that the charger is plugged in and the voltage is stable, and then independently controls the charging indicator light to stay on, indicating "charging in progress"; when the controller 103 receives a battery full charge indicator signal, it independently controls the charging indicator light to turn off or turn green and stay on, indicating "charging complete"; when the controller 103 receives a charging abnormality signal, it independently controls the charging indicator light to provide an alarm prompt at a specific frequency (such as rapid flashing).

[0047] For example, in a temperature monitoring application scenario, when the controller 103 receives an over-temperature alarm signal from the temperature sensor, it independently controls the LED strip to flash yellow or orange to indicate to the user that the device has triggered protection due to overheating.

[0048] For example, in a privacy protection application scenario, when the controller 103 directly captures the "powered on" signal from the camera hardware, it independently forces the red privacy indicator light to light up. Even if the processor 101 is in a frozen or black screen state, the user can still know that the camera has been activated through the indicator light.

[0049] It is understood that in this embodiment of the application, when the processor 101 is in the first state, the controller 103 independently controls the display state of the indicator component 104 according to the first state indication signal, thereby avoiding the problem of abnormal display of the indicator component 104 caused by the short circuit to ground of the GPIO pin of the processor 101 and ensuring the accuracy of the state indication of the indicator component 104.

[0050] In some embodiments, when the processor 101 is in the second state, the controller 103 receives the first state indication signal and the second state indication signal sent by the processor 101, and controls the display state of the indication component 104 in conjunction with the first state indication signal and the second state indication signal.

[0051] It should be noted that the first state includes any one of the following states: standby, power off, or reset. The second state is when the processor 101 is in normal working condition, that is, when the processor 101 can run the operating system, execute applications, manage peripherals, and participate in the control logic of the instruction component 104. The power consumption of the processor 101 in the second state is higher than that in the first state.

[0052] It should be noted that the second state indication signal refers to the control signal generated by the processor 101 and sent to the controller 103 in normal working state, which is used to instruct the controller 103 to adjust the display state of the indicator component 104, such as system sleep indication, power mode switching indication, user-defined lighting effect instructions, etc.

[0053] In this embodiment, when the processor 101 is in the second state, the controller 103 receives a first state indication signal and a second state indication signal sent by the processor 101, and controls the display state of the indicator component 104 based on the first and second state indication signals. Specifically, the second state refers to the processor 101 being in a normal working state, where the processor 101 can run the operating system and execute applications, and its GPIO pins can output high and low levels normally without any limitation of equivalent short circuit to ground. In this state, the processor 101 can send a second state indication signal to the controller 103. The controller 103 simultaneously receives two signals: one is the first state indication signal from the state indication port 105, and the other is the second state indication signal from the processor 101. The controller 103 determines the final display state of the indicator component 104 by combining the two signals according to preset logical rules (such as priority rules, arbitration rules, or superposition rules).

[0054] For example, when controller 103 receives a power-good signal (first status indication signal) from the charging chip, it determines that the charger is plugged in. Simultaneously, after detecting a charging event at the operating system level, processor 101 sends a second status indication signal to controller 103, requesting the charging indicator light to display a breathing light effect. Controller 103 combines the two signals and controls the charging indicator light to illuminate in a breathing mode.

[0055] For example, after the controller 103 receives a power good signal (first state indication signal) from the charging chip, it controls the charging indicator light to stay on. At the same time, if the second state indication signal sent by the processor 101 requires the indicator component to exhibit a breathing effect, the controller 103 can control the charging indicator light to have a breathing effect (i.e., periodic changes in brightness) superimposed on the constant illumination.

[0056] It is understood that in this embodiment of the application, when the processor 101 is in the second state (normal working state), the controller 103 can receive the first state indication signal and the second state indication signal, and control the display state of the indicator component 104 together according to the first state indication signal and the second state indication signal. This not only ensures the reliability of the state indication, but also realizes complex state indication under the synergistic effect of the first state indication signal and the second state indication signal, thereby improving the user experience.

[0057] In some embodiments, the isolation circuit 102 is used to block level interference generated by the processor 101 on the signal input path of the controller 103 when the processor 101 is in a first state.

[0058] In this embodiment, the isolation circuit 102 is used to block the level interference generated by the processor 101 on the signal input path of the controller 103 when the processor 101 is in a first state. Specifically, when the processor 101 is in a power-off state, a reset state, or a standby state, the GPIO pins of the processor 101 are subject to an equivalent short circuit to ground. When the GPIO pins of the processor 101 are directly or indirectly connected to the signal input path of the controller 103, this short circuit to ground state will pull the level on the signal input path low (e.g., 0V), thereby generating level interference. This level interference will cause the status indication signal to fail to be transmitted to the controller 103 normally, thus preventing the controller 103 from accurately determining the current working state of the device, causing the indicator component 104 to display abnormally. To address this, this embodiment provides an isolation circuit 102 between the processor 101 and the signal input path. The isolation circuit 102 has electrical isolation characteristics and can block the electrical influence of the short circuit to ground of the processor 101's GPIO pins on the signal input path when the processor 101 is in the first state.

[0059] In some embodiments, the isolation circuit 102 is implemented using an optocoupler. One end of the optocoupler is coupled to a GPIO pin of the processor 101, and the other end is coupled to a signal input path (i.e., the connection node between the status indicator port 105 and the controller 103). When the processor 101 is in a first state (such as a power-off state), the end of the optocoupler coupled to the GPIO pin of the processor 101 is short-circuited, but the other end is unaffected because the optocoupler internally transmits information via optical signals, and the two circuits are completely electrically isolated. Therefore, the level on the signal input path will not be pulled low, and the status indicator signal can still be transmitted normally to the controller 103.

[0060] In some embodiments, the isolation circuit 102 is implemented using an NMOS transistor. The gate of the NMOS transistor receives a control signal, and its source and drain are connected to the GPIO pin of the processor 101 and the signal input path, respectively. When the processor 101 is in a first state, the gate voltage of the NMOS transistor is controlled to turn it off, thereby cutting off the electrical connection between the processor 101 and the signal input path and blocking level interference.

[0061] It is understood that in this embodiment of the application, when the processor 101 is in the first state, the isolation circuit 102 can effectively block the level interference generated by the processor 101 to the signal input path, ensuring that the status indication signal is transmitted to the controller 103 completely and stably, providing a reliable signal basis for the controller 103 to accurately control the indication component 104.

[0062] In some embodiments, the controller 103 is further configured to: If a second status indication signal is not received from the processor 101 for a certain period of time, and a communication anomaly is determined with the processor 101, the display status of the indication component 104 is independently controlled according to the first status indication signal.

[0063] It should be noted that the specific duration is a pre-set time threshold used to determine whether the communication between the processor 101 and the controller 103 is normal. This duration can be configured according to system requirements, such as being set to 1 second, 3 seconds, 5 seconds, etc., as long as it can distinguish between normal communication intervals and abnormal disconnections. This application embodiment does not specifically limit the value of the specific duration.

[0064] In some embodiments, when the processor 101 is in the second state (normal operating state), it can periodically send a second state indication signal to the controller 103 via a communication interface (e.g., an I2C bus or a dedicated GPIO pin). The controller 103 has an internal timer or counter to monitor the time interval for receiving the second state indication signal. When the controller 103 receives the second state indication signal, the timer resets and restarts. If the controller 103 does not receive any second state indication signal after a preset specific time (e.g., 3 seconds), it determines that a communication anomaly has occurred with the processor 101. The causes of communication anomalies include, but are not limited to: the processor 101 crashing or entering a suspended state, the processor 101 being in a reset loop, or a communication line failure between the processor 101 and the controller 103. After determining a communication anomaly, the controller 103 enters an anomaly handling mode and no longer waits for or relies on instructions from the processor 101. At this time, the controller 103 independently controls the display state of the indicator component 104 based on the received first state indication signal.

[0065] For example, when the communication line between the processor 101 and the controller 103 fails, the processor 101 cannot send the second status indication signal. If the controller 103 does not receive the second status indication signal for a certain period of time (e.g., 3 seconds), it determines that the communication is abnormal. At this time, if the controller 103 receives an over-temperature alarm signal (first status indication signal) from the temperature sensor, the independent control indication component 104 (such as an LED light strip) will flash yellow or orange to indicate to the user that the device has triggered protection due to overheating.

[0066] It is understood that in this embodiment of the application, when a communication abnormality occurs between the processor 101 and the controller 103, the controller 103 can automatically switch to the independent control mode and directly control the indicator component 104 according to the first state indication signal, so as to ensure that the device status can still be accurately presented through the indicator component 104, thereby improving the reliability of the system.

[0067] In some embodiments, such as Figure 3 As shown, the controller 103 includes a delay filtering unit 1031, which is used to filter pulse signals in the first state indication signal whose duration is less than a specific threshold, so as to suppress the indication component 104 from generating unexpected display state jumps due to the non-steady pulse signals in the first state indication signal.

[0068] It should be noted that the delay filtering unit is a logic module located inside the controller 103. It performs time-domain filtering on the received first state indication signal, determining it as a valid signal only if its duration exceeds a specific threshold. This specific threshold is a preset time threshold used to distinguish valid state indication signals from transient interference pulses. Unstable pulse signals refer to extremely short, unstable instantaneous level jumps, such as glitches generated when a charger is plugged in, brief jitters during PD protocol voltage switching, or abnormal pulses generated during PMIC reset. Unexpected display state jumps refer to brief, undesirable on / off changes in the indicator component 104 caused by receiving unstable pulse signals, such as a quick flash of an indicator light followed by a return to its original state, or displaying an incorrect state.

[0069] It should be noted that the first state indication signal comes from upstream functional modules (such as charging chips, PD protocol chips, PMICs, temperature sensors, etc.). During normal operation of the device, these signals are usually stable levels or pulses with clear meaning. However, in actual circuits, due to power transient response, hot-plugging, PD protocol negotiation, PMIC reset, etc., the first state indication signal may contain extremely short-duration non-steady-state pulse signals (e.g., microsecond-level or millisecond-level glitches). These non-steady-state pulses are not real device state changes. If they are directly transmitted to the controller 103 and drive the indicator component 104, it will cause the indicator component 104 to exhibit brief erroneous flickering or state jumps, affecting the user experience. To avoid this situation, this embodiment of the application provides a delay filtering unit 1031 inside the controller 103. The delay filtering unit 1031 performs time-domain filtering on the received first state indication signal: when the signal level changes, the delay filtering unit 1031 does not respond immediately, but starts timing. Only when the duration of the level change exceeds a preset specific threshold is it determined to be a valid state change and output to the subsequent circuit to drive the indication component 104; if the duration of the level change is less than the specific threshold, it is determined to be an unstable pulse signal and filtered (discarded or ignored), without triggering the state change of the indication component 104.

[0070] In some embodiments, the specific threshold is greater than the duration of transient glitches generated during PMIC reset, PD negotiation, or power switching, but less than the effective pulse width of the normal state indication signal. For example, at the moment the charger is plugged in, the Power Good signal may generate a glitch lasting approximately 50 microseconds, while the normal Power Good signal lasts for several seconds or even longer. Therefore, the specific threshold can be set to 1 millisecond to effectively filter glitches without affecting the transmission of the normal signal. Specifically, when a user plugs in the charger, the Power Good signal of the charging chip may generate brief fluctuations (e.g., multiple microsecond-level low-level pulses) before the voltage stabilizes. Without the delay filtering unit 1031, these glitches would cause the controller to misinterpret "charger unplugged and plugged in," causing the charging indicator light to flash rapidly. By setting the delay filtering unit 1031 (e.g., setting the specific threshold to 1 millisecond), these microsecond-level glitches are filtered out, and only a sustained, stable high level (indicating that the voltage is truly stable) is recognized as a valid signal, resulting in a smooth, flicker-free indicator light.

[0071] It is understood that in this embodiment of the application, the delay filtering unit 1031 can effectively filter out the non-steady-state pulse signal in the first state indication signal, ensuring that the indication component 104 only updates the display state when it receives a real and stable state change, thereby avoiding false flickering or unexpected jumps of the indication component 104, and improving the accuracy of the state indication and the user experience.

[0072] In some embodiments, such as Figure 4 As shown, a delay circuit 106 is connected between the controller 103 and each of the status indication ports 105. The delay circuit 106 is used to filter pulse signals with a duration less than a specific threshold in the first status indication signal output by each of the status indication ports 105, so as to suppress the indication component 104 from generating unexpected display status jumps due to the non-steady pulse signals in the first status indication signal.

[0073] It is understood that in this embodiment, the delay circuit 106 is an independent circuit module located between the status indication port 105 and the controller 103, used to perform time-domain filtering on the first status indication signal. Its function is similar to the delay filtering unit 1031 inside the controller 103, but it is located outside the controller 103 and implemented as an independent hardware circuit.

[0074] In this embodiment, the first state indication signal output from the state indication port 105 passes through a delay circuit 106 before being transmitted to the controller 103. The delay circuit 106, as an independent hardware module, is located externally to the controller 103 and connected to the state indication port 105. The function of the delay circuit 106 is to perform time-domain filtering on the input first state indication signal. When the first state indication signal undergoes a level transition, the delay circuit 106 does not immediately transmit the transition to the output terminal but starts timing. Only when the duration of the level transition exceeds a preset specific threshold is the delay circuit 106 determined to be a valid state change and the signal transmitted to the controller 103; if the duration of the level transition is less than the specific threshold, it is determined to be an unsteady pulse signal and filtered (i.e., the output terminal remains unchanged), thereby preventing the pulse signal from reaching the controller 103.

[0075] It should be noted that the delay circuit 106 can be implemented in various hardware methods, including but not limited to: RC delay circuit: Composed of resistors and capacitors, it utilizes the charging and discharging characteristics of the capacitor to achieve delay. When the input pulse width is less than the RC time constant, the capacitor cannot charge or discharge to the threshold voltage, and the output does not respond. Monostable multivibrator: Utilizing the timing characteristics of a monostable multivibrator, the output is triggered only when the input pulse width exceeds a set time; Hardware timer: Precise delay filtering is achieved using an independent timer chip or logic gate circuit.

[0076] It should be noted that, in this embodiment, the selection of the specific threshold can be configured according to the signal characteristics in the actual application scenario. For example, during the charger insertion process, the good power signal may generate glitches lasting approximately 50 to 100 microseconds; during the PD protocol voltage switching process, jitter may occur lasting approximately 1 to 5 milliseconds. Therefore, the specific threshold can be set between 1 and 10 milliseconds, which can effectively filter the above-mentioned transient interference without affecting the transmission of the normal status indication signal (which typically lasts for hundreds of milliseconds or even several seconds).

[0077] For example, when a user plugs in the charger, the charging chip's Power Good signal may generate multiple microsecond-level low-level pulses before the voltage stabilizes. The delay circuit 106 (e.g., using an RC delay circuit with a time constant of 1 millisecond) receives this signal. Because the input pulse width (microseconds) is much smaller than the RC time constant, the output remains in its original state (low level), effectively filtering out these glitches. Only after the input signal stabilizes at a high level and lasts for more than 1 millisecond does the output of the delay circuit 106 become high, transmitting a valid Power Good signal to the controller 103. The controller 103 then controls the charging indicator light to illuminate smoothly without flickering.

[0078] It should be noted that the delay circuit 106 in this embodiment is functionally similar to the delay filtering unit 1031 inside the controller 103 in the aforementioned embodiment, but the implementation location is different. The delay circuit 106 is located outside the controller 103 as an independent hardware circuit. Its advantages are: it does not occupy the internal resources of the controller 103, it is convenient to debug and change the threshold parameters, and it can achieve the same filtering effect even when the controller 103 does not have a built-in delay function.

[0079] In some embodiments, the indicator component control system may simultaneously include a delay filtering unit 1031 inside the controller 103 and an external delay circuit 106 to form multi-level filtering and further improve anti-interference capability.

[0080] It is understood that in this embodiment of the application, the delay circuit 106 can effectively filter out the non-steady-state pulse signal in the first state indication signal, ensuring that the controller 103 only receives the real and stable state change signal, thereby avoiding the indication component 104 from generating unexpected display state jumps (such as false flashing, brief state jumps, etc.) due to non-steady-state pulses, thus improving the accuracy of the state indication and the user experience.

[0081] In some embodiments, the system includes a plurality of status indication ports 105, and the controller 103 is configured to determine a target indication component based on any one of the status indication ports 105, and control the display status of the target indication component.

[0082] It should be noted that the indicator component control system provided in this application embodiment includes multiple status indicator ports 105. These multiple status indicator ports 105 are multiple different status indicator signal sources in the electronic device, such as the power good pin of the charging chip, the status pin of the PD protocol chip, the reset indicator pin of the PMIC, the over-temperature interrupt pin of the temperature sensor, the activation signal pin of the flashing circuit, the power-on detection pin of the camera, etc.

[0083] It should be noted that, in this embodiment, the target indication component refers to an indicator light or indicator element corresponding to a specific status indication signal or a specific functional module. Different status indication ports 105 may correspond to the same or different indication components 104. For example, a charging status signal corresponds to a charging indicator light, a temperature alarm signal corresponds to an overheat alarm light strip, and a camera activation signal corresponds to a privacy indicator light.

[0084] In some embodiments, multiple status indication ports 105 can be connected to different functional modules to output different types of first status indication signals. For example: the first status indication port is connected to the power-good pin of the charging chip and outputs a power-good signal; the second status indication port is connected to the status pin of the PD protocol chip and outputs a PD negotiation status signal; the third status indication port is connected to the over-temperature interrupt pin of the temperature sensor and outputs an overheat alarm signal; the fourth status indication port is connected to the activation signal pin of the flashing circuit and outputs a firmware update status signal; and the fifth status indication port is connected to the hardware power-on detection terminal of the camera and outputs a camera activation signal. The controller 103 can determine the target indication component corresponding to the received different status indication signals and control the target indication component to present the corresponding display state. That is, different status indication signals can independently drive different indication components 104 to achieve parallel management of multiple status indications. For example: when receiving a good power signal from the charging chip, the controller 103 determines the target indicator component as a charging indicator light and controls it to remain constantly lit, indicating that charging is in progress; when receiving an over-temperature alarm signal from the temperature sensor, the controller 103 determines the target indicator component as an LED strip and controls it to flash yellow or orange, indicating that the device is overheating; when receiving an activation signal from the flashing circuit, the controller 103 determines the target indicator component as a status indicator light and controls it to indicate the firmware update process at a specific frequency (such as purple breathing flash); when receiving a hardware power-on signal from the camera, the controller 103 determines the target indicator component as a privacy indicator light and forcibly lights up a red LED to prompt the user that the camera has been activated.

[0085] In some embodiments, the controller 103 includes an OR gate, the plurality of input terminals of the OR gate are respectively connected to the plurality of status indication ports 105, and the output terminal of the OR gate is connected to the target indication component; the controller 103 is further configured to: control the display state of the target indication component according to the logic OR signal output by the OR gate.

[0086] It should be noted that an OR gate is a digital logic gate circuit. When at least one of its inputs is at a valid level (e.g., high), the output is valid; only when all inputs are invalid (e.g., low) is the output invalid. In this embodiment, the OR gate is used to implement a logical OR operation on multiple status indicator signals.

[0087] In some embodiments, multiple different status indication ports 105 may correspond to the same indication component 104. Specifically, when the system needs to share one indication component for multiple status indication signals (e.g., using an indicator light to indicate multiple abnormal states), an OR gate can be used to aggregate the multiple status indication signals. Each input of the OR gate is connected to a status indication port 105 and receives the corresponding first status indication signal. When any one or more status indication ports output a valid level (e.g., a high level, indicating the existence of a certain state that needs to be indicated), the output of the OR gate outputs a valid level, triggering the target indication component to display the corresponding state.

[0088] For example, multiple abnormal status indication signals, such as charging abnormality signals, temperature alarm signals, and system fault signals, are connected to multiple inputs of an OR gate, and the output of the OR gate is connected to a red fault indicator light. When any abnormal status occurs, the corresponding status indication port 105 outputs a high level, the OR gate outputs a high level, and the controller 103 controls the red fault indicator light to light up or flash, alerting the user to the device malfunction. When all abnormal statuses are eliminated and all inputs are at a low level, the OR gate outputs a low level, and the controller 103 controls the fault indicator light to turn off.

[0089] In implementations employing OR gates, controller 103 can further combine other signals (e.g., coded signals for abnormality types) to distinguish different sources of abnormality, thereby controlling the target indicator component to display different flashing patterns or colors, providing the user with richer status information. For example: when a charging abnormality occurs, controller 103 controls the red indicator light to flash slowly at a frequency of 1Hz; when a temperature over-limit occurs, controller 103 controls the red indicator light to flash quickly at a frequency of 4Hz; when a fatal system failure occurs, controller 103 controls the red indicator light to remain constantly lit.

[0090] It is understood that, in this embodiment of the application, the controller 103 can flexibly control the corresponding target indicator component according to the first status indicator signal output by multiple status indicator ports 105, so as to realize the parallel management or summary indication of multiple status indicators and meet the diverse needs of complex electronic devices for status indicators.

[0091] In some embodiments, the system includes a plurality of status indication ports 105, and the controller 103 is further configured to: upon receiving a first status indication signal output from at least two of the plurality of status indication ports 105, determine a target status indication port from the at least two status indication ports 105 according to a specific priority rule, and control the display state of the target indication component according to the first status indication signal output from the target status indication port.

[0092] It should be noted that the specific priority rule is a preset rule used to determine which state should be indicated first when multiple states occur simultaneously. This rule can be pre-configured based on factors such as the importance of the state, security level, and user attention. For example, overheat alarms have higher priority than charging indicators, and privacy protection has higher priority than system status indicators. The target status indicator port is the one selected from multiple status indicator ports according to the specific priority rule, and its output signal will be used to control the status displayed by the target indicator component. The target indicator component refers to the indicator light or indicator element corresponding to the target status indicator port, used to present the user with the current priority status information.

[0093] In this embodiment, multiple status indication ports 105 are connected to different functional modules, outputting different types of first status indication signals. In actual operation, two or more states may occur simultaneously. For example, while the device is charging, the CPU temperature suddenly exceeds the limit, triggering overheat protection; or the user plugs in a charger while the device is performing a firmware update. In these scenarios, the controller 103 will simultaneously receive valid signals output from multiple status indication ports 105. Since a single indicator component can typically only present one display state (e.g., one color, one flashing frequency) at a time, it cannot simultaneously and completely express multiple status information. Therefore, according to specific priority rules, the state that most requires user attention can be selected from multiple simultaneously occurring states for indication.

[0094] For example, during device charging, the CPU temperature gradually rises and eventually exceeds the limit, triggering overheat protection. At this time, the controller 103 simultaneously receives two primary status indication signals: one from the charging chip indicating good power (indicating charging is in progress), and the other from the temperature sensor indicating an overheat alarm (indicating the device is overheating). Based on a specific priority rule (overheat alarm priority is higher than charging indication), the controller 103 determines the status indication port corresponding to the temperature sensor as the target status indication port and controls the indicator component (such as an LED strip) to flash yellow or orange according to the overheat alarm signal, alerting the user to the overheating issue. Once the temperature returns to normal and the overheat alarm signal disappears, the controller 103 switches back to the charging indication state, keeping the charging indicator light constantly on. In this way, the user can be informed of the more urgent overheating situation first and take timely measures (such as stopping device use and waiting for it to cool down).

[0095] It is understood that in this embodiment of the application, when multiple states occur simultaneously, the controller 103 can intelligently select the priority state that the user needs to pay the most attention to for indication according to a specific priority rule, so as to avoid the display confusion of the target indication component due to multiple state conflicts, ensure that the user can obtain key state information in a timely manner, and improve the user experience.

[0096] In some embodiments, the indicator component control system provided in this application further includes: at least one level conversion circuit, wherein the input terminal of each level conversion circuit is connected to each of the status indication ports 105 in a one-to-one correspondence, and the output terminal of each level conversion circuit is connected to the isolation circuit 102 and the controller 103; each level conversion circuit is used to: perform level conversion processing on the corresponding first status indication signal.

[0097] It should be noted that, in this embodiment, the level conversion circuit is a circuit module used to convert the voltage level of the input signal to another voltage level. When the voltage domain of the first state indication signal output by the upstream module is inconsistent with the IO voltage domain of the controller 103, the level conversion circuit is used to achieve voltage matching between the two, ensuring that the signal can be correctly recognized by the controller 103.

[0098] It should be noted that in electronic devices, different functional modules may operate in different voltage domains. For example, a charging chip (Charger IC) may operate in a 5V or 3.3V voltage domain, and its status indicator pin outputs a 5V logic level power-good signal; a PD protocol chip may operate in a 3.3V voltage domain, and its status indicator signal is a 3.3V logic level; a temperature sensor may operate in a 1.8V voltage domain, and its over-temperature alarm signal is a 1.8V logic level; while the GPIO pins of the controller 103 (such as an EC or MCU) typically operate in a 3.3V or 1.8V voltage domain. If signals from different voltage domains are directly connected to the GPIO pins of the controller 103, voltage mismatch may occur, i.e., a high-voltage (e.g., 5V) signal is directly input to the controller's GPIO pins, which can only withstand 3.3V, potentially damaging the controller 103. To avoid this situation, this embodiment of the application provides a level conversion circuit between the status indicator port 105 and the isolation circuit 102 and the controller 103. The number of these level conversion circuits corresponds one-to-one with the number of status indication ports 105, with each status indication port 105 corresponding to one level conversion circuit. The level conversion circuit receives the first status indication signal from the input terminal, performs level conversion processing on it, and converts the signal level at the output terminal to a target level that matches the IO voltage domain of the controller 103.

[0099] In this embodiment, the output of the level conversion circuit is connected to both the isolation circuit 102 and the controller 103. The connection can be as follows: the output of the level conversion circuit is connected to a node on the signal transmission path, and this node is simultaneously connected to one end of the isolation circuit 102 and the signal input of the controller 103. With this connection, the first state indication signal after level conversion is transmitted to the controller 103 for state determination, and also to the isolation circuit 102 so that the processor 101 can obtain the signal through the isolation circuit 102 (when the processor is in the second state).

[0100] It should be noted that the level conversion circuit and the isolation circuit 102 can be independent circuit modules, or they can be integrated into the same chip or the same circuit structure. For example, some integrated level conversion chips already include isolation functions, in which case the level conversion circuit and the isolation circuit 102 can be combined.

[0101] It is understood that, in the embodiments of this application, the level conversion circuit can convert the first state indication signal of different voltage domains into a level that matches the IO voltage of the controller 103, ensuring that the controller 103 can correctly identify various first state indication signals, while protecting the controller 103 from overvoltage damage, thereby improving the system's compatibility and reliability.

[0102] In some embodiments, the level conversion circuit is constructed based on a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes a gate, a drain, and a source. The gate is the input terminal of the level conversion circuit, the drain is the output terminal of the level conversion circuit, and the source is the ground terminal.

[0103] It should be noted that a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a semiconductor device that uses an electric field effect to control current, including both NMOS and PMOS types. The gate is the control electrode of the MOSFET, controlling the conduction and cutoff between the source and drain by applying a voltage. In this embodiment, the gate serves as the input terminal of the level conversion circuit, receiving a first status indication signal from the status indication port 105. The drain is the output electrode of the MOSFET, from which current flows (for NMOS transistors). In this embodiment, the drain serves as the output terminal of the level conversion circuit, connected to the isolation circuit 102 and the controller 103, outputting a level-converted signal. The source is the reference electrode of the MOSFET, typically grounded. In this embodiment, the source serves as the ground terminal.

[0104] In this embodiment, the level conversion circuit utilizes the switching characteristics of an NMOS transistor to achieve level conversion. Specifically, when the first state indication signal output by the state indication port 105 is low (e.g., 0V), the gate voltage of the NMOS transistor is 0V, lower than its turn-on threshold voltage (Vth), and the NMOS transistor is in the off state. At this time, the drain output terminal is pulled up to a high level (e.g., 3.3V or 1.8V) through a pull-up resistor (which can be connected to the I / O power supply of the controller 103), and the controller 103 receives a high-level signal. When the first state indication signal output by the state indication port 105 is high (e.g., 5V, 3.3V, or 1.8V), this high level is applied to the gate of the NMOS transistor. If the gate voltage is higher than the turn-on threshold voltage (Vth) of the NMOS transistor, the NMOS transistor is in the on state, a low-impedance path is formed between the drain and source, the drain output terminal is pulled down to ground potential (0V), and the controller 103 receives a low-level signal. Through the above process, the level conversion circuit converts the level of the input signal: when the input is high, the output is low; when the input is low, the output is high. In other words, the level conversion circuit simultaneously performs level conversion and logic inversion functions.

[0105] It is understood that the embodiments of this application provide a simple and low-cost level conversion circuit implementation that can convert the first state indication signal of different voltage domains into the level of the IO voltage domain of the controller 103, ensuring that the controller 103 can correctly identify various state indication signals.

[0106] In some embodiments, the input terminal of each level conversion circuit is connected to the power supply of the corresponding status indication port 105 via a pull-up resistor, or grounded via a pull-down resistor; the output terminal of each level conversion circuit is connected to the power supply of the general-purpose input / output port of the controller 103 via a pull-up resistor, or grounded via a pull-down resistor.

[0107] It should be noted that the input terminal of the level conversion circuit (e.g., the gate of the MOSFET) is connected to the status indicator port 105. In actual circuits, the status indicator port 105 may output a high impedance state under certain conditions (e.g., the functional module is not powered on or is in a reset state). In this case, if there is no pull-up or pull-down resistor at the input terminal, the gate will be in a floating state, and its level will be uncertain, which may cause the MOSFET to mis-turn on or fail to turn on normally, affecting the reliability of the level conversion. Therefore, in this embodiment, a pull-up resistor or a pull-down resistor is configured at the input terminal. The specific selection depends on the output characteristics of the status indicator port 105 (e.g., open-drain output, push-pull output) and the required default level. A pull-up resistor is connected to the power supply of the status indicator port 105: when the status indicator port 105 outputs a high impedance state, the pull-up resistor pulls the input terminal high to the power supply voltage of the status indicator port (e.g., 5V, 3.3V, or 1.8V), making the input terminal default to a high level. This method is suitable for scenarios where the status indicator port is an open-drain output and requires an external pull-up, or scenarios where the default level requirement is a high level. Pull-down resistor grounding: When the status indicator port 105 outputs a high impedance state, the pull-down resistor pulls the input terminal low to ground (0V), making the input terminal default to a low level. This method is suitable for scenarios where the default level requirement is low, or scenarios where the status indicator port is a push-pull output and the default state is low.

[0108] It should be noted that the output of the level conversion circuit (e.g., the drain of the MOSFET) is connected to the isolation circuit 102 and the GPIO pin of the controller 103. When the MOSFET in the level conversion circuit is turned off, the output is in a high-impedance state (for an open-drain output structure). At this time, if there is no pull-up or pull-down resistor at the output, the output will float, and the GPIO pin of the controller 103 will receive an uncertain level, which may lead to the controller misjudging the state. Therefore, in this embodiment, a pull-up or pull-down resistor is configured at the output. The specific selection depends on the type of level conversion circuit (inverting or non-inverting) and the default level required by the controller 103. A pull-up resistor is connected to the power supply of the controller's GPIO port: when the MOSFET is turned off, the pull-up resistor pulls the output high to the IO power supply voltage of the controller 103 (e.g., 3.3V or 1.8V), making the output high by default. In this configuration, when the input is high, the NMOS transistor is turned on and the output is low; when the input is low, the NMOS transistor is turned off and the output is high, realizing level conversion and logic inversion. Using a pull-down resistor to ground: When the MOSFET is turned off, the pull-down resistor pulls the output terminal low to ground (0V), making the output terminal default to a low level. This method is suitable for scenarios where the output terminal needs to default to a low level.

[0109] It is understood that, in the embodiments of this application, by configuring pull-up resistors or pull-down resistors at the input and output terminals of the level conversion circuit, it can be ensured that the signal line has a definite level state when there is no drive or high impedance, preventing false triggering or logic uncertainty caused by signal floating, and improving the stability and reliability of the system.

[0110] In some embodiments, the output of the isolation circuit 102 is connected to the power supply of the general-purpose input / output port of the processor 101 via a pull-up resistor, or grounded via a pull-down resistor.

[0111] It should be noted that the output terminal of the isolation circuit 102 refers to the end where the isolation circuit 102 is connected to the GPIO pin of the processor 101. When the isolation circuit 102 is in an isolated state (e.g., the processor 101 is in the first state, and the isolation circuit disconnects the electrical connection between the two sides), this output terminal may be in a high-impedance state. If there is no pull-up or pull-down resistor at the output terminal, the GPIO pin of the processor 101 will be in a floating state, and the received level will be uncertain, which may lead to misreading of the state of the processor 101 or malfunction. In addition, during the process of the processor 101 switching from the first state to the second state (normal working state), if the output terminal is floating, transient uncertain levels may also be generated, affecting the stability of the system. To address this, this embodiment configures a pull-up resistor or a pull-down resistor at the output terminal of the isolation circuit 102 to provide a definite default level for the output terminal. When a pull-up resistor is used, one end of the pull-up resistor is connected to the output terminal of the isolation circuit 102, and the other end is connected to the IO power supply (e.g., 3.3V) of the GPIO pin of the processor 101. When the output of isolation circuit 102 is in a high-impedance state, the pull-up resistor pulls the output high to the processor GPIO power supply voltage, causing the GPIO pin of processor 101 to receive a defined high level. When a pull-down resistor is used, one end of the pull-down resistor is connected to the output of isolation circuit 102, and the other end is connected to ground (GND). When the output of isolation circuit 102 is in a high-impedance state, the pull-down resistor pulls the output low to 0V, causing the GPIO pin of processor 101 to receive a defined low level.

[0112] It is understood that in this embodiment of the application, the output of the isolation circuit 102 obtains a definite default level through a pull-up resistor or a pull-down resistor, ensuring that the GPIO pin of the processor 101 will not receive an uncertain level due to floating, thereby improving the stability and reliability of the system under different working states of the processor 101.

[0113] The following examples illustrate possible implementation schemes of the indicator component control system described in one or more of the above embodiments.

[0114] For example, Figure 5 This is the fifth schematic diagram of a control system for an indicator component provided in this application embodiment, as shown below. Figure 5As shown, the system includes: multiple status indication ports 501, a logic inverting circuit 502, an isolation circuit 503, a processor 504 (e.g., an ARM-based system-on-a-chip (SOC)), a controller 505 (e.g., an embedded controller EC or a low-power microcontroller unit (LPMCU)), and multiple indicator components 506. The logic inverting circuit 502 is a level shifting circuit constructed using NMOS transistors. Its inputs are connected to each status indication port 501, and its outputs are connected to the isolation circuit 503 and the controller 505. The logic inverting circuit 502 performs level shifting and logic inversion on the received status indication signals, converting signals from different voltage domains (e.g., 5V, 3.3V, 1.8V) to a level matching the I / O voltage of the controller 505 (e.g., 3.3V). Furthermore, the input of the logic inverting circuit 502 is connected to the I / O power supply of the corresponding status indication port 501 via a pull-up resistor, or grounded via a pull-down resistor. One end of the isolation circuit 503 is connected to the output of the logic inverting circuit 502, and the other end is connected to the processor 504. The isolation circuit 503 is implemented using an NMOS transistor. When the processor 504 is in the first state (e.g., power off, standby, or reset), the isolation circuit 503 can block the level interference of the processor 504 on the status indication signal transmission path, ensuring that the status indication signal can be reliably transmitted to the controller 505. The processor 504 is coupled to the status indication signal transmission path through the isolation circuit 503. The output of the isolation circuit 503 is connected to the I / O power supply of the processor 504 through a pull-up resistor or grounded through a pull-down resistor. When the processor 504 is in the second state (normal operating state), the processor 504 can communicate with the controller 505 through a bus (such as I2C) or GPIO, sending instruction information (i.e., the second status indication signal, such as charging behavior control instructions, battery level information, lighting effect instructions, etc.) to the controller 505. The input of the controller 505 is connected to the output of the logic inverter 502 to receive the status indication signal after level conversion; its communication interface is connected to the processor 504 to receive the instruction information sent by the processor 504. The controller 505 is also connected to multiple indicator components 506 for independently or collaboratively controlling the display status of each indicator component 506 based on the received status indication signals.

[0115] Understandably, when the GPIO pin of processor 504 is effectively short-circuited to ground, the isolation circuit 503 can block the electrical interference of the GPIO pin of processor 504 to the transmission path of the status indication signal, ensuring that controller 505 can reliably receive the status indication signal.

[0116] In this solution, non-steady-state pulse signals generated by power transients, hot-plugging, or protocol negotiation in the status indication signal can be filtered out in the following ways: Software delay filtering: The delay filtering unit inside the controller 505 filters out pulse signals in the status indication signal whose duration is less than a specific threshold. Hardware delay circuit: An independent delay circuit is set between the controller 505 and the status indicator port to filter out non-steady-state pulse signals.

[0117] It is understood that this application provides a universal, low-cost, low-power, and highly stable indicator component control system, which is suitable for various ARM platform electronic devices (such as tablets, laptops, mobile phones, etc.). It can effectively solve the problem of abnormal control of the indicator component caused by the equivalent short circuit to ground of GPIO pins in the processor's power-off, standby, and reset states, and improve the user experience.

[0118] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An indication component control system, the system comprising: processor; And the isolation circuit corresponding to the processor; The controller is used to control the display status of the indicator components; The isolation circuit is used to enable the controller to receive a status indication signal of the indicator component when the processor is in a first state, and to control the display state of the indicator component according to the status indication signal.

2. The indicator component control system according to claim 1, further comprising: At least one status indication port is provided for outputting a first status indication signal; The status indication port is coupled to one end of the controller to form a signal input path for the controller, and the status indication port is coupled to one end of the isolation circuit.

3. The indicator component control system according to claim 2, wherein when the processor is in the first state, the controller independently controls the display state of the indicator component according to the first state indication signal.

4. The indicator component control system according to claim 2, wherein when the processor is in the second state, the controller receives the first state indication signal and the second state indication signal sent by the processor, and controls the display state of the indicator component together according to the first state indication signal and the second state indication signal.

5. The indicator component control system according to claim 1 or 2, wherein the isolation circuit is used to block level interference generated by the processor to the signal input path of the controller when the processor is in the first state.

6. The indicator component control system according to claim 2, wherein the controller is further configured to: If a second status indication signal is not received from the processor for a certain period of time, and a communication anomaly is determined to be present with the processor, then the display status of the indication component is independently controlled according to the first status indication signal.

7. The indicator component control system according to any one of claims 2 to 6, wherein the controller includes a delay filtering unit for filtering pulse signals in the first state indication signal whose duration is less than a specific threshold, so as to suppress the indicator component from generating unexpected display state jumps due to non-steady-state pulse signals in the first state indication signal.

8. The indicator component control system according to any one of claims 2 to 6, wherein a delay circuit is connected between the controller and each of the status indicator ports, the delay circuit being used to filter pulse signals with a duration less than a specific threshold in the first status indicator signals output by each of the status indicator ports, so as to suppress the indicator component from generating unexpected display status jumps due to non-steady-state pulse signals in the first status indicator signals.

9. The indicator component control system according to any one of claims 2 to 6, the system comprising a plurality of status indicator ports, the controller being configured to determine a target indicator component based on any one of the status indicator ports, and to control the display status of the target indicator component.

10. The indicator component control system according to any one of claims 2 to 6, the system comprising a plurality of status indicator ports, the controller further being configured to: upon receiving a first status indicator signal output from at least two of the plurality of status indicator ports, determine a target status indicator port from the at least two status indicator ports according to a specific priority rule, and control the display state of the target indicator component according to the first status indicator signal output from the target status indicator port.

Images