Industrial software development layered collaborative operation training device and evaluation method

Abstract

This invention discloses a hierarchical collaborative operation training device and evaluation method for industrial software development. The method includes: an edge teaching processing module receiving operation tasks from a host computer and configuring an industrial control physical simulation environment; during debugging operations, the edge teaching processing module continuously acquires operation behavior data via a communication interaction module; the underlying real-time control module independently runs a hard real-time control loop; the communication interaction module implements priority tag-based transmission timing isolation for the control command data and operation behavior data generated by the hard real-time control loop; the edge teaching processing module extracts the register modification sequence and corresponding timing context of the operator on the underlying real-time control module during debugging from the operation behavior data, compares the register modification sequence with a pre-constructed standard error correction state machine path, generates a quantitative operation score and an operation behavior diagnostic report, and pushes them to the operation terminal and / or management terminal to overcome jitter problems.

Description

Technical Field

[0001] This invention relates to the field of industrial software development training technology, specifically to a hierarchical collaborative operation training device and evaluation method for industrial software development. Background Technology

[0002] In industrial software development training, the training platform must simultaneously meet the strict determinism of hard real-time control tasks and the comprehensive collectability of student operation process data.

[0003] However, existing platforms generally adopt a single-processor integrated architecture, deploying real-time control logic and tasks such as teaching management and data throughput within the same processing unit for time-sharing execution. This architectural coupling means that the numerous data requests triggered by frequent student operations during debugging (such as program downloading and breakpoint setting) directly compete for bus and interrupt resources with hard real-time tasks such as sensor acquisition and motor driving, causing unexpected jitter in the hard real-time control output. To avoid interfering with control determinism, the system is forced to limit or interrupt the acquisition of data during the debugging process, resulting in the inability to obtain key process behavior information such as student operation register sequences and troubleshooting steps.

[0004] Therefore, on a single-processor training platform, the determinism of hard real-time control and the full acquisition of operational behavior data constitute an irreconcilable technical contradiction, which severely restricts the depth and accuracy of training evaluation. Summary of the Invention

[0005] To overcome the shortcomings of existing technologies, this invention provides a hierarchical collaborative operation training device and evaluation method for industrial software development, in order to solve the problems in existing technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A hierarchical collaborative operation training evaluation method for industrial software development is applied to an operation training device. The operation training device includes a low-level real-time control module and an edge teaching processing module that are physically separated, as well as a communication interaction module connecting the two. The evaluation method includes: The edge teaching processing module receives operation tasks from the host computer, parses the sensor type, actuator type and control logic requirements contained in the operation tasks, generates hardware configuration instructions and sends them to the underlying real-time control module through the communication interaction module to configure the industrial control physical simulation environment. The operator performs a full-process training operation on the operating terminal, including code writing, compilation and download, online debugging and functional verification; During the debugging operation performed by the operator, the edge teaching processing module continuously acquires operation behavior data through the communication interaction module; at the same time, the underlying real-time control module independently runs a hard real-time control loop to maintain deterministic output of sensor data acquisition and actuator drive signals. The communication interaction module implements priority tag-based transmission timing isolation between the control command data and the operation behavior data generated by the hard real-time control loop, so that the transmission of the operation behavior data does not occupy the transmission time slot of the control command data, thereby achieving both the response determinism of the hard real-time control loop and the fullness of the operation behavior data acquisition. The edge teaching processing module extracts the register modification sequence and corresponding timing context of the underlying real-time control module by the operator during the debugging process from the operation behavior data, and compares the register modification sequence with the pre-built standard error correction state machine path, and generates a quantitative operation score and operation behavior diagnosis report based on the comparison result. The edge teaching processing module pushes the quantitative operation score and diagnostic report to the operation terminal and / or management terminal.

[0007] In one embodiment, priority tag-based transmission timing isolation includes: The communication interaction module maintains a high-priority instruction queue and a low-priority acquisition queue; When generating control command data frames, the underlying real-time control module adds a high-priority tag to the control command data frames; when requesting operation behavior data, the edge teaching processing module adds a low-priority tag to the data request frames. The communication interaction module has a built-in leaky bucket flow shaping scheduler. The leaky bucket flow shaping scheduler takes data frames from the high-priority instruction queue at a fixed rate and sends them. It only sends data frames from the low-priority acquisition queue during the time slice when the high-priority instruction queue is empty. When the leaky bucket traffic shaping scheduler detects that the interrupt load rate of the underlying real-time control module exceeds a preset threshold, the leaky bucket traffic shaping scheduler dynamically reduces the number of service tokens in the low-priority collection queue to actively suppress the uplink traffic of operation behavior data until the interrupt load rate falls back below the preset threshold.

[0008] In one embodiment, acquiring operational behavior data includes: The underlying real-time control module is equipped with a hardware breakpoint acquisition unit. The hardware breakpoint acquisition unit uses the on-chip debugging component of the underlying real-time control module to configure hardware breakpoints on the addresses of key peripheral registers that the operator's program may modify. When the processor of the underlying real-time control module executes a write operation instruction and accesses the register address of the configured hardware breakpoint, the on-chip debug component captures the instruction address, written data value and system clock count value of the write operation between the commit phase and write-back phase of the processor pipeline, generates a breakpoint trigger record, and writes the breakpoint trigger record into a dedicated trace buffer. The edge teaching processing module periodically reads the breakpoint trigger records accumulated in the dedicated tracking buffer through the low-priority acquisition channel of the communication interaction module.

[0009] In one embodiment, the extraction of the operator's register modification sequence to the underlying real-time control module and the corresponding timing context includes: The edge teaching processing module reads the breakpoint trigger record, sorts it according to the timestamp of the system clock count value, and reconstructs the instruction address sequence, write data sequence and operation time interval sequence of all write operation instructions executed by the operator on the key peripheral register during the debugging process; The instruction address sequence is used to restore the modified register, the write data sequence is used to restore the modified parameter value, and the operation time interval sequence represents the operator's debugging response speed and troubleshooting efficiency.

[0010] In one embodiment, the register modification sequence is compared with a pre-built standard error-correcting state machine path, and a quantified operation score is generated based on the comparison result, including: The edge teaching processing module pre-stores the optimal error correction state transition diagram for preset fault points in the operation task. The optimal error correction state transition diagram defines the standard register operation sequence from the fault trigger state to the fault recovery state, as well as the judgment condition for each state node. The edge teaching processing module maps the register modification sequence actually executed by the operator during the debugging process to the optimal error correction state transition graph, calculates the state transition edit distance between the actual path and the optimal path, and the number of redundant operation states contained in the actual path. The state transition edit distance and the number of redundant operation states are used as input parameters to input a weighted scoring function to generate the quantified operation score.

[0011] In one embodiment, the collaborative teaching device further includes a sensor and actuator module, which is electrically connected to the underlying real-time control module; Before configuring the industrial control physical simulation environment, the following is also included: The edge teaching processing module sends hardware link diagnostic commands to the underlying real-time control module. In response to the hardware link diagnostic command, the underlying real-time control module outputs a subthreshold excitation current pulse to the target sensor interface in the sensor and actuator module. The amplitude of the subthreshold excitation current pulse is lower than the minimum driving threshold that triggers the actuator action corresponding to the target sensor. The underlying real-time control module synchronously acquires the voltage response signal of the target sensor interface and transmits the voltage response signal back to the edge teaching processing module; The edge teaching processing module compares the measured impedance value of the voltage response signal with the pre-stored normal wiring impedance range. If the measured impedance value exceeds the normal wiring impedance range, it is determined that there is a hardware connection fault in the target sensor interface. When generating the quantitative operation score, the weight of the evaluation scoring item associated with the target sensor interface is set to zero, and a hardware maintenance alarm is pushed to the management terminal.

[0012] In one embodiment, the edge teaching processing module adopts a containerized virtual teaching instance architecture at runtime, and the method further includes: The edge teaching processing module creates and manages multiple isolated container instances, each container instance corresponding to an independent training station; Each container instance is allocated a dedicated or limited processor core time slice, memory bandwidth limit, and input / output queue weight, so that the steps executed by different operators can be executed concurrently in their respective container instances without interference.

[0013] In one embodiment, it further includes: When the underlying real-time control module detects an interruption in the communication link with the edge teaching processing module, the underlying real-time control module will cyclically write the newly collected operation behavior data into the circular buffer in the local non-volatile memory in a preset format, and maintain the bitmap of the written frame sequence number. Once the communication link is re-established, the edge teaching processing module sends a resume request to the underlying real-time control module. The resume request includes the sequence number of the last frame successfully received by the edge teaching processing module. The underlying real-time control module compares the sequence number of the last successfully received frame with the locally written frame sequence number bitmap, and only reads data frames within the missing sequence number range from the circular buffer and retransmits them to the edge teaching processing module. After the retransmission is completed, the edge teaching processing module merges the data from the offline period with the data from the online period into the global dataset.

[0014] An industrial software development hierarchical collaborative operation training device, used to execute an industrial software development hierarchical collaborative operation training evaluation method as described in any one of the preceding claims, comprising: The underlying real-time control module has a built-in hardware breakpoint acquisition unit and a ring buffer unit. The edge teaching processing module is physically separated from the underlying real-time control module and is equipped with a state machine path comparison and evaluation unit. The communication interaction module is communicatively connected to both the underlying real-time control module and the edge teaching processing module. The host computer teaching management terminal is communicatively connected to the edge teaching processing module.

[0015] Compared with existing technologies, the beneficial effects of this invention are as follows: First, by separating the underlying real-time control module and the edge teaching processing module in physical hardware, this invention eliminates the resource competition between the hard real-time control task and the teaching data processing task for the same processing unit at the system architecture level, thus overcoming the control jitter problem caused by the coupling of the two types of tasks in traditional single-processor training platforms.

[0016] Secondly, based on the physical layered architecture, this invention implements priority tag-based transmission timing isolation between control command data and training behavior data through a communication interaction module. This ensures that the acquisition and transmission of behavior data only occupy the idle time slots of control command transmission, thereby ensuring that the acquisition of behavior data is no longer interrupted or limited due to the need to avoid interference with control while maintaining the deterministic response of hard real-time control. This solves the long-standing technical contradiction between the deterministic nature of hard real-time control and the full acquisition of behavior data.

[0017] Based on the comprehensive behavioral data guaranteed by the aforementioned architecture and transmission method, the edge teaching processing module can extract the sequence of modifications made to the underlying registers by students during debugging and the corresponding timing context, and compare them with the pre-built standard error correction state machine path. This process evaluation method deepens the evaluation from the traditional platform's "right or wrong result" assessment to a logical quantitative analysis of the efficiency of the debugging path and the merits of the troubleshooting strategy, thereby significantly improving the depth of training evaluation and the accuracy of diagnosis, and realizing a leap from static result assessment to dynamic process evaluation. Attached Figure Description

[0018] Figure 1 A flowchart illustrating a hierarchical collaborative operation training and evaluation method for industrial software development provided by this invention; Figure 2 A schematic diagram of the framework flow of a hierarchical collaborative operation training and evaluation method for industrial software development provided by the present invention; Figure 3This invention provides an overall structural block diagram of a hierarchical collaborative operation training device for industrial software development training. Figure 4 A schematic diagram illustrating the interaction between the underlying real-time control module and the edge teaching processing module of the device of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Industrial software development training needs to simultaneously satisfy the control determinism of hard real-time physical scenarios and the full evaluability of student operation processes. However, existing training platforms generally suffer from the following technical deficiencies in terms of design architecture, process evaluation, and fault handling: Existing training platforms mostly adopt a single-processor integrated architecture, deploying industrial control logic and teaching management logic on the same processor for time-sharing execution. During training, operators (such as students) frequently perform debugging operations such as program downloading, breakpoint setting, and memory monitoring, triggering a large number of background data throughput requests. These requests compete with underlying hard real-time tasks such as motor control and sensor acquisition for processor bus resources and interrupt response channels. The consequences are: unexpected jitter in hard real-time control tasks, distorted PWM output waveforms, and sensor sampling window drift, causing the physical phenomena observed by the operator to be inconsistent with the logical expectations of the written code, making it impossible to establish a correct understanding of the causal relationships in software development.

[0021] Due to the aforementioned architectural limitations, current practical training evaluations heavily rely on manual teacher inspections, manual recording, or static comparisons based solely on the final program output. Key process behaviors such as operator debugging paths, register operation sequences, and troubleshooting strategies are not systematically collected and retained. Some solutions using online judges (OJs) can only determine whether the output matches expectations, failing to assess the code's internal structure or evaluate the operator's mastery of low-level hardware operations. This leaves teaching evaluation at the level of correct or incorrect results, severely disconnected from the core competency indicators required by industrial software engineering practice, such as process standardization, clear structure, and efficient troubleshooting.

[0022] The one-sidedness of the evaluation system further leads to the lack of troubleshooting guidance. When complex problems such as hardware-level communication failures, timing conflicts, or incorrect interrupt priority configuration occur in the operator's code, the existing system can only echo the compiler's standard error codes and cannot provide guidance for troubleshooting based on the causal relationship between software and hardware. When faced with faults such as serial port data loss or abnormal motor noise, operators lack the ability to establish logical connections between the phenomena and low-level operations such as interrupt priority settings, DMA buffer size configuration, and PID parameter tuning, thus limiting the effectiveness of practical training.

[0023] Furthermore, existing training equipment lacks the ability to diagnose its own hardware health status in real time. When sensors experience zero-point drift, actuator wiring becomes loose, or interface impedance is abnormal, even if the operator has written the correct code, they cannot achieve the expected physical effect. However, the evaluation system still determines that the operator has not completed the function and deducts the corresponding points. This evaluation distortion caused by equipment hardware failure seriously affects the fairness and accuracy of teaching evaluation.

[0024] This invention discloses a layered collaborative operation training device for industrial software development. The whole machine adopts a hardware architecture with two-layer functional separation, which highly restores the real development logic of "low-level real-time control and edge computing" in industrial sites, and solves the core problem of mutual interference between teaching management tasks and hard real-time control tasks in traditional single-processor training platforms.

[0025] like Figure 1 As shown, the device includes a low-level real-time control module, an edge teaching processing module, a communication interaction module, a sensor and actuator module, and a host computer teaching management terminal; among which, The underlying real-time control module can use a 32-bit microcontroller based on the ARM Cortex-M7 core (such as the STM32H743), with a main frequency of no less than 400MHz, equipped with a memory protection unit (MPU) and dual Flash partitions. This module has a dedicated hard real-time task domain, focusing on sensor data acquisition, actuator drive control, and bidirectional data interaction with the edge teaching processing module in industrial training scenarios. It integrates a hardware breakpoint acquisition unit, utilizing the on-chip CoreSight debugging architecture's DWT (Data Watchpoint and Track) unit, which can configure up to 8 hardware breakpoints for key peripheral register addresses modified by the operator's program; it also has a built-in ring buffer unit, allocating a dedicated storage area in the on-chip Flash for offline caching of operational behavior data during communication interruptions.

[0026] The edge teaching processing module can utilize a multi-core ARM Cortex-A55 big.LITTLE architecture embedded high-performance application processor (such as the Rockchip RK3588) and run an embedded Linux system with the PREEMPT_RT real-time kernel patch. This module exclusively occupies the soft real-time teaching task domain, running a containerized virtual teaching instance architecture. It creates an independent Docker container instance for each training workstation and uses Cgroups control group mechanisms to bind independent CPU cores and limit memory bandwidth, achieving strict resource isolation between workstations. Internally, it includes a state machine path comparison and evaluation unit, used to extract operational behavior features from register modification sequences and perform graph theory comparisons with standard paths to generate quantitative scores.

[0027] The communication interaction module connects the underlying real-time control module and the edge teaching processing module, and its physical interface supports both RS-485 differential serial bus and 100M industrial Ethernet. Internally, this module is equipped with a high-priority command queue, a low-priority acquisition queue, and a leaky bucket traffic shaping scheduler. It implements priority-label-based transmission timing isolation between hard real-time control command data and operational behavior data, ensuring absolute priority transmission of control commands and adaptive suppression of behavioral data traffic.

[0028] The sensor and actuator module includes various devices commonly found in industrial environments, such as temperature sensors and photoelectric switches, as well as actuators like stepper motors and relays. It features a modular and detachable structure, and allows for flexible combination of various industrial components, including temperature sensors, photoelectric switches, Hall encoders, stepper motor drivers, and relay modules, to build realistic industrial control environments. This module can receive subthreshold excitation current pulses and has the capability to acquire and transmit voltage response signals, enabling non-destructive self-diagnosis of the hardware link before practical training.

[0029] The host computer teaching management terminal can be a regular desktop computer or a portable laptop, allowing teachers to complete tasks such as editing and distributing operational tasks (e.g., practical training tasks), tracking all practical training process data, conducting statistical analysis of class learning, and exporting individual diagnostic reports for operators (e.g., students), thereby achieving overall management of the entire practical training teaching process.

[0030] like Figures 1 to 4 As shown, this invention provides a hierarchical collaborative operation training and evaluation method for industrial software development, applied to an operation training device. The operation training device includes a low-level real-time control module and an edge teaching processing module separately configured on physical hardware, as well as a communication interaction module connecting the two. The evaluation method includes: The S100 edge teaching processing module receives operation tasks from the host computer, parses the sensor type, actuator type and control logic requirements contained in the operation tasks, generates hardware configuration instructions and sends them to the underlying real-time control module through the communication interaction module to configure the industrial control physical simulation environment. Specifically, teachers, based on the course progress and the students' learning situation, edit and distribute targeted industrial software development operation tasks through a host computer teaching management terminal. These tasks cover a variety of types, including basic code writing, industrial equipment linkage control, and troubleshooting.

[0031] In one embodiment, after the edge teaching processing module receives the operation task issued by the host computer, before configuring the industrial control physical simulation environment, it further includes: The edge teaching processing module sends hardware link diagnostic commands to the underlying real-time control module. In response to hardware link diagnostic commands, the underlying real-time control module outputs a subthreshold excitation current pulse to the target sensor interface in the sensor and actuator module. The amplitude of the subthreshold excitation current pulse is lower than the minimum drive threshold required to trigger the actuator corresponding to the target sensor. Specifically, in response to diagnostic commands, the underlying real-time control module controls its analog-to-digital converter to output a subthreshold excitation current pulse to the target sensor interface in the sensor and actuator module. The amplitude of the subthreshold excitation current pulse is strictly controlled to be lower than the minimum drive threshold required to trigger the corresponding actuator (such as a relay coil or a stepper motor driver chip enable pin), such as 2-3mA.

[0032] The underlying real-time control module synchronously acquires the voltage response signal of the target sensor interface and sends the voltage response signal back to the edge teaching processing module. Specifically, the underlying real-time control module synchronously starts the analog-to-digital converter, acquires the voltage response signal of the target sensor interface, calculates the measured impedance value through Ohm's law, encapsulates the measured impedance value into a response message, and sends it back to the edge teaching processing module.

[0033] The edge teaching processing module compares the measured impedance value of the voltage response signal with the pre-stored normal wiring impedance range; If the measured impedance value is within the normal range, the hardware link is determined to be normal, and the process proceeds to step S100. If the measured impedance value exceeds the normal wiring impedance range, it is determined that there is a hardware connection fault in the target sensor interface. When generating the quantitative operation score, a mapping relationship between the faulty equipment identifier and the evaluation scoring item is established. The weight of the evaluation scoring item associated with the target sensor interface is set to zero, and a hardware maintenance alarm containing the faulty interface number, measured impedance value, and predicted fault type is pushed to the management terminal to eliminate the evaluation distortion caused by the physical fault of the equipment from the source.

[0034] In this embodiment, subthreshold excitation current injection and impedance spectroscopy analysis achieve non-destructive hardware link diagnosis, and the diagnostic results are linked to the dynamic zeroing of evaluation weights. The evaluation system has hardware fault detection and adaptive anti-interference capabilities, ensuring that score deductions are only due to operator incompetence rather than physical equipment failures, significantly improving the reliability and fairness of teaching evaluation.

[0035] After the hardware link diagnostics are successful, the edge teaching processing module automatically completes the following parsing and configuration tasks: The analysis task includes the sensor types, actuator types, and control logic requirements. Retrieve the corresponding hardware interface mapping table from the local task configuration library; The hardware configuration command is generated and sent to the underlying real-time control module through the communication interaction module. The underlying real-time control module executes instructions to complete the configuration of IO pin functions, setting of communication baud rate, initialization of PWM timer and setting of sensor sampling period, thus completing the one-click initialization of the industrial control physical scene.

[0036] In this embodiment, the edge teaching processing module automatically parses the task semantics and generates hardware configuration instructions for distribution, realizing one-click initialization of the training scenario, significantly improving task switching efficiency and reducing teachers' administrative workload.

[0037] S200: The operator performs a full-process training operation on the operating terminal, including code writing, compilation and download, online debugging and functional verification. Specifically, the operator independently conducts practical training on a dedicated operating terminal, completing the entire process of code writing, program compilation and download, online debugging, function verification, and fault repair in sequence. The entire process is completed autonomously without the need for on-site guidance from a teacher.

[0038] S300: During the operator's debugging operation, the edge teaching processing module continuously acquires operation behavior data through the communication interaction module; at the same time, the underlying real-time control module independently runs a hard real-time control loop to maintain the deterministic output of sensor data acquisition and actuator drive signals. Among them, the communication interaction module implements priority tag-based transmission timing isolation for the control command data and operation behavior data generated by the hard real-time control loop, so that the transmission of operation behavior data does not occupy the transmission time slot of control command data, thereby achieving both the response determinism of the hard real-time control loop and the fullness of operation behavior data acquisition. Specifically, during the debugging process performed by the operator, the following two behaviors with different real-time requirements occur simultaneously: On one hand, the underlying real-time control module independently runs a hard real-time control loop, reading sensor data at a defined sampling period and updating actuator drive signals at a defined PWM period to maintain the normal operation of the industrial control physical scenario. This loop runs in a bare-metal or lightweight real-time operating system environment and does not participate in any instructional logic processing.

[0039] On the other hand, the edge teaching processing module continuously acquires the operator's operation behavior data through the communication interaction module, including but not limited to program download records, debugging logs, parameter modification operations, and troubleshooting steps.

[0040] To address the issue of unexpected jitter in control commands caused by frequent operator debugging operations and hard real-time control tasks competing for bus resources in traditional single-processor architectures, the communication module implements priority-label-based transmission timing isolation for the two types of data. Specifically, this includes: S310, the communication interaction module maintains a high-priority instruction queue and a low-priority acquisition queue; The communication module internally maintains two logical transmission queues: The high-priority instruction queue is dedicated to carrying control instruction data frames generated by the underlying real-time control module. The low-priority acquisition queue is dedicated to carrying operation behavior data frames requested by the edge teaching processing module.

[0041] When generating control command data frames, the S320 and the underlying real-time control module attach high-priority tags to the control command data frames; when requesting operation behavior data, the edge teaching processing module attaches low-priority tags to the data request frames. Specifically, when the underlying real-time control module generates control command data frames, it writes a high-priority tag in the frame header field of the data frame; when the edge teaching processing module initiates an operation behavior data request, it writes a low-priority tag in the frame header field of the request frame.

[0042] The S330 communication interaction module has a built-in leaky bucket flow shaping scheduler. The leaky bucket flow shaping scheduler takes data frames from the high-priority instruction queue at a fixed rate and sends them. It only sends data frames from the low-priority acquisition queue during the time slice when the high-priority instruction queue is empty. S340. When the leaky bucket traffic shaping scheduler detects that the interrupt load rate of the underlying real-time control module exceeds a preset threshold, the scheduler dynamically reduces the number of service tokens in the low-priority acquisition queue to actively suppress the uplink traffic of operational behavior data until the interrupt load rate falls back below the preset threshold. When the load rate returns to normal, the scheduler gradually restores the number of service tokens in the low-priority acquisition queue.

[0043] Specifically, the communication interaction module has a built-in leaky bucket traffic shaping scheduler, whose scheduling logic is as follows: Data frames are retrieved from the high-priority instruction queue and sent with priority at a fixed transmission clock cycle; Data frames are only retrieved from the low-priority acquisition queue and sent during time slices when the high-priority instruction queue is empty; The interrupt load rate of the underlying real-time control module is monitored in real time. When the interrupt load rate exceeds a preset threshold (e.g., 70%), the leaky bucket scheduler dynamically reduces the number of service tokens allocated to low-priority collection queues to actively suppress the uplink traffic of operational behavior data. When the interruption load rate falls below the preset threshold, the leaky bucket scheduler gradually restores the number of service tokens for the low-priority collection queues and restores normal data throughput.

[0044] In this embodiment, a dual-priority queue architecture and a leaky bucket traffic shaping scheduler are introduced. Combined with real-time interrupt load rate monitoring and dynamic service token adjustment, absolute priority transmission of control command data and adaptive suppression of behavioral data traffic are achieved. Even under the most intensive operator debugging operations, the end-to-end transmission latency of hard real-time control commands is always controlled within a certain range, and no perceptible jitter occurs in the physical scene response; at the same time, behavioral data obtains maximum throughput bandwidth during link idle periods, realizing deterministic multiplexing of the link.

[0045] Through the aforementioned timing isolation, the transmission of operational behavior data does not occupy the transmission time slots of control command data, while simultaneously achieving deterministic response of the hard real-time control loop and comprehensive acquisition of operational behavior data. Even under the most intensive operator debugging operations, the end-to-end transmission delay of hard real-time control commands is always kept within a defined range, and no perceptible jitter occurs in the physical scene response.

[0046] In one embodiment, this method uses a non-intrusive hardware breakpoint acquisition method to obtain operational behavior data, specifically including: The S350 is equipped with a hardware breakpoint acquisition unit within the underlying real-time control module. The hardware breakpoint acquisition unit uses the on-chip debugging component of the underlying real-time control module to configure hardware breakpoints on the addresses of key peripheral registers that the operator's program may modify. S360. When the processor of the underlying real-time control module executes a write operation instruction and accesses the register address of the configured hardware breakpoint, the on-chip debug component captures the instruction address, written data value and system clock count value of the write operation between the commit phase and write-back phase of the processor pipeline, generates a breakpoint trigger record, and writes the breakpoint trigger record to a dedicated trace buffer. The S370 edge teaching processing module periodically reads the breakpoint trigger records accumulated in the dedicated tracking buffer through the low-priority acquisition channel of the communication interaction module.

[0047] Specifically, a hardware breakpoint acquisition unit is configured within the underlying real-time control module. This unit utilizes the on-chip integrated debugging and tracing components of the underlying real-time control module (such as the DWT unit in the ARM CoreSight debugging architecture). The specific configuration and capture process is as follows: Based on the type of operation task, the edge teaching processing module sends a list of key peripheral register addresses that need to be monitored to the underlying real-time control module, such as the PWM duty cycle comparison register (TIMx->CCRx), the ADC conversion result register (ADCx->DR), and the serial port baud rate configuration register. The hardware breakpoint acquisition unit uses the hardware comparator of the on-chip debug component to configure a hardware breakpoint for each register address in the list. When the processor of the underlying real-time control module executes a write operation instruction and accesses the register address of the configured hardware breakpoint, the on-chip debug component captures the following information between the commit and write-back phases of the processor pipeline, before the instruction execution effect is visible to the external bus: The program counter value of the write operation instruction, i.e., the instruction address; The data value written to the register; The current system clock cycle count is used as a timestamp; The on-chip debugging component packages the above three pieces of information into a breakpoint trigger record and writes it into a dedicated trace buffer inside the chip. This process is completed entirely by the hardware path, without occupying the main processor's execution cycle, and has zero latency impact on the actual runtime sequence of the program being debugged.

[0048] The edge teaching processing module reads the breakpoint trigger records accumulated in the dedicated tracking buffer in a periodic polling manner through the low-priority acquisition channel of the communication interaction module.

[0049] In this embodiment, the built-in debugging component of the chip captures register write operations via a hardware path between the commit and write-back stages of the processor pipeline, and writes them to a dedicated trace buffer without occupying the main processor's execution cycle. This achieves non-intrusive acquisition: the acquisition process has zero latency impact on the processor pipeline, does not change the actual runtime sequence of the operator's code, and can capture all register modification behaviors (including unexpected abnormal write operations).

[0050] This invention implements priority-label-based timing isolation between hard real-time control command data and operational behavior data through a communication interaction module. The deterministic response of the hard real-time control loop is guaranteed, and the physical phenomena observed by the operator strictly correspond to their code logic; simultaneously, all teaching behavior data is collected and not lost due to communication congestion.

[0051] The S400 edge teaching processing module extracts the register modification sequence and corresponding timing context of the underlying real-time control module by the operator during the debugging process from the operation behavior data, and compares the register modification sequence with the pre-built standard error correction state machine path. Based on the comparison results, it generates a quantitative operation score and operation behavior diagnosis report. The edge teaching processing module reads the breakpoint trigger record set obtained from the underlying real-time control module, sorts it in ascending order according to the timestamp of the system clock count value, and reconstructs multi-dimensional structured sequence data: the instruction address sequence is used to restore which registers the operator modified during debugging; the written data sequence is used to restore the specific parameter values ​​written by the operator to each register; and the operation time interval sequence is used to characterize the operator's reaction speed and troubleshooting efficiency to a certain fault. Specifically, this includes: The S410 edge teaching processing module reads the breakpoint trigger record, sorts it according to the timestamp of the system clock count value, and reconstructs the instruction address sequence, write data sequence and operation time interval sequence of all write operation instructions executed by the operator on the key peripheral registers during the debugging process. The instruction address sequence is used to restore the modified registers, the write data sequence is used to restore the modified parameter values, and the operation time interval sequence represents the operator's debugging response speed and troubleshooting efficiency.

[0052] Specifically, the edge learning processing module reads the breakpoint trigger record set obtained from the underlying real-time control module, sorts it in ascending order according to the timestamp of the system clock count value, and reconstructs multi-dimensional structured sequence data: Instruction address sequence: The program counter values ​​of each write operation instruction arranged in chronological order, used to reconstruct which registers were modified by the operator during debugging. By reverse-engineering the debug symbol table using the instruction addresses, the register names can be further deduced.

[0053] Write data sequence: The data values ​​written to the registers that correspond one-to-one with the instruction address sequence. This is used to restore the specific parameter values ​​written by the operator to each register, such as changing the PWM duty cycle from 0x3FF to 0x2AA.

[0054] Operation time interval sequence: The time difference between two adjacent register write operations, used to characterize the operator's reaction speed and troubleshooting efficiency to a certain fault. The shorter and more uniform the time interval, the faster and more decisive the operator is in locating the fault.

[0055] In this embodiment, after sorting by timestamp, three dimensions—instruction address, written data, and time interval—are extracted from the original records to construct structured sequence data. This elevates the underlying hardware tracking data into a structured feature vector that can be directly consumed by the evaluation algorithm, thus establishing a data processing link from hardware acquisition to intelligent evaluation.

[0056] Subsequently, the edge teaching processing module compares the extracted register modification sequence with the pre-built standard error correction state machine path to generate a quantitative operation score. The specific process is as follows: S420 and the edge teaching processing module pre-store the optimal error correction state transition diagram for the fault injection point corresponding to the operation task. The optimal error correction state transition diagram defines the standard register operation sequence from the fault trigger state to the fault recovery state, as well as the judgment condition for each state node. Specifically, the edge learning processing module pre-stores the optimal error correction state transition diagram corresponding to the current operation task. This state transition diagram is pre-constructed by the teacher or system designer and defined in the form of a directed graph: Status nodes: Represent key stages in the troubleshooting process, such as: fault triggering status, fault detection status, preliminary troubleshooting status, parameter adjustment status, function verification status, fault recovery status, etc. Transition edge: Represents the standard register operation sequence required to transition from one state to another, and the decision condition on that transition edge (e.g., reading the ADC value and determining whether it is within the normal range).

[0057] The S430 edge teaching processing module maps the register modification sequence actually executed by the operator during debugging to the optimal error correction state transition diagram according to the combination characteristics of operation address and data value. It calculates the state transition edit distance between the actual path and the optimal path (i.e., how many insertion, deletion, and replacement operations are required for the actual state transition sequence to be transformed into the optimal state transition sequence), as well as the number of redundant operation states contained in the actual path (i.e., the number of invalid state nodes that the operator enters and exits during the troubleshooting process and that do not lead to fault recovery). S440. Using the state transition edit distance and the number of redundant operation states as two input parameters, input them into a weighted scoring function to generate a quantitative operation score. This score not only reflects the correctness or incorrectness of the function implementation, but also deeply evaluates the efficiency of the operator's debugging path, the quality of the troubleshooting strategy, and the clarity of the operation logic, possessing interpretability at the graph theory algorithm level; For example: in, To quantify the performance evaluation, the operator's final score is usually mapped to a standard range of 0-100 points.

[0058] The state transition edit distance is the minimum number of edit operations (including insertion, deletion, and replacement of state nodes) required to convert the actual state transition path operated by the operator during troubleshooting into a standard error correction path. The larger the value, the further the operator's troubleshooting path deviates from the optimal path.

[0059] This is a preset normalization threshold constant for the maximum allowed editing distance. It is used to make GED dimensionless, preventing a single metric from dominating the score due to extremely long paths.

[0060] This represents the number of redundant operational states. During troubleshooting, this is the number of invalid state nodes that the operator enters but subsequently exits without contributing to the final fault recovery. This value reflects the degree of confusion in the operator's troubleshooting logic and the cost of trial and error.

[0061] The maximum allowed redundancy is a preset normalization threshold constant, which is used to normalize the number of redundant operations.

[0062] , representing the path deviation weight, is the percentage of "accuracy of obstacle removal strategy" among all evaluation dimensions.

[0063] and The weight for redundant operations represents the percentage of "clarity and simplicity of troubleshooting logic" among all evaluation dimensions.

[0064] In this embodiment, by constructing an optimal error-correcting state transition graph, the operator's actual operation sequence is mapped to the state machine space. The state transition edit distance and the number of redundant states are calculated and substituted into a weighted scoring function. The evaluation model possesses graph theory algorithm depth and interpretability: it not only provides a score but also specifically points out the detours the operator took on the troubleshooting path, providing data support for targeted teaching guidance.

[0065] After the scoring is calculated, a comprehensive weighted average is applied based on traditional dimensions such as code standardization and functional completion to generate a detailed operational behavior diagnostic report. This report identifies the operator's weaknesses, points out detours and redundant steps in the troubleshooting process, and provides targeted improvement suggestions. For example: Code Standardization (20%): Evaluate the completeness of code comments, naming conventions, and structural clarity; Functionality Completion (30%): Evaluate the percentage and correctness of the implemented functionalities of the task; Debugging efficiency (15%): Evaluate the number of debugging attempts, debugging duration, and problem resolution speed; Fault handling capability (20%): Assess the accuracy of fault identification, clarity of troubleshooting logic, and repair effectiveness; Operational compliance (15%): Assess the standardization of tool use, awareness of safe operation, and degree of adherence to procedures.

[0066] This invention extracts the register modification sequence and timing context, performs graph theory comparison with the standard error-correcting state machine path, and calculates the state transition edit distance. The evaluation dimensions are expanded from the depth of the result's correctness or error to the quality of the process, achieving a quantitative and accurate assessment of the operator's debugging behavior and troubleshooting efficiency. The evaluation results are interpretable.

[0067] The S500 edge teaching processing module pushes quantitative operation scores and diagnostic reports to the operation terminal and / or management terminal.

[0068] Specifically, the edge learning processing module synchronously pushes quantitative operation scores and diagnostic reports to operating terminals (such as student terminals) and / or management terminals (such as teacher terminals). Operating terminals can instantly view scores, error messages, and guided improvement suggestions; management terminals can view the learning statistics of all operators in the class, the distribution of common weaknesses, and individualized diagnostic reports.

[0069] Meanwhile, the edge learning processing module monitors the operator's training progress and knowledge mastery in real time, and automatically pushes progressively challenging tasks based on the quantitative scoring results: Those with lower scores (e.g., scores of 0-60) will be automatically assigned basic reinforcement tasks to strengthen their basic skills training; Those with average scores (e.g., 60-80 points) will be given standard advanced tasks to improve their overall application skills; Those who score higher (e.g., 80 points or above) will be given challenging extension tasks to cultivate their innovative problem-solving abilities.

[0070] When a code error, logic anomaly, or communication failure is detected, the device matches the error type based on a preset error pattern knowledge base and combines it with the operator's current node position in the state transition diagram to output a guiding prompt pointing to the correct direction for troubleshooting, rather than directly giving the final answer, thus fundamentally cultivating the operator's ability to troubleshoot independently.

[0071] In this embodiment, scores and diagnostic reports are calculated locally and in real time at the edge and pushed out immediately. This enables real-time evaluation feedback, allowing operators to adjust their learning strategies in real time during training and improving the efficiency of practical teaching.

[0072] In one embodiment, it further includes: When the underlying real-time control module detects an interruption in the communication link with the edge teaching processing module, the underlying real-time control module will cyclically write the newly collected operation behavior data into the circular buffer in the local non-volatile memory in a preset format, and maintain the bitmap of the written frame sequence number. Once the communication link is re-established, the edge teaching processing module sends a resume request to the underlying real-time control module. The resume request contains the sequence number of the last frame successfully received by the edge teaching processing module. The underlying real-time control module compares the sequence number of the last successfully received frame with the locally written frame sequence number bitmap, and only reads the data frames within the missing sequence number range from the circular buffer and retransmits them to the edge teaching processing module. After the retransmission is completed, the edge teaching processing module merges the data from the offline period with the data from the online period into the global dataset, and then continues to execute the subsequent evaluation process to ensure the integrity and continuity of the operational behavior data throughout the entire process.

[0073] Specifically, when the communication link between the underlying real-time control module and the edge teaching processing module is unexpectedly interrupted due to physical factors (such as loose network cables or excessive electromagnetic interference), the following process is executed: When the physical layer chip of the underlying real-time control module detects that the link status register has changed to Link Down, it triggers an interrupt to notify the main control logic. The main control logic then writes the subsequently acquired operation data in a preset format (such as frame number + timestamp + data payload) cyclically into a circular buffer in local non-volatile memory (such as on-chip Flash). Simultaneously, it maintains a bitmap of the written frame numbers to efficiently record which frame number positions in the circular buffer are occupied by valid data.

[0074] Once the physical layer of the link is re-established, the edge teaching processing module sends a resume request message to the underlying real-time control module. The message contains the sequence number of the last frame successfully received and acknowledged by the edge teaching processing module.

[0075] The underlying real-time control module compares the sequence number of the last successfully received frame with the locally written frame sequence number bitmap to calculate the range of missing frame sequence numbers. The underlying real-time control module only reads data frames within the missing range from the circular buffer, arranges them in ascending order of sequence number to form retransmission data packets, and sends them back.

[0076] After receiving the retransmitted data packet, the edge teaching processing module merges the offline data with the online data according to the timestamp and restores the complete global dataset. Then, it continues to execute the evaluation process of step S400 normally.

[0077] In this embodiment, a lightweight breakpoint resumption protocol is defined, employing a circular buffer offline caching, frame sequence number bitmap handshake, and selective retransmission for missing intervals. This ensures zero data loss during communication interruptions, and upon link recovery, only missing data segments are transmitted instead of a full retransmission, balancing data integrity and retransmission efficiency while guaranteeing continuous evaluation.

[0078] In one embodiment, the edge teaching processing module employs a virtualization instance architecture based on Linux container technology at runtime, and the method further includes: The edge teaching processing module creates and manages multiple isolated container instances, each corresponding to an independent training workstation; that is, an independent container instance is created for each physical training workstation, and each container instance runs an independent training process collection daemon process and evaluation algorithm instance. Each container instance is allocated a dedicated or limited processor core time slice, memory bandwidth limit, and I / O queue weight, ensuring that steps executed by different operators are performed concurrently within their respective container instances without interference. Specifically, this includes: By using Linux kernel Cgroups control groups, each container instance is bound to an independent CPU core (CPU core affinity settings) and a memory bandwidth limit is set to prevent abnormal code written by an operator (such as infinite loops or memory leaks) from exhausting the system resources of the edge module; Each container instance is assigned an independent virtual network interface, and the communication traffic of each training station is isolated through a virtual local area network to prevent broadcast storms or ARP spoofing and other unexpected network behaviors from interfering with other stations. Steps S1 to S5, which are executed for different training workstations, run concurrently within each container instance. The process space, file system view, and network stack of each container are not visible to each other, thus achieving secure multi-tenant isolation.

[0079] In this embodiment, a containerized virtual instance architecture is adopted, combined with Cgroups' CPU affinity binding, memory bandwidth limitations, and independent network namespaces to achieve hard isolation of resources at each workstation. A single edge hardware unit can securely and stably serve multiple training workstations concurrently, significantly reducing the hardware deployment cost of multi-workstation training labs and improving system scalability.

[0080] The application of this invention will be illustrated below using the task of troubleshooting PWM motor speed control faults as an example: Before the practical training, the teacher constructs the optimal error correction state transition diagram for this task. The standard path is defined as: Fault trigger (motor does not turn) → State A (check PWM timer enable bit, operate register TIMx_CR1) → State B (check GPIO multiplexing function configuration, operate register GPIOx_AFR) → State C (check PWM duty cycle comparison value, operate register TIMx_CCRx) → Function verification (motor runs normally) → Fault recovery.

[0081] At the start of the training, the system first performs hardware link diagnostics. The underlying real-time control module injects a 2-3mA subthreshold excitation current pulse into the motor drive interface, synchronously acquiring and transmitting the voltage response signal. The edge teaching processing module calculates the measured impedance value and compares it with the normal range to confirm that the hardware wiring is intact and rule out the possibility of physical faults in the equipment.

[0082] Subsequently, the system completes scene initialization. The system pre-injects a fault into the PWM duty cycle compare register (TIMx_CCRx) (setting its value to 0x0000). After the operator gets on the machine, they observe that the motor is not turning and begin debugging and troubleshooting.

[0083] During the debugging process, the operator's actual operation sequence was as follows: first, the watchdog configuration register, which was unrelated to the fault, was modified; then the UART baud rate register was modified; then the GPIO output data register was modified; and after many ineffective trials, the TIMx_CCRx register was finally located and the correct duty cycle value was written.

[0084] Throughout the process, the hardware breakpoint acquisition unit of the underlying real-time control module captures the instruction address, written value, and system clock timestamp of each write operation in a completely non-intrusive manner between the processor pipeline commit and write-back phases. All breakpoint trigger records are transmitted to the edge teaching processing module through a low-priority acquisition channel without interfering with the normal output of the PWM waveform.

[0085] After reading all breakpoint trigger records, the edge teaching processing module sorts them by timestamp and reconstructs the operator's instruction address sequence, data write sequence, and operation time interval sequence. Mapping these sequences to the optimal error-correction state transition diagram for "PWM motor speed control fault troubleshooting" reveals that the operator's actual path is "fault trigger → (modify watchdog register) → (modify UART register) → (modify GPIO output) → parameter adjustment → function verification → fault recovery." Compared to the optimal path, the operator's path contains three redundant state nodes, the state transition edit distance is 5, and the operation time interval sequence shows that the first three invalid operations take a relatively long time.

[0086] The weighted scoring system showed that the operator's debugging efficiency and fault handling ability scores were significantly low. The system automatically generated a diagnostic report and pushed it to the operator's terminal, stating: "Your troubleshooting path covered registers unrelated to PWM motor control, such as watchdog and UART configuration, which constitutes invalid troubleshooting operations and increases troubleshooting time. It is recommended that you prioritize checking the timer enable bits and GPIO multiplexing function configuration registers directly related to the PWM output." The management terminal then compiled a heatmap of redundant operation types for this task across the entire class, revealing common problems among most operators in the GPIO multiplexing function configuration stage, thus providing data support for targeted explanations in subsequent classes.

[0087] like Figures 3 to 4 As shown, an industrial software development hierarchical collaborative operation training device is used to execute an industrial software development hierarchical collaborative operation training evaluation method as described above, comprising: The underlying real-time control module has a built-in hardware breakpoint acquisition unit and a ring buffer unit. The edge teaching processing module is physically separated from the underlying real-time control module, runs a containerized virtual instance architecture, and is configured with a state machine path comparison and evaluation unit. The communication and interaction module connects the underlying real-time control module and the edge teaching processing module, and is equipped with a high-priority instruction queue, a low-priority acquisition queue, and a leaky bucket flow shaping scheduler. The sensor and actuator module is electrically connected to the underlying real-time control module, supporting the injection and response acquisition of subthreshold excitation signals; The host computer teaching management terminal communicates with the edge teaching processing module.

[0088] Specifically, the underlying real-time control module uses an ARM Cortex-M7 series 32-bit microcontroller (such as the STM32H743), with a main frequency of no less than 400MHz, and is equipped with a memory protection unit and dual Flash partitions. This module has the following built-in features: Hardware breakpoint acquisition unit: Utilizing the on-chip CoreSight debugging architecture's DWT unit, it supports configuring hardware breakpoints simultaneously for up to 8 peripheral register addresses, enabling non-intrusive data capture; Circular buffer unit: A dedicated storage area is allocated in the on-chip Flash to cyclically buffer operation behavior data during communication interruption and maintain the frame sequence number bitmap.

[0089] The edge learning processing module uses a multi-core ARM Cortex-A76 + Cortex-A55 big.LITTLE embedded processor (such as the Rockchip RK3588) and runs a Linux operating system with the PREEMPT_RT real-time kernel patch. This module is configured with: State machine path comparison and evaluation unit: It extracts the register modification sequence from the operation behavior data, compares it with the pre-constructed optimal error correction state transition diagram, calculates the state transition edit distance, and generates a complete algorithm chain for quantitative scoring; Containerized virtual instance architecture: Create an independent Docker container instance for each training workstation, and combine Cgroups to achieve CPU core binding and memory bandwidth isolation.

[0090] Communication module: The physical interface simultaneously supports RS-485 differential serial bus (for high-priority command channels) and 100M industrial Ethernet (for low-priority acquisition channels). Internal configuration includes: High-priority instruction queue and low-priority acquisition queue: physically isolated dual queues; Leaky bucket flow shaping scheduler: Based on hardware timer interrupt drive, it realizes absolute priority of control command data transmission and real-time adaptive suppression of behavioral data flow.

[0091] The host computer teaching management terminal can be a regular desktop computer or a portable laptop, running teaching management software, which allows teachers to complete tasks such as editing and distributing operation tasks, tracking data of the entire training process, statistical analysis of class learning, and exporting individual diagnostic reports for operators.

[0092] In this embodiment, the device operates through a two-layer hierarchical collaborative architecture: the bottom real-time control module exclusively occupies the hard real-time task domain, and the edge teaching processing module exclusively occupies the soft real-time teaching task domain. The two are decoupled and interact with each other only through the dual priority channels of the communication interaction module, thereby realizing the monitoring, traceability and quantifiable evaluation of the entire process of industrial software development training.

[0093] This invention completely solves the technical problem of teaching behavior interfering with hard real-time control in traditional single-processor training platforms by physically separating the underlying real-time control module and the edge teaching processing module, combined with the priority tag transmission timing isolation mechanism of the communication interaction module. Under arbitrary debugging operations, the deterministic response of the underlying hard real-time control loop remains unaffected, and the physical scene behavior strictly corresponds to the operator's code logic. By non-intrusive capture of register modification sequences through hardware breakpoints, combined with the optimal error correction state transition graph and state transition edit distance calculation, the evaluation dimensions are expanded from the depth of result correctness to process capability indicators such as debugging path efficiency, operational standardization, and the quality of troubleshooting strategies. The evaluation results possess interpretability at the graph theory algorithm level.

[0094] Furthermore, this invention possesses a hierarchical error knowledge graph that ranges from grammatical mapping to semantic reasoning and then to system-level causal relationship matching. This allows for cross-level causal troubleshooting guidance for complex hardware-level faults, improving the teaching model from simply telling the operator where the error occurred to guiding them to understand why the error happened. Through a hardware link diagnostic mechanism using subthreshold excitation current injection and impedance spectrum analysis, the training device performs a non-destructive self-check of its hardware status before each task initialization, dynamically linking the diagnostic results to evaluation weight adjustments, effectively eliminating evaluation distortion caused by equipment failures. A containerized virtual instance architecture enables secure concurrent services from a single edge hardware to multiple training workstations, and a circular buffer and frame sequence number bitmap handshake achieve zero data loss and efficient selective retransmission during communication interruptions.

[0095] The foregoing description of specific exemplary embodiments of the present invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is obvious that many changes and variations can be made based on the above teachings. Although embodiments of the invention have been shown and described, these specific embodiments are merely explanations of the invention and are not intended to limit it. The specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. The purpose of selecting and describing exemplary embodiments is to explain the specific principles of the invention and its practical application, so that those skilled in the art, after reading this specification, can make modifications, substitutions, variations, and various choices and changes to the embodiments as needed without departing from the principles and spirit of the invention, provided that such modifications, substitutions, variations, and choices and changes are within the scope of the claims of the invention and are protected by patent law.

Claims

1. A hierarchical collaborative operation training and evaluation method for industrial software development, applied to an operation training device, the operation training device comprising a low-level real-time control module and an edge teaching processing module separately configured on physical hardware, and a communication interaction module connecting the two, characterized in that, Evaluation methods include: The edge teaching processing module receives the operation tasks issued by the host computer, parses the sensor type, actuator type and control logic requirements contained in the operation tasks, generates hardware configuration instructions and sends them to the underlying real-time control module through the communication interaction module to configure the industrial control physical simulation environment. The operator performs a full-process training operation on the operating terminal, including code writing, compilation and download, online debugging and functional verification; During the debugging operation performed by the operator, the edge teaching processing module continuously acquires operation behavior data through the communication interaction module; at the same time, the underlying real-time control module independently runs a hard real-time control loop to maintain deterministic output of sensor data acquisition and actuator drive signals. The communication interaction module implements priority tag-based transmission timing isolation for the control command data and operation behavior data generated by the hard real-time control loop, so that the transmission of the operation behavior data does not occupy the transmission time slot of the control command data, thereby achieving both the response determinism of the hard real-time control loop and the fullness of the operation behavior data acquisition. The edge teaching processing module extracts the register modification sequence and corresponding timing context of the underlying real-time control module by the operator during the debugging process from the operation behavior data, and compares the register modification sequence with the pre-built standard error correction state machine path, and generates a quantitative operation score and operation behavior diagnosis report based on the comparison result. The edge teaching processing module pushes the quantitative operation score and diagnostic report to the operation terminal and / or management terminal.

2. The industrial software development layered collaborative operation training evaluation method of claim 1, wherein, Priority-label-based transmission timing isolation includes: The communication interaction module maintains a high-priority instruction queue and a low-priority acquisition queue; When generating control command data frames, the underlying real-time control module adds a high-priority tag to the control command data frames; when requesting operation behavior data, the edge teaching processing module adds a low-priority tag to the data request frames. The communication interaction module has a built-in leaky bucket flow shaping scheduler. The leaky bucket flow shaping scheduler takes data frames from the high-priority instruction queue at a fixed rate and sends them. It only sends data frames from the low-priority acquisition queue during the time slice when the high-priority instruction queue is empty. When the leaky bucket traffic shaping scheduler detects that the interrupt load rate of the underlying real-time control module exceeds a preset threshold, the leaky bucket traffic shaping scheduler dynamically reduces the number of service tokens in the low-priority collection queue to actively suppress the uplink traffic of operation behavior data until the interrupt load rate falls back below the preset threshold.

3. The industrial software development layered collaborative operation training evaluation method of claim 2, wherein, Obtain operational behavior data, including: The underlying real-time control module is equipped with a hardware breakpoint acquisition unit. The hardware breakpoint acquisition unit uses the on-chip debugging component of the underlying real-time control module to configure hardware breakpoints on the addresses of key peripheral registers that the operator's program may modify. When the processor of the underlying real-time control module executes a write operation instruction and accesses the register address of the configured hardware breakpoint, the on-chip debug component captures the instruction address, written data value and system clock count value of the write operation between the commit phase and write-back phase of the processor pipeline, generates a breakpoint trigger record, and writes the breakpoint trigger record into a dedicated trace buffer. The edge teaching processing module periodically reads the breakpoint trigger records accumulated in the dedicated tracking buffer through the low-priority acquisition channel of the communication interaction module.

4. The industrial software development layered collaborative operation training evaluation method of claim 3, wherein, Extract the sequence of register modifications made by the operator to the underlying real-time control module and the corresponding timing context, including: The edge teaching processing module reads the breakpoint trigger record, sorts it according to the timestamp of the system clock count value, and reconstructs the instruction address sequence, write data sequence and operation time interval sequence of all write operation instructions executed by the operator on the key peripheral register during the debugging process; The instruction address sequence is used to restore the modified register, the write data sequence is used to restore the modified parameter value, and the operation time interval sequence represents the operator's debugging response speed and troubleshooting efficiency.

5. The industrial software development layered collaborative operation training evaluation method of claim 4, wherein, The register modification sequence is compared with a pre-built standard error-correcting state machine path, and a quantified operation score is generated based on the comparison result, including: The edge teaching processing module pre-stores the optimal error correction state transition diagram for preset fault points in the operation task. The optimal error correction state transition diagram defines the standard register operation sequence from the fault trigger state to the fault recovery state, as well as the judgment condition for each state node. The edge teaching processing module maps the register modification sequence actually executed by the operator during the debugging process to the optimal error correction state transition graph, calculates the state transition edit distance between the actual path and the optimal path, and the number of redundant operation states contained in the actual path. The state transition edit distance and the number of redundant operation states are used as input parameters to input a weighted scoring function to generate the quantified operation score.

6. The industrial software development layered collaborative operation training evaluation method of claim 5, wherein, The collaborative teaching device also includes a sensor and actuator module, which is electrically connected to the underlying real-time control module; Before configuring the industrial control physical simulation environment, the following is also included: The edge teaching processing module sends hardware link diagnostic commands to the underlying real-time control module. In response to the hardware link diagnostic command, the underlying real-time control module outputs a subthreshold excitation current pulse to the target sensor interface in the sensor and actuator module. The amplitude of the subthreshold excitation current pulse is lower than the minimum driving threshold that triggers the actuator action corresponding to the target sensor. The underlying real-time control module synchronously acquires the voltage response signal of the target sensor interface and transmits the voltage response signal back to the edge teaching processing module; The edge teaching processing module compares the measured impedance value of the voltage response signal with the pre-stored normal wiring impedance range. If the measured impedance value exceeds the normal wiring impedance range, it is determined that there is a hardware connection fault in the target sensor interface. When generating the quantitative operation score, the weight of the evaluation scoring item associated with the target sensor interface is set to zero, and a hardware maintenance alarm is pushed to the management terminal.

7. The industrial software development layered collaborative operation training evaluation method of claim 1, wherein, The edge learning processing module adopts a containerized virtual teaching instance architecture at runtime, and the method further includes: The edge teaching processing module creates and manages multiple isolated container instances, each container instance corresponding to an independent training station; Each container instance is allocated a dedicated or limited processor core time slice, memory bandwidth limit, and input / output queue weight, so that the steps executed by different operators can be executed concurrently in their respective container instances without interference.

8. The industrial software development layered collaborative operation training evaluation method of claim 1, wherein, Also includes: When the underlying real-time control module detects an interruption in the communication link with the edge teaching processing module, the underlying real-time control module will cyclically write the newly collected operation behavior data into the circular buffer in the local non-volatile memory in a preset format, and maintain the bitmap of the written frame sequence number. Once the communication link is re-established, the edge teaching processing module sends a resume request to the underlying real-time control module. The resume request includes the sequence number of the last frame successfully received by the edge teaching processing module. The underlying real-time control module compares the sequence number of the last successfully received frame with the locally written frame sequence number bitmap, and only reads data frames within the missing sequence number range from the circular buffer and retransmits them to the edge teaching processing module. After the retransmission is completed, the edge teaching processing module merges the data from the offline period with the data from the online period into the global dataset.

9. An industrial software development hierarchical collaborative operation training device, used to execute the industrial software development hierarchical collaborative operation training evaluation method as described in any one of claims 1 to 8, characterized in that, include: The underlying real-time control module has a built-in hardware breakpoint acquisition unit and a ring buffer unit. The edge teaching processing module is physically separated from the underlying real-time control module and is equipped with a state machine path comparison and evaluation unit. The communication interaction module is communicatively connected to both the underlying real-time control module and the edge teaching processing module. The host computer teaching management terminal is communicatively connected to the edge teaching processing module.

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