Display device and electronic device having the same

Abstract

This application relates to a display device and an electronic device including the display device. The display device includes: a display panel including a display area having a plurality of pixels and a non-display area outside the display area; a scan driver in the non-display area and including a plurality of stages; and a plurality of clock lines in the non-display area and configured to transmit clock signals for controlling the operation of the scan driver to the plurality of stages of the scan driver, wherein each of the plurality of clock lines includes: a first sub-clock line; a second sub-clock line spaced apart from and arranged parallel to the first sub-clock line; and at least one connection portion configured to partially electrically connect the first sub-clock line and the second sub-clock line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0017426, filed on February 11, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure relate to display devices and electronic devices including such display devices. Background Technology

[0004] With the development of multimedia, interest in display devices is increasing. For example, there is growing interest in display devices such as liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs).

[0005] A display device may include a display area and a non-display area (or dead zone (DS) area). The display area may include multiple pixels, pixel driving circuitry, scan lines, data lines, etc. The non-display area may include a data driver, a scan driver, signal lines for transmitting various control signals, clock lines for transmitting clock signals, power lines for supplying power, ground lines, etc.

[0006] Clock signals can be transmitted via clock lines to corresponding drivers (e.g., scan drivers, data drivers, etc.) for the synchronization of various signals (e.g., scan signals, data signals, etc.). However, as the length of the clock line increases, the deviation between the signal waveform at the beginning and end of the clock line may also increase. As the resistive component (or resistivity) of the clock line decreases, the deviation between waveforms may tend to increase. This deviation can adversely affect the quality of the display device. Therefore, it is desirable to prevent, reduce, or minimize the deviation in the waveform.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0008] Some aspects of embodiments of this disclosure include a display device capable of preventing or reducing deviations in signal waveforms on a clock line and an electronic device including the display device.

[0009] Some aspects of embodiments of this disclosure include a display device with relatively improved quality and an electronic device including the display device.

[0010] A display device according to some embodiments of the present disclosure may include: a display panel including a display area having a plurality of pixels and a non-display area outside the display area; a scan driver in the non-display area and including a plurality of stages; and a plurality of clock lines in the non-display area and configured to transmit clock signals for controlling the operation of the scan driver to the plurality of stages of the scan driver. According to some embodiments, each of the plurality of clock lines may include: a first sub-clock line; a second sub-clock line spaced apart from and arranged parallel to the first sub-clock line; and at least one connection portion configured to partially electrically connect the first sub-clock line and the second sub-clock line.

[0011] According to some implementations, the first sub-clock line and the second sub-clock line can be formed in a double-stacked structure.

[0012] According to some implementations, multiple clock lines may include a carry clock line configured to transmit a carry clock signal, a global clock line configured to transmit a global clock signal, a scan clock line configured to transmit a scan clock signal, and a sense clock line configured to transmit a sense clock signal.

[0013] According to some implementations, the clock line may also include a third sub-clock line that is spaced apart from and arranged parallel to the second sub-clock line.

[0014] According to some implementations, at least one connection portion can connect a first sub-clock line, a second sub-clock line, and a third sub-clock line.

[0015] According to some implementations, at least one connection portion may include: a first connection portion configured to connect a first sub-clock line and a second sub-clock line; and a second connection portion configured to connect a second sub-clock line and a third sub-clock line.

[0016] According to some implementations, at least one connection portion may include: a first connection portion configured to connect a first sub-clock line, a second sub-clock line, and a third sub-clock line; and a second connection portion configured to connect the first sub-clock line and the second sub-clock line or the second sub-clock line and the third sub-clock line.

[0017] According to some implementations, at least one connecting portion includes multiple connecting portions, the lengths and widths of which may be equal (or substantially equal) to each other or different from each other.

[0018] According to some implementations, multiple clock lines can be repeatedly connected to a specified number of consecutive stages in multiple stages.

[0019] According to some implementations, the length of at least one connecting portion may be equal to (or substantially equal to) the length of one of the successive stages.

[0020] An electronic device according to some embodiments of the present disclosure may include: a display device; and a processor connected to the display device and configured to control the operation of the display device. According to some embodiments, the display device may include: a display panel including a display area having a plurality of pixels and a non-display area outside the display area; a scan driver in the non-display area and including a plurality of stages; and a plurality of clock lines formed in the non-display area and configured to transmit clock signals for controlling the operation of the scan driver to the plurality of stages of the scan driver. According to some embodiments, each of the plurality of clock lines may include: a first sub-clock line; a second sub-clock line spaced apart from and arranged parallel to the first sub-clock line; and at least one connection portion configured to partially electrically connect the first sub-clock line and the second sub-clock line. Attached Figure Description

[0021] The above and other aspects, features, and other characteristics of some embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a perspective view showing a display device according to some embodiments; Figure 1B This is a plan view showing a display device according to some embodiments; Figure 2 This is a schematic view of a scan driver of a display device according to some embodiments; Figure 3 It is shown Figure 2 Detailed view of area A; Figure 4 It is shown Figure 2 Detailed view of area B; Figure 5 This is a view showing a clock line with a double-stacked structure according to some embodiments; Figure 6 This is a view showing clock lines with various structures according to some embodiments; Figure 7 It is a block diagram of an electronic device according to some embodiments; and Figure 8 This is a schematic diagram illustrating different applications of an electronic device according to some implementations. Detailed Implementation

[0022] In the following description, some aspects of embodiments of this disclosure will be described in more detail with reference to the accompanying drawings. Specific embodiments of this disclosure will be illustrated in the drawings and described in the following detailed description in connection with them, but this is not intended to limit the various embodiments of this disclosure to a particular form. For example, it will be apparent to those skilled in the art to which this disclosure pertains that various modifications can be made to the embodiments of this disclosure.

[0023] Figure 1A This is a perspective view showing a display device according to some embodiments, and Figure 1B This is a plan view showing a display device according to some embodiments.

[0024] Before the detailed description, in this disclosure, "upper part," "top," and "upper surface" refer to the upward direction (i.e., the Z-axis direction) based on the display panel 110, and "lower part," "bottom," and "lower surface" refer to the downward direction (i.e., the direction opposite to the Z-axis direction) based on the display panel 110. Additionally, "upper side," "lower side," "left side," and "right side" indicate the direction when the display panel 110 is viewed in a plane. For example, "upper side" corresponds to the Y-axis direction, "lower side" corresponds to the direction opposite to the Y-axis direction, "left side" corresponds to the direction opposite to the X-axis direction, and "right side" corresponds to the X-axis direction.

[0025] In this disclosure, the display device 100 according to some embodiments of this disclosure is a device for displaying moving images (e.g., video) or still (e.g., static) images, and can be used as a display screen for various products such as portable electronic devices including mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc., as well as multimedia devices (e.g., displays for vehicles, head-up displays, etc.) installed in, embedded in, or integrated with automobiles, or home appliances (e.g., televisions, etc.), laptop computers, monitors, billboards, and Internet of Things (IoT) devices. Furthermore, the display device 100 according to some embodiments of this disclosure can be included in various types of electronic devices. For example, the display device 100 according to some embodiments of this disclosure can be incorporated into rigid, flexible, foldable, rollable, or wearable electronic devices.

[0026] In the following description, a display device 100 according to some embodiments is shown and described as a medium-to-large-sized display device including a plurality of data drivers 120, but the embodiments according to this disclosure are not limited thereto. The display device 100 according to some embodiments may be a small-sized display device including a single data driver 120. In this case, the flexible film 130, the source circuit board 140, and the connecting member 150 may be omitted. Furthermore, when the display device 100 according to some embodiments is a small-sized display device, the data driver 120 and the timing controller 170 may be integrated into a single integrated circuit and placed on a circuit board, or may be bonded to the first substrate 111 of the display panel 110. Examples of medium-to-large-sized display devices include televisions and monitors, and examples of small-sized display devices include smartphones and tablet PCs.

[0027] refer to Figure 1A and Figure 1B According to some embodiments, the display device 100 may include a display panel 110, a data driver 120, a flexible film 130, a source circuit board 140, a connecting member 150, a control circuit board 160, a timing controller 170, and a scan driver 180.

[0028] The display panel 110 can be formed in a rectangular shape. For example, as shown in the figure. Figure 1B As shown, the display panel 110 can have a rectangular shape, having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction). The corners of the display panel 110 can be formed as right angles or curved with a curvature (e.g., a set or predetermined curvature). The planar shape of the display panel 110 is not limited to a rectangle and can be formed as other polygonal, circular, or elliptical shapes. Furthermore, although... Figure 1A and Figure 1B The display panel 110 is shown to be formed as flat, but embodiments according to this disclosure are not limited thereto. The display panel 110 may include curved portions bent with a curvature (e.g., a set or predetermined curvature).

[0029] According to some embodiments, the display panel 110 may include a first substrate 111 and a second substrate 112. The second substrate 112 may be arranged to face a first surface of the first substrate 111. The first substrate 111 and the second substrate 112 may be formed as rigid substrates or flexible substrates. The first substrate 111 may be made of glass or plastic. The second substrate 112 may be made of glass, plastic, a sealing film, or a barrier film. Optionally, the second substrate 112 may be omitted.

[0030] According to some embodiments, the display panel 110 may be an organic light-emitting display panel using organic light-emitting diodes, a quantum dot light-emitting display panel including a quantum dot light-emitting layer, an inorganic light-emitting display panel including inorganic semiconductors, or an ultra-miniature light-emitting display panel using micro light-emitting diodes (LEDs). Hereinafter, for ease of description, the display panel 110 will be described as an example of an organic light-emitting display panel.

[0031] The display panel 110 may include pixels formed therein (e.g., those described below). Figure 2 The pixels PX in the image are used to display the display area DA and the non-display area NDA as the outer region surrounding the display area DA (e.g., outside the display area DA or outside the range of the display area DA).

[0032] In the display area DA, not only pixels can be arranged, but also scan signal lines, data lines, and drive voltage lines connected to the pixels can be arranged. The scan signal lines can be arranged within the display area DA in a first direction (X-axis direction). The data lines can be arranged within the display area DA in a second direction (Y-axis direction) that intersects (e.g., perpendicularly) the first direction (X-axis direction). The drive voltage lines can be arranged within the display area DA in the second direction (Y-axis direction).

[0033] The non-display area NDA can be defined as the area from the outer boundary of the display area DA to the edge of the display panel 110. For example, the non-display area NDA can surround the display area DA and be located at the periphery of the display panel 110, but embodiments according to this disclosure are not limited thereto. This includes multiple stages that sequentially output scan signals (e.g., those described below). Figure 2 The scan driver 180 (multiple levels ST1 to STn) can be located in the non-display area NDA.

[0034] The scan driver 180 can be connected via multiple scan control lines (e.g., Figure 2 The scan control line SL is connected to the flexible film 130. The scan driver 180 can receive scan control signals from the timing controller 170 via multiple scan control lines. The scan control signals may include multiple clock signals, gate on-voltage, and gate off-voltage. The scan driver 180 can generate a scan signal based on the scan control signals and output the generated scan signal via the scan signal line. The following will refer to... Figures 2 to 4 The scan driver 180 is described in more detail.

[0035] at the same time, Figure 1BAn example is shown in which the scan driver 180 is formed in a non-display area NDA on both sides of the display area DA (such as the left and right sides of the display area DA), but embodiments according to this disclosure are not limited thereto. For example, the scan driver 180 may be formed only in a non-display area NDA on one side of the display area DA (such as the left or right side).

[0036] The flexible film 130 may have one side attached to a first surface of the first substrate 111 of the display panel 110 and another side attached to a surface of the source circuit board 140. For example, because the size of the second substrate 112 is smaller than the size of the first substrate 111, one side of the first substrate 111 may be exposed and not covered by the second substrate 112. The flexible film 130 may be attached to the exposed side of the first substrate 111 that is not covered by the second substrate 112. For example, the flexible film 130 may be attached to the first surface of the first substrate 111 and a surface of the source circuit board 140 using an anisotropic conductive film, but embodiments according to this disclosure are not limited thereto.

[0037] According to some embodiments, the flexible film 130 may be a flexible film such as a carrier package or a chip-on-film (COF). The flexible film 130 may be bent toward the lower portion of the first substrate 111. When the flexible film 130 is bent toward the lower portion of the first substrate 111, the source circuit board 140, the connecting member 150, and the control circuit board 160 may be located on the lower surface of the display panel 110. Although Figure 1A and Figure 1B An example is shown where eight flexible films 130 are attached to a first substrate 111 of a display panel 110, but the number of flexible films 130 is not limited to eight.

[0038] The data driver 120 may be located on one surface of the flexible film 130. The data driver 120 may be formed as an integrated circuit (IC). The data driver 120 may convert digital video data (DATA) into analog data voltage based on the data control signal of the timing controller 170, and supply the voltage to the data lines of the display panel 110 through the flexible film 130.

[0039] The source circuit board 140 can be connected to the control circuit board 160 via a connecting member 150. The source circuit board 140 may include a first connector 151 to which one side of the connecting member 150 is connected (e.g., inserted). The source circuit board 140 may be a flexible printed circuit board (FPCB) or a printed circuit board (PCB).

[0040] The connecting member 150 can connect the source circuit board 140 and the control circuit board 160. The connecting member 150 can be a flexible cable, but is not limited thereto according to embodiments of this disclosure.

[0041] The control circuit board 160 can be connected to the source circuit board 140 via a connecting member 150. The control circuit board 160 may include a second connector 152 to which the other side of the connecting member 150 is connected (e.g., inserted). The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

[0042] at the same time, Figure 1A and Figure 1B An example is shown where the source circuit board 140 and the control circuit board 160 are connected by four connecting members 150, but the number of connecting members 150 is not limited to four. Furthermore, Figure 1A and Figure 1B An example including two source circuit boards 140 is shown, but the number of source circuit boards 140 is not limited to two. Furthermore, when the number of flexible films 130 is small, the source circuit boards 140 can be omitted. When the source circuit boards 140 are omitted, the connecting member 150, the first connector 151, and the second connector 152 are also omitted, and in this case, the flexible film 130 can be directly connected to the control circuit board 160.

[0043] The timing controller 170 may be located on one surface of the control circuit board 160. The timing controller 170 may be formed as an integrated circuit.

[0044] According to some implementations, the timing controller 170 can receive data from an electronic device (e.g., Figure 7 The processor (such as a central processing unit (CPU), application processor (AP), or graphics processing unit (GPU)) on the main circuit board of the electronic device 10 receives digital video data and timing signals. The timing controller 170 can generate source control signals for controlling the timing of the data driver 120 and scan control signals for controlling the timing of the scan driver 180 based on the timing signals. The timing controller 170 can output scan control signals (e.g., clock signals) to the scan driver 180 and transmit digital video data (DATA) along with the source control signals to the data driver 120. According to some embodiments, the timing controller 170 may include clock generation circuitry.

[0045] Figure 2 This is a schematic view of a scan driver of a display device according to some embodiments. Figure 3 It is shown Figure 2 A detailed view of area A, and Figure 4 It is shown Figure 2 Detailed view of area B.

[0046] refer to Figure 2 , Figure 3 and Figure 4According to some embodiments, the scan driver 180 of the display device 100 is positioned in the non-display area NDA and can provide (or apply) scan signals to a plurality of pixels PX arranged in multiple rows and columns (e.g., n×m, where n and m are natural numbers greater than 0) within the display area DA via scan signal lines S1 to Sn. For example, a scan signal can be provided to a plurality of pixels PX located in the same row. Similarly, the data driver 120 can provide (or apply) data signals to a plurality of pixels PX arranged in multiple rows and columns (e.g., n×m, where n and m are natural numbers greater than 0) within the display area DA via data lines D1 to Dm. For example, a data signal can be provided to a plurality of pixels PX located in the same column. The scan signal lines S1 to Sn and the data lines D1 to Dm are connected to the pixels PX and can intersect each other in the display area DA while remaining insulated from each other.

[0047] The scan driver 180 can generate scan signals based on scan control signals and provide the generated scan signals to each pixel PX via scan signal lines S1 to Sn. The scan driver 180 can include multiple stages ST1 to STn. Scan signal lines S1 to Sn can be connected to the output terminals of the multiple stages ST1 to STn respectively. For example, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the sixth scan signal line S6, the seventh scan signal line S7, the eighth scan signal line S8, the (n-7)th scan signal line Sn-7, the (n-6)th scan signal line Sn-6, the (n-5)th scan signal line Sn-5, the (n-4)th scan signal line Sn-4, the (n-3)th scan signal line Sn-3, the (n-2)th scan signal line Sn-2, and so on. The n-1 scan signal line Sn-1 and the nth scan signal line Sn can be connected to the first level ST1, the second level ST2, the third level ST3, the fourth level ST4, the fifth level ST5, the sixth level ST6, the seventh level ST7, the eighth level ST8, the n-7th level STn-7, the n-6th level STn-6, the n-5th level STn-5, the n-4th level STn-4, the n-3rd level STn-3, the n-2nd level STn-2, the n-1st level STn-1, and the nth level STn, respectively.

[0048] The scan driver 180 can be connected to the flexible membrane 130 via the scan control line SL. The scan driver 180 can receive scan control signals from the timing controller 170 via the scan control line SL. The scan control signals may include clock signals and control signals. Meanwhile, although in Figure 2 The scan control line SL is shown as a single line, but the scan control line SL can include multiple lines. For example, as shown... Figure 2 , Figure 3 and Figure 4As shown, the scan control line SL may include multiple clock lines configured to transmit clock signals. For example, the clock lines may include a carry clock line for transmitting a carry clock signal, a global clock line for transmitting a global clock signal, a scan clock line for transmitting a scan clock signal, and a sense clock line for transmitting a sense clock signal, but they are not limited thereto.

[0049] Multiple clock lines include a first clock line C1 to a fourth clock line C4, and except in certain areas, the first clock lines C1 to the fourth clock lines C4 can extend parallel to each other from the lower end to the upper end of the display device 100. Meanwhile, scan drivers 180 are respectively arranged on the left and right sides of the display device 100. Therefore, as will be described below, the first clock line C1 is divided into a first-1 clock line C1-1 and a first-2 clock line C1-2, the second clock line C2 is divided into a second-1 clock line C2-1 and a second-2 clock line C2-2, the third clock line C3 is divided into a third-1 clock line C3-1 and a third-2 clock line C3-2, and the fourth clock line C4 is divided into a fourth-1 clock line C4-1 and a fourth-2 clock line C4-2.

[0050] According to some implementations, each clock line may include multiple lines. For example, a first-1 clock line C1-1 may include a first sub-clock line C1a, a second sub-clock line C1b arranged parallel to and spaced apart from the first sub-clock line C1a, and at least one connecting portion C1c electrically connecting the first sub-clock line C1a and the second sub-clock line C1b at at least one point. Here, the dimensions (widths, hereinafter) W1 of the first sub-clock line C1a in the first direction (X-axis direction) and the width W2 of the second sub-clock line C1b in the first direction (X-axis direction) may be equal to (or substantially equal to) each other or different from each other. Furthermore, the overall width W of the first-1 clock line C1-1 in the first direction (X-axis) may be equal to (or substantially equal to) the width of a conventional clock line. As used herein, "substantially equal" means that the dimensions are exactly the same or, even if they are not exactly the same, are nearly similar to each other.

[0051] The second sub-clock line C1b can be electrically connected to the scan driver 180 via the connecting line C1d. The dimension (or length) h of at least one connecting portion C1c in the second direction (Y-axis) can be equal to (or substantially equal to) the dimension of a stage in the second direction.

[0052] Levels ST1 to STn can be connected to the first clock line C1 to the fourth clock line C4 in a certain number (e.g., a set or predetermined number) (e.g., four) of consecutive levels in a repetitive cycle to receive clock signals. For example, the first level ST1 and the (n-7)th level STn-7 can be connected to the fourth-1 clock line C4-1, the third level ST3 and the (n-5)th level STn-5 can be connected to the third-1 clock line C3-1, the fifth level ST5 and the (n-3)th level STn-3 can be connected to the second-1 clock line C2-1, and the seventh level ST7 and the (n-1)th level STn-1 can be connected to the first-1 clock line C1-1. In addition, the second stage ST2 and the (n-6)th stage STn-6 can be connected to the fourth-2 clock line C4-2, the fourth stage ST4 and the (n-4)th stage STn-4 can be connected to the third-2 clock line C3-2, the sixth stage ST6 and the (n-2)th stage STn-2 can be connected to the second-2 clock line C2-2, and the eighth stage ST8 and the nth stage STn can be connected to the first-2 clock line C1-2.

[0053] Furthermore, although the scan driver 180 is shown above to use four clock signals, the number of clock signals can be less than or more than four. For example, the number of clock signals can be two, six, eight, or more.

[0054] The embodiments of this disclosure described above can divide a clock line into two sub-lines and connect them at at least one point. As a result, since the widths W1 and W2 of the line through which the clock signal travels are reduced and the travel path (or travel length) p of the clock signal becomes longer compared to a conventional clock line, the embodiments of this disclosure can have the effect of increased resistance of the clock line. Consequently, the display device 100 according to some embodiments of this disclosure can prevent (or reduce or minimize) the generation of waveform deviations at the beginning and end portions of each clock line.

[0055] Furthermore, although the two scan drivers 180 of the display device 100 shown and described above are positioned on the left and right sides of the non-display area NDA, one scan driver may instead be positioned on either the left or right side of the non-display area NDA. Additionally, the display device 100 may also include a gate driver and / or a pixel driver. In this case, the display device 100 may have a scan driver positioned on the left (or right) side, while the gate driver or pixel driver is positioned on the right (or left) side.

[0056] Figure 5 This is a diagram illustrating a clock line with a double-stacked structure according to some embodiments.

[0057] refer to Figure 5According to some implementations, the clock line can have a dual stacked structure. In the following, the first clock line C1-1 will be described as an example.

[0058] The first -1 sub-clock line C1a-1 and the second -1 sub-clock line C1b-1 are positioned on a substrate 111 or 112, which may be made of an insulating material such as glass or plastic. An insulating layer 113 is positioned on the upper surface of the first -1 sub-clock line C1a-1 and the second -1 sub-clock line C1b-1, and the first -2 sub-clock line C1a-2 and the second -2 sub-clock line C1b-2 are positioned on the upper surface of the insulating layer 113. A connecting portion C1c and a connecting line C1d are located on the upper surface of the first -2 sub-clock line C1a-2 and the second -2 sub-clock line C1b-2.

[0059] Meanwhile, according to some embodiments, the first-1 sub-clock line C1a-1 and the first-2 sub-clock line C1a-2 can be connected through a first contact hole (e.g., a through hole), and the second-1 sub-clock line C1b-1 and the second-2 sub-clock line C1b-2 can be connected through a second contact hole (e.g., another through hole). The first sub-clock line C1a and the second sub-clock line C1b can have a double stacked structure.

[0060] Figure 6 This is a view showing clock lines with various structures according to some embodiments.

[0061] refer to Figure 6 According to some embodiments, each clock line may include three sub-clock lines C-1, C-2, and C-3. Furthermore, at least one of the position, size, and length of the connection portion connecting each sub-clock line can vary. For example, as in... Figure 6 As indicated by the identification symbol 610, the first connecting part Ca and the second connecting part Cb can connect the first sub-clock line C-1, the second sub-clock line C-2 and the third sub-clock line C-3.

[0062] As another example, such as in Figure 6 As indicated by the identification symbol 620, the first connection part Ca can connect the first sub-clock line C-1 and the second sub-clock line C-2, while the second connection part Cb can connect the second sub-clock line C-2 and the third sub-clock line C-3.

[0063] As another example, such as in Figure 6 As indicated by the identification symbol 630, the first connecting part Ca can connect the first sub-clock line C-1 and the second sub-clock line C-2 at the middle part of the clock line, while the second connecting part Cb can connect the second sub-clock line C-2 and the third sub-clock line C-3 at the bottom part of the clock line.

[0064] As another example, such as in Figure 6 As indicated by the identification symbol 640, the first connection portion Ca can connect the first sub-clock line C-1 and the second sub-clock line C-2 or connect the second sub-clock line C-2 and the third sub-clock line C-3. Meanwhile, the second connection portion Cb can connect the first sub-clock line C-1, the second sub-clock line C-2 and the third sub-clock line C-3.

[0065] As another example, such as in Figure 6 As indicated by the identification symbol 650, the lengths of the first connecting portion Ca and the second connecting portion Cb can be different from each other.

[0066] at the same time, Figure 6 The examples are merely illustrative and, because various combinations are possible, do not limit this disclosure. Furthermore, each clock line may include four or more sub-clock lines. Additionally, each clock line may include three or more connection portions.

[0067] The display device 100 according to the embodiments can be applied to various electronic devices. Electronic devices according to some embodiments include the aforementioned display device 100, and may also include modules or devices with additional functions in addition to the display device.

[0068] Figure 7 It is a block diagram of an electronic device according to some embodiments.

[0069] refer to Figure 7 According to some embodiments, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0070] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0071] The memory 13 can store the data information necessary for the operation of the processor 12 or the display module 11. When the processor 12 runs the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and then the display module 11 can process the received signals and output image information through the display screen.

[0072] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power necessary for the operation of the electronic device 10.

[0073] At least one of the components of the electronic device 10 described above may be included in the display device 100 according to the above embodiment. Furthermore, some portions of independent modules functionally integrated into a single module may be included in the display device 100, while other portions may be provided separately from the display device 100. For example, the display device 100 may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided as parts of another device within the electronic device 10, rather than the display device 100.

[0074] Figure 8 This is a schematic diagram illustrating different applications of an electronic device according to various embodiments.

[0075] refer to Figure 8 According to the embodiments, the various electronic devices to which the display device is applied may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as central information displays (CID) and rearview mirror displays arranged on the dashboard, central instrument panel, or instrument panel of a vehicle.

[0076] Various embodiments of this disclosure can prevent or reduce deviations in the signal waveform on the clock line. In other words, various embodiments of this disclosure can provide a clock signal without deviation. As a result, various embodiments of this disclosure can improve the quality of the display device (e.g., the uniformity of image quality).

[0077] The various embodiments of this disclosure and the terminology used herein are not intended to limit the technical features described herein to the specific embodiments, but should be interpreted as including various modifications, equivalents, or substitutions of these embodiments. Regarding the description of the drawings, similar or related components may be referred to by similar reference numerals. It should be understood that, unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to an item may include one or more things. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “A, B, or C,” and “at least one of A, B, and C” may include any or all possible combinations of these items listed together in the corresponding one of the phrases. As used herein, terms such as “first” and “second” or “first” and “second” may be used to simply distinguish one component from another and do not limit the corresponding component in other respects (e.g., importance or order). It should be understood that, with or without the terms “operably” or “communically”, if a component (e.g., the first component) is referred to as “joined to” or “connected to” another component (e.g., the second component), it means that the component can be joined directly (e.g., by wiring), wirelessly, or via a third component to the other component.

[0078] The term "module" as used in the various embodiments of this disclosure can include a unit implemented in hardware, software, or firmware, and can be used interchangeably with terms such as logic, logic block, section, or circuit. A module can be a part integrally formed therewith, or the smallest unit or part of that part that performs one or more functions. For example, according to some embodiments, a module can be implemented as an application-specific integrated circuit (ASIC).

[0079] Various embodiments of this disclosure can be implemented by software (e.g., a program) comprising one or more instructions stored in a machine-readable storage medium (e.g., internal or external memory). For example, a processor of the machine (e.g., electronic device 10) can invoke at least one instruction among the one or more instructions stored in the storage medium and can execute that instruction. This allows at least one function to be performed according to the invoked at least one instruction. The one or more instructions may include code produced by a compiler or code that can be executed by a decoder. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, "non-transitory storage medium" means that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), and with regard to this term, no distinction is made between cases where data is semi-permanently stored in the storage medium and cases where data is temporarily stored in the storage medium.

[0080] According to some embodiments, methods according to various embodiments of this disclosure can be provided as included in a computer program product. The computer program product can be traded between a seller and a buyer. The computer program product can be distributed in the form of a device-readable storage medium (e.g., an optical disc read-only memory (CD-ROM)), or distributed through an app store (e.g., downloaded or uploaded), or distributed directly between two user devices or distributed online. In online distribution, at least a portion of the computer program product can be stored at least temporarily in a device-readable storage medium (such as the manufacturer's server, the app store's server, or the memory of a relay server), or temporarily generated.

[0081] According to various embodiments, each of the above-described components or elements (e.g., a module or program) may include one or more entities or sub-components. According to various embodiments, one or more components or their operations may be omitted from the above-described components, or one or more other components or their operations may be added to the component. Optionally or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as the functions performed by the corresponding components among the multiple components prior to integration. According to various embodiments, the operations performed by modules, programs, or other components may be executed sequentially, in parallel, repeatedly, or heuristically; one or more operations may be performed in a different order or omitted, or one or more other operations may be added to the one or more operations.

Claims

1. A display device, comprising: The display panel includes a display area in which a plurality of pixels are arranged and a non-display area outside the display area; The scan driver is located in the non-display area and includes multiple levels; as well as Multiple clock lines are located in the non-display area and are configured to transmit clock signals for controlling the operation of the scan driver to the multiple stages of the scan driver. Each of the plurality of clock lines includes: First sub-clock line; The second sub-clock line is spaced apart from and arranged parallel to the first sub-clock line; and At least one connection portion is configured to partially ground-connect the first sub-clock line and the second sub-clock line.

2. The display device according to claim 1, wherein The first sub-clock line and the second sub-clock line have a dual stacked structure.

3. The display device according to claim 1, wherein The multiple clock lines include a carry clock line configured to transmit a carry clock signal, a global clock line configured to transmit a global clock signal, a scan clock line configured to transmit a scan clock signal, and a sensing clock line configured to transmit a sensing clock signal.

4. The display device according to claim 1, wherein The clock line also includes a third sub-clock line that is spaced apart from and arranged parallel to the second sub-clock line.

5. The display device of claim 4, wherein, The at least one connection portion connects the first sub-clock line, the second sub-clock line, and the third sub-clock line.

6. The display device according to claim 4, wherein, The at least one connection portion includes: The first connection portion is configured to connect the first sub-clock line and the second sub-clock line; and The second connection portion is configured to connect the second sub-clock line and the third sub-clock line.

7. The display device according to claim 4, wherein, The at least one connection portion includes: A first connection portion is configured to connect the first sub-clock line, the second sub-clock line, and the third sub-clock line; and The second connection portion is configured to connect the first sub-clock line and the second sub-clock line or to connect the second sub-clock line and the third sub-clock line.

8. The display device according to claim 1, wherein, The at least one connection portion includes multiple connection portions, and The lengths and widths of the plurality of connecting portions are equal to or different from each other.

9. The display device according to claim 1, wherein, The multiple clock lines are repeatedly connected to a specified number of consecutive stages in the multiple stages, and The length of at least one connecting portion is equal to the length of one of the consecutive stages.

10. An electronic device comprising: Display device; as well as A processor, connected to the display device and configured to control the operation of the display device. The display device includes: The display panel includes a display area in which a plurality of pixels are arranged and a non-display area outside the display area; A scan driver, in the non-display area, and including multiple levels; and Multiple clock lines are formed in the non-display area and configured to transmit clock signals for controlling the operation of the scan driver to the multiple stages of the scan driver. Each of the plurality of clock lines includes: First sub-clock line; The second sub-clock line is spaced apart from and arranged parallel to the first sub-clock line; and At least one connection portion is configured to partially ground-connect the first sub-clock line and the second sub-clock line.

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