Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a gate drive circuit and a plurality of binding terminals electrically connected with the gate drive circuit, the gate drive circuit comprising a signal generation module and a signal output module electrically connected; the display panel further comprises a first power signal line connected with the signal generation module and a second power signal line connected with the signal output module, the first power signal line and the second power signal line are configured to transmit high-level signals, and the first power signal line and the second power signal line are respectively connected with different binding terminals; the application transmits signals to the first power signal line and the second power signal line through different binding terminals respectively, thereby avoiding the influence of the fluctuation of the signal in the first power signal line on the signal transmission of the second power signal line, improving the transmission stability of the signal in the second power signal line, and improving the stability of the output signal of the signal output module.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Currently, the gate drive circuit mainly includes a signal generation unit and a signal output unit. The VGH signal connected to the transistor in the output unit is connected to the VGH signal connected to the transistor in the signal generation unit. However, since the transistor in the signal generation unit is also electrically connected to a clock signal, when the clock signal changes, it will affect the VGH signal, causing the VGH signal to fluctuate, which in turn affects the stability of the output signal of the signal output unit. Summary of the Invention

[0003] This application provides a display panel and display device that can improve the transmission stability of signals in the second power signal line and improve the stability of the output signal of the signal output module.

[0004] This application provides a display panel, which includes a gate driving circuit and a plurality of bonding terminals electrically connected to the gate driving circuit. The gate driving circuit includes a signal generation module and a signal output module electrically connected to each other. The display panel further includes a first power signal line connected to the signal generation module and a second power signal line connected to the signal output module. The first power signal line and the second power signal line are configured to transmit a high-level signal, and the first power signal line and the second power signal line are respectively connected to different bonding terminals.

[0005] In one embodiment of this application, the signal generation module includes a first control module, the first control module and the signal output module are both connected to a first node, and the first control module is connected to the first power signal line.

[0006] In one embodiment of this application, the first control module includes a first transistor and a second transistor, and the signal output module includes a first output transistor; The first source-drain terminal of the first transistor is connected to the first power signal line, the first source-drain terminal of the first output transistor is connected to the second power signal line, the first source-drain terminal of the second transistor is connected to the third power signal line, the second source-drain terminal of the first transistor, the second source-drain terminal of the second transistor, and the control terminal of the first output transistor are all connected to the first node, and the third power signal line is configured to transmit a low-level signal.

[0007] In one embodiment of this application, the signal generation module further includes a second control module and a voltage regulator module. The first control module, the second control module, and the voltage regulator module are all connected to the second node, and the second control module and the voltage regulator module are both connected to the first power signal line.

[0008] In one embodiment of this application, the second control module includes a third transistor, and the voltage regulator module includes a switching transistor; The first source-drain terminal of the third transistor and the first source-drain terminal of the switching transistor are both connected to the first power signal line. The second source-drain terminal of the third transistor and the control terminal of the switching transistor are both connected to the second node of the first control module.

[0009] In one embodiment of this application, the signal generation module further includes a third control module and a shielding module, both of which are connected to the voltage regulator module, and the shielding module is also connected to the signal output module; The third control module includes a fourth transistor, the shielding module includes a shielding transistor, and the signal output module includes a second output transistor. The first source-drain terminal of the fourth transistor is connected to the start signal line. The second source-drain terminal of the fourth transistor, the first source-drain terminal of the shielding transistor, and the voltage regulator module are all connected to the third node. The second source-drain terminal of the shielding transistor and the control terminal of the second output transistor are both connected to the fourth node. The control terminal of the shielding transistor is connected to the third power signal line, and the first source-drain terminal of the second output transistor is connected to the fourth power signal line. Both the third and fourth power signal lines are configured to transmit low-level signals.

[0010] In one embodiment of this application, the first power signal line partially overlaps with the signal output module along the thickness direction of the display panel, and the second power signal line partially overlaps with the signal output module along the thickness direction of the display panel.

[0011] In one embodiment of this application, in a top view, the first power signal line is located between the signal generation module and the second power signal line, and the second power signal line is located between the first power signal line and the signal output terminal of the signal output module.

[0012] In one embodiment of this application, the display panel includes at least two conductive layers disposed along the thickness direction of the display panel, and the first power signal line and the second power signal line are located in the same conductive layer, or the first power signal line and the second power signal line are located in different conductive layers.

[0013] In accordance with the above-mentioned objectives of this application, embodiments of this application also provide a display device, the display device including the display panel as described above.

[0014] This application provides a display panel and display device that transmit signals to a first power signal line and a second power signal line through different bonding terminals, thereby avoiding the influence of signal fluctuations in the first power signal line on the signal transmission of the second power signal line, improving the signal transmission stability in the second power signal line, and improving the stability of the output signal of the signal output module.

[0015] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0017] Figure 1 This is a schematic diagram of a planar distribution of a display panel provided in an embodiment of this application; Figure 2 A schematic diagram of a gate driving circuit provided in an embodiment of this application; Figure 3 A film stacking diagram of a gate driving circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 5 A schematic diagram of a light-shielding layer provided in an embodiment of this application; Figure 6 A schematic diagram of a semiconductor layer provided in an embodiment of this application; Figure 7 A schematic diagram of the structure of the first gate layer provided in an embodiment of this application; Figure 8 This is a schematic diagram of a second gate layer provided in an embodiment of this application; Figure 9 A schematic diagram of the structure of the first conductive layer provided in an embodiment of this application; Figure 10 This is a schematic diagram of a second conductive layer provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0019] Please refer to Figure 1 , Figure 2 as well as Figure 3 This application provides a display panel, which includes a gate driving circuit GA and a plurality of bonding terminals 11 electrically connected to the gate driving circuit GA. The gate driving circuit GA includes a signal generation module 100 and a signal output module 200 electrically connected to each other. The display panel also includes a first power signal line VGH1 connected to the signal generation module 100 and a second power signal line VGH2 connected to the signal output module 200. The first power signal line VGH1 and the second power signal line VGH2 are configured to transmit high-level signals, and the first power signal line VGH1 and the second power signal line VGH2 are respectively connected to different bonding terminals 11.

[0020] It should be noted that in this embodiment, the first power signal line VGH1 and the second power signal line VGH2 are respectively connected to different bonding terminals 11; and in the connection path of the first power signal line VGH1 and the connection path of the second power signal line VGH2, the first power signal line VGH1 may undergo at least one wire change during the connection with the bonding terminal 11, and similarly, the second power signal line VGH2 may undergo at least one wire change during the connection with the bonding terminal 11; while the first power signal line VGH1 and the second power signal line VGH2 are not connected in the connection path, that is, they are set at intervals.

[0021] In the implementation process, the embodiments of this application transmit signals to the first power signal line VGH1 and the second power signal line VGH2 through different binding terminals 11, thereby avoiding the influence of signal fluctuations in the first power signal line VGH1 on the signal transmission of the second power signal line VGH2, improving the signal transmission stability in the second power signal line VGH2, and improving the stability of the output signal of the signal output module 200.

[0022] Specifically, please refer to Figure 1 and Figure 2The display panel may include a display area AA and a non-display area NA adjacent to the display area AA. The non-display area NA may be set around the display area AA, and the non-display area NA may be the border area of ​​the display panel.

[0023] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and used to implement the display function of the display panel, and a gate driving circuit module 12 disposed in the non-display area NA, wherein the gate driving circuit module 12 is used to input control signals to the sub-pixels PX in the display area AA.

[0024] In some embodiments, each sub-pixel PX is provided with a pixel driving circuit, and the gate driving circuit module 12 is used to input a gate control signal to the transistor in the pixel driving circuit PD; wherein, multiple sub-pixels PX can be arranged along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect; for example, multiple sub-pixels PX arranged along the first direction X can be regarded as a row of sub-pixels PX, and multiple sub-pixels PX arranged along the second direction Y can be regarded as a column of sub-pixels PX.

[0025] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0026] In some embodiments, the gate drive circuit module 12 includes a plurality of cascaded gate drive circuits GA, and each gate drive circuit GA can be used to transmit control signals to at least one row of sub-pixels PX.

[0027] In some embodiments, a bonding terminal 11 is provided on the lower side of the display area AA, and the display panel also includes a data signal line extending into the display area AA and connected to the pixel driving circuit. The bonding terminal 11 can be connected to an external circuit, and the bonding terminal 11 transmits signals input from the external circuit to the data signal line, thereby driving the display panel to display an image. In addition, the bonding terminal 11 can also transmit signals input from the external circuit to the gate driving circuit GA. For example, the bonding terminal 11 can be bonded to a chip or a flip-chip film, etc., to provide power and driving signals to the display panel.

[0028] In some embodiments, the gate driving circuit module 12 is disposed in the non-display area NA, and the gate driving circuit module 12 may be disposed on both sides of the display area AA. The gate driving circuit module 12 located on one side of the display area AA may include a plurality of gate driving circuits GA arranged along the second direction Y. Each gate driving circuit GA may be used to transmit control signals to at least one row of sub-pixels PX, and the opposite ends of the same row of sub-pixels PX may be respectively connected to a gate driving circuit GA.

[0029] In some embodiments, multiple pixel driving circuits can be arrayed within the display area AA. The pixel driving circuits can be pixel driving circuits such as 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, and 9T6C.

[0030] Please refer to Figure 2 The gate drive circuit GA includes a signal generation module 100 and a signal output module 200. The signal generation module 100 can be used to control the on / off state of the thin-film transistor in the signal output module 200, thereby controlling the signal output terminal Gout of the signal output module 200 to output a signal.

[0031] The signal generation module 100 includes a first control module 101. The first control module 101 and the signal output module 200 are both connected to the first node N1. The first control module 101 is connected to the first power signal line VGH1.

[0032] In some embodiments, the first control module 101 includes a first transistor T1 and a second transistor T2, the signal output module 200 includes a first output module 201, and the first output module 201 includes a first output transistor T01; the first source-drain terminal of the first transistor T1 is connected to the first power signal line VGH1, the first source-drain terminal of the first output transistor T01 is connected to the second power signal line VGH2, the first source-drain terminal of the second transistor T2 is connected to the third power signal line VGL1, the second source-drain terminal of the first transistor T1, the second source-drain terminal of the second transistor T2 and the control terminal of the first output transistor T01 are all connected to the first node N1, and the third power signal line VGL1 is configured to transmit a low-level signal VGL.

[0033] Furthermore, the control terminal of the first transistor T1 is connected to the start signal line STV, so the first transistor T1 can be turned on and off by the signal in the start signal line STV, thereby realizing the on and off control of the current path between the first power signal line VGH1 and the first node N1.

[0034] In some embodiments, the second source-drain terminal of the first output transistor T01 is connected to the signal output terminal Gout of the signal output module 200, so that the first output transistor T01 can transmit the signal in the second power signal line VGH2 to the signal output terminal Gout under the control of the potential of the first node N1.

[0035] In some embodiments, the first output module 201 further includes a second capacitor C2, with one plate of the second capacitor C2 connected to the second power signal line VGH2 and the other plate of the second capacitor C2 connected to the first node N1, so as to maintain the potential of the first node N1 by using the second capacitor C2.

[0036] The signal generation module 100 also includes a second control module 102 and a voltage regulator module 103. The first control module 101, the second control module 102 and the voltage regulator module 103 are all connected to the second node N2. The second control module 102 and the voltage regulator module 103 are all connected to the first power signal line VGH1.

[0037] In some embodiments, the second control module 102 includes a third transistor T3, and the voltage regulator module 103 includes a switching transistor Ts; the first source-drain terminal of the third transistor T3 and the first source-drain terminal of the switching transistor Ts are both connected to the first power signal line VGH1, and the second source-drain terminal of the third transistor T3 and the control terminal of the switching transistor Ts are both connected to the first control module 101 at the second node N2.

[0038] Furthermore, the control terminal of the third transistor T3 is connected to the start signal line STV, and the second source-drain terminal of the third transistor T3, the control terminal of the switching transistor Ts, and the control terminal of the second transistor T2 are all connected to the second node N2.

[0039] It should be noted that the control terminal of the second transistor T2 is electrically connected to the second node N2, so as to control the conduction and cutoff of the second transistor T2 through the signal of the second node N2, thereby realizing the on-off control of the current path between the third power supply signal line VGL1 and the first node N1. This helps to reduce the number of control signals used by the gate drive circuit GA, and also reduces the risk that the signals in the first power supply signal line VGH1 and the third power supply signal line VGL1 are simultaneously applied to the first node N1.

[0040] In some embodiments, the second control module 102 further includes a first capacitor C1, one plate of the first capacitor C1 is connected to a clock signal XCK, and the other plate of the first capacitor C1 is connected to a second node N2, so as to couple the level variation of the clock signal XCK to the second node N2 through the first capacitor C1.

[0041] In some embodiments, the signal generation module further includes a third control module 104 and a shielding module 105, both of which are connected to the voltage regulator module 103, and the shielding module 105 is also connected to the signal output module 200.

[0042] The third control module 104 includes a fourth transistor T4, the shielding module 105 includes a shielding transistor Tsd, the signal output module 200 also includes a second output module 202, and the second output module 202 includes a second output transistor T02. The first source-drain terminal of the fourth transistor T4 is connected to the start signal line STV. The second source-drain terminal of the fourth transistor T4, the first source-drain terminal of the shielding transistor Tsd, and the voltage regulator module 103 are all connected to the third node N3. The second source-drain terminal of the shielding transistor Tsd and the control terminal of the second output transistor T02 are both connected to the fourth node N4. The control terminal of the shielding transistor Tsd is connected to the third power signal line VGL1. The first source-drain terminal of the second output transistor T02 is connected to the fourth power signal line VGL2. The third power signal line VGL1 and the fourth power signal line VGL2 are both configured to transmit low-level signals.

[0043] In some embodiments, the control terminal of the fourth transistor T4 is connected to the clock signal XCK, and the second source-drain terminal of the fourth transistor T4, the first source-drain terminal of the shielding transistor Tsd, and the second source-drain terminal of the switching transistor Ts are all connected to the third node N3.

[0044] It should be noted that the signal supplied by the third power signal line VGL1 can control the conduction and cutoff of the shielding transistor Tsd, thereby shielding the effect of the level fluctuation in the clock signal line XCK on the potential of the fourth node N4 through the shielding transistor Tsd.

[0045] In some embodiments, the shielding transistor Tsd can remain in the on state to continuously shield the effect of level changes in the clock signal line XCK on the potential of the fourth node N4.

[0046] It should be understood that when the first power signal line VGL1 is at a low voltage end, the shielding transistor Tsd is a P-type transistor; in other embodiments of this application, when the first power signal line VGL1 is at a high voltage end, the shielding transistor Tsd is an N-type transistor.

[0047] In some embodiments, the second source-drain terminal of the second output transistor T02 is connected to the signal output terminal Gout of the signal output module 200, so as to transmit the signal in the fourth power signal line VGL2 to the signal output terminal Gout under the control of the potential of the fourth node N4.

[0048] In some embodiments, the second output module 202 further includes a third capacitor C3, and one plate of the third capacitor C3 is connected to the fourth node N4, and another plate of the third capacitor C3 is connected to the signal output terminal Gout of the signal output module 200, so as to improve the stability of the potential of the fourth node N4 by utilizing the third capacitor C3.

[0049] In this embodiment, the first power signal line VGH1 and the second power signal line VGH2 are configured to transmit a high-level signal VGH. The first power signal line VGH1 and the second power signal line VGH2 are respectively connected to different bonding terminals 11, and the first power signal line VGH1 and the second power signal line VGH2 are not connected. Therefore, in this embodiment, the first power signal line VGH1 and the second power signal line VGH2 are transmitted through different bonding terminals 11, thereby avoiding the influence of signal fluctuations in the first power signal line VGH1 on the signal transmission of the second power signal line VGH2. This can improve the signal transmission stability in the second power signal line VGH2 and improve the stability of the output signal of the signal output module 200.

[0050] In some embodiments, the display panel includes at least two conductive layers disposed along the thickness direction of the display panel, and the first power signal line VGH1 and the second power signal line VGH2 are located in the same conductive layer, or the first power signal line VGH1 and the second power signal line VGH2 are located in different conductive layers, which can further increase the spacing between the first power signal line VGH1 and the second power signal line VGH2, and further reduce the impact of signal fluctuations in the first power signal line VGH1 on the signal transmission stability of the second power signal line VGH2.

[0051] In addition, the first source-drain terminals of the first transistor T1, the first source-drain terminals of the third transistor T3, and the first source-drain terminals of the switching transistor Ts in the signal generation module 100 are all connected to the first power supply signal line VGH1.

[0052] It should be noted that the aforementioned control terminal can be the gate of a transistor, the first source-drain terminal can be one of the source and drain terminals of the transistor, and the second source-drain terminal can be the other of the source and drain terminals of the transistor. Each transistor in the gate drive circuit GA can employ a single-gate or dual-gate design.

[0053] It should be noted that at least one of the following components included in the gate drive circuit GA: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the switching transistor Ts, the shielding transistor Tsd, the first output transistor T01, and the second output transistor T02 can be an N-type transistor or a P-type transistor. The active layer of each transistor in the gate drive circuit GA can include silicon semiconductor material or oxide semiconductor material. The silicon semiconductor material includes monocrystalline silicon, polycrystalline silicon, or amorphous silicon, etc. The oxide semiconductor material includes indium gallium zinc oxide or indium zinc oxide, etc.

[0054] It is understood that the gate drive circuit GA of this application may include 7 or 8 transistors. The smaller number of transistors in the gate drive circuit GA helps to reduce the layout space occupied by it. When the gate drive circuit GA is used in a display panel, it facilitates the implementation of a narrow bezel design.

[0055] In addition, it should be understood that, Figure 2 This is merely an illustrative diagram and is not limited to the gate drive circuit GA used in this application. Figure 2 Based on the disclosure of this application, those skilled in the art can still modify the design of each module of the gate drive circuit GA. The modules and units in the gate drive circuit GA can also be implemented in simpler or more complex forms using a greater number of components. These components include, but are not limited to, transistors, capacitors, and other devices.

[0056] The following is about Figure 4 The structure of the gate drive circuit GA in this application is described below.

[0057] Please refer to Figure 1 and Figure 4 In some embodiments, the display area AA and the non-display area NA of the display panel may be provided with a substrate 71 and an array driving layer disposed on the substrate 71. The array driving layer may include a pixel driving circuit located in the display area AA and a gate driving circuit located in the non-display area NA. Within the display area AA, the display panel may also include a pixel definition layer disposed on the array driving layer and a light-emitting device disposed on the pixel definition layer. The film structure in the non-display area NA is described below.

[0058] In some embodiments, substrate 71 may include a substrate and a buffer layer disposed on the substrate. When the display panel is a bottom-emitting display device or a double-sided emitting display device, substrate 71 may use a transparent substrate. When the display panel is a top-emitting display device, substrate 71 may use a translucent or opaque substrate or a transparent substrate.

[0059] In this embodiment, a substrate is used to support the various film layers disposed on the substrate. The substrate can be made of an insulating material such as glass, quartz, or polymer resin. The substrate can be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials used for flexible substrates include, but are not limited to, polyimide (PI).

[0060] In this embodiment, the substrate may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material, such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0061] Please refer to Figure 4 The array driving layer may include multiple thin-film transistors (TFTs). These TFTs can be etch-block type, back-channel etch type, or classified according to the position of the gate and active portion as bottom-gate TFTs, top-gate TFTs, etc., or according to their performance as N-type TFTs, P-type TFTs; among them, Figure 4 The thin-film transistor in the text does not represent Figure 2 The structural diagram of any transistor in this application is merely a schematic diagram of the various film layers of the display panel.

[0062] Please refer to Figure 4 The display panel includes a light-shielding layer 10 disposed on a substrate 71, a first insulating layer 72 disposed on the substrate 71 and covering the light-shielding layer 10, a semiconductor layer 20 disposed on the first insulating layer 72, a second insulating layer 73 disposed on the first insulating layer 72 and covering the semiconductor layer 20, a first gate layer 30 disposed on the second insulating layer 73, a third insulating layer 74 disposed on the second insulating layer 73 and covering the first gate layer 30, a second gate layer 40 disposed on the third insulating layer 74, a fourth insulating layer 75 disposed on the third insulating layer 74 and covering the second gate layer 40, a first conductive layer 50 disposed on the fourth insulating layer 75, a first planarization layer 76 disposed on the fourth insulating layer 75 and covering the first conductive layer 50, a second conductive layer 60 disposed on the first planarization layer 76, and a second planarization layer 77 disposed on the first planarization layer 76 and covering the second conductive layer 60.

[0063] It should be noted that the display panel also includes a pixel definition layer and a plurality of anodes disposed on the second planarization layer 77. The pixel definition layer has a plurality of pixel openings disposed corresponding to the plurality of anodes, and each pixel opening exposes at least a portion of the surface of the corresponding anode on the side away from the second planarization layer 77.

[0064] The display panel also includes multiple light-emitting parts disposed within multiple pixel openings and a cathode layer covering multiple light-emitting parts and a pixel definition layer. The light-emitting parts are disposed within the pixel openings and located on the corresponding anodes. The stacked anodes, light-emitting parts, and cathode layers can constitute a light-emitting device. The anode transmits holes to the light-emitting parts, and the cathode layer transmits electrons to the light-emitting parts. The holes and electrons recombine in the light-emitting parts to excite light, thereby realizing the light-emitting function of the display panel.

[0065] In some embodiments, the display panel further includes an encapsulation layer and a touch layer disposed on the cathode layer. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer stacked sequentially, and the touch layer may be disposed on the side of the second inorganic encapsulation layer away from the organic encapsulation layer. The touch layer may include at least one touch metal layer and a touch insulating layer covering the touch metal layer.

[0066] In some embodiments, the material of the light-shielding layer 10 may include at least one of molybdenum, titanium, chromium, aluminum, and copper.

[0067] In some embodiments, the material of the semiconductor layer 20 may be silicon semiconductor or metal oxide, for example, in this application the material of the semiconductor layer 20 may be low-temperature polycrystalline silicon.

[0068] In some embodiments, the first insulating layer 72, the second insulating layer 73, the third insulating layer 74, and the fourth insulating layer 75 are respectively disposed on the corresponding light-shielding layer 10, semiconductor layer 20, gate layer, and conductive layer, so that the light-shielding layer 10, semiconductor layer 20, gate layer, and conductive layer of different layers are disposed separately; and the materials of the first insulating layer 72, the second insulating layer 73, the third insulating layer 74, and the fourth insulating layer 75 can be inorganic materials composed of silicon oxynitride or organic materials with planarity.

[0069] In some embodiments, the first gate layer 30 and the second gate layer 40 are respectively disposed on corresponding insulating layers, and the materials of the first gate layer 30 and the second gate layer 40 can be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0070] In some embodiments, the materials of the first conductive layer 50 and the second conductive layer 60 may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium trilayer metal, etc.

[0071] In some embodiments, the first planarization layer 76 and the second planarization layer 77 are laid in an integral layer to ensure the flatness of the film layer of the array driving layer. The materials of the first planarization layer 76 and the second planarization layer 77 can be inorganic materials composed of silicon oxynitride or organic materials with flatness.

[0072] It is understood that each thin-film transistor and signal line in the gate drive circuit GA can be located in the array drive layer. For example, the active part of each thin-film transistor can be located in the semiconductor layer 20, and the other electrodes of each thin-film transistor or the connected signal lines can be located in the light-shielding layer 10, the first gate layer 30, the second gate layer 40, the first conductive layer 50 and the second conductive layer 60.

[0073] The technical solution of this application is described below using the structure of each film layer in two adjacent gate drive circuits GA along the second direction Y as an example.

[0074] Please refer to Figure 2 , Figure 3 as well as Figure 5 The light-shielding layer 10 includes a first output bottom gate T01G1, a second output bottom gate T02G1, a first bottom gate T1G1, a second bottom gate T2G1, a third bottom gate T3G1, a fourth bottom gate T4G1, a switch bottom gate TsG1, and a shielding bottom gate TsdG1.

[0075] It should be noted that in the gate drive circuit GA provided in this application embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the switching transistor Ts, the shielding transistor Tsd, the first output transistor T01, and the second output transistor T02 are all dual-gate structures.

[0076] Wherein, the first output bottom gate T01G1 is the bottom gate of the first output transistor T01, the second output bottom gate T02G1 is the bottom gate of the second output transistor T02, the first bottom gate T1G1 is the bottom gate of the first transistor T1, the second bottom gate T2G1 is the bottom gate of the second transistor T2, the third bottom gate T3G1 is the bottom gate of the third transistor T3, the fourth bottom gate T4G1 is the bottom gate of the fourth transistor T4, the switching bottom gate TsG1 is the bottom gate of the switching transistor Ts, and the shielding bottom gate TsdG1 is the bottom gate of the shielding transistor Tsd.

[0077] Among them, the first bottom gate T1G1, the second bottom gate T2G1, the third bottom gate T3G1, the fourth bottom gate T4G1, the switching bottom gate TsG1, and the shielding bottom gate TsdG1 are located on the left side of the gate drive circuit GA, and the first output bottom gate T01G1 and the second output bottom gate T02G1 are located on the right side of the gate drive circuit GA.

[0078] Furthermore, the first bottom gate T1G1, the third bottom gate T3G1, and the fourth bottom gate T4G1 are arranged along the first direction X, and the first bottom gate T1G1 and the third bottom gate T3G1 are connected; the second bottom gate T2G1 is located on one side of the first bottom gate T1G1 and the fourth bottom gate T4G1 along the second direction Y, the switch bottom gate TsG1 is located on the side of the second bottom gate T2G1 away from the first bottom gate T1G1 and the fourth bottom gate T4G1 along the second direction Y, and the second bottom gate T2G1 and the switch bottom gate TsG1 are connected, while the shielding bottom gate TsdG1 is located on the side of the second bottom gate T2G1 and the switch bottom gate TsG1 away from the first bottom gate T1G1 and the fourth bottom gate T4G1.

[0079] Please refer to Figure 2 , Figure 3 as well as Figure 6The semiconductor layer 20 includes a first output active part T01A, a second output active part T02A, a first active part T1A, a second active part T2A, a third active part T3A, a fourth active part T4A, a switching active part TsA, and a shielding active part TsdA.

[0080] Wherein, the first output active part T01A is the active part of the first output transistor T01, the second output active part T02A is the active part of the second output transistor T02, the first active part T1A is the active part of the first transistor T1, the second active part T2A is the active part of the second transistor T2, the third active part T3A is the active part of the third transistor T3, the fourth active part T4A is the active part of the fourth transistor T4, the switching active part TsA is the active part of the switching transistor Ts, and the shielding active part TsdA is the active part of the shielding transistor Tsd.

[0081] In some embodiments, the first output active portion T01A and the second output active portion T02A in the same gate drive circuit GA extend along the second direction Y and are connected to form a rectangle, and the long side of the rectangle is parallel to the second direction Y.

[0082] The first active part T1A, the second active part T2A, the third active part T3A, the fourth active part T4A, the switching active part TsA, and the shielding active part TsdA are located on the left side of the gate drive circuit GA, while the first output active part T01A and the second output active part T02A are located on the right side of the gate drive circuit GA.

[0083] Furthermore, the first active part T1A, the third active part T3A, and the fourth active part T4A are arranged along the first direction X, and the first active part T1A and the third active part T3A are connected and form an L-shape; the second active part T2A is located on one side of the third active part T3A along the second direction Y, the switching active part TsA is located on the side of the second active part T2A away from the third active part T3A along the second direction Y, and the shielding active part TsdA is located on the side of the switching active part TsA away from the second active part T2A along the second direction Y, and the switching active part TsA and the shielding active part TsdA are connected and form an L-shape.

[0084] The orthographic projection of the first output gate T01G1 on the substrate 71 overlaps with the orthographic projection of the first output active part T01A on the substrate 71. The orthographic projection of the second output gate T02G1 on the substrate 71 overlaps with the orthographic projection of the second output active part T02A on the substrate 71. The orthographic projection of the first gate T1G1 on the substrate 71 overlaps with the orthographic projection of the first active part T1A on the substrate 71. The orthographic projection of the second gate T2G1 on the substrate 71 overlaps with the orthographic projection of the second active part T2A on the substrate 71. The images overlap: the orthographic projection of the third bottom gate T3G1 on the substrate 71 overlaps with the orthographic projection of the third active part T3A on the substrate 71; the orthographic projection of the fourth bottom gate T4G1 on the substrate 71 overlaps with the orthographic projection of the fourth active part T4A on the substrate 71; the orthographic projection of the switching bottom gate TsG1 on the substrate 71 overlaps with the orthographic projection of the switching active part TsA on the substrate 71; and the orthographic projection of the shielding bottom gate TsdG1 on the substrate 71 overlaps with the orthographic projection of the shielding active part TsdA on the substrate 71.

[0085] It is understandable that in the above-mentioned thin-film transistor, the area where the active part and the bottom gate overlap can be the channel region of the active part. The potential on the bottom gate is used to control whether the channel region forms a current path, thereby controlling whether the thin-film transistor is turned on or off.

[0086] Please refer to Figure 2 , Figure 3 as well as Figure 7 The first gate layer 30 includes a first output top gate T01G2, a second output top gate T02G2, a first top gate T1G2, a second top gate T2G2, a third top gate T3G2, a fourth top gate T4G2, a switching top gate TsG2, and a shielding top gate TsdG2.

[0087] Wherein, the first output top gate T01G2 is the top gate of the first output transistor T01, the second output top gate T02G2 is the top gate of the second output transistor T02, the first top gate T1G2 is the top gate of the first transistor T1, the second top gate T2G2 is the top gate of the second transistor T2, the third top gate T3G2 is the top gate of the third transistor T3, the fourth top gate T4G2 is the top gate of the fourth transistor T4, the switching top gate TsG2 is the top gate of the switching transistor Ts, and the shielding top gate TsdG2 is the top gate of the shielding transistor Tsd.

[0088] The first output top gate T01G2 and the first output bottom gate T01G1 overlap at least partially along the thickness direction of the display panel, and the first output top gate T01G2 and the first output bottom gate T01G1 are located on opposite sides of the channel region of the first output active part T01A along the thickness direction of the display panel, so as to control the on and off of the first output transistor T01.

[0089] The second output top gate T02G2 and the second output bottom gate T02G1 overlap at least partially along the thickness direction of the display panel, and the second output top gate T02G2 and the second output bottom gate T02G1 are located on opposite sides of the channel region of the second output active portion T02A along the thickness direction of the display panel, so as to control the on and off of the second output transistor T02.

[0090] The first top gate T1G2 and the first bottom gate T1G1 overlap at least partially along the thickness direction of the display panel, and the first top gate T1G2 and the first bottom gate T1G1 are located on opposite sides of the channel region of the first active portion T1A along the thickness direction of the display panel, so as to control the on / off state of the first transistor T1.

[0091] The second top gate T2G2 and the second bottom gate T2G1 overlap at least partially along the thickness direction of the display panel, and the second top gate T2G2 and the second bottom gate T2G1 are located on opposite sides of the channel region of the second active part T2A along the thickness direction of the display panel, so as to control the on and off of the second transistor T2.

[0092] The third top gate T3G2 and the third bottom gate T3G1 overlap at least partially along the thickness direction of the display panel, and the third top gate T3G2 and the third bottom gate T3G1 are located on opposite sides of the channel region of the third active part T3A along the thickness direction of the display panel, so as to control the on / off state of the third transistor T3.

[0093] The fourth top gate T4G2 and the fourth bottom gate T4G1 overlap at least partially along the thickness direction of the display panel, and the fourth top gate T4G2 and the fourth bottom gate T4G1 are located on opposite sides of the channel region of the fourth active part T4A along the thickness direction of the display panel, so as to control the on / off state of the fourth transistor T4.

[0094] The top switch gate TsG2 and the bottom switch gate TsG1 overlap at least partially along the thickness direction of the display panel, and the top switch gate TsG2 and the bottom switch gate TsG1 are located on opposite sides of the channel region of the active switch portion TsA along the thickness direction of the display panel, so as to control the on and off of the switch transistor Ts.

[0095] The top shielding gate TsdG2 and the bottom shielding gate TsdG1 overlap at least partially along the thickness direction of the display panel, and the top shielding gate TsdG2 and the bottom shielding gate TsdG1 are located on opposite sides of the channel region of the active shielding portion TsdA along the thickness direction of the display panel, so as to control the on / off state of the shielding transistor Tsd.

[0096] In some embodiments, the first gate layer 30 further includes a first electrode plate C11, a second electrode plate C12, and a third electrode plate C13, wherein the first electrode plate C11 is located between the fourth top gate T4G2 and the shielding top gate TsdG2 along the second direction Y, and the first electrode plate C11 is connected to the second top gate T2G2 and the switching top gate TsG2, the second top gate T2G2 is located on one side of the first electrode plate C11 along the first direction X, and the switching top gate TsG2 is located on one side of the first electrode plate C11 along the second direction Y.

[0097] The second electrode plate C21 is located between the first top gate T1G2 and the first output top gate T01G2 along the first direction X, and is connected to the first output top gate T01G2; the third electrode plate C31 is located between the shield top gate TsdG2 and the second output top gate T02G2 along the first direction X, and is connected to the second output top gate T02G2.

[0098] Please refer to Figure 2 , Figure 3 as well as Figure 8 The second gate layer 40 includes a fourth electrode C12, a fifth electrode C22, a sixth electrode C32, and a signal output terminal Gout of the signal output module 200.

[0099] The fourth electrode C12 and the first electrode C11 are aligned and partially overlapped along the thickness direction of the display panel to form the first capacitor C1; the fifth electrode C22 and the second electrode C21 are aligned and partially overlapped along the thickness direction of the display panel to form the second capacitor C2; the sixth electrode C32 and the third electrode C31 are aligned and partially overlapped along the thickness direction of the display panel to form the third capacitor C3; and the signal output terminal Gout is connected to the sixth electrode C32.

[0100] Please refer to Figure 2 , Figure 3 , Figure 9 as well as Figure 10 The first conductive layer 50 includes a clock signal line XCK, a first power signal line VGH1, a third power signal line VGL1, a start signal line STV, a first connecting line 51, a second connecting line 52, a third connecting line 53, a fourth connecting line 54, a fifth connecting line 55, a sixth connecting line 56, a seventh connecting line 57, an eighth connecting line 58, a ninth connecting line 59, a tenth connecting line 510, an eleventh connecting line 511, and a twelfth connecting line 512.

[0101] The second conductive layer 60 includes a second power signal line VGH2 and a fourth power signal line VGL2, and both the second power signal line VGH2 and the fourth power signal line VGL2 extend along the second direction Y. The fourth power signal line VGL2 is located on one side of the second power signal line VGH2 along the first direction X.

[0102] It should be noted that, in this embodiment, the first power signal line VGH1 and the second power signal line VGH2 are transmitted through different bonding terminals 11, thereby avoiding the influence of signal fluctuations in the first power signal line VGH1 on the signal transmission of the second power signal line VGH2, and improving the signal transmission stability of the second power signal line VGH2. Furthermore, in this embodiment, the first power signal line VGH1 and the second power signal line VGH2 are disposed in different layers, and are respectively disposed in the first conductive layer 50 and the second conductive layer 60, which further increases the spacing between the first power signal line VGH1 and the second power signal line VGH2, further reducing the probability that signal fluctuations in the first power signal line VGH1 will affect the signal transmission of the second power signal line VGH2, and improving the stability of the output signal of the signal output module 200.

[0103] Among them, the clock signal line XCK, the first power signal line VGH1, the third power signal line VGL1, and the start signal line STV all extend along the second direction Y. The clock signal line XCK includes the first clock signal line XCK1 and the second clock signal line XCK2 arranged sequentially along the first direction X. The third power signal line VGL1 is located along the first direction X on the side of the second clock signal line XCK2 away from the first clock signal line XCK1. The first power signal line VGH1 is located along the first direction X on the side of the third power signal line VGL1 away from the second clock signal line XCK2. The drive signal... Line STV is located along the first direction X on the side of the first power signal line VGH1 away from the third power signal line VGL1; while the first connecting line 51, the second connecting line 52, the third connecting line 53, the fourth connecting line 54, the fifth connecting line 55, the sixth connecting line 56, the seventh connecting line 57 and the eighth connecting line 58 are located between the adjacent first power signal line VGH1 and the third power signal line VGL1, and the ninth connecting line 59, the tenth connecting line 510, the eleventh connecting line 511 and the twelfth connecting line 512 are located between the adjacent first power signal line VGH1 and the start signal line STV.

[0104] The first clock signal line XCK1 and the second clock signal line XCK2 can be connected to two adjacent gate drive circuits GA along the second direction Y, respectively.

[0105] In some embodiments, the clock signal line XCK can be connected to the fourth bottom gate T4G1 and the fourth top gate T4G2 to input a clock signal to the control terminal of the fourth transistor T4.

[0106] In addition, the clock signal line XCK is connected to the fourth plate C12 so that the first plate C1 is connected to the clock signal.

[0107] The third power supply signal line VGL1 is connected to the shielding top gate TsdG2, and the shielding top gate TsdG2 is connected to the shielding bottom gate TsdG1 through the sixth connection line 56, so as to input the third power supply signal, i.e., low level potential, to the control terminal of the shielded transistor Tsd.

[0108] The first power signal line VGH1 is connected to the first active part T1A, the third active part T3A and the switching active part Ts to input the first power signal, i.e., the high-level potential, to the first source-drain terminal of the first transistor T1, the first source-drain terminal of the third transistor T3 and the first source-drain terminal of the switching transistor Ts.

[0109] The start signal line STV can be connected to the first bottom gate T1G1, the first top gate T1G2, the third bottom gate T3G1, and the third top gate T3G2. At the same time, the fourth active part T4A is connected to the first bottom gate T1G1, the first top gate T1G2, the third bottom gate T3G1, and the third top gate T3G2 through the first connecting line 51 to input a start signal to the first source-drain terminal of the fourth transistor T4.

[0110] The second connection line 52 is connected to the third active part T1A, the first electrode plate C11, the second top gate T2G1, the second bottom gate T2G2, the switch bottom gate TsG1, and the switch top gate TsG2, and the potential on the second connection line 52 can be regarded as the potential of the second node N2.

[0111] The third connection line 53 is connected between the fourth active part T4A and the shielded active part TsdA, and the potential on the third connection line 53 can be regarded as the potential of the third node N3.

[0112] The fourth connection line 54 is connected to the first active part T1A, the second active part T2A, the first output bottom gate T01G1, and the second plate C21, and the potential on the fourth connection line 54 can be regarded as the potential on the first node N1.

[0113] The fifth connection line 55 is connected to the second active part T2A and the shielding top gate TsdG2; then the second active part T2A and the third power signal line VGL1 can be connected through the shielding top gate TsdG2 and the fifth connection line 55 to input a low level potential to the second active part T2A.

[0114] The sixth connection line 56 is connected to the shielded top gate TsdG2 and the shielded bottom gate TsdG1, so that both the top and bottom gates of the shielded transistor Tsd are electrically connected to the third power supply signal line VGL1 to input a low-level potential to the control terminal of the shielded transistor Tsd.

[0115] The seventh connection line 57 is connected to the shielded active part TsdA, the second output bottom gate T02G1, the second output top gate T02G2 and the third plate C31, and the potential on the seventh connection line 57 can be regarded as the potential on the fourth node N4.

[0116] The eighth connection line 58 is connected to the sixth electrode plate C32 and the first connection line 51 in the adjacent gate drive circuit GA. Since the sixth electrode plate C32 is connected to the signal output terminal Gout and is integrally formed, the eighth connection line 58 can be used to transmit the output signal of the current gate drive circuit GA to the next stage gate drive circuit GA to realize the cascade transmission of signals. Specifically, the eighth connection line 58 in the current gate drive circuit GA is connected to the first connection line 51 in the next stage gate drive circuit GA, so that the signal output terminal Gout of the current gate drive circuit GA can be used as the start signal in the next stage gate drive circuit GA, and input to the control terminal of the first transistor T1, the control terminal of the third transistor T3 and the first source-drain terminal of the fourth transistor T4 in the next stage gate drive circuit GA, that is, input to the fourth active part T4A, the first bottom gate T1G1, the first top gate T1G2, the third bottom gate T3G1 and the third top gate T3G2.

[0117] For example, in multiple cascaded gate drive circuits GA, the control terminals of the first transistor T1, the third transistor T3, and the first source-drain terminals of the fourth transistor T4 in the first-stage gate drive circuit GA can be connected to the start signal line STV. The control terminals of the first transistor T1, the third transistor T3, and the first source-drain terminals of the fourth transistor T4 in the gate drive circuits GA from the second stage onwards are connected to the eighth connection line 58 in the previous-stage gate drive circuit GA, and the signal output terminal Gout of the previous-stage gate drive circuit GA can be used as the start signal.

[0118] Each gate drive circuit GA corresponds to at least one ninth connection line 59, and the ninth connection line 59 is connected to the first output active part T01A and the second power signal line VGH2, so as to input the high level potential in the second power signal line VGH2 to the first output active part T01A.

[0119] The tenth connection line 510 is connected to the first output active part T01A and the signal output terminal Gout to transmit the signal in the first output active part T01A to the signal output terminal Gout.

[0120] The eleventh connection line 511 is connected to the second output active part T02A and the fourth power signal line VGL2 to input the low-level potential in the fourth power signal line VGL2 to the second output active part T02A.

[0121] The twelfth connecting line 512 is connected to the second output active section T02A and the signal output terminal Gout, so as to transmit the signal in the second output active section T02A to the absorbed output terminal Gout.

[0122] As mentioned above, in the film layer stack of the gate driving circuit GA provided in this application embodiment, the first power signal line VGH1 partially overlaps with the signal output module 200 along the thickness direction of the display panel, and the second power signal line VGH2 partially overlaps with the signal output module 200 along the thickness direction of the display panel. Since the load in the power signal line is relatively high, the width of the power signal line is relatively large. However, in this application embodiment, both the first power signal line VGH1 and the second power signal line VGH2 are set to partially overlap with the signal output module 200, which can reduce the space occupied by the gate driving circuit GA and help to achieve a narrow bezel of the display panel.

[0123] In some embodiments, in a top view, the first power signal line VGH1 is located between the signal generation module 100 and the second power signal line VGH2, while the second power signal line VGH2 is located between the first power signal line VGH1 and the signal output terminal Gout of the signal output module 200. This facilitates the connection between the first power signal line VGH1 and the thin-film transistor in the signal generation module 100, and also prevents the first power signal line VGH1 and the second power signal line VGH2 from exceeding the range of the gate drive circuit GA, thereby saving space and facilitating the narrow bezel design of the display panel.

[0124] It is understandable that the above top view can be considered as a top view obtained from the perspective along the thickness direction of the display panel.

[0125] In summary, this embodiment transmits signals to the first power signal line VGH1 and the second power signal line VGH2 through different bonding terminals 11, thereby avoiding the influence of signal fluctuations in the first power signal line VGH1 on the signal transmission of the second power signal line VGH2, and improving the signal transmission stability of the second power signal line VGH2. Furthermore, this embodiment sets the first power signal line VGH1 and the second power signal line VGH2 in different layers, and respectively in the first conductive layer 50 and the second conductive layer 60, further increasing the spacing between the first power signal line VGH1 and the second power signal line VGH2, further reducing the probability that signal fluctuations in the first power signal line VGH1 will affect the signal transmission of the second power signal line VGH2, and improving the stability of the output signal of the signal output module 200.

[0126] In addition, this application embodiment also provides a display device, which includes a display panel as described in the above embodiments.

[0127] In some embodiments, the display device includes a mobile phone, tablet, television, computer, wearable device, virtual reality display device, etc.

[0128] It is understood that since the display device has the same display panel as in the above embodiments, the display device has the same beneficial effects as in the above embodiments, which will not be repeated here.

[0129] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0131] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0132] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a gate driving circuit and a plurality of bonding terminals electrically connected to the gate driving circuit. The gate driving circuit includes a signal generation module and a signal output module electrically connected to each other. The display panel further includes a first power signal line connected to the signal generation module and a second power signal line connected to the signal output module. The first power signal line and the second power signal line are configured to transmit a high-level signal, and the first power signal line and the second power signal line are respectively connected to different bonding terminals.

2. The display panel of claim 1, wherein, The signal generation module includes a first control module, which and the signal output module are both connected to a first node. The first control module is connected to the first power signal line.

3. The display panel of claim 2, wherein, The first control module includes a first transistor and a second transistor, and the signal output module includes a first output transistor; The first source-drain terminal of the first transistor is connected to the first power signal line, the first source-drain terminal of the first output transistor is connected to the second power signal line, the first source-drain terminal of the second transistor is connected to the third power signal line, the second source-drain terminal of the first transistor, the second source-drain terminal of the second transistor, and the control terminal of the first output transistor are all connected to the first node, and the third power signal line is configured to transmit a low-level signal.

4. The display panel of claim 2, wherein, The signal generation module further includes a second control module and a voltage regulator module. The first control module, the second control module, and the voltage regulator module are all connected to the second node. The second control module and the voltage regulator module are both connected to the first power signal line.

5. The display panel of claim 4, wherein, The second control module includes a third transistor, and the voltage regulator module includes a switching transistor; The first source-drain terminal of the third transistor and the first source-drain terminal of the switching transistor are both connected to the first power signal line. The second source-drain terminal of the third transistor and the control terminal of the switching transistor are both connected to the second node of the first control module.

6. The display panel of claim 4, wherein, The signal generation module further includes a third control module and a shielding module. Both the third control module and the shielding module are connected to the voltage regulator module, and the shielding module is also connected to the signal output module. The third control module includes a fourth transistor, the shielding module includes a shielding transistor, and the signal output module includes a second output transistor. The first source-drain terminal of the fourth transistor is connected to the start signal line. The second source-drain terminal of the fourth transistor, the first source-drain terminal of the shielding transistor, and the voltage regulator module are all connected to the third node. The second source-drain terminal of the shielding transistor and the control terminal of the second output transistor are both connected to the fourth node. The control terminal of the shielding transistor is connected to the third power signal line, and the first source-drain terminal of the second output transistor is connected to the fourth power signal line. Both the third and fourth power signal lines are configured to transmit low-level signals.

7. The display panel of any one of claims 1 to 6, wherein, The first power signal line partially overlaps with the signal output module along the thickness direction of the display panel, and the second power signal line partially overlaps with the signal output module along the thickness direction of the display panel.

8. The display panel of any one of claims 1 to 6, wherein, In the top view, the first power signal line is located between the signal generation module and the second power signal line, and the second power signal line is located between the first power signal line and the signal output terminal of the signal output module.

9. The display panel of any one of claims 1 to 6, wherein, The display panel includes at least two conductive layers disposed along the thickness direction of the display panel, and the first power signal line and the second power signal line are located in the same conductive layer, or the first power signal line and the second power signal line are located in different conductive layers.

10. A display device, characterized by comprising: The display device includes a display panel as described in any one of claims 1 to 9.

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