Black field time compensation circuit based on binary coding, constant current driving chip and display system

Abstract

The application relates to a black field time compensation circuit, a constant current driving chip, a display system and a black field time compensation method. The black field time compensation circuit comprises a first configuration module, a second configuration module, an encoding module, a comparison module and a compensation module. The second configuration module is used for configuring an optimization coefficient and a compensation step length of a black field time to be compensated; the encoding module is used for encoding the serial numbers of display groups, and obtaining the encoding numbers corresponding to each display group; the comparison module is used for comparing the encoding numbers with the optimization coefficient; and the compensation module is configured to: in one frame display period, if the encoding number of the display group corresponding to each line scanning is less than or equal to the optimization coefficient, the number of clock periods contained in the initial line period of the display group is added by the compensation step length, otherwise, the initial line period remains unchanged. The scheme of the application can avoid the actual refresh rate from being reduced due to the black field between frames and ensure that the refresh rate in the group is consistent, thereby improving the display effect.

Description

[0001] This invention is a divisional application of patent application No. 202510672941.8, filed on May 23, 2025, entitled "Black Time Compensation Circuit, Constant Current Drive Chip, Display System and Black Time Compensation Method". Technical Field

[0002] This application relates to the field of display technology, and in particular to a black screen time compensation circuit, a constant current drive chip, a display system, and a black screen time compensation method. Background Technology

[0003] When a display screen is used, it typically displays the video frame by frame. The frame display time is determined by the video source frame rate. For example, if the video source frame rate is 60Hz, then the frame display time is approximately 16.6ms.

[0004] Meanwhile, displays are typically driven by constant current driver chips. For some constant current driver chips (such as those used in transparent screens), automatic line wrapping is required internally. Therefore, the driving time for a single row of LEDs by this type of constant current driver chip is an integer multiple of the clock cycle (DCLK). Assuming one clock cycle is T, the number of line scans on the display is N, the number of display groups is M, and the driving time (line cycle) for a single row of LEDs by the constant current driver chip is K*T, then the time to display one frame is M*N*K*T. This time, M*N*K*T, must be less than the frame display time determined by the video source frame rate (e.g., 16.6ms).

[0005] However, since the clock cycle is usually discrete and discontinuous, the driving time for all LED beads, M*N*K*T, will not be very close to a display frame time (e.g., 16.6ms) in some applications. The difference between the two is the inter-frame black screen time. The existence of the inter-frame black screen time will cause the actual refresh rate to be lower when displaying the last line of the last display group, thus affecting the display effect. Summary of the Invention

[0006] Therefore, it is necessary to provide a binary-encoded black field time compensation circuit, a constant current drive chip, and a display system that can improve the display effect, addressing the aforementioned technical problems.

[0007] On one hand, this application provides a blackout time compensation circuit, applied to a constant current drive chip for a display screen, comprising: The first configuration module is used to configure the initial line cycle of the display screen; The second configuration module is used to configure the optimization coefficient and compensation step size for the black screen time to be compensated. The encoding module is used to convert the sequence numbers of M display groups into M initial q-bit binary numbers, and to reverse the order of each initial q-bit binary number to form M encoded numbers; The comparison module is used to compare the number of codes with the optimization coefficients; The compensation module is configured to: within a frame display period, if the number of codes in the display group corresponding to each line scan is less than or equal to the optimization coefficient, add the number of clock cycles contained in the initial line period of the display group to the compensation step size; if the number of codes is greater than the optimization coefficient, keep the initial line period of the display group unchanged. The display screen has N rows, and one frame is divided into M display groups. The i-th display group has an index T. i Let i be a positive integer in the range [1, M], the compensation step size be k1, and the number of clock cycles included in the black field time to be compensated be P1. <k1*M*N。

[0008] In some implementations, k1=1.

[0009] In some implementations, k1 is an integer greater than 1.

[0010] In some implementations, the optimization coefficient is equal to A⁻¹; where A is P₁ divided by k. 1* The quotient obtained from N.

[0011] In some implementations, the number of clock cycles P1 included in the blackout time to be compensated is obtained from the control card.

[0012] Secondly, this application provides a constant current driving chip, which includes the black screen time compensation circuit of any of the foregoing.

[0013] Thirdly, this application provides a display system comprising: Display screen; The constant current driving chip described in the second aspect is used to drive the display screen; The control card is connected to the aforementioned constant current drive chip and is used to control the aforementioned constant current drive chip.

[0014] In some implementations, the control card is also used to obtain the initial black screen time of the display screen, and to send the remainder obtained by dividing the number of clock cycles P2 included in the initial black screen time by k1*M*N as the number of clock cycles P1 included in the black screen time to be compensated to the constant current drive chip.

[0015] In some implementations, the control card compensates the original row cycle to obtain an initial row cycle, which includes (K+k1*C) clock cycles; where C is the quotient obtained by dividing the number of clock cycles P2 included in the initial black screen time by k1*M*N; and K is the number of clock cycles included in the original row cycle.

[0016] The aforementioned binary-encoded black screen time compensation circuit, constant current drive chip, and display system configure optimization coefficients and compensation step sizes for the black screen time to be compensated, encode the sequence number of the display groups, and obtain the code number corresponding to each display group. Simultaneously, by comparing the code number with the optimization coefficients, a subset of display groups are selected from multiple display groups on the screen for line period compensation. This distributes the black screen time to be compensated to the line period of each row of LEDs in each selected display group, thereby reducing the inter-frame black screen time and avoiding the refresh rate drop problem when displaying the last line of a frame, thus improving the display effect. Furthermore, by comparing the code number with the optimization coefficients, this application effectively disperses the distribution of the selected display groups across all display groups, facilitating the relatively even selection of a subset of display groups from multiple display groups, rather than concentrating them in consecutively numbered display groups, thereby further improving the display effect.

[0017] Meanwhile, in this application, for the display groups selected according to the number of codes, since the initial row period of these display groups is compensated in the same way when displaying the display groups corresponding to the number of codes from row 1 to row N, the refresh rate within the group is consistent when displaying these display groups (for example, displaying all subframes i from row 1 to row N), thereby further improving the display effect. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a block diagram of the system shown in one embodiment; Figure 2 This is a block diagram of a black screen time compensation circuit in one embodiment; Figure 3a This is a partial structural diagram of a display system in one embodiment; Figure 3b This is a schematic diagram illustrating the display timing of multiple sub-frames of a single display frame in one embodiment; Figure 4 This is a schematic diagram of the corresponding table of optimization coefficients in one embodiment; Figure 5 This is a flowchart of a black screen time compensation method in one embodiment.

[0020] Explanation of reference numerals in the attached figures: 100 - Display screen, 200 - Constant current drive chip, 300 - Control card, 10 - First configuration module, 20 - Second configuration module, 30 - Encoding module, 40 - Comparison module, 50 - Compensation module. Detailed Implementation

[0021] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0023] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another.

[0024] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0025] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0026] In one embodiment, see Figure 1 A display system is provided, including a display screen 100, a constant current drive chip 200, and a control card 300.

[0027] The display screen 100 may be, but is not limited to, a transparent screen.

[0028] The constant current driver chip 200 is used to drive the display screen 100.

[0029] To improve the refresh rate, the display screen 100 can use a grouped display method. When using grouped display, one frame of image is divided into M subframes (i.e., M display groups). The sum of the grayscale values ​​of all subframes equals the total grayscale value of that frame. The total grayscale value corresponds to the brightness of the LEDs. See Figure 3; for a given LED, its total grayscale value corresponds to its brightness. Subframe T1, subframe T2, ..., subframe T... M The sum of the gray levels equals the total gray value. When displaying a frame, it is displayed line by line, subframe by subframe. Please refer to [link / reference]. Figure 3a and Figure 3b Taking a common anode display screen, scanning line by line starting from the first row and using a grouped display method as an example, when displaying one frame, the display order is: subframe T1 of row 1, subframe T1 of row 2, ..., subframe T1 of row N, subframe T2 of row 1, subframe T2 of row 2, ..., subframe T2 of row N, ..., subframe T1 of row 1 M , second row subframe T M Nth row subframe T M The specific display process is as follows: First, subframe T1 of the first row is displayed. The horizontal output transistor for the first row is turned on, while the transistors for the other rows remain off. This provides anode power to the LEDs in the first row, and each constant current driver chip 200 is activated based on the displayed data (grayscale value of subframe T1), providing constant current to the LEDs connected to its constant current output channel, thus illuminating the LEDs. The duration of LED illumination depends on the grayscale value of that subframe.

[0030] After the first line is displayed, the second subframe T1 begins to be displayed. The horizontal output transistor for the second line is turned on, while the horizontal output transistors for the other lines are turned off. The constant current driver chip outputs a constant current to light up the LEDs in the second line based on the displayed data (the grayscale value of the second subframe T1).

[0031] After displaying subframe T1 in this manner, begin displaying subframes T2, ..., T1 in the same way. M Once all subframes have been displayed, the current frame is complete. This process constitutes one complete frame display cycle.

[0032] In this application, the LEDs are displayed line by line and frame by frame based on the above method. The driving time for a line of LEDs is an integer multiple of the clock cycle. The driving time of the constant current driver chip 200 for a line of LEDs is the line cycle.

[0033] The control card 300 is connected to the constant current drive chip 200 and is used to control the constant current drive chip 200.

[0034] The control card 300 can send clock cycles to the constant current driver chip 200. The frequency of the clock cycles sent by the control card 300 to the constant current driver chip 200 can be a series of commonly used values, such as 8MHz, 8.5MHz, and 9MHz. That is, the frequency selection is discrete and discontinuous. Therefore, the selection of the clock cycle is also discrete and discontinuous, which may lead to inter-frame blackout periods between adjacent frames.

[0035] Meanwhile, the constant current driver chip 200 includes a black screen time compensation circuit. The black screen time compensation circuit is used to compensate the black screen time to be compensated in the inter-frame black screen time to the initial line period corresponding to the relevant display group, thereby reducing the inter-frame black screen time.

[0036] In one embodiment, the control card 300 is also used to acquire the initial black screen time of the display screen 100. Simultaneously, the control card 300 uses the remainder obtained by dividing the number of clock cycles P2 included in the initial black screen time by k1*M*N as the black screen time to be compensated and sends it to the constant current driver chip 200. Here, N is the number of line scans of the display screen 100, M is the number of display groups (i.e., subframes) into which one frame of image is divided, and the sequence number of the i-th display minute in these M display groups is T. i , where i is a positive integer in the range [1, M]. For example, the M display groups are numbered T1, T2, ..., T... M That is, in this application, for each LED, the M subframes into which one frame of the image is divided are numbered T1, T2, ..., T... M k1 is the compensation step size, and k1 is an integer greater than or equal to 1. The compensation step size is the number of clock cycles used to compensate the initial row period in the relevant display group of each row of LEDs.

[0037] For example, the initial black time t1 of the display screen 100 can be the original inter-frame black time.

[0038] Assuming the time of one clock cycle is T, the number of rows scanned by the display screen 100 is N, and the number of display groups is M, then the original row cycle (driving time for one row of LEDs) in the constant current driver chip 200 of each display group of the display screen 100 is K*T. Therefore, the original driving time for all display groups of all LEDs is M*N*K*T. Here, K is a positive integer.

[0039] At this point, the initial black screen time t1 of the display screen 100 can be calculated by subtracting the original inter-frame black screen time obtained by M*N*K*T from the display frame time t2. The display frame time can be determined based on the video source frame rate. For example, if the video source frame rate is 60Hz, then the display frame time t2 is equal to 1 / 60, approximately 16.6ms.

[0040] The number of clock cycles P2 included in the initial blackout time t1 can be the quotient B obtained by dividing t1 by T, where T is the time of one clock cycle.

[0041] Simultaneously, dividing P2 (the number of clock cycles included in the initial blackout time t1) by k1*M*N yields a quotient C (an integer) and a remainder. After calculating this remainder using the above method, the control card 300 sends it as the number of clock cycles P1 included in the blackout time to be compensated to the constant current driver chip 200, thereby enabling the constant current driver chip 200 to compensate for the blackout time (or the number of clock cycles P1 included). Furthermore, since P1 is the remainder of P2 divided by k1*M*N, therefore, P1... <k1*M*N。

[0042] It is understandable that at this point, the clock cycle number P2 included in the initial black time (the original inter-frame black time) can be divided into two parts: one part is k1*M*N*C, and the other part is the black time to be compensated.

[0043] For example, the original row cycle of the display 100 may include K clock cycles.

[0044] The control card 300 can allocate and add the k1*M*N*C portion of the initial black screen time (the original inter-frame black screen time) to the M*N original line cycles corresponding to one frame of image (one line cycle corresponds one-to-one with one display group / subframe), thereby forming the initial line cycle of the display screen 100 that needs to be configured in the constant current driver chip 200. This initial line cycle includes (K+k1*C) clock cycles. The compensation step size k1 can be 1 or an integer greater than 1, which can be set according to actual needs. Please refer to [link to relevant documentation]. Figure 3b That is, the N display groups T1 corresponding to rows 1 to N, the N display groups T2 corresponding to rows 1 to N, ..., the N display groups T1 corresponding to rows 1 to N. M Each of the corresponding M*N original row cycles is compensated for k1*C clock cycles.

[0045] In this embodiment, the control card 300 and the constant current driver chip 200 compensate for different parts of the initial black field time. The control card 300 undertakes part of the calculation, so the constant current driver chip 200 does not need to perform too much calculation, thereby effectively reducing the power consumption of the constant current driver chip 200.

[0046] In one embodiment, see Figure 2 The black screen time compensation circuit includes a first configuration module 10, a second configuration module 20, an encoding module 30, a comparison module 40, and a compensation module 50.

[0047] The first configuration module 10 is used to configure the initial line cycle of the display screen 100.

[0048] For example, referring to the above embodiments, the initial row cycle may include (K+k1*C) clock cycles, where K is the number of clock cycles included in the original row cycle of the display screen 100.

[0049] The second configuration module 20 is used to configure the optimization coefficient and compensation step size for the black field time to be compensated.

[0050] The optimization coefficient for the black screen time to be compensated determines the number of display groups selected for compensation. This optimization coefficient can be determined based on the number of clock cycles P1 included in the black screen time to be compensated, the compensation step size k1, and the number of line scans N. Wherein, P1... <k1*M*N。

[0051] The compensation step size k1 can be configured as 1 or as an integer greater than 1.

[0052] The encoding module 30 is used to encode the sequence number of the display group and obtain the encoding number corresponding to each display group.

[0053] Display the group numbers T1, T2, ..., T M It can be a sequence number that starts from 0 and increments by 1.

[0054] For example, the value of the display group number M is 8, meaning there are 8 display groups. The sequence numbers of these 8 display groups can be 0, 1, 2, 3, 4, 5, 6, 7, which are T1, T2, ..., T... (as mentioned earlier). M The numbers are 0, 1, 2, 3, 4, 5, 6, and 7 in sequence. At this point, the encoding module 30 can encode 0, 1, 2, 3, 4, 5, 6, and 7 to obtain the code number corresponding to each of the eight display groups. Please refer to [link / reference needed]. Figure 3b The sum of the sub-grayscale values ​​of subframes T1, T2, ..., T8 corresponding to any row is the total grayscale value, and the sequence numbers of each subframe are 0, 1, ..., 7, respectively. Therefore, in this application, if the number of subframes into which a frame is divided is determined, the sequence number of each subframe is determined, and the number of codes is then determined based on the subframe sequence number.

[0055] The comparison module 40 is used to compare the number of codes with the optimization coefficients. The comparison module 40 may include a comparator, etc.

[0056] The compensation module 50 is configured as follows: within a frame display period, if the number of codes of the display group corresponding to each line scan is less than or equal to the optimization coefficient, the number of clock cycles contained in the initial line period of the display group is increased by the compensation step size; if the number of codes of the display group corresponding to each line scan is greater than the optimization coefficient, the initial line period of the display group remains unchanged.

[0057] When the number of codes in a display group is less than or equal to the optimization coefficient, the number of clock cycles contained in the initial line period of the display group can be increased by a compensation step size. For example, if the number of clock cycles contained in the initial line period is (K+k1*C), then (K+k1*C) can be increased by a compensation step size k1, so that after compensation, the number of clock cycles contained in the final line period of the display group is (K+k1*C+k1).

[0058] In this application, if it is determined that the subframe corresponding to the encoding number needs to be compensated based on the encoding number, then within a frame display period (for example, scanning from the first row subframe T1 row by row and subframe by subframe to the Nth row subframe TM), all rows of subframes corresponding to the encoding number need to be compensated.

[0059] Based on the preceding description of line-by-line and sub-frame-by-subframe display and a frame display cycle, it can be known that a frame display cycle consists of M*N line scans, for example, Figure 3b In the middle, subframe T1 is displayed sequentially from the first row to the Nth row, subframe T2 is displayed sequentially from the first row to the Nth row, and so on, until subframe T is displayed sequentially from the first row to the Nth row. M In this application, within a frame display period, for these M*N line scans, if it is determined that the number of codes corresponding to the sequence number of a display group for a certain line scan is less than or equal to the optimization coefficient, then compensation will be applied to that display group. Since the total grayscale value of each LED is divided into M display groups, i.e., M sub-grayscale values, for each LED, the sequence numbers of its M display groups are T1, T2, ..., T... M Therefore, within a frame display cycle, if a certain sequence number (or code number) is selected, all display groups corresponding to that sequence number (or code number) will be compensated.

[0060] See Figure 3b Taking N scans and a frame divided into M display groups (subframes) as an example, all rows have the same subframe i with the same sequence number and the same number of codes. For example, the sequence number of all subframes T1 is 0, and the sequence number of all subframes T... M The sequence number is M-1. Therefore, using the compensation method of this application, if the number of codes corresponding to sequence number G is less than or equal to the optimization coefficient, then in one frame display period, compensation is performed on all display groups with sequence number G. For example, see... Figure 3b If the number of codes corresponding to the first display group (corresponding to the first subframe T1) is less than or equal to the optimization coefficient, then when displaying the display group (T1) sequentially from the first row to the Nth row, the number of clock cycles contained in the initial row period corresponding to all display groups T1 is increased by the compensation step size k1.

[0061] Therefore, in this application, for a frame display period, if it is determined that the line period corresponding to a display group with a certain sequence number (or code number) needs to be compensated, the actual compensation is made for the line period corresponding to all display groups with that sequence number within the frame display period.

[0062] When the number of codes in a display group is greater than the optimization factor, the number of clock cycles contained in the initial line period of the display group can be kept unchanged. For example, if the number of clock cycles contained in the initial line period is (K+k1*C), then the number of clock cycles contained in the final line period of the display group will be (K+k1*C).

[0063] In this application, an image frame is divided into multiple display groups (M groups), and each display group has an independent code number. The code number of some display groups is less than or equal to the optimization coefficient, while the code number of some display groups is greater than the optimization coefficient.

[0064] In the black screen time compensation circuit of this embodiment, the optimization coefficient and compensation step size of the black screen time to be compensated are configured by the second configuration module 20, and the sequence number of the display group is encoded by the encoding module 30 to obtain the encoding number corresponding to each display group. Simultaneously, the comparison module 40 compares the encoding number with the optimization coefficient, thereby selecting a portion of the display groups from the multiple display groups of the display screen 100 for line period compensation. This disperses the black screen time across the display groups, reducing the inter-frame black screen time and avoiding the problem of reduced actual refresh rate due to excessive inter-frame black screen when displaying the last line of the last subframe of a certain frame, thus improving the display effect. Furthermore, in this embodiment, by comparing the encoding number and the optimization coefficient, the distribution of the selected display groups across all display groups is effectively dispersed, and the compensation is not concentrated in display groups with consecutive sequence numbers, thereby further improving the display effect.

[0065] Meanwhile, in this embodiment, for a frame display period, if it is determined that the line period corresponding to a display group with a certain sequence number (or code number) needs to be compensated, the actual compensation is performed on the line periods corresponding to all display groups with that sequence number within the frame display period. That is, within a frame display period, the number of clock cycles contained in the initial line period of all display groups corresponding to a selected sequence number is increased by a compensation step size k1. This ensures that when displaying the display group from line 1 to line N (for example, during the display of all subframes T1 within a frame period), the refresh rate is consistent, thus guaranteeing a consistent refresh rate within the display group and further improving the display effect.

[0066] In one embodiment, the second configuration module 20 is configured to divide the black screen time P1 to be compensated by k. 1*The quotient A obtained from N determines the optimization coefficient. A*N is the maximum number of selectable display groups. In practical applications, the number of selected groups varies depending on the selection algorithm. In the following text, when the data obtained after reversing is directly used as the code number, the preferred number of compensated groups is A*N. When the highest s bits of the data obtained after reversing are used as the code number, if A is even, the preferred number of compensated groups is A*N; if A is odd, then an even number is taken down from A. For example, if A=5, then the number of compensated groups is 4*N.

[0067] Optionally, the compensation step size can be set to 1. Then, the second configuration module 20 can be configured to determine the optimization coefficients based on the quotient A obtained by dividing the black screen time P1 by N.

[0068] At this point, optimization coefficients can be configured quickly.

[0069] In one embodiment, the encoding module 30 is used to convert the sequence numbers of the M display groups into M initial q-bit binary numbers, and to reverse the order of each initial q-bit binary number to form M encoded numbers, wherein the q value is determined according to the number of binary bits of the M value.

[0070] For example, the row sweep number N is 12, and the display group number M is 8. Since 8 has 3 bits in binary, the value of q is 3.

[0071] At this point, the display group number M is 8, meaning there are 8 display groups. The sequence numbers of the 8 display groups are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. The encoding module 30 converts 0, 1, 2, 3, 4, 5, 6, and 7 into 8 initial 3-bit binary numbers. The 8 initial 3-bit binary numbers are 000, 001, 010, 011, 100, 101, 110, and 111. The 8 3-bit binary numbers after reversing the order are 000, 100, 010, 110, 001, 101, 011, and 111. These 8 3-bit binary numbers form 8 encoded numbers. The values ​​represented by these 8 encoded numbers are 0, 4, 2, 6, 1, 5, 3, and 7, respectively.

[0072] At this point, the optimization coefficient can be selected from 0 to 7. For example, the specific value of the optimization coefficient is related to the aforementioned quotient A, and can be A-1. When the number of codes corresponding to a display group is less than or equal to the optimization coefficient, the display group corresponding to that number of codes is selected and subjected to row period compensation, with a compensation step size of k1.

[0073] For example, if the optimization coefficient is 0 and the only display group with a coding number less than or equal to the optimization coefficient is the first group, then the number of clock cycles contained in the initial row cycle of the first display group is increased by k1.

[0074] For example, if the optimization coefficient is 1, then the display groups with a coding number less than or equal to the optimization coefficient are the first display group and the fifth display group. Then, the number of clock cycles contained in the initial line period corresponding to the first display group and the initial line period corresponding to the fifth display group are both increased by k1.

[0075] In one embodiment, the encoding module 30 is used to convert the sequence numbers of the M display groups into M initial q-bit binary numbers, and to reverse the order of each initial q-bit binary number. Then, for the reversed M q-bit binary numbers, the high s bits are selected to generate M s-bit binary numbers to form M encoded numbers, wherein the q value is determined according to the number of binary bits of the M value.

[0076] The optimization coefficient is less than or equal to 2 s -1.

[0077] For example, the row sweep number N is 12, and the display group number M is 8. Also, 8 has 3 bits in binary. Therefore, the value of q is 3. And in this case, s takes a value less than or equal to 3. For example, s takes 2. Therefore, the optimization coefficient is less than or equal to 2. 2 -1 means less than or equal to 3.

[0078] At this point, the display group number M is 8, meaning there are 8 display groups. The sequence numbers of the 8 display groups are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. The encoding module 30 converts 0, 1, 2, 3, 4, 5, 6, and 7 into 8 initial 3-bit binary numbers. The 8 initial 3-bit binary numbers are 000, 001, 010, 011, 100, 101, 110, and 111. Then, the 8 initial 3-bit binary numbers are reversed to form M q-bit binary numbers. The 8 reversed 3-bit binary numbers are 000, 100, 010, 110, 001, 101, 011, and 111. The high 2 bits of the 8 reversed 3-bit binary numbers are taken to generate 8 2-bit binary numbers. These 8 2-bit binary numbers are 00, 10, 01, 11, 00, 10, 01, and 11. These eight 2-bit binary numbers form eight encoded numbers. These eight encoded numbers represent the values ​​0, 2, 1, 3, 0, 2, 1, and 3, respectively.

[0079] If the optimization coefficient is 0, then the encoding number of the first display group is 0, and the encoding number of the fifth display group is 0, which is less than or equal to the optimization coefficient. In the display process of one frame (for example, starting from the first row subframe T1, the second row subframe T1, ..., the Nth row subframe T1 are displayed sequentially),... MThe number of clock cycles in the initial row period of all subframes with sequence numbers 0 and 4 (i.e., subframe T1 and subframe T5) is increased by a compensation step size k1. When k1 is 1, the number of clock cycles in the initial row period of subframes T1 and T5 is increased by 1.

[0080] If the optimization coefficient is 1, then the encoding number of the first display group (0), the encoding number of the third display group (1), the encoding number of the fifth display group (0), and the encoding number of the seventh display group (3) are all less than or equal to the optimization coefficient. Therefore, during the display of one frame (for example, starting from the first row subframe T1, and sequentially displaying the second row subframe T1, ..., the Nth row subframe T1...),... M The number of clock cycles in the initial row period of all subframes with serial numbers 0, 2, 4, and 6 (i.e., subframes T1, T3, T5, and T7) is increased by a compensation step size k1. When k1 is 1, the number of clock cycles in the initial row period of each of these four display groups is increased by 1.

[0081] If the optimization coefficient is 2, then the encoding number of the first display group (0), the encoding number of the second display group (2), the encoding number of the third display group (1), the encoding number of the fifth display group (0), the encoding number of the sixth display group (2), and the encoding number of the seventh display group (3) are all less than or equal to the optimization coefficient. Therefore, during the display of one frame (for example, starting from the first row subframe T1, sequentially displaying the second row subframe T1, ..., the Nth row subframe T...),... M The number of clock cycles in the initial row period of all subframes numbered 0, 1, 2, 4, 5, and 6 (i.e., subframes T1, T2, T3, T5, T6, and T7) is increased by a compensation step size k1. When k1 is 1, the number of clock cycles in the initial row period of each of these six display groups is increased by 1.

[0082] If the optimization coefficient is 3, then the number of codes for all display groups is less than or equal to the optimization coefficient. Therefore, the number of clock cycles contained in the initial line period for all display groups (all subframes) is increased by a compensation step size k1. When k1 is 1, the number of clock cycles contained in each initial line period within all display groups is increased by 1.

[0083] In this embodiment, the encoding module 30 obtains the encoded number by converting binary values ​​into encoding, which can achieve a uniform distribution of the selected display group among all groups, thereby effectively improving the display effect.

[0084] In one embodiment, the second configuration module 20 is used to... When the configuration optimization coefficient is b iThat is, the second configuration module 20 is used to ensure that the value of the number of clock cycles P1 included in the black field time to be compensated is greater than or equal to a. i *N*k1, and less than a i+1 When *N*k1, the configuration optimization coefficient is b. i .

[0085] Among them, a i For less than or equal to b i The number of codes, a i+1 For less than or equal to b i The number of +1 codes, 0≤b i ≤2 s -2. Where less than or equal to b i The number of codes, i.e., the optimization coefficient is b. i When [the number of groups is displayed], you can optionally show the number of groups.

[0086] Specifically, the following explanation uses an example where the row scan number N is 12, the display group number M is 8, q is 3, s is 2, and the compensation step size is 1. Referring to the aforementioned embodiments and... Figure 4 The table shown below: Assuming the optimization coefficient is 0, the number of codes less than or equal to 0 is 2, and the number of codes less than or equal to (0+1) is 4. Therefore, the optimization coefficient is 0 when P1 satisfies 2*12≤P1<4*12.

[0087] Assuming the optimization coefficient is 1, the number of codes less than or equal to 1 is 4, and the number of codes less than or equal to (1+1) is 6. Therefore, the optimization coefficient is 1 when P1 satisfies 4*12≤P1<6*12.

[0088] Assuming the optimization coefficient is 2, the number of codes less than or equal to 2 is 6, and the number of codes less than or equal to (2+1) is 8. Therefore, the optimization coefficient is 2 when P1 satisfies 6*12≤P1<8*12.

[0089] Assuming the optimization coefficient is 3, the number of codes less than or equal to 3 is 8. Therefore, the optimization coefficient is 3 when P1 satisfies 8*12≤P1.

[0090] In this embodiment, binary numerical conversion encoding can be used to form Figure 4 The contents of columns A and B are used to determine the contents of column C. Then, based on the correspondence between columns A and C and the range of the clock cycle number P1 included in the black screen time to be compensated, the optimization coefficient can be quickly configured. For example, if the clock cycle number P1 included in the black screen time to be compensated is 85, and 85 in column C falls within the range of 72 ≤ P < 96, then based on the correspondence between columns A and C, the optimization coefficient can be determined to be 2.

[0091] In other embodiments, such as Figure 4 As shown, the contents of column D can be derived from column C. Column D represents the range of the quotient A obtained by dividing the black time P1 to be compensated by the number of row scans N.

[0092] Therefore, the optimization coefficient can be easily determined by dividing the black field time P1 to be compensated by the number of line scans N.

[0093] For example, the number of clock cycles included in the black screen time to be compensated is P1, which is 85. The quotient A obtained by dividing 85 by 12 is 7, with a remainder of 1. In column D, 7 is between 6 ≤ P / 12 < 8. Therefore, based on the correspondence between columns A and D, the optimization coefficient can be configured as 2.

[0094] Alternatively, the number of clock cycles included in the blackout period to be compensated is P1, which is 85. Dividing 85 by 12 yields a quotient A of 7 with a remainder of 1. Then, in column B, we find the number closest to 7 but less than 7. This number is 6. Based on the correspondence between columns A and B, the optimization coefficient can be configured to 2.

[0095] As can be understood, the specific example above uses a value of 8 for the number of groups M. In actual applications, the number of groups M may be larger, therefore the value q, determined by the number of binary digits of M, may also be larger. In this case, the value s can be selected according to the requirements; that is, there are multiple ways to select the value s. For example, if the value q is 5, the value s can be 2, 3, or 4, etc. When different values ​​of s are selected, the contents of columns A and B as shown in the figure will be different. The specific value of s to be selected can be set according to actual needs.

[0096] In one embodiment, see Figure 5 A black screen time compensation method is also provided, applied to the constant current drive chip 200 of the display screen 100, including: Step S10: Configure the initial line cycle of the display screen 100; Step S20: Configure the optimization coefficient and compensation step size for the black screen time to be compensated; Step S30: Encode the sequence number of the display group to obtain the code number corresponding to each display group; Step S40: Within a frame display period, if the number of codes for the display group corresponding to each line scan is less than or equal to the optimization coefficient, add the number of clock cycles contained in the initial line period of the display group corresponding to the number of codes to the compensation step size; if the number of codes for the display group corresponding to each line scan is greater than the optimization coefficient, keep the initial line period of the display group corresponding to the number of codes unchanged. Wherein, the number of line scans of display screen 100 is N, the number of display groups is M, the compensation step size is k1, and the number of clock cycles included in the black field time to be compensated is P1. <k1*M*N。

[0097] In one embodiment, step S30 includes: Step S31: Convert the sequence numbers of the M display groups into M initial q-bit binary numbers, where the q value is determined based on the number of binary bits in the M value; Step S32: Reverse the order of each initial q-bit binary number; Step S33: For the M q-bit binary numbers arranged in reverse order, select the high s bits to generate M s-bit binary numbers to form M encoded numbers, where s≤q.

[0098] For specific limitations on black screen time compensation methods, please refer to the limitations on black screen time compensation circuits mentioned above, which will not be elaborated further here.

[0099] It should be understood that, although Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0100] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0101] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A black field time compensation circuit based on binary coding, applied to a constant current driving chip of a display screen, characterized in that, include: The first configuration module is used to configure the initial line cycle of the display screen; The second configuration module is used to configure the optimization coefficient and compensation step size for the black screen time to be compensated. The encoding module is used to convert the sequence numbers of M display groups into M initial q-bit binary numbers, and to reverse the order of each initial q-bit binary number to form M encoded numbers; A comparison module is used to compare the number of codes with the optimization coefficients; The compensation module is configured to: within a frame display period, if the number of codes in the display group corresponding to each line scan is less than or equal to the optimization coefficient, add the number of clock cycles contained in the initial line period of the display group to the compensation step size; if the number of codes is greater than the optimization coefficient, keep the initial line period of the display group unchanged. The display screen has N rows, and one frame is divided into M display groups. The i-th display group has an index T. i Let i be a positive integer in the range [1, M], the compensation step size be k1, and the number of clock cycles included in the black field time to be compensated be P1. <k1*M*N。 2. The black frame time compensation circuit according to claim 1, characterized by, k1=1。 3. The black frame time compensation circuit of claim 1, wherein, k1 is an integer greater than 1.

4. The black frame time compensation circuit according to any one of claims 1 to 3, characterized by, The optimization coefficient is equal to A-1; where A is P1 divided by k 1* N the resulting quotient.

5. The dark- field time compensation circuit of claim 4, wherein, The number of clock cycles P1 included in the black field time to be compensated is obtained from the control card.

6. A constant current driving chip, characterized in that, Includes the black field time compensation circuit as described in any one of claims 1-5.

7. A display system characterized by, include: Display screen; The constant current driving chip according to claim 6 is used to drive the display screen; A control card is connected to the constant current drive chip and is used to control the constant current drive chip.

8. The display system of claim 7, wherein, The control card is also used to obtain the initial black screen time of the display screen, and to send the remainder obtained by dividing the number of clock cycles P2 included in the initial black screen time by k1*M*N as the number of clock cycles P1 included in the black screen time to be compensated to the constant current drive chip.

9. The display system of claim 8, wherein, The control card compensates the original row period to obtain the initial row period, which includes (K+k1*C) clock cycles; where C is the quotient obtained by dividing the number of clock cycles P2 included in the initial black screen time by k1*M*N; and K is the number of clock cycles included in the original row period.

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