Display panel and display device

Abstract

This application discloses a display panel and display device, including a pixel circuit. The pixel circuit includes a pulse width modulation (PWM) module and an amplitude modulation (AM) module. The PWM module outputs a pulse width setting signal, and the AM module outputs an amplitude setting signal. The PWM module receives at least a first signal and provides the first signal to a first node of the AM module. The operation of the pixel circuit includes a first time period and a second time period. During the first time period, the first node receives the first signal, and during the second time period, the first node receives the first signal. The first signal has a first level during the first time period and a second level during the second time period, which are different from the first level. The operation of the pixel circuit includes a light-emitting stage and a non-light-emitting stage. The first time period and the light-emitting stage overlap, and the second time period is located within the non-light-emitting stage. This display panel can alleviate the phenomenon of dim brightness in black screens and improve display quality.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the development of display technology, more and more display panels are using pixel circuits that combine pulse width modulation (PWM) and pulse amplitude modulation (PAM) circuits to control the light-emitting state of the light-emitting elements. However, display panels that use pixel circuits that combine PWM and PAM circuits to control the light-emitting state of the light-emitting elements exhibit a phenomenon where black areas appear slightly bright, affecting display quality. Summary of the Invention

[0003] In view of the above problems, this application provides a display panel and display device to alleviate the phenomenon of dim brightness in black screens and improve display quality. The specific solution is as follows:

[0004] A display panel includes: a pixel circuit, the pixel circuit including a pulse width modulation module and an amplitude modulation module, the pulse width modulation module being used to output a pulse width setting signal, and the amplitude modulation module being used to output an amplitude setting signal; the pulse width modulation module receiving at least a first signal, and the pulse width modulation module providing the first signal to a first node of the amplitude modulation module, wherein...

[0005] The operation of the pixel circuit includes a first time period and a second time period. During the first time period, the first node receives the first signal, and during the second time period, the first node receives the first signal.

[0006] The first signal is at a first level during the first time period, and the first signal is at a second level during the second time period, wherein the second level is different from the first level;

[0007] The operation of the pixel circuit includes a light-emitting stage and a non-light-emitting stage. The first time period and the light-emitting stage overlap, and the second time period is located within the non-light-emitting stage.

[0008] Optionally, the display panel further includes: a first signal control circuit, which receives a second signal and provides the first signal to the pulse width modulation module based on the second signal;

[0009] The second signal is either the first level or the second level.

[0010] Optionally, the first signal control circuit includes: a first control switch and a first comparator; wherein,

[0011] The input terminal of the first control switch receives the second signal, the output terminal is electrically connected to the positive input terminal of the first comparator, and the control terminal receives the first control signal;

[0012] The negative input terminal of the first comparator is electrically connected to its output terminal, and the output terminal outputs the first signal.

[0013] Wherein, the second signal is a first level, the first control signal controls the first control switch to be turned on during the first time period, and the output terminal of the first comparator outputs a first level; during the second time period, it controls the first control switch to be turned off, and the output terminal of the first comparator outputs a second level.

[0014] Optionally, the pulse width modulation module also receives a first emission control signal and a ramp signal. Under the control of the first emission control signal and the ramp signal, the pulse width modulation module provides the first signal to the first node.

[0015] The amplitude modulation module receives at least a second light emission control signal and a first power supply signal, and outputs the amplitude setting signal under the control of the second light emission control signal and the signal received by the first node.

[0016] The first time period overlaps with the conduction time period corresponding to the first light emission control signal, and also overlaps with the conduction time period corresponding to the second light emission control signal;

[0017] The second time period overlaps with the conduction time period corresponding to the first light emission control signal, but does not overlap with the conduction time period corresponding to the second light emission control signal.

[0018] Optionally, the second time period includes a first sub-time period, which is located within the conduction period corresponding to the first light emission control signal and within the cutoff period corresponding to the second light emission control signal.

[0019] Optionally, the second time period further includes a second sub-time period, which is located within the cutoff time period corresponding to the first light emission control signal and within the cutoff time period corresponding to the second light emission control signal.

[0020] Optionally, during the operation of the pixel circuit, the start time of the second time period is not earlier than the end time of the conduction time period corresponding to the second light emission control signal in the current working cycle, and the end time of the second time period is not later than the moment when the voltage of the ramp signal begins to increase in the next working cycle.

[0021] Optionally, during the operation of the pixel circuit, within the same working cycle, the start time of the second time period is not earlier than the end time of the conduction time period corresponding to the second light emission control signal, and not later than the end time of the conduction time period corresponding to the first light emission control signal.

[0022] Optionally, within the same working cycle, the start time of the second time period is the end time of the conduction period corresponding to the second light emission control signal, and the end time of the second time period is the end time of the conduction duration corresponding to the first light emission control signal.

[0023] Optionally, the start time of the conduction period of the first light-emitting control signal is earlier than the start time of the conduction period of the second light-emitting control signal.

[0024] Optionally, during the operation of the pixel circuit in the same working cycle, the moment when the voltage of the ramp signal begins to increase is later than the end of the conduction duration corresponding to the first scan signal and the end of the conduction duration corresponding to the second scan signal. The moment when the voltage of the ramp signal increases to the third level is no later than the start of the conduction period corresponding to the first light emission control signal. The third level is the maximum voltage that the ramp signal can output.

[0025] The operation of the pixel circuit includes an initialization period and a data writing period. The conduction period corresponding to the first scan signal is the period for initializing the first node; the conduction period corresponding to the second scan signal is the period for writing data to the first node.

[0026] Optionally, the operation of the pixel circuit includes multiple working cycles. Within the same working cycle, the moment when the voltage of the ramp signal decreases to the fourth level is the end moment of the conduction duration corresponding to the second light emission control signal. The fourth level is the minimum voltage value that the ramp signal can output.

[0027] Optionally, it also includes: a ramp signal control circuit, the ramp signal control circuit comprising: a second control switch, a third control switch, a current source, and a second comparator; wherein,

[0028] The input terminal of the second control switch receives a third signal, the output terminal is electrically connected to the positive input terminal of the second comparator, and the control terminal receives a second control signal.

[0029] The negative input terminal of the second comparator is electrically connected to its output terminal, and the output terminal outputs the ramp signal;

[0030] One end of the current source is electrically connected to the output terminal of the second control switch, and the other end is grounded;

[0031] The third control switch has its input terminal electrically connected to the output terminal of the second control switch, and its output terminal is grounded through the first capacitor. The control terminal receives a third control signal.

[0032] In the third time period, the second control signal controls the second control switch to turn on, the third control signal controls the third control switch to turn on, the second comparator outputs the third signal to the pulse width modulation module, and the voltage of the ramp signal gradually increases to its maximum output voltage value; in the fourth time period, the second control signal controls the second control switch to turn off, the third control signal controls the third control switch to turn on, and the voltage of the ramp signal gradually decreases.

[0033] During the second time period, the second control signal controls the second control switch to close, the third control signal controls the third control switch to close, and the output of the second comparator outputs the fourth level.

[0034] Optionally, the third control switch includes multiple sub-control switches, the input terminal of each sub-control switch is electrically connected to the output terminal of the second control switch, the output terminal is grounded through a first capacitor, and the control terminal inputs the third control signal.

[0035] Optionally, the pulse width modulation module includes a first driving transistor, which is located on the path through which the first signal is transmitted to the first node;

[0036] The ramp signal is provided to the control terminal of the first driving transistor, and the voltage value of the second level is greater than the difference between the minimum voltage that the ramp signal can output and the threshold voltage of the first driving transistor.

[0037] Optionally, the pulse width modulation module includes a first driving transistor;

[0038] The pulse width modulation module also receives a reference voltage, which is provided to the control terminal of the first driving transistor; the minimum voltage that the ramp signal can output is not greater than the voltage value of the reference voltage.

[0039] Optionally, the amplitude modulation module includes a second driving transistor; the amplitude modulation module also receives a reference voltage, a first power supply signal, and a second power supply signal, the reference voltage being provided to the control terminal of the second driving transistor, the voltage value of the first power supply signal being greater than the voltage value of the second power supply signal, and the second level and the second power supply signal satisfying: VH2_2×e^(-t / (R0C1))-PVEE <Vled_on;

[0040] Wherein, PVEE represents the second power signal, VH2_2 represents the second level, Vled_on represents the turn-on voltage of the light-emitting element electrically connected to the output terminal of the pixel circuit, C1 represents the capacitance value of the second capacitor, one end of the second capacitor is electrically connected to the first power signal, and the other end is electrically connected to the control terminal of the second driving transistor, t represents the discharge time of the second capacitor, and R0 represents the trace resistance of the reference voltage transmitted to the pixel circuit.

[0041] Optionally, the pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor, wherein the control terminal of the second driving transistor is connected to the first node;

[0042] The control terminal of the first driving transistor, the first node, and the output terminal of the pixel circuit are electrically connected to the same reference voltage transmission line and receive the reference voltage at the same time.

[0043] Optionally, the pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor, wherein the control terminal of the second driving transistor is connected to the first node;

[0044] The control terminal of the first driving transistor, the first node, and the output terminal of the pixel circuit are electrically connected to the same reference voltage transmission line; the control terminal of the first driving transistor and the output terminal of the pixel circuit receive the reference voltage at different time periods, and the first node and the output terminal of the pixel circuit receive the reference voltage at different time periods.

[0045] Optionally, the pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor, wherein the control terminal of the second driving transistor is connected to the first node;

[0046] The control terminal of the first driving transistor and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at the same time.

[0047] The first node and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at the same time.

[0048] Optionally, the pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor, wherein the control terminal of the second driving transistor is connected to the first node;

[0049] The control terminal of the first driving transistor and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at different time periods;

[0050] The first node and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at different time periods.

[0051] A display device comprising the display panel described in any of the preceding claims.

[0052] In the display panel and display device provided in the embodiments of this application, the operation of the pixel circuit includes a first time period and a second time period. In the first time period, the first node receives a first signal, and in the second time period, the first node receives the first signal. That is, in both the first and second time periods, the first node receives the first signal. The difference is that the first signal is at a first level in the first time period and at a second level in the second time period. The second level is different from the first level, so that the first node receives different level signals in the first and second time periods.

[0053] In this application, the first time period and the light-emitting stage overlap so that the first level can be transmitted to the first node during the light-emitting stage. The second time period is located within the non-light-emitting stage so that the second level can be transmitted to the first node during the non-light-emitting stage. This does not affect the working state of the light-emitting element and resets the first node, thereby reducing the probability that the working state of the light-emitting element will be affected due to incomplete reset of the first node (i.e., failure to reach the target reset level). This alleviates the phenomenon of slightly bright black screen and color shift on the display panel and improves the display quality of the display panel. Attached Figure Description

[0054] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0055] Figure 1 A schematic diagram of the pixel circuit in a display panel provided in this application;

[0056] Figure 2 for Figure 1 The timing diagram corresponding to the pixel circuit shown;

[0057] Figure 3 This is a schematic diagram of some of the reference voltage signal transmission lines in the display panel;

[0058] Figure 4 Timing diagram corresponding to the pixel circuit in another display panel provided in this application;

[0059] Figure 5 A schematic diagram of the pixel circuit in another display panel provided in this application;

[0060] Figure 6 A schematic diagram of the first signal control circuit in another display panel provided in this application;

[0061] Figure 7 A schematic diagram of yet another display panel provided in this application;

[0062] Figure 8 Timing diagram of pixel circuitry in another display panel provided in this application;

[0063] Figure 9 Timing diagram of pixel circuitry in another display panel provided in this application;

[0064] Figure 10 Timing diagram of pixel circuitry in another display panel provided in this application;

[0065] Figure 11 Timing diagram of pixel circuitry in another display panel provided in this application;

[0066] Figure 12 Timing diagram of pixel circuitry in another display panel provided in this application;

[0067] Figure 13 Timing diagram of pixel circuitry in another display panel provided in this application;

[0068] Figure 14 Timing diagram of pixel circuitry in another display panel provided in this application;

[0069] Figure 15 A schematic diagram of the pixel circuit in another display panel provided in this application;

[0070] Figure 16 A schematic diagram of the ramp signal control circuit in another type of display panel provided in this application;

[0071] Figure 17 A schematic diagram showing the RC delay of pixel circuits at different positions from the reference voltage input terminal in another display panel provided in this application;

[0072] Figure 18 A schematic diagram of the pixel circuit in another display panel provided in this application;

[0073] Figure 19 A schematic diagram of the pixel circuit in another display panel provided in this application;

[0074] Figure 20 A schematic diagram showing the electrical connection between each pixel circuit and the first reference voltage transmission line, the second reference voltage transmission line and the third reference voltage transmission line in another display panel provided in this application.

[0075] Figure 21 A schematic diagram of the pixel circuit in another display panel provided in this application;

[0076] Figure 22 This is a schematic diagram of a display device provided in this application. Detailed Implementation

[0077] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0078] The terminology used in the embodiments section of this application is only for explaining specific embodiments of this application and is not intended to limit this application. Various modifications and variations can be made to this application without departing from its spirit or scope. Moreover, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems, which is obvious to those skilled in the art. Therefore, this application is intended to cover modifications and variations of this application that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0079] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] As described in the background section, display panels that use pixel circuits combining pulse width modulation and pulse amplitude modulation to control the light-emitting state of light-emitting elements exhibit a phenomenon where black areas are slightly bright, affecting display quality.

[0081] Specifically, the pixel circuit that uses a combination of pulse width modulation circuit and pulse amplitude modulation circuit works as follows: the pulse amplitude modulation circuit is used to output driving current to the light-emitting element, and the pulse width modulation circuit controls the time for the pulse amplitude modulation circuit to output driving current to the light-emitting element.

[0082] like Figure 1 and Figure 2 As shown, Figure 1 This application illustrates a pixel circuit, which includes a PAM module (i.e., pulse amplitude modulation circuit) and a PWM module (i.e., pulse width modulation circuit). Figure 2The timing diagram of the pixel circuit during operation is shown, combined with... Figure 1 and Figure 2 It can be seen that the working process of this pixel circuit includes:

[0083] During the low-level period of Scan1 input (initialization phase), transistors M0 and M1 are turned on, and the reference voltage Vref resets node N1. After node N1 is reset, transistor M4 is turned on. At the same time, transistors M8 and M9 are turned on, and the reference voltage Vref resets node Q1. After node Q1 is reset, transistor M13 is turned on. Transistor M16 is turned on, and the reference voltage Vref resets node Q4.

[0084] During the low-level period of Scan2 input (data writing phase), transistors M5, M3 and M2 are turned on, and the PWM_DATA signal is written to node N1 through transistors M5, M3 and M2. Transistors M15, M11 and M10 are turned on, and the PAM_DATA signal is written to node Q1 through transistors M15, M13, M11 and M10.

[0085] During the period when the PAM_EM input is low (the light-emitting control stage), transistors M12 and M14 are turned on, and the PVDD signal is transmitted to the light-emitting element to control it to emit light. During this process, when the PWM_EM input is low, transistors M7 and M6 are turned on, and the Sweep signal drops from high level at a fixed rate. When the Sweep signal drops to the turn-on voltage of transistor M4, transistor M4 is turned on, and the high level of the VH2 signal is transmitted to node Q1 through transistors M7, M4, and M6, controlling transistor M13 to turn off, and the light-emitting element stops emitting light.

[0086] It should be noted that the display panel displays images by sequentially displaying multiple frames. During the display of each frame, the pixel circuit's operation includes the aforementioned initialization phase, data writing phase, and light emission control phase. Furthermore, the reset of node Q4 in the pixel circuit is performed simultaneously with the resets of nodes N1 and Q1, using the reference voltage Vref transmitted via the same reference voltage transmission signal line.

[0087] However, during the actual display process, in the data writing stage of the first frame, the potential of node N1 in the pixel circuit is pulled high by the PWM_DATA signal, and the potential of node Q1 is pulled high by the PAM_DATA signal. In the light-emitting control stage of the first frame, the potential of node Q1 is also pulled high by the VH2 signal. This causes the reference voltage Vref to have a counter-effect on the reference voltage Vref when resetting nodes N1 and Q1 after the first frame is displayed, further increasing the potential of Vref. Furthermore, the further the pixel circuit is from the input of the reference voltage signal transmission line, the higher the potential of its input reference voltage Vref is. This prevents the Q4 node from being reset to the target low level when the reference voltage Vref is used to reset the light-emitting element. If the potential of node Q4 after reset reaches the turn-on voltage of the light-emitting element, the light-emitting element will start to emit light, resulting in a faint glow when displaying a black screen.

[0088] like Figure 3 As shown, Figure 3 A schematic diagram of a portion of the reference voltage signal transmission lines in the display panel is shown. Figure 3 As can be seen, the reference voltage signal transmission line in the display panel includes a first reference voltage signal transmission line V10 that provides a reference voltage for each pixel circuit and a second reference voltage signal transmission line V20 that provides a reference voltage for the first reference voltage signal transmission line V10. Along the extension direction of the first reference voltage signal transmission line V10, the brightness is greater at positions farther away from the second reference voltage signal transmission line V20, and the phenomenon of dim brightness in black screens is more severe.

[0089] It should be noted that, because the second reference voltage signal transmission line V20 has a larger linewidth and lower transmission impedance, while the first reference voltage signal transmission line V10 has a smaller linewidth and higher transmission impedance, therefore... Figure 3 The slight brightness in the black screen is mainly related to the distance between the pixel circuit and the second reference voltage signal transmission line V20.

[0090] In addition, if the display panel includes red, blue and green light-emitting elements, since the turn-on voltage of the red light-emitting element is lower than that of the blue and green light-emitting elements, when the reference voltage Vref is pulled up, the turn-on voltage of the red light-emitting element will be reached first, so that the dim brightness of the black screen will mainly appear as a red screen.

[0091] Furthermore, in low grayscale display, when the reference voltage Vref is pulled up to the turn-on voltage of the red light-emitting element, some of the non-lit red light-emitting elements in the display screen will be lit up, causing the display screen to be reddish and producing color shift.

[0092] In view of this, embodiments of this application provide a display panel, such as Figure 1 and Figure 4 As shown, Figure 4 The timing diagram for the pixel circuit includes a pixel circuit 10, which comprises a pulse width modulation (PWM) module and an amplitude modulation (PAM) module. The PWM module outputs a pulse width setting signal to control the emission duration of the light-emitting element D electrically connected to the pixel circuit 10. The PAM module outputs an amplitude setting signal to control the magnitude of the driving current supplied to the light-emitting element D electrically connected to the pixel circuit 10. In this embodiment, the PWM module receives at least a first signal VH2, and provides the first signal VH2 to the first node Q1 of the PAM module.

[0093] It should be noted that, Figure 4 In the various pulse signals, a low level corresponds to a conduction signal and a high level corresponds to a cutoff signal, as illustrated in the diagram. However, this application is not limited to this. In other embodiments of this application, a high level may correspond to a conducting chip and a low level to a cutoff signal, depending on the specific circumstances. The following description uses a low level to correspond to a conduction signal and a high level to correspond to a cutoff signal to describe the display panel provided in the embodiments of this application.

[0094] Specifically, the operation of the pixel circuit 10 includes a first time period T1 and a second time period T2. During the first time period T1, the first node Q1 receives the first signal VH2, and during the second time period T2, the first node Q1 receives the first signal VH2. That is, during both the first time period T1 and the second time period T2, the first node Q1 receives the first signal VH2. The difference is that the first signal VH2 is at a first level VH2_1 during the first time period T1, and at a second level VH2_2 during the second time period T2. The second level VH2_2 is different from the first level VH2_1, so that the first node Q1 receives different level signals during the first time period T1 and the second time period T2.

[0095] It should be noted that, continuing as Figure 4As shown, the operation of the pixel circuit 10 includes a light-emitting phase T3 and a non-light-emitting phase T4. The light-emitting phase T3 is the time period during which the light-emitting element D electrically connected to the pixel circuit 10 is in a light-emitting state, and the non-light-emitting phase T4 is the time period during which the light-emitting element D electrically connected to the pixel circuit 10 is in a non-light-emitting state. In this embodiment, the first time period T1 and the light-emitting phase T3 overlap, allowing the first level VH2_1 to be transmitted to the first node Q1 during the light-emitting phase T3. The second time period T2 is located within the non-light-emitting phase T4, allowing the second level VH2_2 to be transmitted to the first node Q1 during the non-light-emitting phase T4.

[0096] In this embodiment, the second level VH2_2 is transmitted to the first node Q1 during the non-light-emitting stage T4. This ensures that when the first node Q1 is at the second level VH2_2, it does not affect the working state of the light-emitting element D. In addition, the transmission of the second level VH2_2 to the first node Q1 can reset the first node Q1, thereby reducing the probability that the working state of the light-emitting element D will be affected due to the incomplete reset of the first node Q1 (i.e., failure to reach the target reset level). This alleviates the phenomenon of slightly bright black screens and color shift on the display panel, and improves the display quality of the display panel.

[0097] Optionally, in one embodiment of this application, the first node Q1 is electrically connected to the control terminal of the P-type transistor. In this embodiment, the first level VH2_1 is high and the second level VH2_2 is low. In other embodiments of this application, the first node Q1 is electrically connected to the control terminal of the N-type transistor. In this embodiment, the first level VH2_1 is low and the second level VH2_2 is high. This application does not limit this, and it depends on the specific situation. The following description uses the example of the first node Q1 being electrically connected to the control terminal of the P-type transistor to describe the display panel provided in the embodiments of this application.

[0098] Optionally, in one embodiment of this application, the following continues... Figure 1 As shown, the pulse width modulation module (PWM) includes a first driving transistor M4, and the amplitude modulation module (PAM) includes a second driving transistor M13. In this embodiment, the operating state of the second driving transistor M13 can affect the on / off state of the transmission path of the driving current to the light-emitting element D, and the operating state of the first driving transistor M4 can affect the operating state of the second driving transistor M13. The control terminal of the second driving transistor M13 is electrically connected to the first node Q1.

[0099] Specifically, the operation of the pixel circuit includes:

[0100] During the initialization phase W1, the control terminal of the first driving transistor M4 (i.e., the second node N1), the control terminal of the second driving transistor M13 (i.e., the first node Q1), and the anode of the light-emitting element D (i.e., the third node Q4) are reset.

[0101] During the data writing phase W2, the first data signal PWM_DATA is written to the control terminal of the first driving transistor M4 (i.e., the second node N1), and the second data signal PAM_DATA is written to the control terminal of the second driving transistor M13 (i.e., the first node Q1).

[0102] During the light emission control phase W3, the first power supply signal PVDD is transmitted to the anode of the light-emitting element D (i.e., the third node Q4) to provide driving current to the light-emitting element D. The ramp signal Sweep is transmitted to the control terminal of the first driving transistor M4 (i.e., the second node N1) so that when the first driving transistor M4 is turned on, the first level VH2_1 is input to the control terminal of the second driving transistor M13 (i.e., the first node Q1) to control the second driving transistor M13 to turn off, so that the light-emitting element D stops emitting light.

[0103] It should be noted that during the initialization phase W1, the reference voltage Vref resets the first node Q1 to reset the control terminal of the second driving transistor M13. During the light-emitting phase T3, the first level VH2_1 is transmitted to the first node Q1 to control the second driving transistor M13 to turn off, thereby cutting off the transmission path of the driving current. This causes the light-emitting element D, which is electrically connected to the pixel circuit 10, to switch from the light-emitting state to the non-light-emitting state. During the non-light-emitting phase T4, the second level VH2_2 is transmitted to the first node Q1 to reset the first node Q1. This reduces the probability that the first node Q1 cannot be reset to the target reset level during the initialization phase W1 of the next frame display process, thus reducing the probability that the second driving transistor M13 will be turned on when it should be in the off state. This reduces the probability of black screen with slight brightness and color shift on the display panel, improves display contrast, reduces color shift, and ultimately improves display quality.

[0104] Optionally, in one embodiment of this application, such as Figure 5As shown, the display panel also includes a first signal control circuit 20. The first signal control circuit 20 receives a second signal VH2_0 and provides a first signal VH2 to the pulse width modulation module PWM based on the second signal VH2_0. This allows the display panel to use the same input signal VH2_0 to output a first level VH2_1 in the first time period T1 and a second level VH2_2 in the second time period T2, simplifying the structure of the display panel. It should be noted that in this embodiment, the second signal VH2_0 can be either the first level VH2_1 or the second level VH2_2, depending on the implementation structure of the first signal control circuit.

[0105] Specifically, in one embodiment of this application, such as Figure 6 As shown, the first signal control circuit 20 may include a first control switch K1 and a first comparator U1. The input terminal of the first control switch K1 receives a second signal VH2_0, and its output terminal is electrically connected to the positive input terminal of the first comparator U1. The control terminal receives a first control signal VH2_CTL. The negative input terminal of the first comparator U1 is electrically connected to its output terminal, and its output terminal outputs the first signal VH2. Optionally, in this embodiment, the second signal VH2_0 is a first level VH2_1. During the first time period T1, the first control signal VH2_CTL controls the first control switch K1 to turn on. The second signal VH2_0 is transmitted to the positive input terminal of the first comparator U1 via the first control switch K1. The first comparator U1 compares the potential at its positive input terminal with the potential at its negative input terminal and outputs the result. Since the negative input terminal of the first comparator U1 is electrically connected to its output terminal, the potential at its output terminal follows the change in the potential at its positive input terminal. At this time, the output terminal of the first comparator U1 outputs the first level VH2_1. During the second time period T2, the first control signal VH2_CTL controls the first control switch K1 to close, the positive input terminal of the first comparator U1 is floating, and the first signal VH2 output by the output terminal of the first comparator U1 is the second level VH2_2.

[0106] With the above settings, the first signal control circuit can output the first level VH2_1 in the first time period T1 and the second level VH2_2 in the second time period T2 based on the second signal VH2_0, thereby providing the first node Q1 of the pixel circuit 10 with signals of different levels in different time periods and realizing the pre-initialization function of the first node Q1.

[0107] It should be noted that the first control switch K1 can be a thin-film transistor, whose gate receives the first control signal VH2_CTL, its first terminal (source or drain) receives the second signal VH2_0, and its second terminal (drain or source) is connected to the positive input terminal of the first comparator U1. The first control signal VH2_CTL is at the on level in the first time period T1 and at the off level in the second time period T2.

[0108] Optionally, in one embodiment of this application, the first comparator U1 is an operational amplifier to increase the strength of the output signal of the first signal control circuit 20, thereby increasing the driving capability of the first signal control circuit 20. However, this application does not limit this and it depends on the specific circumstances.

[0109] Optionally, in one embodiment of this application, the following continues... Figure 6 As shown, the first signal control circuit 20 also includes a pull-down resistor R1. One end of the pull-down resistor R1 is electrically connected to the second pole of the first control switch K1, and the other end is grounded to provide a stable DC operating point for the positive input terminal of the first comparator U1 (i.e., to prevent it from floating), ensuring that the first comparator U1 outputs the second level during the period when the first control switch K1 is off, and improving the anti-interference capability of the first signal control circuit.

[0110] In some embodiments of this application, the output of the first comparator U1 is also connected to the first signal input of the pixel circuit 10 to provide the pixel circuit 10 with a first signal VH2. Optionally, the first signal control circuit 20 is integrated into the control circuit of the display panel, for example, integrated into the gate driving circuit or the data driving circuit, thereby reducing the number of external components of the display panel and improving the integration. However, this application does not limit this and it depends on the specific circumstances.

[0111] like Figure 7 As shown, in one embodiment of this application, the display panel further includes a gate driving circuit 30 and a data driving circuit 40, wherein the gate driving circuit 30 is used to provide a first scan signal Scan1 and a second scan signal Scan2 to the pixel circuit 10, and the data driving circuit 40 is used to provide a first data signal PWM_DATA and a second data signal PAM_DATA to the pixel circuit 10.

[0112] Optionally, in one embodiment of this application, the display panel includes a display area 100 and a border area 200, the gate driving circuit 30 and the data driving circuit 40 are located in the border area 200, and the pixel circuit 10 and its corresponding light-emitting element D are located in the display area 100 to control the display of the display area 100.

[0113] In some other embodiments of this application, the first control switch K1 can be implemented by multiple transistors connected in series or in parallel to enhance its conduction capability or reduce leakage current, which can be determined according to actual design requirements.

[0114] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 1As shown, the pulse width modulation module (PWM) also receives a first light emission control signal (PWM_EM) and a ramp signal (Sweep). Under the control of the first light emission control signal (PWM_EM) and the ramp signal (Sweep), the PWM module provides a first signal (VH2) to the first node (Q1). The amplitude modulation module (PAM) receives at least a second light emission control signal (PAM_EM) and a first power supply signal (PVDD). Under the control of the second light emission control signal (PAM_EM) and the signal received by the first node (Q1), it outputs an amplitude setting signal.

[0115] Specifically, in combination Figure 4 The timing diagram shows that the first time period T1 overlaps with the conduction period T5 corresponding to the first light-emitting control signal PWM_EM, and also overlaps with the conduction period T6 corresponding to the second light-emitting control signal PAM_EM. It should be noted that the conduction period T6 corresponding to the second light-emitting control signal PAM_EM is within the same time period as the light-emitting stage T3. Since the conduction period T6 corresponding to the second light-emitting control signal PAM_EM is located within the conduction period T5 corresponding to the first light-emitting control signal PWM_EM, the overlap between the first time period T1 and the conduction period T5, as well as the overlap between the second light-emitting control signal PAM_EM and the conduction period T6, means that the first time period T1 overlaps with the light-emitting stage T3. This allows the pulse width modulation module PWM to provide the first level VH2_1 to the first node Q1 during this time period, controlling the second driving transistor M13 to turn off, and the light-emitting element D to stop emitting light.

[0116] like Figure 4 and Figure 8 As shown, the second time period T2 overlaps with the conduction period T5 corresponding to the first light-emitting control signal PWM_EM, but does not overlap with the conduction period T6 corresponding to the second light-emitting control signal PAM_EM. That is, the second time period T2 is located in the non-light-emitting stage T2 after the light-emitting element D corresponding to the current frame of the display image stops emitting light and before the light-emitting element D corresponding to the next frame of the display image starts emitting light. During at least a portion of the second time period T2, the first light-emitting control signal PWM_EM is at the on level and the second light-emitting control signal PAM_EM is at the off level, so that the pulse width modulation module PWM provides the second level VH2_2 to the first node Q1 during this time period to pre-initialize the first node Q1, thereby reducing the degree to which the reference voltage Vref of W1 is pulled high during the initialization stage of the next frame of the display image.

[0117] With the above settings, the second time period T2 transmits the second level VH2_2 to the first node Q1 through the conduction period T5 of the first light-emitting control signal PWM_EM, and the pre-initialization function of the first node Q1 can be realized without setting an additional control signal. At the same time, the second time period T2 and the conduction period T6 of the second light-emitting control signal PAM_EM do not overlap, ensuring that the second level VH2_2 will not be transmitted to the first node Q1 during the light-emitting element D, thus avoiding affecting the normal light-emitting of the light-emitting element D.

[0118] Optionally, in one embodiment of this application, the following continues... Figure 8 As shown, the second time period T2 includes a first sub-time period T21, which is located within the conduction period T5 corresponding to the first light-emitting control signal PWM_EM and within the cutoff period corresponding to the second light-emitting control signal PAM_EM (i.e., it does not overlap with the conduction period T6 corresponding to the second light-emitting control signal PAM_EM). That is, after the light-emitting element D stops emitting light, during the period when the first light-emitting control signal PWM_EM is a conduction signal, the second level VH2_2 is transmitted to the first node Q1 through the pulse width modulation module PWM to achieve the pre-initialization of the first node Q1.

[0119] Optionally, in one embodiment of this application, the following continues... Figure 8 As shown, the second time period T2 also includes a second sub-time period T22. The second sub-time period T22 is located within the cutoff period corresponding to the first light-emitting control signal PWM_EM (i.e., it does not overlap with the conduction period T5 corresponding to the first light-emitting control signal PWM_EM) and within the cutoff period corresponding to the second light-emitting control signal PAM_EM (i.e., it does not overlap with the conduction period T6 corresponding to the second light-emitting control signal PAM_EM). That is, during the period when both the first light-emitting control signal PWM_EM and the second light-emitting control signal PAM_EM are cutoff signals, the first signal VH2_ continues to be the second level VH2_2. It should be noted that in the second sub-time period T22, since both the first light-emitting control signal PWM_EM and the second light-emitting control signal PAM_EM are cutoff signals, the second level VH2_2 will not be transmitted to the first node Q1 and will not affect the operation of the pixel circuit 10. In other embodiments of this application, during the period when both the first light-emitting control signal PWM_EM and the second light-emitting control signal PAM_EM are cutoff signals, the first signal VH2 can also be the first level VH2_1, continuing as... Figure 4 As shown, this application does not impose any limitations on this matter; the specific circumstances will determine the appropriate course of action.

[0120] Specifically, based on the above embodiments, in one embodiment of this application, the following continues... Figure 8As shown, the duration of the first sub-period T21 can be shorter than the duration of the second sub-period T22. In this case, the proportion of the first sub-period T21 within the second sub-period T2 is less than 50%. In another embodiment of this application, as shown... Figure 9 As shown, the duration of the first sub-period T21 can be equal to the duration of the second sub-period T22. In this case, the proportion of the first sub-period T21 within the second sub-period T2 is 50%. In another embodiment of this application, as shown... Figure 10 As shown, the duration of the first sub-period T21 can be longer than the duration of the second sub-period T22. In this case, the proportion of the first sub-period T21 in the second sub-period T2 is greater than 50%. This application does not limit this, and it depends on the specific circumstances.

[0121] It should be noted that, in this embodiment, within the second time period T2, the duration of the second sub-time period T22 can be greater than zero, and so on. Figures 8-10 As shown, it can also be equal to zero, and so on. Figure 4 As shown, this application does not impose any limitations on this, and the specifics depend on the circumstances. If the duration of the second sub-period T22 is zero, then the duration of the second sub-period T2 is the same as the duration of the first sub-period T21.

[0122] Optionally, in one embodiment of this application, the following continues... Figure 8 As shown, during the operation of the pixel circuit 10, the start time of the second time period T2 is no earlier than the end time of the conduction period T6 corresponding to the second light emission control signal PAM_EM in the current working cycle, and the end time of the second time period T2 is no later than the moment T0 when the voltage of the slope signal Sweep in the next working cycle begins to increase. That is, the start time of the second time period T2 is after the moment T7 when the second light emission control signal PAM_EM switches from the conduction signal to the cutoff signal, and the end time of the second time period T2 is no later than the moment T0 when the voltage of the slope signal Sweep in the next frame of the display begins to rise, so as to avoid the setting of the second time period T2 affecting the subsequent normal working timing.

[0123] It should be noted that in other embodiments of this application, such as Figure 11 As shown, the cutoff time of the second time period T2 can also be later than the time T0 when the voltage of the slope signal Sweep in the next working cycle begins to increase. For example, the duration of the second time period T2 is the scanning time of one row of pixels in the display panel. This application does not limit this, as long as the cutoff time of the second time period T2 is not later than the time when the first driving transistor M4 switches to conduct under the control of the slope signal Sweep. However, since the time when the first driving transistor M4 switches to conduct under the control of the slope signal Sweep is difficult to determine, this embodiment sets the cutoff time of the second time period T2 to be no later than the time T0 when the voltage of the slope signal Sweep in the next working cycle begins to increase, so as to facilitate the control of the first signal VH2.

[0124] Optionally, in one embodiment of this application, the following continues... Figure 4 and Figure 8 As shown, during the operation of the pixel circuit, within the same working cycle, the start time of the second time period T2 is no earlier than the end time of the conduction period T6 corresponding to the second light emission control signal PAM_EM, and no later than the end time of the conduction period T5 corresponding to the first light emission control signal PWM_EM, so that the second time period T2 overlaps with the conduction period T5 corresponding to the first light emission control signal PWM_EM, but does not overlap with the conduction period T6 corresponding to the second light emission control signal PWM_EM.

[0125] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 8 As shown, within the same working cycle, the start time of the second time period T2 is the end time T7 of the conduction time period T6 corresponding to the second light emission control signal PAM_EM. However, this application does not limit this to the specific time period. In other embodiments of this application, such as... Figure 12 As shown, within the same working cycle, the start time of the second time period T2 can also be later than the end time T7 of the conduction period T6 corresponding to the second light emission control signal PAM_EM. As long as the second time period T2 overlaps with the conduction period T5 corresponding to the first light emission control signal PWM_EM, the second level VH2_2 can be transmitted to the first node Q1 to achieve the pre-initialization of the first node Q1.

[0126] Based on the above embodiments, in one embodiment of this application, the following continues... Figure 4 As shown, within the same working cycle, the start time of the second time period T2 is the end time of the conduction period T6 corresponding to the second light emission control signal PAM_EM, and the end time of the second time period T2 is the end time of the conduction period T5 corresponding to the first light emission control signal PWM_EM. That is, the second time period T2 overlaps with the latter half of the conduction period T5 of the first light emission control signal PWM_EM. Pre-initialization begins immediately after the second light emission control signal PAM_EM is turned off and ends when the first light emission control signal PWM_EM is turned off, so as to facilitate the control of the start and end times of the second time period T2.

[0127] Continue as Figure 1As shown, the pixel circuit 10 includes a first light-emitting control circuit and a second light-emitting control circuit. The first light-emitting control circuit receives control from a first light-emitting control signal PWM_EM, and the second light-emitting control circuit receives control from a second light-emitting control signal PAM_EM. Specifically, the first light-emitting control circuit includes a first light-emitting control transistor M7 and a second light-emitting control transistor M6, and the second light-emitting control circuit includes a third light-emitting control transistor M12 and a fourth light-emitting control transistor M14. The control terminals of the first light-emitting control transistor M7 and the second light-emitting control transistor M6 both receive control from the first light-emitting control signal PWM_EM, and the control terminals of the third light-emitting control transistor M12 and the fourth light-emitting control transistor M14 both receive control from the second light-emitting control signal PAM_EM.

[0128] Specifically, the first terminal of the first light-emitting control transistor M7 receives the first signal VH2, and its second terminal is electrically connected to the first terminal of the first driving transistor M4. The second terminal of the first driving transistor M4 is electrically connected to the first terminal of the second light-emitting control transistor M6, and the second terminal of the second light-emitting control transistor M6 is electrically connected to the first node Q1. The first terminal of the third light-emitting control transistor M12 receives the first power supply signal PVDD, and its second terminal is electrically connected to the first terminal of the second driving transistor M13. The second terminal of the second driving transistor M13 is electrically connected to the first terminal of the fourth light-emitting control transistor M14, and the second terminal of the fourth light-emitting control transistor M14 is electrically connected to the anode of the light-emitting element D (i.e., the third node Q4). The cathode of the light-emitting element D is electrically connected to the second power supply signal PVEE.

[0129] In this embodiment, when the second driving transistor M13 and the second light-emitting control circuit are turned on, the first power signal PVDD is transmitted to the anode of the light-emitting element D, driving the light-emitting element D to emit light. When at least one of the second driving transistor M13 and the second light-emitting control circuit is turned off, the first power signal PVDD cannot be transmitted to the anode of the light-emitting element D, and the light-emitting element D does not emit light. When the first driving transistor M4 and the first light-emitting control circuit are turned on, the first level VH2_1 is transmitted to the control terminal of the second driving transistor M13, controlling the second driving transistor M13 to turn off, and the light-emitting element D no longer emits light. When at least one of the first driving transistor M4 and the first light-emitting control circuit is not turned on, the first level VH2_1 cannot be transmitted to the control terminal of the second driving transistor M13.

[0130] Combination Figure 4It can be seen that during the initialization phase W1, the first scan signal Scan1 is a conducting signal, the reference voltage Vref is transmitted to the first node Q1, the second driving transistor M13 is turned on, and at the same time, the reference voltage Vref is transmitted to the second node N1, the first driving transistor M4 is turned on. After the first driving transistor M4 and the second driving transistor M13 are turned on, the first scan signal Scan1 is switched to a cutoff signal, and the first driving transistor M4 and the second driving transistor M13 remain in the conducting state.

[0131] During the light emission control stage W3, the second light emission control signal PAM_EM is switched to a conduction signal, the second light emission control circuit is turned on, and the first power supply signal PVDD is transmitted to the anode of the light emission element D through the second light emission control circuit and the second driving transistor M13, and the light emission element D starts to emit light.

[0132] In the light-emitting control phase W3, the ramp signal Sweep first switches to a high level, pulling the potential of the second node N1 high, causing the first driving transistor M4 to turn off. Then, the ramp signal Sweep drops from the high level at a fixed rate. Before the ramp signal Sweep drops from the high level at a fixed rate, the first light-emitting control signal PWM_EM switches to a conduction signal, and the first light-emitting control circuit is turned on. When the ramp signal Sweep drops to the conduction voltage of the first driving transistor M4, the first driving transistor M4 is turned on. At this time, the first light-emitting control circuit is also turned on, thereby providing the first signal VH2 to the first node Q1 through the first light-emitting control circuit and the first driving transistor M4, causing the second driving transistor M13 to switch to the off state, and the light-emitting element D stops emitting light.

[0133] Because the turn-on time of the first driving transistor M4 is difficult to determine during the process of the slope signal Sweep falling from high level at a fixed rate, and the RC delay of different areas of the display panel is different, the transmission time of the first light-emitting control signal PWM_EM to different pixel circuits 10 is different. If the first driving transistor M4 is turned on Δt time earlier than the first light-emitting control circuit PWM_EM, the turn-off time of the light-emitting element D will be delayed by Δt, affecting the display of the black screen, and thus affecting the display of the display panel.

[0134] Furthermore, since the turn-on time of the first driving transistor M4 is definitely later than the turn-on time of the second light-emitting control circuit (i.e., the time when the second light-emitting control signal PAM_EM switches to the turn-on signal), in order to ensure that the light-emitting element D has a light-emitting duration, therefore, in an optional embodiment of this application, the following continues... Figure 4As shown, the start time of the conduction period T5 of the first light-emitting control signal PWM_EM is earlier than the start time of the conduction period T6 of the second light-emitting control signal PAM_EM. That is, in the light-emitting phase of the same working cycle, the first light-emitting control signal PWM_EM becomes a conducting signal before the second light-emitting control signal PAM_EM, thereby ensuring that the first driving transistor M4 is already in the conducting state before the light-emitting element D emits light. This makes the cutoff time of the light-emitting element D the moment when the ramp signal Sweep drops to the conduction voltage of the first driving transistor M4, thereby improving the accuracy of the control of the light-emitting duration of the light-emitting element D and improving the display quality of the display panel.

[0135] Because there is an RC delay between the signal input terminal of the ramp signal Sweep and the second node N1 (i.e., the control terminal of the first driving transistor M4), it takes a certain amount of time for the voltage of the ramp signal Sweep to be supplied to the second node N1. Furthermore, it also takes a certain amount of time for the voltage of the ramp signal Sweep to change from the on signal to the off signal. If the moment when the ramp signal Sweep switches to the off signal coincides with the moment when the first light-emitting control signal PWM_EM switches to the on signal, due to the RC delay, the moment when the voltage of the second node N1 switches to the off voltage may be later than the moment when the first light-emitting control signal PWM_EM switches to the on signal. This would cause the first signal VH2 input to the first light-emitting control circuit to be transmitted to the second node Q1, causing the voltage of the second node Q1 to switch to the off voltage, resulting in display screen instability.

[0136] Therefore, in one optional embodiment of this application, such as Figure 13 As shown, during the same working cycle, the voltage of the slope signal Sweep begins to increase at time T8, which is later than the end time T10 of the conduction period corresponding to the first scan signal Scan1 and the end time T9 of the conduction period corresponding to the second scan signal Scan2. Furthermore, the voltage of the slope signal Sweep increases to the third level at time T11, which is not later than the start time T5 of the conduction period corresponding to the first light emission control signal PWM_EM. The third level is the maximum voltage that the slope signal Sweep can output. It should be noted that in this embodiment, the working process of the pixel circuit 10 includes an initialization period W1 and a data writing period W2. The conduction period corresponding to the first scan signal Scan1 is the period for initializing the first node Q1, and the conduction period corresponding to the second scan signal Scan2 is the period for writing data to the first node Q1.

[0137] In this embodiment, the ramp signal Sweep begins to rise after the initialization phase W1 and the data writing phase W2 are completed. This ensures that the voltage change of the ramp signal Sweep does not affect the reset and data writing of the second node N1. The ramp signal Sweep rises to its maximum value before the first light-emitting control signal PWM_EM switches to the on signal, so that the first driving transistor M4 has entered the off state before the first light-emitting control signal PWM_EM switches to the on signal. This avoids the phenomenon that the light-emitting element D emits light during periods when it is not needed, causing display screen disorder.

[0138] Optionally, in one embodiment of this application, the operation of the pixel circuit 10 includes multiple operating cycles, such as... Figure 14 As shown, within the same working cycle, the moment T12 when the voltage of the ramp signal Sweep decreases to the fourth level is the end time of the conduction period T6 corresponding to the second light emission control signal PAM_EM. Here, the fourth level is the minimum voltage that the ramp signal Sweep can output, so that when the second light emission control signal PAM_EM switches from the on signal to the off signal, the ramp signal Sweep quickly decreases to the conduction voltage required by the first driving transistor M4, thereby ensuring that the conduction time of the first driving transistor M4 is no later than the moment when the first signal VH2 switches to the second level VH2_2, thus ensuring the pre-initialization of the first node Q1 by the first signal VH2.

[0139] Based on the above embodiments, in one embodiment of this application, such as Figure 15 As shown, the display panel also includes a ramp signal control circuit 50, such as... Figure 16 As shown, the ramp signal control circuit 50 includes: a second control switch K2, a third control switch K3, a current source Is, and a second comparator U2. The second control switch K2 receives the third signal Sweep_IN at its input terminal, and its output terminal is electrically connected to the positive input terminal of the second comparator U2. Its control terminal receives the second control signal Sweep_EN. The negative input terminal of the second comparator U2 is electrically connected to its output terminal, and its output terminal outputs the ramp signal Sweep. One end of the current source Is is electrically connected to the output terminal of the second control switch K2, and the other end is grounded. The input terminal of the third control switch K3 is electrically connected to the output terminal of the second control switch K2, and its output terminal is grounded through a first capacitor C10. Its control terminal receives the third control signal SW_CTL.

[0140] It should be noted that, in this embodiment, during the third time period, the second control signal Sweep_EN controls the second control switch K2 to turn on, and the third control signal SW_CTL controls the third control switch K3 to turn on. The third signal Sweep_IN is transmitted to the positive input terminal of the second comparator U2 via the second control switch K2, and charges the first capacitor C10. The output terminal of the second comparator U2 outputs a ramp signal Sweep to the ramp signal input terminal of the pulse width modulation module PWM. At this time, the voltage of the ramp signal Sweep gradually increases to its maximum output voltage value (i.e., the third level). During the fourth time period, the second control signal Sweep_EN controls... The second control switch K2 is closed, and the third control signal SW_CTL controls the third control switch K3 to be turned on. The current source Is discharges the first capacitor C10, and the voltage of the slope signal Sweep gradually decreases. In the second time period T2, the second control signal Sweep_EN controls the second control switch K2 to be closed, and the third control signal SW_CTL controls the third control switch K3 to be closed, breaking the path between the first capacitor C10 and the positive input terminal of the second comparator U2. The current source Is quickly pulls down the voltage of the slope signal Sweep, so that the output terminal of the second comparator U2 outputs the fourth level (i.e., the minimum voltage that the slope signal Sweep can output).

[0141] With the above settings, the ramp signal control circuit 50 can generate the required ramp signal Sweep, and at the moment when the second control signal Sweep_EN switches from the on signal to the off signal and / or at the beginning of the second time period T2, the path between the first capacitor C10 and the positive input terminal of the second comparator U2 is disconnected, so that the ramp signal Sweep is quickly pulled down to the fourth level, so as to ensure that the first driving transistor M4 can be reliably turned on during the pre-initialization stage, so that the second level VH2_2 is transmitted to the first node Q1 through the first driving transistor M4, thereby realizing the pre-initialization of the first node Q1.

[0142] Optionally, in one embodiment of this application, the third control switch K3 may include multiple sub-control switches connected in parallel. The input terminal of each sub-control switch is electrically connected to the output terminal of the second control switch K2, and the output terminal is grounded through the first capacitor C10. The control terminal inputs the third control signal SW_CTL. However, this application does not limit this, and the specific implementation depends on the circumstances.

[0143] Optionally, in one embodiment of this application, the second comparator U2 is an operational amplifier to increase the strength of the output signal of the ramp signal control circuit 50, thereby increasing the driving capability of the ramp signal control circuit 50. However, this application does not limit this and it depends on the specific circumstances.

[0144] Based on any of the above embodiments, in an embodiment of the present application, continue as Figure 1 shown, the pulse width modulation module PWM includes a first driving transistor M4. The first driving transistor M4 is located on the path where the first signal VH2 is transmitted to the first node Q1. The ramp signal Sweep is provided to the control terminal (i.e., the second node N1) of the first driving transistor M4; in this embodiment, the first driving transistor M4 is a P-type transistor, and the voltage value of the second level VH2_2 is greater than the difference between the minimum voltage value (i.e., the fourth level) that the ramp signal Sweep can output and the threshold voltage Vth of the first driving transistor M4.

[0145] Specifically, the conduction condition of a P-type transistor is that the difference in its gate-source voltage Vgs is less than its threshold voltage Vth (the threshold voltage is negative). Therefore, the conduction condition of the first driving transistor M4 is: Vgs_M4 < Vth_M4 (Vth_M4 is negative), where Vgs_M4 = Vg_M4 - Vs_M4 = Vg_M4 - VH2_2, then the conduction condition of the first driving transistor M4 is: Vg_M4 - VH2_2 < Vth_M4. Here, VH2_2 represents the voltage value of the second level, and Vth_M4 represents the threshold voltage of the first driving transistor M4.

[0146] In the pre-initialization stage, Vg_M4 = Sweep_min (the lowest voltage of the ramp signal), substituting it in we get: Sweep_min - VH2_2 < Vth_M4, that is, VH2_2 > Sweep_min - Vth_M4. Sweep_min represents the minimum voltage value (i.e., the fourth level) of the ramp signal Sweep. If this condition is not met, the first driving transistor M4 may not be fully conductive, affecting the pre-initialization effect of the first node Q1.

[0147] Based on any of the above embodiments, continue as Figure 1 shown, the pulse width modulation module PWM includes a first driving transistor M4. The pulse width modulation module PWM also receives a reference voltage Vref. The reference voltage Vref is provided to the control terminal (i.e., the second node N1) of the first driving transistor M4. The minimum voltage value (i.e., the fourth level) that the ramp signal Sweep can output is not greater than the voltage value of the reference voltage Vref, so that when the minimum voltage value that the ramp signal Sweep can output is transmitted to the second node N1, the potential of the first node N1 can be reduced, further alleviating the phenomenon that the potential of the second node N1 of W1 pulls up the reference voltage Vref during the initialization stage, reducing the probability that when using the reference voltage Vref to reset the anode (i.e., the third node Q4) of the light-emitting element D, it cannot be reset to the target reset level, and improving the phenomenon of slightly bright black screen and color deviation.

[0148] Based on any of the above embodiments, in one embodiment of this application, the amplitude modulation module PAM includes a second driving transistor M13. The amplitude modulation module PAM also receives a reference voltage Vref, a first power supply signal PVDD, and a second power supply signal PVEE. The reference voltage Vref is provided to the control terminal (i.e., the first node Q1) of the second driving transistor M13, and the voltage value of the first power supply signal PVDD is greater than the voltage value of the second power supply signal PVEE.

[0149] Optionally, in one embodiment of this application, the amplitude modulation module PAM further includes a second capacitor C1. One end of the second capacitor C1 is electrically connected to the control terminal (first node Q1) of the second driving transistor M13, and the other end is electrically connected to the first power signal PVDD, so as to store charge in the initialization stage W1 and maintain the potential of the first node Q1 in the light emission control stage W3.

[0150] As mentioned above, during the initialization phase W1, the reference voltage Vref resets the first node Q1. During the data writing phase W2 and the light emission control phase W3 of the first frame display, the potential of the first node Q1 is pulled high by the second data signal PAM_DATA and the first level VH2_1 of the first signal VH2. During the initialization phase W1 of the second frame display, the high potential of the first node Q1 has a counter-effect on the reference voltage Vref, pulling the potential of the reference voltage Vref high. Simultaneously, during the initialization phase W1, the reference voltage Vref is also used to reset the output terminal of the pixel circuit 10 (i.e., the anode of the light-emitting element D, i.e., the third node Q4). If the reference voltage Vref is pulled high, the third node Q4 cannot be reset to the target reset level. When the voltage difference between the potential of the third node Q4 and the second power supply signal PVEE reaches the turn-on voltage of the light-emitting element D, the light-emitting element D begins to emit light, causing the black screen to become slightly brighter.

[0151] Moreover, this phenomenon manifests differently for pixel circuits located at different positions along the first reference voltage signal transmission line. (Combined with...) Figure 17As shown, V1 represents the reference voltage Vref received by the pixel circuit at the proximal end (closer to the signal input end of the first reference voltage signal transmission line), and V3 represents the reference voltage Vref received by the pixel circuit at the distal end (farther from the signal input end of the first reference voltage signal transmission line). Here, R0 is the trace resistance for the reference voltage transmitted by the first reference voltage signal transmission line to reach this pixel circuit, and C1 is the second capacitor in the pixel circuit. According to the capacitor discharge formula V(t)=V0×e^(-t / (RC)), within the same discharge time t, the farther the pixel circuit is from the signal input end of the first reference voltage signal transmission line, the larger its corresponding trace resistance R0, and the larger V(t) is. That is, the reference voltage Vref received by the pixel circuit farther from the signal input end of the first reference voltage signal transmission line is pulled higher. Therefore, the black screen micro-brightness phenomenon of the pixel circuit farther from the signal input end of the first reference voltage signal transmission line is more serious.

[0152] To ensure that the light-emitting element D remains off during the black screen display, it is necessary to make the voltage difference between the potential of the third node Q4 after reset and the voltage of the second power supply signal PVEE less than the turn-on voltage Vled_on of the light-emitting element D, that is, VQ4 - PVEE < Vled_on. During the initialization stage W1, the potential VQ4 of the third node Q4 is approximately equal to the potential after being reset by the reference voltage Vref. If leakage is not considered and the lower plate voltage of the second capacitor C1 is the second level VH2_2, then the potential VQ4 of the third node Q4 after discharge can be expressed as: VQ4 = VH2_2×e^(-t / (R0C1)), where t represents the discharge time of the second capacitor C1, R0 represents the trace resistance for the reference voltage Vref to reach this pixel circuit, and C1 represents the capacitance value of the second capacitor C1.

[0153] Therefore, to ensure that the light-emitting element D remains off after reset, it is necessary to satisfy: VH2_2×e^(-t / (R0C1)) - PVEE < Vled_on.

[0154] By satisfying the above relationship, it can be ensured that during the initialization stage W1, even if the reference voltage Vref is pulled up by the counteraction of the potentials of the second node N1 and the first node Q1, the voltage difference between the reset potential of the third node Q4 and the second power supply signal PVEE is still less than the turn-on voltage of the light-emitting element D, so that the light-emitting element D does not emit light, thereby effectively improving the black screen micro-brightness phenomenon and color deviation phenomenon.

[0155] As known from the foregoing, the turn-on voltage of the red light-emitting element is less than the turn-on voltages of the blue light-emitting element and the green light-emitting element. When the voltage of the reference voltage Vref is pulled up, it will first reach the turn-on voltage of the red light-emitting element, so that the micro-brightness phenomenon of the black screen mainly shows a red screen.

[0156] Therefore, in one embodiment of this application, when the display panel includes a red light-emitting element, a blue light-emitting element, and a green light-emitting element, Vled_on is the turn-on voltage of the red light-emitting element, so as to further improve the phenomenon of dim brightness in black screen and color deviation.

[0157] Optionally, in one embodiment of this application, the voltage value of the reference voltage Vref is not greater than the voltage value of the second power signal PVEE, so as to further reduce the voltage difference between the potential of the third node Q4 after the initialization phase W1 is reset and the second power signal PVEE by setting the voltage value of the reference voltage Vref to be no higher than PVEE, thereby better ensuring that the light-emitting element D remains in the off state when the screen is black.

[0158] It should be noted that when the reference voltage Vref and the second power signal PVEE are negative, the absolute value of the reference voltage Vref is not less than the absolute value of the second power signal PVEE; when the reference voltage Vref and the second power signal PVEE are positive, the absolute value of the reference voltage Vref is not greater than the absolute value of the second power signal PVEE.

[0159] Optionally, in one embodiment of this application, the voltage value of the reference voltage Vref is in the range of -8V to -4V, so as to improve the reset effect of the reference voltage Vref when resetting the first node Q1, the second node N1 and the third node Q4 using the reference voltage Vref.

[0160] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 1 As shown, the pulse width modulation module (PWM) includes a first driving transistor M4, and the amplitude modulation module (PAM) includes a second driving transistor M13. The control terminal of the second driving transistor M13 is connected to the first node Q1. The control terminal of the first driving transistor M4 (second node N1), the first node Q1, and the output terminal of the pixel circuit 10 (third node Q4) are electrically connected to the same reference voltage transmission line and receive the reference voltage Vref in the same time period.

[0161] Specifically, in one embodiment of this application, the pulse width modulation module (PWM) further includes a first initialization circuit, and the amplitude modulation module (PAM) further includes a second initialization circuit and a third initialization circuit. The first initialization circuit includes a first transistor M0 and a second transistor M1, the second initialization circuit includes a third transistor M8 and a fourth transistor M9, and the fourth initialization circuit includes a fifth transistor M16. Under the control of the first scan signal Scan1, the first transistor M0 and the second transistor M1 transmit the reference voltage Vref to the second node N1 to reset the second node N1; under the control of the first scan signal Scan1, the third transistor M8 and the fourth transistor M9 transmit the reference voltage Vref to the first node Q1 to reset the first node Q1; and under the control of the first scan signal Scan1, the fifth transistor M16 transmits the reference voltage Vref to the third node Q4 to reset the third node Q4.

[0162] like Figure 4 As shown, during the initialization phase W1 when the first scan signal Scan1 is low, the second node N1, the first node Q1, and the third node Q4 are simultaneously reset by the reference voltage Vref. Since the first node Q1 is pre-initialized in the second time period T2, its potential has been pulled low before the initialization phase W1 begins. Therefore, when the first scan signal Scan1 is low, the reaction of the first node Q1 to the reference voltage Vref is weakened, and the reference voltage Vref is not significantly pulled high. This ensures that the third node Q4 can be reset to the target reset level, avoiding slightly bright black areas and mitigating color shift, thereby improving display quality.

[0163] Optionally, in another embodiment of this application, such as Figure 18 As shown, the pulse width modulation (PWM) module includes a first driving transistor M4, and the amplitude modulation (PAM) module includes a second driving transistor M13. The control terminal of the second driving transistor M13 is connected to the first node Q1. The control terminal of the first driving transistor M4 (second node N1), the first node Q1, and the output terminal of the pixel circuit 10 (i.e., the third node Q4) are electrically connected to the same reference voltage transmission line. The control terminal of the first driving transistor M4 (second node N1) and the output terminal of the pixel circuit 10 (third node Q4) receive the reference voltage Vref at different time periods, and the first node Q1 and the output terminal of the pixel circuit 10 (i.e., the third node Q4) also receive the reference voltage Vref at different time periods.

[0164] Specifically, in this embodiment, the reset period of the third node Q4 is staggered from the reset periods of the second node N1 and the first node Q1. For example, different scan time controls can be used to avoid the reaction of the second node N1 and the first node Q1 on Vref from affecting the reset effect of the third node Q4, and further ensure that the third node Q4 can be reset to the target low level.

[0165] It should be noted that in the above embodiments, the first node Q1 and the second node N1 may receive the reference voltage Vref at the same time period or at different time periods. This application does not limit this, and it depends on the specific situation.

[0166] Optionally, in one embodiment of this application, the first node Q1 and the second node N1 are reset during the conduction period corresponding to the first scan signal Scan1, and the third node Q4 is reset during the conduction period corresponding to the second scan signal Scan2. That is, the third node Q4 is reset during the data input stage to simplify the circuit structure and signal line arrangement in the display panel. However, this application does not limit this. In other embodiments of this application, the third node Q4 can also be set with a separate control signal to control its reset time, depending on the specific situation.

[0167] Specifically, in one embodiment of this application, the following continues... Figure 18 As shown, the pulse width modulation module (PWM) also includes a first initialization circuit, and the amplitude modulation module (PAM) also includes a second initialization circuit and a third initialization circuit. The first initialization circuit includes a first transistor M0 and a second transistor M1, the second initialization circuit includes a third transistor M8 and a fourth transistor M9, and the fourth initialization circuit includes a fifth transistor M16. Under the control of the first scan signal Scan1, the first transistor M0 and the second transistor M1 transmit the reference voltage Vref to the second node N1 to reset the second node N1. Under the control of the first scan signal Scan1, the third transistor M8 and the fourth transistor M9 transmit the reference voltage Vref to the first node Q1 to reset the first node Q1. Under the control of the second scan signal Scan2, the fifth transistor M16 transmits the reference voltage Vref to the third node Q4 to reset the third node Q4.

[0168] Optionally, in yet another embodiment of this application, such as Figure 19As shown, the pulse width modulation (PWM) module includes a first driving transistor M4, and the amplitude modulation (PAM) module includes a second driving transistor M13. The control terminal of the second driving transistor M13 is connected to the first node Q1. The control terminal of the first driving transistor M4 (the second node N1) and the output terminal of the pixel circuit 10 (i.e., the third node Q4) are electrically connected to different reference voltage transmission lines, receiving the reference voltage Vref in the same time period; the first node Q1 and the output terminal of the pixel circuit 10 (i.e., the third node Q4) are electrically connected to different reference voltage transmission lines, receiving the reference voltage Vref in the same time period.

[0169] In this embodiment, the third node Q4, the second node N1, and the first node Q1 all use different reference voltage transmission lines to provide reference voltages. This makes the reference voltage transmission line corresponding to the third node Q4 independent of the reference voltage transmission lines corresponding to the first node Q1 and the second node N1. This ensures that even if the potentials of the second node N1 and the first node Q1 have a counteracting effect on the reference voltage transmission lines they are connected to, it will not affect the potential of the reference voltage transmission line connected to the third node Q4, thus guaranteeing the reset effect of the third node Q4.

[0170] It should be noted that in this embodiment, the first node Q1 and the second node N1 can be electrically connected to the same reference voltage transmission line to simplify the circuit structure and the number of signal lines in the display panel, or they can be electrically connected to different reference voltage transmission lines so that the reference voltage transmission lines corresponding to the first node Q1 and the second node N1 are independent of each other. This application does not limit this, and it depends on the specific situation.

[0171] Specifically, in one embodiment of this application, the following continues... Figure 19 As shown, the pulse width modulation module (PWM) further includes a first initialization circuit, and the amplitude modulation module (PAM) further includes a second initialization circuit and a third initialization circuit. The first initialization circuit includes a first transistor M0 and a second transistor M1; the second initialization circuit includes a third transistor M8 and a fourth transistor M9; and the fourth initialization circuit includes a fifth transistor M16. Under the control of the first scan signal Scan1, the first transistor M0 and the second transistor M1 provide the reference voltage transmitted through the first reference voltage transmission line Vref1 to the second node N1, resetting the second node N1. Under the control of the first scan signal Scan1, the third transistor M8 and the fourth transistor M9 provide the reference voltage transmitted through the second reference voltage transmission line Vref2 to the first node Q1, resetting the first node Q1. Under the control of the first scan signal Scan1, the fifth transistor M16 provides the reference voltage transmitted through the third reference voltage transmission line Vref3 to the third node Q4, resetting the third node Q4.

[0172] Optionally, in one embodiment of this application, such as Figure 20 As shown, the second node N1 in each pixel circuit is electrically connected to the same first reference voltage transmission line Vref1, the first node Q1 in each pixel circuit is electrically connected to the same second reference voltage transmission line Vref2, and the third node Q4 in each pixel circuit is electrically connected to the same third reference voltage transmission line Vref3. This ensures that the reference voltage transmission lines corresponding to the first node Q1, the second node N1, and the third node Q4 are independent of each other. This way, even if the potentials of the second node N1 and the first node Q1 have a counteracting effect on their respective reference voltage transmission lines, it will not affect the potential of the reference voltage transmission line to which the third node Q4 is connected, thus guaranteeing the reset effect of the third node Q4.

[0173] Optionally, in another embodiment of this application, such as Figure 21 As shown, the pulse width modulation (PWM) module includes a first driving transistor M4, and the amplitude modulation (PAM) module includes a second driving transistor M13. The control terminal of the second driving transistor M13 is connected to the first node Q1. The control terminal of the first driving transistor M4 (second node N1) and the output terminal of the pixel circuit 10 (third node Q4) are electrically connected to different reference voltage transmission lines and receive the reference voltage Vref at different time periods. The first node Q1 and the output terminal of the pixel circuit (third node Q4) are also electrically connected to different reference voltage transmission lines and receive the reference voltage Vref at different time periods. This embodiment combines time-division reset and independent reference voltage transmission lines, further improving the reset reliability of the third node Q4 and more effectively avoiding the phenomenon of slightly bright black screens.

[0174] Based on any of the above embodiments, in one embodiment of this application, the following continues... Figure 1 As shown, the pulse width modulation module PWM also receives the first data signal PWM_DATA. In this embodiment, the pulse width modulation module PWM further includes a sixth transistor M5, a seventh transistor M2, and an eighth transistor M3. The first terminal of the fifth transistor M5 receives the first data signal PWM_DATA, and the second terminal is electrically connected to the first terminal of the first driving transistor M4. The second terminal of the first driving transistor M4 is electrically connected to the first terminal of the eighth transistor M3. The second terminal of the eighth transistor M3 is electrically connected to the first terminal of the seventh transistor M2. The second terminal of the seventh transistor M2 is electrically connected to the second node N1. The control terminals of the sixth transistor M5, the seventh transistor M2, and the eighth transistor M3 all receive the control of the second scan signal Scan2. Under the control of the second scan signal Scan2, the first data signal PWM_DATA is written into the first node N1.

[0175] The amplitude modulation module PAM also receives a second data signal PAM_DATA. In this embodiment, the amplitude modulation module PWM further includes a ninth transistor M15, a tenth transistor M10, and an eleventh transistor M11. The first terminal of the ninth transistor M15 receives the first data signal PAM_DATA, and the second terminal is electrically connected to the first terminal of the second driving transistor M13. The second terminal of the second driving transistor M13 is electrically connected to the first terminal of the eleventh transistor M11. The second terminal of the eleventh transistor M11 is electrically connected to the first terminal of the tenth transistor M10. The second terminal of the tenth transistor M10 is electrically connected to the first node Q1. The control terminals of the ninth transistor M15, the tenth transistor M10, and the eleventh transistor M11 all receive the control of the second scan signal Scan2. Under the control of the second scan signal Scan2, the second data signal PAM_DATA is written into the first node Q1.

[0176] Based on any of the above embodiments, in one embodiment of this application, the pulse width modulation module PWM further includes a third capacitor C0. The first plate of the third capacitor C0 receives the slope signal Sweep, and the second plate is electrically connected to the second node N1 so as to provide the voltage value of the slope signal Sweep to the second node N1 through coupling.

[0177] Based on any of the above embodiments, in one embodiment of this application, the display panel may be a Mini-LED display panel, an OLED display panel or a Micro-LED display panel. This application does not limit the specific type of display panel and may use it as appropriate.

[0178] Correspondingly, such as Figure 22 As shown, this application embodiment also provides a display device, which includes the display panel provided in any of the above embodiments. Since the relevant content of the display panel has been described in detail in the above embodiments, it will not be repeated here.

[0179] Optionally, in one embodiment of this application, the display device may be a mobile phone, tablet computer, wearable device, in-vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), or other device with display function. This application does not limit the scope of the device and the specific device may be selected based on the circumstances.

[0180] In summary, in the display panel and display device provided in this application embodiment, the operation of the pixel circuit 10 includes a first time period T1 and a second time period T2. During the first time period T1, the first node Q1 receives the first signal VH2, and during the second time period T2, the first node Q1 receives the first signal VH2. That is, during both the first time period T1 and the second time period T2, the first node Q1 receives the first signal VH2. The difference is that the first signal VH2 is at a first level VH2_1 during the first time period T1 and at a second level VH2_2 during the second time period T2. The second level VH2_2 is different from the first level VH2_1, so that the first node Q1 receives different level signals during the first time period T1 and the second time period T2.

[0181] In this embodiment, the first time period T1 overlaps with the light-emitting stage, so that the first level VH2_1 can be transmitted to the first node Q1 during the light-emitting stage. The second time period T2 is located within the non-light-emitting stage, so that the second level VH2_2 can be transmitted to the first node Q1 during the non-light-emitting stage. This does not affect the working state of the light-emitting element D and resets the first node Q1, thereby reducing the probability that the working state of the light-emitting element D will be affected due to the incomplete reset of the first node Q1 (i.e., failure to reach the target reset level). This alleviates the phenomenon of slightly bright black screens and color shift on the display panel and improves the display quality of the display panel.

[0182] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0183] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

Claims

1. A display panel, characterized in that, include: A pixel circuit, comprising a pulse width modulation (PWM) module and an amplitude modulation (AM) module, wherein the PWM module outputs a pulse width setting signal, and the AM module outputs an amplitude setting signal; the PWM module receives at least a first signal, and provides the first signal to a first node of the AM module, wherein... The operation of the pixel circuit includes a first time period and a second time period. During the first time period, the first node receives the first signal, and during the second time period, the first node receives the first signal. The first signal is at a first level during the first time period, and the first signal is at a second level during the second time period, wherein the second level is different from the first level; The operation of the pixel circuit includes a light-emitting stage and a non-light-emitting stage. The first time period and the light-emitting stage overlap, and the second time period is located within the non-light-emitting stage.

2. The display panel according to claim 1, characterized in that, The display panel further includes: a first signal control circuit, which receives a second signal and provides the first signal to the pulse width modulation module based on the second signal; The second signal is either the first level or the second level.

3. The display panel according to claim 2, characterized in that, The first signal control circuit includes: a first control switch and a first comparator; wherein, The input terminal of the first control switch receives the second signal, the output terminal is electrically connected to the positive input terminal of the first comparator, and the control terminal receives the first control signal; The negative input terminal of the first comparator is electrically connected to its output terminal, and the output terminal outputs the first signal. Wherein, the second signal is a first level, the first control signal controls the first control switch to be turned on during the first time period, and the output terminal of the first comparator outputs a first level; during the second time period, it controls the first control switch to be turned off, and the output terminal of the first comparator outputs a second level.

4. The display panel according to claim 1, characterized in that, The pulse width modulation module also receives a first light emission control signal and a ramp signal. Under the control of the first light emission control signal and the ramp signal, the pulse width modulation module provides the first signal to the first node. The amplitude modulation module receives at least a second light emission control signal and a first power supply signal, and outputs the amplitude setting signal under the control of the second light emission control signal and the signal received by the first node. The first time period overlaps with the conduction time period corresponding to the first light emission control signal, and also overlaps with the conduction time period corresponding to the second light emission control signal; The second time period overlaps with the conduction time period corresponding to the first light emission control signal, but does not overlap with the conduction time period corresponding to the second light emission control signal.

5. The display panel according to claim 4, characterized in that, The second time period includes a first sub-time period, which is located within the conduction period corresponding to the first light emission control signal and within the cutoff period corresponding to the second light emission control signal.

6. The display panel according to claim 5, characterized in that, The second time period also includes a second sub-time period, which is located within the cutoff time period corresponding to the first light emission control signal and within the cutoff time period corresponding to the second light emission control signal.

7. The display panel according to claim 5, characterized in that, During the operation of the pixel circuit, the start time of the second time period is no earlier than the end time of the conduction time period corresponding to the second light emission control signal in the current working cycle, and the end time of the second time period is no later than the moment when the voltage of the ramp signal begins to increase in the next working cycle.

8. The display panel according to claim 5, characterized in that, During the operation of the pixel circuit, within the same working cycle, the start time of the second time period is no earlier than the end time of the conduction time period corresponding to the second light emission control signal, and no later than the end time of the conduction time period corresponding to the first light emission control signal.

9. The display panel according to claim 8, characterized in that, Within the same working cycle, the start time of the second time period is the end time of the conduction period corresponding to the second light emission control signal, and the end time of the second time period is the end time of the conduction duration corresponding to the first light emission control signal.

10. The display panel according to claim 4, characterized in that, The start time of the conduction period of the first light emission control signal is earlier than the start time of the conduction period of the second light emission control signal.

11. The display panel according to claim 4, characterized in that, The operation of the pixel circuit is within the same working cycle. The time when the voltage of the ramp signal starts to increase is later than the end time of the conduction duration corresponding to the first scan signal and the end time of the conduction duration corresponding to the second scan signal. The time when the voltage of the ramp signal increases to the third level is no later than the start time of the conduction period corresponding to the first light emission control signal. The third level is the maximum voltage that the ramp signal can output. The operation of the pixel circuit includes an initialization period and a data writing period. The conduction period corresponding to the first scan signal is the period for initializing the first node; the conduction period corresponding to the second scan signal is the period for writing data to the first node.

12. The display panel according to claim 4, characterized in that, The operation of the pixel circuit includes multiple working cycles. Within the same working cycle, the moment when the voltage of the ramp signal decreases to the fourth level is the end time of the conduction duration corresponding to the second light emission control signal. The fourth level is the minimum voltage value that the ramp signal can output.

13. The display panel according to claim 12, characterized in that, Also includes: A ramp signal control circuit, comprising: a second control switch, a third control switch, a current source, and a second comparator; wherein, The input terminal of the second control switch receives a third signal, the output terminal is electrically connected to the positive input terminal of the second comparator, and the control terminal receives a second control signal. The negative input terminal of the second comparator is electrically connected to its output terminal, and the output terminal outputs the ramp signal; One end of the current source is electrically connected to the output terminal of the second control switch, and the other end is grounded; The third control switch has its input terminal electrically connected to the output terminal of the second control switch, and its output terminal is grounded through the first capacitor. The control terminal receives a third control signal. In the third time period, the second control signal controls the second control switch to turn on, the third control signal controls the third control switch to turn on, the second comparator outputs the third signal to the pulse width modulation module, and the voltage of the ramp signal gradually increases to its maximum output voltage value; in the fourth time period, the second control signal controls the second control switch to turn off, the third control signal controls the third control switch to turn on, and the voltage of the ramp signal gradually decreases. During the second time period, the second control signal controls the second control switch to close, the third control signal controls the third control switch to close, and the output of the second comparator outputs the fourth level.

14. The display panel according to claim 13, characterized in that, The third control switch includes multiple sub-control switches. The input terminal of each sub-control switch is electrically connected to the output terminal of the second control switch, and the output terminal is grounded through a first capacitor. The control terminal receives the third control signal.

15. The display panel according to claim 4, characterized in that, The pulse width modulation module includes a first driving transistor, which is located on the path from the first signal to the first node. The ramp signal is provided to the control terminal of the first driving transistor, and the voltage value of the second level is greater than the difference between the minimum voltage that the ramp signal can output and the threshold voltage of the first driving transistor.

16. The display panel according to claim 4, characterized in that, The pulse width modulation module includes a first driving transistor; The pulse width modulation module also receives a reference voltage, which is provided to the control terminal of the first driving transistor; the minimum voltage that the ramp signal can output is not greater than the voltage value of the reference voltage.

17. The display panel according to claim 4, characterized in that, The amplitude modulation module includes a second driving transistor; the amplitude modulation module also receives a reference voltage, a first power supply signal, and a second power supply signal. The reference voltage is provided to the control terminal of the second driving transistor. The voltage value of the first power supply signal is greater than the voltage value of the second power supply signal. The second voltage level and the second power supply signal satisfy: VH2_2×e^(-t / (R0C1))-PVEE <Vled_on; Wherein, PVEE represents the second power signal, VH2_2 represents the second level, Vled_on represents the turn-on voltage of the light-emitting element electrically connected to the output terminal of the pixel circuit, C1 represents the capacitance value of the second capacitor, one end of the second capacitor is electrically connected to the first power signal, and the other end is electrically connected to the control terminal of the second driving transistor, t represents the discharge time of the second capacitor, and R0 represents the trace resistance of the reference voltage transmitted to the pixel circuit.

18. The display panel according to any one of claims 1-17, characterized in that, The pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor. The control terminal of the second driving transistor is connected to the first node. The control terminal of the first driving transistor, the first node, and the output terminal of the pixel circuit are electrically connected to the same reference voltage transmission line and receive the reference voltage at the same time.

19. The display panel of any one of claims 1-17, wherein, The pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor. The control terminal of the second driving transistor is connected to the first node. The control terminal of the first driving transistor, the first node, and the output terminal of the pixel circuit are electrically connected to the same reference voltage transmission line. The control terminal of the first driving transistor and the output terminal of the pixel circuit receive the reference voltage at different time periods, and the first node and the output terminal of the pixel circuit receive the reference voltage at different time periods.

20. The display panel of any one of claims 1-17, wherein, The pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor. The control terminal of the second driving transistor is connected to the first node. The control terminal of the first driving transistor and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at the same time. The first node and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at the same time.

21. The display panel of any of claims 1-17, wherein, The pulse width modulation module includes a first driving transistor, and the amplitude modulation module includes a second driving transistor. The control terminal of the second driving transistor is connected to the first node. The control terminal of the first driving transistor and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at different time periods; The first node and the output terminal of the pixel circuit are electrically connected to different reference voltage transmission lines, and receive the reference voltage at different time periods.

22. A display device comprising: Includes the display panel as described in any one of claims 1-21.

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