Display panel and control circuit thereof

Abstract

The application provides a display panel and a control circuit thereof. The control circuit comprises a temperature detection module, a level conversion module and a control module. The temperature detection module detects a first temperature signal of a target region in the display panel. The level conversion module outputs a target clock pulse signal and a first clock control signal according to the first temperature signal. The control module comprises an inverting unit, a selection unit, a first resistive unit and a second resistive unit. The resistance of the first resistive unit is greater than that of the second resistive unit. The inverting unit receives the first clock control signal and outputs a second clock control signal. The selection unit selects one resistive unit to be coupled with a gate drive circuit according to the second clock control signal, so as to adjust the current of the target clock pulse signal flowing through the gate drive circuit. The application selects the first resistive unit or the second resistive unit to be coupled with the gate drive circuit, so that the control circuit can dynamically adjust the driving current of the gate drive circuit according to the actual temperature of the target region.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to display panels and their control circuits. Background Technology

[0002] Nowadays, display panels have increasingly higher refresh rates, and the operating frequency of the gate drive circuit is also increasing. Since the gate drive circuit is typically located in a specific area of ​​the display panel, the temperature generated during its operation will affect the display panel. For example, if the gate drive circuit generates a high temperature, it can cause display abnormalities. Summary of the Invention

[0003] The display panel and its control circuit provided in this application can effectively improve the temperature of the gate drive circuit during operation and reduce display abnormalities caused by temperature.

[0004] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: to provide a control circuit for a display panel, the control circuit including: a temperature detection module, a level conversion module and a control module; The temperature detection module is configured to detect the temperature of a target area in the display panel and generate a first temperature signal based on the temperature; wherein, the target area is provided with a gate driving circuit; The level conversion module is coupled to the temperature detection module and is configured to output a target clock pulse signal and output a first clock control signal according to the first temperature signal; The control module includes an inverting unit, a selection unit, a first resistive unit, and a second resistive unit; the resistance value of the first resistive unit is greater than that of the second resistive unit. The input terminal of the inverting unit is coupled to the level conversion module and is configured to receive the first clock control signal, invert the first clock control signal, and output the second clock control signal. The input terminal of the selection unit is coupled to the level conversion module and is configured to receive the target clock pulse signal. The control terminal of the selection unit is coupled to the output terminal of the inverting unit and is configured to receive the second clock control signal. The first output terminal of the selection unit is coupled to one end of the first resistive unit, and the second output terminal of the selection unit is coupled to one end of the second resistive unit. The other end of the first resistive unit and the other end of the second resistive unit are used to couple to the gate drive circuit. The selection unit is configured to select, according to the second clock control signal, to couple the input terminal of the selection unit to the gate drive circuit through the first resistive unit or the second resistive unit, and adjust the current flowing through the gate drive circuit of the target clock pulse signal.

[0005] In one embodiment, the inverting unit includes: a first transistor and a second transistor; The first terminal of the first transistor is used to receive the first voltage signal; The first terminal of the second transistor is coupled to the second terminal of the first transistor, and the second terminal of the second transistor is used to receive a second voltage signal; the voltage of the second voltage signal is less than the voltage of the first voltage signal; the coupling point between the first terminal of the second transistor and the second terminal of the first transistor serves as the output terminal of the inverting unit. The control terminals of the first and second transistors are coupled to a level conversion module and are configured to receive a first clock control signal.

[0006] In one embodiment, the selection unit includes: a first selection subunit and a second selection subunit; The input terminal of the first selection subunit is coupled to the level conversion module and is configured to receive the target clock pulse signal. The first control terminal of the first selection subunit is coupled to the level conversion module and is configured to receive the first clock control signal. The second control terminal of the first selection subunit is coupled to the output terminal of the inverting unit and is configured to receive the second clock control signal. The output terminal of the first selection subunit is coupled to one end of the first resistive unit. The input terminal of the second selection subunit is coupled to a level conversion module and is configured to receive a target clock pulse signal. The first control terminal of the second selection subunit is coupled to a level conversion module and is configured to receive a first clock control signal. The second control terminal of the second selection subunit is coupled to the output terminal of the inverting unit and is configured to receive a second clock control signal. The output terminal of the second selection subunit is coupled to one end of the second resistive unit.

[0007] In one embodiment, the first selection subunit includes a third transistor and a fourth transistor; The control terminal of the third transistor is coupled to the first control terminal of the first selection subunit and is configured to receive the first clock control signal. The control terminal of the fourth transistor is the second control terminal of the first selection subunit coupled to the output terminal of the inverting unit, and is configured to receive the second clock control signal; The first terminal of the third transistor is coupled to the first terminal of the fourth transistor, and is coupled to the level conversion module as the input terminal of the first selection sub-unit, and is configured to receive the target clock pulse signal; The second terminal of the third transistor is coupled to the second terminal of the fourth transistor, and the output terminal of the first selection sub-unit is coupled to one end of the first resistive unit. The third transistor turns on in response to the first clock control signal being a high-level signal, and the fourth transistor turns on in response to the second clock control signal being a low-level signal.

[0008] In one embodiment, the second selection subunit includes a fifth transistor and a sixth transistor; The control terminal of the sixth transistor is coupled to the first control terminal of the second selection subunit and is configured to receive the first clock control signal. The control terminal of the fifth transistor is the second control terminal of the second selection subunit, coupled to the output terminal of the inverting unit, and is configured to receive the second clock control signal; The first terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and is coupled to the level conversion module as the input terminal of the second selection sub-unit, and is configured to receive the target clock pulse signal; The second terminal of the fifth transistor is coupled to the second terminal of the sixth transistor, and the output terminal of the second selection sub-unit is coupled to one end of the second resistive unit. The fifth transistor turns on in response to the second clock control signal being high, and the sixth transistor turns on in response to the first clock control signal being low.

[0009] In one embodiment, the level conversion module includes a timing control unit and a level conversion unit; The timing control unit is coupled to the temperature detection module and is configured to receive a first temperature signal, output a primary clock pulse signal, and output a primary clock control signal based on the first temperature signal and the primary clock pulse signal. The level conversion unit is coupled to the timing control unit and is configured to convert the primary clock pulse signal into the target clock pulse signal and the primary clock control signal into the first clock control signal.

[0010] In one embodiment, the timing control unit responds to the first temperature signal being a low-level signal by outputting a primary clock control signal as a low-level signal, and the output first clock control signal being a low-level signal to obtain a high-level second clock control signal. The selection unit is configured to select, according to the high-level second clock control signal, to couple the input terminal of the selection unit to the gate drive circuit through a second resistive unit. The timing control unit responds to the first temperature signal being a high-level signal by controlling the primary clock control signal, thereby changing the first clock control signal so that the high level of the first clock control signal appears earlier than the high level of the target clock pulse signal. The selection unit is configured to, when the second clock control signal is low, select to couple the input terminal of the selection unit to the gate drive circuit through the first resistive unit, and when the target clock pulse signal is low and the second clock control signal is high, select to couple the input terminal of the selection unit to the gate drive circuit through the second resistive unit.

[0011] In one embodiment, the temperature detection module includes: a data acquisition unit and an output unit; The input terminal of the acquisition unit is coupled to the power input terminal and is configured to acquire the temperature of the target area in the display panel and generate an initial temperature signal based on the temperature. The output unit is coupled to the acquisition unit and the level conversion module, and is configured to generate a first temperature signal based on the initial temperature signal.

[0012] In one embodiment, the acquisition unit includes a first voltage divider unit and a voltage follower unit; The first terminal of the first voltage divider unit is connected to the power input terminal, the second terminal of the first voltage divider unit is grounded, and the voltage divider node of the first voltage divider unit is connected to the first input terminal of the voltage follower unit; the second input terminal of the voltage follower unit is connected to the output terminal of the voltage follower unit, and the output terminal of the voltage follower unit is connected to the output unit. The output unit includes: a second voltage divider unit, a third voltage divider unit, and an operational amplifier unit; The first end of the second voltage divider unit is connected to the output of the voltage follower unit, the second end of the second voltage divider unit is connected to the output of the operational amplifier unit, and the voltage divider node of the second voltage divider unit is connected to the first input of the operational amplifier unit; the first end of the third voltage divider unit is connected to the power input, the second end of the third voltage divider unit is grounded, and the voltage divider node of the third voltage divider unit is connected to the second input of the operational amplifier unit; the output of the operational amplifier unit is used to output the first temperature signal.

[0013] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: to provide a display panel, the display panel including: a gate driving circuit and a control circuit; The gate driving circuit is disposed on the array substrate of the display panel; The control circuit is coupled to the gate drive circuit, and the control circuit is the control circuit provided by the first technical solution above.

[0014] The beneficial effects of this application are as follows: Unlike the prior art, the control circuit of the display panel of this application detects the temperature of the target area of ​​the display panel through a temperature detection module, and then outputs a target clock pulse signal through a level conversion module. It also outputs a first clock control signal based on the first temperature signal, and in the control module, it uses an inverting unit to invert the first clock control signal and outputs a second clock control signal. This allows the selection unit in the control module to select the first resistive unit or the second resistive unit to be coupled to the gate drive circuit based on the second clock control signal, thereby dynamically adjusting the current flowing through the gate drive circuit of the target clock pulse signal. Specifically, when the first temperature signal indicates a high temperature, the selection unit selects the first resistive unit to couple with the gate drive circuit, so that the target clock pulse signal flows through a larger resistor, thereby limiting the current flowing through the gate drive circuit traces, and thus reducing the heat generation of the gate drive circuit traces. This effectively improves the temperature of the gate drive circuit during operation, prevents local overheating from causing display abnormalities on the display panel, and helps protect the normal display function of the display panel. When the first temperature signal indicates a low temperature, the selection unit selects the second resistive unit to couple with the gate drive circuit, so that the target clock pulse signal can be transmitted with less resistance loss, ensuring the display quality of the display panel at low / normal temperatures. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the structure of an embodiment of the control circuit for the display panel provided in this application; Figure 2 Provided for this application Figure 1 A circuit diagram of one embodiment of a medium temperature detection module; Figure 3 Provided for this application Figure 1 A schematic diagram illustrating the hysteresis effect of an embodiment of a temperature detection module; Figure 4 Provided for this application Figure 1 A circuit diagram of the first embodiment of the control module; Figure 5 Provided for this application Figure 1 A schematic diagram of the structure of the first embodiment of the level conversion module; Figure 6 Provided for this application Figure 1 A schematic diagram of the structure of the second embodiment of the level conversion module; Figure 7 Provided for this application Figure 1 A circuit diagram of the second embodiment of the control module; Figure 8 Provided for this application Figure 1 A schematic diagram of the third embodiment of the level conversion module; Figure 9 Provided for this application Figure 1 A schematic diagram of the structure of the fourth embodiment of the level conversion module; Figure 10 Provided for this application Figure 1 A circuit diagram of the third embodiment of the control module; Figure 11 Provided for this application Figure 10 A timing waveform diagram of one embodiment; Figure 12 A schematic diagram of the structure of an embodiment of the display panel provided in this application.

[0017] Reference numerals: Display panel 1000, array substrate 100, gate drive circuit 110, control circuit 200, temperature detection module 210, level conversion module 220, control module 230, inverting unit 231, selection unit 232, first resistive unit R_H, second resistive unit R_L, initial temperature signal Vt, first temperature signal Vs, primary clock pulse signal CPV, target clock pulse signal CKV, primary clock control signal CK_CTL_OUT, first clock control signal CK_CTL, second clock control signal CK_CTL', first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, first selection subunit 2321, second selection subunit 2322, timing control unit 221, level conversion unit 222, acquisition unit 211, output unit 212, thermistor R0, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, voltage follower unit OP1, operational amplifier unit OP2, first voltage divider unit 2111, second voltage divider unit 2112, third voltage divider unit 2113, voltage divider node N1 of the first voltage divider unit, voltage divider node N2 of the second voltage divider unit, voltage divider node N3 of the third voltage divider unit, power input terminal VCC. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0020] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0023] like Figure 1 As shown, Figure 1 This is a schematic diagram of an embodiment of the control circuit for the display panel provided in this application. The control circuit 200 includes a temperature detection module 210, a level conversion module 220, and a control module 230. The temperature detection module 210 is configured to detect the temperature of a target area in the display panel 1000 and generate a first temperature signal Vs based on the temperature; wherein, a gate driving circuit 110 is provided in the target area; the level conversion module 220 is coupled to the temperature detection module 210 and is configured to output a target clock pulse signal CKV and output a first clock control signal CK_CTL based on the first temperature signal Vs.

[0024] It should be noted that the target area in this application embodiment can be, for example, a location in the display panel 1000 where the wiring is dense and the current carrying capacity is large, such as the area on the lower side of the display panel 1000 where the gate driving circuit 110 is provided.

[0025] In this embodiment, the temperature detection module 210 is used to monitor the temperature status of the target area in the display panel 1000 in real time and generate a first temperature signal Vs, which can be a voltage signal. It is understood that the temperature detection module 210 includes a temperature-sensing element capable of detecting temperature changes, such as a thin-film NTC (Negative Temperature Coefficient) thermistor R0, whose resistance changes according to temperature. When the temperature rises, the resistance of the thin-film thermistor R0 decreases; when the temperature decreases, the resistance of the thin-film thermistor R0 increases. Based on this, when the temperature rises, the first temperature signal Vs generated by the temperature detection module 210 is a high-level signal; when the temperature decreases, the first temperature signal Vs generated by the temperature detection module 210 is a low-level signal.

[0026] In this embodiment, the level conversion module 220 is responsible for converting low-voltage logic level signals into level signals suitable for the operation of the high-voltage drive circuit inside the display panel 1000. For example, it converts low-level logic signals into VGH (Voltage Gate High) and VGL (Voltage Gate Low) signals. Specifically, it outputs the first clock control signal CK_CTL according to the first temperature signal Vs and transmits it to the control module 230. At the same time, it directly transmits the target clock pulse signal CKV to the control module 230.

[0027] The control module 230 further includes an inverting unit 231, a selection unit 232, a first resistive unit R_H, and a second resistive unit R_L; the resistance value of the first resistive unit R_H is greater than that of the second resistive unit R_L. The input terminal of the inverting unit 231 is coupled to a level conversion module 220 and is configured to receive a first clock control signal CK_CTL, invert the first clock control signal CK_CTL, and output a second clock control signal CK_CTL'.

[0028] It should be noted that in this embodiment, the first resistive unit R_H can be a high-resistance resistor or multiple low-resistance resistors connected in series; the second resistive unit R_L can be a low-resistance resistor.

[0029] The input terminal of the selection unit 232 is coupled to the level conversion module 220 and is configured to receive the target clock pulse signal CKV. The control terminal of the selection unit 232 is coupled to the output terminal of the inverting unit 231 and is configured to receive the second clock control signal CK_CTL'. The first output terminal of the selection unit 232 is coupled to one end of the first resistive unit R_H, and the second output terminal of the selection unit 232 is coupled to one end of the second resistive unit R_L. The other end of the first resistive unit R_H and the other end of the second resistive unit R_L are used to couple to the gate drive circuit 110.

[0030] The selection unit 232 is configured to select, according to the second clock control signal CK_CTL', to couple the input terminal of the selection unit 232 to the gate drive circuit 110 through the first resistive unit R_H or the second resistive unit R_L, and adjust the current flowing through the gate drive circuit 110 of the target clock pulse signal CKV.

[0031] It should be noted that the inverting unit 231 in the control module 230 is used to generate complementary control signals based on the received first clock control signal CK_CTL, that is, to invert the first clock control signal CK_CTL and output a second clock control signal CK_CTL', so as to drive different paths in the selection unit 232. When the first clock control signal CK_CTL is at a high level, the second clock control signal CK_CTL' is at a low level. When the first clock control signal CK_CTL is at a low level, the second clock control signal CK_CTL' is at a high level.

[0032] In this embodiment, the selection unit 232 can select to couple the input terminal of the selection unit 232 to the gate drive circuit 110 through the first resistive unit R_H or the second resistive unit R_L according to the high or low level state of the second clock control signal CK_CTL', thereby adjusting the current flowing through the gate drive circuit 110 of the target clock pulse signal CKV. Specifically, when the second clock control signal CK_CTL' is a low-level signal, the input terminal of the selection unit 232 is coupled to the gate drive circuit 110 through the first resistive unit R_H, so that the target clock pulse signal CKV flows through a larger resistor, thereby limiting the current flowing through the traces of the gate drive circuit 110, thereby reducing the heat generation of the traces, preventing the liquid crystal material from undergoing a phase change due to excessive local temperature, and helping to protect the normal display function of the display panel 1000; when the second clock control signal CK_CTL' is a high-level signal, the input terminal of the selection unit 232 is coupled to the gate drive circuit 110 through the second resistive unit R_L, so that the target clock pulse signal CKV can be transmitted with a smaller resistance loss, ensuring the display quality of the panel at low / normal temperatures.

[0033] In this embodiment, the temperature of the target area of ​​the display panel 1000 is detected by the temperature detection module 210, and then the target clock pulse signal CKV is output by the level conversion module 220. The first clock control signal CK_CTL is output according to the first temperature signal Vs. The first clock control signal CK_CTL is inverted by the inverting unit 231 in the control module 230, and the second clock control signal CK_CTL' is output. This allows the selection unit 232 in the control module 230 to select the first resistive unit R_H or the second resistive unit R_L to be coupled to the gate drive circuit 110 according to the second clock control signal CK_CTL', thereby dynamically adjusting the current flowing through the gate drive circuit 110 of the target clock pulse signal CKV. Specifically, when the first temperature signal Vs indicates a high temperature, the selection unit 232 selects the first resistive unit R_H to couple with the gate drive circuit 110, so that the target clock pulse signal CKV flows through a larger resistor, thereby limiting the current flowing through the traces of the gate drive circuit 110, thereby reducing the heat generation of the traces of the gate drive circuit 110, effectively improving the temperature of the gate drive circuit 110 during operation, preventing local overheating from causing display abnormalities in the display panel 1000, and helping to protect the normal display function of the display panel 1000; when the first temperature signal Vs indicates a low temperature, the selection unit 232 selects the second resistive unit R_L to couple with the gate drive circuit 110, so that the target clock pulse signal CKV can be transmitted with less resistance loss, ensuring the display quality of the display panel 1000 at low / normal temperatures.

[0034] See Figure 2 The temperature detection module 210 includes a data acquisition unit 211 and an output unit 212. The input terminal of the data acquisition unit 211 is coupled to the power input terminal VCC and is configured to acquire the temperature of a target area in the display panel 1000, and generate an initial temperature signal Vt based on the temperature. The output unit 212 is coupled to the data acquisition unit 211 and the level conversion module 220, and is configured to generate a first temperature signal Vs based on the initial temperature signal Vt.

[0035] It should be noted that the acquisition unit 211 in this embodiment is used to monitor the temperature of the target area in the display panel 1000 in real time, and generate an initial temperature signal Vt based on the temperature. The target area can be, for example, a region with dense wiring, high current carrying capacity, and susceptible to heat generation from high refresh rates, such as the lower corner of the display panel 1000.

[0036] Understandably, the temperature detection module 210 includes a temperature sensing element that can detect temperature changes, such as a thin-film NTC (Negative Temperature Coefficient) thermistor R0, whose resistance decreases as the temperature increases.

[0037] Output unit 212 receives the initial temperature signal Vt from acquisition unit 211 and converts it into a logic level signal suitable for processing by level conversion module 220, namely the first temperature signal Vs. Output unit 212 can be directly connected to the input of level conversion module 220 through the output of comparator, or connected through intermediate buffer circuit.

[0038] In a specific embodiment, a temperature threshold is set to define the state of the temperature signal of the target area corresponding to the display panel 1000. When the acquisition unit 211 detects that the temperature of the target area is lower than the temperature threshold, the output unit 212 outputs a low-level first temperature signal Vs; when the temperature of the target area is detected to be higher than the temperature threshold, the output unit 212 outputs a high-level first temperature signal Vs.

[0039] This embodiment includes a temperature detection module 210 comprising a data acquisition unit 211 and an output unit 212. The data acquisition unit 211 enables the control circuit 200 to accurately acquire the real-time temperature of the target area and generate an initial temperature signal Vt, which helps to reflect the actual temperature change trend. The output unit 212 generates a first temperature signal Vs based on the initial temperature signal Vt, enabling the subsequent level conversion module 220 to receive clear and standard control signals, thus ensuring the accuracy of the first clock control signal CK_CTL output by the level conversion module 220.

[0040] In this embodiment, the first temperature signal Vs generated by the output unit 212 can accurately characterize the temperature state. This allows the subsequent control module 230 to select the second resistive unit R_L to couple with the gate drive circuit 110 when the output unit 212 outputs a low-level first temperature signal Vs. This enables the target clock pulse signal CKV to be transmitted with less resistance loss, ensuring the display quality of the display panel 1000 at low / normal temperatures. When the output unit 212 outputs a high-level first temperature signal Vs, the selection unit 232 selects the first resistive unit R_H to couple with the gate drive circuit 110. This allows the target clock pulse signal CKV to flow through a larger resistor, thereby limiting the current flowing through the traces of the gate drive circuit 110. This reduces the heat generated by the traces of the gate drive circuit 110, effectively improving the temperature of the gate drive circuit 110 during operation and preventing local overheating from causing display abnormalities in the display panel 1000. This helps protect the normal display function of the display panel 1000.

[0041] In one embodiment, the acquisition unit 211 includes a first voltage divider unit 2111 and a voltage follower unit OP1; the first end of the first voltage divider unit 2111 is connected to the power input terminal VCC, the second end of the first voltage divider unit 2111 is grounded, and the voltage divider node of the first voltage divider unit 2111 is connected to the first input terminal of the voltage follower unit OP1; the second input terminal of the voltage follower unit OP1 is connected to the output terminal of the voltage follower unit OP1, and the output terminal of the voltage follower unit OP1 is connected to the output unit 212.

[0042] In a specific embodiment, the first voltage divider unit 2111 includes a thermistor R0 and a first resistor R1. The first end of the thermistor R0 is connected to the power input terminal VCC, and the second end of the thermistor R0 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is grounded. The connection point of the thermistor R0 and the first resistor R1 is the voltage divider node of the first voltage divider unit 2111, which is connected to the non-inverting input terminal, i.e., the first input terminal, of the voltage follower unit OP1. The first voltage divider unit 2111 uses the power supply voltage as excitation and, based on the characteristic that the resistance of the thermistor R0 changes with temperature, converts the physical quantity of temperature into an analog voltage signal at the voltage divider node. Because the voltage follower has extremely high input impedance and extremely low output impedance, the inverting input terminal (i.e., the second input terminal) of the voltage follower unit OP1 is connected to the output terminal to form negative feedback. Its function is to buffer and isolate the weak voltage signal collected by the first voltage divider unit 2111, prevent the load effect of the subsequent circuit from affecting the voltage division accuracy of the first voltage divider unit 2111, and ensure that the initial temperature signal Vt transmitted to the output unit 212 is stable and undistorted.

[0043] This embodiment, by setting up a first voltage divider unit 2111 and a voltage follower unit OP1, enables the temperature acquisition process to obtain the voltage divider signal of the thermistor R0 with high impedance, avoiding signal attenuation caused by load effects, thereby improving the initial accuracy of temperature detection. The introduction of the voltage follower unit OP1 isolates the mutual influence between the voltage divider network and the subsequent circuits, which is beneficial to ensuring the stability of signal transmission.

[0044] In one embodiment, the output unit 212 includes: a second voltage divider unit 2112, a third voltage divider unit 2113, and an operational amplifier unit OP2; the first terminal of the second voltage divider unit 2112 is connected to the output terminal of the voltage follower unit OP1, the second terminal of the second voltage divider unit 2112 is connected to the output terminal of the operational amplifier unit OP2, and the voltage divider node N2 of the second voltage divider unit is connected to the first input terminal of the operational amplifier unit OP2; the first terminal of the third voltage divider unit 2113 is connected to the power input terminal VCC, the second terminal of the third voltage divider unit 2113 is grounded, and the voltage divider node N3 of the third voltage divider unit is connected to the second input terminal of the operational amplifier unit OP2; the output terminal of the operational amplifier unit OP2 is used to output a first temperature signal Vs.

[0045] In a specific embodiment, the second voltage divider unit 2112 includes a fourth resistor R4 and a fifth resistor R5. The first end of the fourth resistor R4 is connected to the output of the voltage follower unit OP1, and the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the output of the operational amplifier unit OP2. The connection point of the fourth resistor R4 and the fifth resistor R5 serves as the voltage divider node N2 of the second voltage divider unit, and is connected to the non-inverting input terminal, i.e., the first input terminal, of the operational amplifier unit OP2.

[0046] The third voltage divider unit 2113 includes a second resistor R2 and a third resistor R3. The first end of the second resistor R2 is connected to the power input terminal VCC, and the second end of the second resistor R2 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is grounded. The connection point of the second resistor R2 and the third resistor R3 serves as the voltage divider node N3 of the third voltage divider unit, and is connected to the inverting input terminal, i.e., the second input terminal, of the operational amplifier unit OP2.

[0047] In this embodiment, the operational amplifier unit OP2 is used to receive the initial temperature signal Vt output by the acquisition unit 211 and output the first temperature signal Vs.

[0048] In a specific embodiment, the initial temperature signal Vt output by the voltage follower unit OP1 is equal to the voltage division value of the thermistor R0 and the first resistor R1. The voltage follower unit OP1 can ensure that the voltage supplied to the fourth resistor R4 is stable. The voltage division of the second resistor R2 and the third resistor R3 serves as a reference voltage. Initially, the temperature is low, and the initial temperature signal Vt is divided by the fourth resistor R4 and the fifth resistor R5. The voltage at the non-inverting input (+) of the operational amplifier unit OP2 does not exceed the voltage division value of the second resistor R2 and the third resistor R3. It can be understood that the voltage division value of the second resistor R2 and the third resistor R3 is a fixed value. At this time, the voltage at the non-inverting input (+) of the operational amplifier unit OP2 is less than the voltage at the inverting input (-), and the output first temperature signal Vs is 0.

[0049] It should be noted that, see Figure 3 The operational amplifier unit OP2 and the second voltage divider unit 2112 in the output unit 212 constitute a comparator with hysteresis characteristics, which is used to shape the initial temperature signal Vt and determine the threshold, so that the first temperature signal Vs has different flip thresholds during the temperature rise and fall, thereby preventing the circuit state from switching repeatedly near the critical temperature point.

[0050] In a specific embodiment, because the output and non-inverting input of operational amplifier unit OP2 are connected to a fifth resistor R5, the positive feedback will cause the voltage at the non-inverting input of operational amplifier unit OP2 to rise higher. Therefore, the initial temperature signal Vt voltage needs to be lower so that the voltage at the non-inverting input of operational amplifier unit OP2 is lower than that at the inverting input. This achieves... Figure 3 The hysteresis effect in the process.

[0051] It should be noted that the purpose of adding hysteresis in this embodiment is to prevent the temperature of the gate drive circuit 110 from rising again after the circuit detects high temperature and switches to high resistance, and then switches back to low resistance. This avoids such repeated cycles.

[0052] Specifically, when the operational amplifier unit OP2 outputs a high level, the voltage threshold at the non-inverting input is raised through the fifth resistor R5; when the operational amplifier unit OP2 outputs a low level, the voltage threshold at the non-inverting input is lowered through the fifth resistor R5. This results in the circuit having two different switching thresholds: the upper threshold VH and the lower threshold VL.

[0053] In a specific embodiment, when the temperature rises, the resistance of the thermistor R0 decreases, and the voltage divider increases. When it exceeds the upper threshold VH, the first temperature signal Vs output by the operational amplifier unit OP2 is at a high level. When the temperature decreases, the resistance of the thermistor R0 increases, and the voltage divider decreases. Only when the voltage is lower than the lower threshold VL will the operational amplifier unit OP2 output the first temperature signal Vs at a low level.

[0054] This embodiment uses a comparator circuit with positive feedback, consisting of a second voltage divider unit 2112, a third voltage divider unit 2113, and an operational amplifier unit OP2, to ensure that the temperature signal has a clear hysteresis window when crossing the threshold. This avoids frequent switching of the first temperature signal Vs between high and low levels near the critical temperature point due to small temperature fluctuations or circuit noise.

[0055] In the embodiments of this application, the transistor includes a P-type MOS transistor and an N-type MOS transistor, wherein the conduction condition of the N-type MOS transistor is that Vgs (gate-source voltage) is greater than Vth (threshold voltage); and the conduction condition of the P-type MOS transistor is that Vgs is less than Vth.

[0056] See Figure 4In one embodiment, the inverting unit 231 includes a first transistor M1 and a second transistor M2. A first terminal of the first transistor M1 is used to receive a first voltage signal; a first terminal of the second transistor M2 is coupled to a second terminal of the first transistor M1, and the second terminal of the second transistor M2 is used to receive a second voltage signal. The voltage of the second voltage signal is less than the voltage of the first voltage signal. The coupling point between the first terminal of the second transistor M2 and the second terminal of the first transistor M1 serves as the output terminal of the inverting unit 231. The control terminals of the first transistor M1 and the second transistor M2 are coupled to a level conversion module 220 and are configured to receive a first clock control signal CK_CTL.

[0057] It should be noted that the inverting unit 231 in this embodiment is composed of a first transistor M1 and a second transistor M2 connected in series. The first transistor M1 can be a P-type MOS transistor, and the second transistor M2 can be an N-type MOS transistor. Based on this, the first transistor M1 and the second transistor M2 complement each other's threshold voltage loss.

[0058] In this embodiment, the first voltage signal is a high-level driving voltage signal VGH, and the second voltage signal is a low-level driving voltage VGL, with VGL voltage being lower than VGH.

[0059] In a specific embodiment, the control terminals of the first transistor M1 and the second transistor M2 are both coupled to the first clock control signal CK_CTL output by the level conversion module 220. When the first clock control signal CK_CTL is high, the first transistor M1 is off, the second transistor M2 is on, and the output of the inverting unit 231 is pulled low to the second voltage signal level. When the first clock control signal CK_CTL is low, the first transistor M1 is on, the second transistor M2 is off, and the output of the inverting unit 231 is pulled high to the first voltage signal level, thereby realizing the signal inversion function and outputting the second clock control signal CK_CTL'. The main purpose of the inverting unit 231 is to generate complementary control logic levels.

[0060] In a specific embodiment, when the first clock control signal CK_CTL is high, the inverting unit 231 outputs a low level, causing the transistors corresponding to the low-resistance path (i.e., the fifth transistor M5 and the sixth transistor M6) in the selection unit 232 to turn on, or the transistors corresponding to the high-resistance path (i.e., the third transistor M3 and the fourth transistor M4) to turn off, thereby ensuring fast transmission and low loss of the target clock pulse signal CKV under normal temperature. When the first clock control signal CK_CTL is low, the inverting unit 231 outputs a high level, causing the transistors corresponding to the high-resistance path (i.e., the third transistor M3 and the fourth transistor M4) in the selection unit 232 to turn on, or the transistors corresponding to the low-resistance path (i.e., the fifth transistor M5 and the sixth transistor M6) to turn off, thereby limiting current in high-temperature environments.

[0061] In this embodiment, an inverting unit 231 composed of a first transistor M1 and a second transistor M2 connected in series is set up, and the control terminal of the inverting unit 231 is coupled to the level conversion module 220. The first clock control signal CK_CTL, which has been boosted by the level conversion module 220, is received, inverted, and the second clock control signal CK_CTL' is output. This allows precise control of the input terminal of the selection unit 232, which is coupled to the gate drive circuit 110 through the first resistive unit R_H or the second resistive unit R_L, thereby adjusting the current flowing through the gate drive circuit 110 of the target clock pulse signal CKV.

[0062] In one embodiment, the selection unit 232 includes: a first selection subunit 2321 and a second selection subunit 2322; the input terminal of the first selection subunit 2321 is coupled to a level conversion module 220 and configured to receive a target clock pulse signal CKV; the first control terminal of the first selection subunit 2321 is coupled to the level conversion module 220 and configured to receive a first clock control signal CK_CTL; the second control terminal of the first selection subunit 2321 is coupled to the output terminal of the inverting unit 231 and configured to receive a second clock control signal CK_CTL'; the first selection subunit 2321... The output terminal of 21 is coupled to one end of the first resistive unit R_H; the input terminal of the second selection subunit 2322 is coupled to the level conversion module 220 and is configured to receive the target clock pulse signal CKV; the first control terminal of the second selection subunit 2322 is coupled to the level conversion module 220 and is configured to receive the first clock control signal CK_CTL; the second control terminal of the second selection subunit 2322 is coupled to the output terminal of the inverting unit 231 and is configured to receive the second clock control signal CK_CTL'; and the output terminal of the second selection subunit 2322 is coupled to one end of the second resistive unit R_L.

[0063] It should be noted that the selection unit 232 in this embodiment is used to select whether the input terminal of the selection unit 232 is coupled to the gate drive circuit 110 through the first resistive unit R_H or the second resistive unit R_L, so as to adjust the current of the target clock pulse signal CKV flowing through the gate drive circuit 110.

[0064] In one embodiment, when it is necessary to select a high-resistance resistor, i.e., the first resistive unit R_H, the first selection subunit 2321 is turned on and the second selection subunit 2322 is turned off; when it is necessary to select a low-resistance resistor, i.e., the second resistive unit R_L, the second selection subunit 2322 is turned on and the first selection subunit 2321 is turned off.

[0065] In order to ensure that the high and low levels of the target clock pulse signal CKV can be transmitted normally, in this embodiment, the first selection subunit 2321 and the second selection subunit 2322 need to be configured with an N-type MOS transistor and a P-type MOS transistor connected in parallel. The N-type MOS transistor and the P-type MOS transistor can complement each other's threshold voltage loss.

[0066] In one embodiment, the first selection subunit 2321 includes a third transistor M3 and a fourth transistor M4.

[0067] The control terminal of the third transistor M3 is coupled to the first control terminal of the first selection subunit 2321 and connected to the level conversion module 220, and is configured to receive the first clock control signal CK_CTL.

[0068] The control terminal of the fourth transistor M4 is the second control terminal of the first selection subunit 2321, coupled to the output terminal of the inverting unit 231, and is configured to receive the second clock control signal CK_CTL'; the first terminal of the third transistor M3 is coupled to the first terminal of the fourth transistor M4, and serves as the input terminal of the first selection subunit 2321, coupled to the level conversion module 220, and is configured to receive the target clock pulse signal CKV.

[0069] The second terminal of the third transistor M3 is coupled to the second terminal of the fourth transistor M4, and serves as the output terminal of the first selection subunit 2321, which is coupled to one end of the first resistive unit R_H.

[0070] The third transistor M3 turns on in response to the first clock control signal CK_CTL being high, and the fourth transistor M4 turns on in response to the second clock control signal CK_CTL' being low.

[0071] In a specific embodiment, the third transistor M3 can be an N-type MOS transistor, which conducts when the gate-source voltage is greater than the threshold voltage, that is, when the first clock control signal CK_CTL is high, the third transistor M3 conducts; the fourth transistor M4 can be a P-type MOS transistor, which conducts when the gate-source voltage is less than the threshold voltage, that is, when the first clock control signal CK_CTL is high, it is turned on by the low-level second clock control signal CK_CTL' output by the inverting unit 231.

[0072] Based on this, when the first clock control signal CK_CTL is high, the third transistor M3 is turned on, and in conjunction with the second clock control signal CK_CTL' output by the inverting unit 231, the fourth transistor M4 is turned on, thereby selecting the first resistive unit R_H, so that the target clock pulse signal CKV flows through a larger resistor, thereby limiting the current flowing through the gate drive circuit 110 trace, thereby reducing the heat generation of the trace, preventing the liquid crystal material from undergoing a phase change due to excessive local temperature, and helping to protect the normal display function of the display panel 1000.

[0073] In one embodiment, the second selection subunit 2322 includes a fifth transistor M5 and a sixth transistor M6. The control terminal of the sixth transistor M6 is the first control terminal of the second selection subunit 2322, coupled to the level conversion module 220, and is configured to receive a first clock control signal CK_CTL. The control terminal of the fifth transistor M5 is the second control terminal of the second selection subunit 2322, coupled to the output terminal of the inverting unit 231, and is configured to receive a second clock control signal CK_CTL'; the first terminal of the fifth transistor M5 is coupled to the first terminal of the sixth transistor M6, serving as the input terminal of the second selection subunit 2322, coupled to the level conversion module 220, and is configured to receive a target clock pulse signal CKV; the second terminal of the fifth transistor M5 is coupled to the second terminal of the sixth transistor M6, serving as the output terminal of the second selection subunit 2322, coupled to one end of the second resistive unit R_L.

[0074] The fifth transistor M5 is turned on in response to the second clock control signal CK_CTL' being high, and the sixth transistor M6 is turned on in response to the first clock control signal CK_CTL being low.

[0075] In a specific embodiment, the fifth transistor M5 can be an N-type MOS transistor, which conducts when the gate-source voltage is greater than the threshold voltage. That is, when the first clock control signal CK_CTL is low, the second clock control signal CK_CTL', which is high-level, is turned on by the output of the inverting unit 231. The sixth transistor M6 can be a P-type MOS transistor, which conducts when the gate-source voltage is less than the threshold voltage. That is, when the first clock control signal CK_CTL is low, the sixth transistor M6 is turned on.

[0076] Specifically, when the first clock control signal CK_CTL is low and the second clock control signal CK_CTL' is high, the sixth transistor M6 and the fifth transistor M5 are turned on. At this time, the second selection sub-unit 2322 is in the on state, connecting the second resistive unit R_L to the circuit. Conversely, when the first clock control signal CK_CTL is high and the second clock control signal CK_CTL' is low, the sixth transistor M6 and the fifth transistor M5 are turned off, and the second selection sub-unit 2322 is in the off state. When the second selection sub-unit 2322 is in the on state, the target clock pulse signal CKV can be transmitted with less resistive loss, ensuring the display quality of the panel at low / normal temperatures.

[0077] This embodiment avoids threshold voltage loss when switching a single transistor by using complementary control logic and structure of the first selection subunit 2321 and the second selection subunit 2322. This minimizes the amplitude loss of the target clock pulse signal CKV when it passes through the selection unit 232, which is beneficial to improving signal integrity. At the same time, it achieves a balance between the trace temperature of the gate drive circuit 110 and the display performance at high and low / normal temperatures.

[0078] See Figure 5 , Figure 6 , Figure 8 and Figure 9 In one embodiment, the level conversion module 220 includes a timing control unit 221 and a level conversion unit 222; the timing control unit 221 is coupled to the temperature detection module 210 and is configured to receive a first temperature signal Vs, output a primary clock pulse signal CPV, and output an initial clock control signal CK_CTL_OUT based on the first temperature signal Vs and the primary clock pulse signal CPV; the level conversion unit 222 is coupled to the timing control unit 221 and is configured to convert the primary clock pulse signal CPV into a target clock pulse signal CKV and convert the initial clock control signal CK_CTL_OUT into a first clock control signal CK_CTL.

[0079] In this embodiment, since the initial clock control signal CK_CTL_OUT output by the timing control unit 221 is not suitable for directly driving the high-voltage panel circuit, a level conversion unit 222 is required for conversion. The level conversion unit 222 is coupled to the timing control unit 221, and its function is to convert the low-voltage primary clock pulse signal CPV into a high-voltage target clock pulse signal CKV suitable for panel operation, and simultaneously convert the low-voltage initial clock control signal CK_CTL_OUT into a high-voltage first clock control signal CK_CTL. For example, it can convert 3.3V or 1.8V logic levels into panel driving voltages such as VGH (approximately 30V) and VGL (approximately -10V).

[0080] It should be noted that the timing control unit 221 in this embodiment can be, for example, a timing controller, and this embodiment does not limit the number of level conversion units 222.

[0081] See Figure 5 and Figure 6The level conversion module 220 includes a timing control unit 221 and a level conversion unit 222. Specifically, the timing control unit 221 outputs a primary clock pulse signal CPV to the level conversion unit 222, and the level conversion unit 222 converts the primary clock pulse signal CPV into a target clock pulse signal CKV. The level conversion unit 222 is also used to receive a first temperature signal Vs and output a first clock control signal CK_CTL to the control module 230 based on the first temperature signal Vs.

[0082] See Figure 8 and Figure 9 The level conversion module 220 includes a timing control unit 221 and two level conversion units 222. Specifically, the timing control unit 221 receives a first temperature signal Vs, outputs a primary clock pulse signal CPV to one of the level conversion units 222, and outputs an initial clock control signal CK_CTL_OUT to the other level conversion unit 222 based on the first temperature signal Vs and the primary clock pulse signal CPV. Based on this, one level conversion unit 222 converts the primary clock pulse signal CPV into a target clock pulse signal CKV and transmits it to the control module 230, while the other level conversion unit 222 converts the initial clock control signal CK_CTL_OUT into a first clock control signal CK_CTL and transmits it to the control module 230.

[0083] See Figure 7 and Figure 10 Because in this embodiment Figure 5 and Figure 6 The timing control unit 221 is only used to output primary clock pulse signals: CPV1, CPV2, ..., CPVn, which are then output as target clock pulse signals: CKV1, CKV2, ..., CKVn via the level conversion unit 222. Additionally, the level conversion unit 222 also outputs a first clock control signal CK_CTL based on the received first temperature signal Vs. Therefore, corresponding to... Figure 7 It includes multiple control modules 230, each used to receive the target clock pulse signal CKV output by the level conversion unit 222, including CKV1, CKV2, ..., CKVn, and the multiple control modules 230 receive the same first clock control signal CK_CTL. Further, the multiple control modules 230 output gate drive signals: GOA_CKV1, GOA_CKV2, ..., GOA_CKVn.

[0084] Due to this embodiment Figure 9The timing control unit 221 receives a first temperature signal Vs and outputs primary clock pulse signals: CPV1, CPV2, ..., CPVn. Based on the first temperature signal Vs and the primary clock pulse signals, it outputs primary clock control signals: CK_CTL1_OUT, CK_CTL2_OUT, ..., CK_CTLn_OUT. Then, one level conversion unit 222 converts the multiple primary clock pulse signals CKV into target clock pulse signals: CKV1, CKV2, ..., CKVn. Another level conversion unit 222 converts the multiple primary clock control signals CK_CTL_OUT into multiple first clock control signals CK_CTL1, CK_CTL2, ..., CK_CTLn. Based on this... Figure 10 The system includes multiple control modules 230, each receiving a target clock pulse signal CKV and a first clock control signal CK_CTL. Furthermore, each control module 230 outputs a gate drive signal: GOA_CKV1, GOA_CKV2, ..., GOA_CKVn.

[0085] In this embodiment, the timing control unit 221 and the level conversion unit 222 work together to enable the circuit to dynamically adjust the transmission characteristics of the clock signal according to the temperature state, which is beneficial to improving the adaptability and display performance of the display panel 1000 in different temperature environments.

[0086] In one embodiment, the timing control unit 221 responds to the first temperature signal Vs being a low-level signal by outputting an initial clock control signal CK_CTL_OUT being a low-level signal and outputting a first clock control signal CK_CTL being a low-level signal, thereby obtaining a high-level second clock control signal CK_CTL'. The selection unit 232 is configured to select, based on the high-level second clock control signal CK_CTL', to couple the input terminal of the selection unit 232 to the gate drive circuit 110 through the second resistive unit R_L.

[0087] Specifically, when the temperature of the target area is low, the first temperature signal Vs generated by the temperature detection module 210 is a low-level signal. Then, the initial clock control signal CK_CTL_OUT output by the timing control unit 221 is a low-level signal. After being converted by the level conversion unit 222, it is converted into a first control signal that is also low-level. For the control unit, the received first clock control signal CK_CTL is a low-level signal, so the sixth transistor M6 is turned on. The high-level second clock control signal CK_CTL' output by the inverting unit 231 further controls the fifth transistor M5 to turn on, thereby turning on the second selection sub-unit 2322. That is, the selection unit 232 is configured to select the input terminal of the selection unit 232 to be coupled to the gate drive circuit 110 through the second resistive unit R_L according to the high-level second clock control signal CK_CTL', so that the target clock pulse signal CKV can be transmitted with a small resistance loss, ensuring the display quality of the panel at low / normal temperatures.

[0088] In this embodiment, the timing control unit 221 outputs a low-level control signal in a low-temperature state and, together with the selection unit 232, turns on the second resistive unit R_L, so that the clock signal is transmitted through a low-resistance path in a low-temperature environment, which is beneficial to increase the driving current and ensure the charging efficiency and display quality of the panel.

[0089] See Figure 11 Taking the gate drive circuit of 8CK as an example, in response to the first temperature signal Vs being a high-level signal, the timing waveforms of the target clock pulse signal CKV, the first clock control signal CK_CTL, and the gate drive signal GOA_CKV output by the control module 230 through connecting different resistive units are detected.

[0090] In one embodiment, the timing control unit 221, in response to the first temperature signal Vs being a high-level signal, controls the initial clock control signal CK_CTL_OUT, thereby changing the first clock control signal CK_CTL so that the high level of the first clock control signal CK_CTL appears earlier than the high level of the target clock pulse signal CKV. The selection unit 232 is configured to, when the second clock control signal CK_CTL' is a low-level signal, select to couple the input terminal of the selection unit 232 to the gate drive circuit 110 through the first resistive unit R_H; and when the target clock pulse signal CKV is a low-level signal and the second clock control signal CK_CTL' is a high-level signal, select to couple the input terminal of the selection unit 232 to the gate drive circuit 110 through the second resistive unit R_L.

[0091] It should be noted that, since the target clock pulse signal CKV output by the timing control unit 221 precharges the high-level signal in advance, the impact on the display quality of the display panel 1000 is relatively small when the target clock pulse signal CKV is high, and relatively large when the target clock pulse signal CKV is low. Based on this, this embodiment controls the initial clock control signal CK_CTL_OUT through the timing control unit 221, thereby changing the first clock control signal CK_CTL so that the high level of the first clock control signal CK_CTL appears earlier than the high level of the target clock pulse signal CKV.

[0092] In a specific embodiment, when the temperature of the target area is high, the first temperature signal Vs received by the timing control unit 221 is at a high level. Therefore, the initial clock control signal CK_CTL_OUT and the primary clock pulse signal CPV output by the timing control unit 221 are both at a high level. The target clock pulse signal CKV and the first clock control signal CK_CTL obtained after conversion by the level conversion unit 222 are also at a high level. The high-level first clock control signal CK_CTL controls the third transistor M3 to turn on. Since the high level of the first clock control signal CK_CTL occurs earlier than the high level of the target clock pulse signal CKV, it can be understood that the second clock control signal CK_CTL output by the inverting unit 231 will also be at a high level. The low-level signal of CTL' also appears earlier than the low-level signal of the target clock pulse signal CKV. That is, for the selection unit 232, when the second clock control signal CK_CTL' becomes low, the target clock pulse signal CKV is still high. Based on this, the fourth transistor M4 is turned on, thereby turning on the first selection sub-unit 2321. That is, the input terminal of the selection unit 232 is coupled to the gate drive circuit 110 through the first resistive unit R_H, so that the target clock pulse signal CKV flows through a larger resistor, thereby limiting the current flowing through the traces of the gate drive circuit 110, thereby reducing the heat generation of the traces, preventing the liquid crystal material from undergoing a phase change due to excessive local temperature, and helping to protect the normal display function of the display panel 1000.

[0093] Furthermore, when the target clock pulse signal CKV goes low, the corresponding first clock control signal CK_CTL also goes low, which controls the sixth transistor M6 to turn on. The high-level second clock control signal CK_CTL' output by the inverting unit 231 controls the fifth transistor M5 to turn on, thereby turning on the second selection sub-unit 2322. That is, the selection unit 232 is configured to select the input terminal of the selection unit 232 to be coupled to the gate drive circuit 110 through the second resistive unit R_L according to the high-level second clock control signal CK_CTL', so that the target clock pulse signal CKV can be transmitted with less resistance loss, ensuring the display quality of the panel at low / normal temperatures.

[0094] In this embodiment, the timing control unit 221 controls the high level of the first clock control signal CK_CTL to appear earlier than the high level of the target clock pulse signal CKV under high temperature conditions. This allows the selection unit 232 to switch to the first resistive unit R_H in advance, so that the target clock pulse signal CKV flows through a larger resistor, thereby limiting the current flowing through the gate drive circuit 110 traces, reducing the heat generation of the traces, preventing the liquid crystal material from undergoing a phase change due to excessively high local temperatures, and protecting the normal display function of the display panel 1000. By switching the selection unit 232 to the second resistive unit R_L when the target clock pulse signal CKV is low and the second clock control signal CK_CTL' is low, the target clock pulse signal CKV can be transmitted with less resistance loss, ensuring the display quality of the panel at low / normal temperatures.

[0095] In a specific embodiment, the timing control unit 221 and the selection unit 232 work together to enable the circuit to dynamically adjust the different resistance values ​​of the resistive unit coupled to the gate drive circuit 110 according to the temperature. This helps to solve the problem of high-temperature trace heating while taking into account the image quality requirements of the display screen.

[0096] See Figure 12 The display panel 1000 includes a gate driving circuit 110 and a control circuit 200. The gate driving circuit 110 is disposed on the array substrate 100 of the display panel 1000. The control circuit 200 is coupled to the gate driving circuit 110 and is the control circuit 200 in any of the above embodiments.

[0097] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0098] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0099] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A control circuit for a display panel, characterized in that, include: A temperature detection module is configured to detect the temperature of a target area in the display panel and generate a first temperature signal based on the temperature; wherein the target area is provided with a gate driving circuit. A level conversion module, coupled to the temperature detection module, is configured to output a target clock pulse signal and output a first clock control signal according to the first temperature signal; The control module includes an inverting unit, a selection unit, a first resistive unit, and a second resistive unit; the resistance value of the first resistive unit is greater than that of the second resistive unit. The input terminal of the inverting unit is coupled to the level conversion module and is configured to receive the first clock control signal, invert the first clock control signal, and output the second clock control signal. The input terminal of the selection unit is coupled to the level conversion module and configured to receive the target clock pulse signal. The control terminal of the selection unit is coupled to the output terminal of the inverting unit and configured to receive the second clock control signal. The first output terminal of the selection unit is coupled to one end of the first resistive unit, and the second output terminal of the selection unit is coupled to one end of the second resistive unit. The other ends of the first resistive unit and the other ends of the second resistive unit are used to couple to the gate driving circuit. The selection unit is configured to select, according to the second clock control signal, to couple the input terminal of the selection unit to the gate drive circuit through the first resistive unit or the second resistive unit, and adjust the current flowing through the gate drive circuit of the target clock pulse signal.

2. The control circuit according to claim 1, characterized in that, The inverting unit includes: A first transistor, wherein a first terminal of the first transistor is used to receive a first voltage signal; A second transistor has a first terminal coupled to a second terminal of the first transistor, and the second terminal of the second transistor is used to receive a second voltage signal; the voltage of the second voltage signal is less than the voltage of the first voltage signal; the coupling point between the first terminal of the second transistor and the second terminal of the first transistor serves as the output terminal of the inverting unit. The control terminals of the first transistor and the second transistor are coupled to the level conversion module and are configured to receive the first clock control signal.

3. The control circuit according to claim 2, characterized in that, The selection unit includes: The first selection subunit has an input terminal coupled to the level conversion module and is configured to receive the target clock pulse signal. The first control terminal of the first selection subunit is coupled to the level conversion module and is configured to receive the first clock control signal. The second control terminal of the first selection subunit is coupled to the output terminal of the inverting unit and is configured to receive the second clock control signal. The output terminal of the first selection subunit is coupled to one end of the first resistive unit. The second selection subunit has its input terminal coupled to the level conversion module and configured to receive the target clock pulse signal. The first control terminal of the second selection subunit is coupled to the level conversion module and configured to receive the first clock control signal. The second control terminal of the second selection subunit is coupled to the output terminal of the inverting unit and configured to receive the second clock control signal. The output terminal of the second selection subunit is coupled to one end of the second resistive unit.

4. The control circuit according to claim 3, characterized in that, The first selection subunit includes a third transistor and a fourth transistor; The control terminal of the third transistor is the first control terminal of the first selection subunit coupled to the level conversion module and is configured to receive the first clock control signal. The control terminal of the fourth transistor is the second control terminal of the first selection subunit coupled to the output terminal of the inverting unit, and is configured to receive the second clock control signal. The first terminal of the third transistor is coupled to the first terminal of the fourth transistor, and is coupled to the level conversion module as the input terminal of the first selection sub-unit, and is configured to receive the target clock pulse signal; The second terminal of the third transistor is coupled to the second terminal of the fourth transistor, and serves as the output terminal of the first selection sub-unit coupled to one end of the first resistive unit. The third transistor turns on in response to the first clock control signal being a high-level signal, and the fourth transistor turns on in response to the second clock control signal being a low-level signal.

5. The control circuit according to claim 3, characterized in that, The second selection subunit includes a fifth transistor and a sixth transistor; The control terminal of the sixth transistor is the first control terminal of the second selection subunit coupled to the level conversion module and is configured to receive the first clock control signal. The control terminal of the fifth transistor is the second control terminal of the second selection subunit coupled to the output terminal of the inverting unit, and is configured to receive the second clock control signal; The first terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, and is coupled to the level conversion module as the input terminal of the second selection sub-unit, and is configured to receive the target clock pulse signal; The second terminal of the fifth transistor is coupled to the second terminal of the sixth transistor, and serves as the output terminal of the second selection sub-unit coupled to one end of the second resistive unit; The fifth transistor turns on in response to the second clock control signal being a high-level signal, and the sixth transistor turns on in response to the first clock control signal being a low-level signal.

6. The control circuit according to claim 1, characterized in that, The level conversion module includes a timing control unit and a level conversion unit; The timing control unit is coupled to the temperature detection module and is configured to receive the first temperature signal, output a primary clock pulse signal, and output a primary clock control signal based on the first temperature signal and the primary clock pulse signal. The level conversion unit is coupled to the timing control unit and is configured to convert the primary clock pulse signal into the target clock pulse signal and the primary clock control signal into the first clock control signal.

7. The control circuit according to claim 6, characterized in that, The timing control unit responds to the first temperature signal being a low-level signal by outputting the primary clock control signal as a low-level signal, and the output of the first clock control signal being a low-level signal to obtain a high-level second clock control signal. The selection unit is configured to select, according to the high-level second clock control signal, to couple the input terminal of the selection unit to the gate drive circuit through the second resistive unit. The timing control unit responds to the first temperature signal being a high-level signal by controlling the primary clock control signal to change the first clock control signal, so that the high level of the first clock control signal appears earlier than the high level of the target clock pulse signal. The selection unit is configured to, when the second clock control signal is a low-level signal, select to couple the input terminal of the selection unit to the gate drive circuit through the first resistive unit, and when the target clock pulse signal is a low-level signal and the second clock control signal is a high-level signal, select to couple the input terminal of the selection unit to the gate drive circuit through the second resistive unit.

8. The control circuit according to claim 1, characterized in that, The temperature detection module includes: a data acquisition unit and an output unit; The input terminal of the acquisition unit is coupled to the power input terminal and is configured to acquire the temperature of the target area in the display panel and generate an initial temperature signal based on the temperature. The output unit is coupled to the acquisition unit and the level conversion module, and is configured to generate the first temperature signal based on the initial temperature signal.

9. The control circuit according to claim 8, characterized in that, The acquisition unit includes a first voltage divider unit and a voltage follower unit; The first terminal of the first voltage divider unit is connected to the power input terminal, the second terminal of the first voltage divider unit is grounded, and the voltage divider node of the first voltage divider unit is connected to the first input terminal of the voltage follower unit; the second input terminal of the voltage follower unit is connected to the output terminal of the voltage follower unit, and the output terminal of the voltage follower unit is connected to the output unit; The output unit includes: a second voltage divider unit, a third voltage divider unit, and an operational amplifier unit; The first end of the second voltage divider unit is connected to the output end of the voltage follower unit, the second end of the second voltage divider unit is connected to the output end of the operational amplifier unit, and the voltage dividing node of the second voltage divider unit is connected to the first input end of the operational amplifier unit; the first end of the third voltage divider unit is connected to the power input end, the second end of the third voltage divider unit is grounded, and the voltage dividing node of the third voltage divider unit is connected to the second input end of the operational amplifier unit; the output end of the operational amplifier unit is used to output the first temperature signal.

10. A display panel, characterized in that, The display panel includes: A gate driving circuit is disposed on the array substrate of the display panel; A control circuit, which is coupled to the gate drive circuit, wherein the control circuit is the control circuit described in any one of claims 1 to 9.

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