Image correction method and system for special-shaped LED display screen

Abstract

A method and system for image correction of irregularly shaped LED displays, relating to the field of image display. In this method, each physical pixel of the irregularly shaped LED display is acquired, and correction mapping parameters are generated. Using the correction mapping parameters, interpolation calculations are performed on the video pixel stream to generate geometrically corrected target pixels. Based on the physical scanning order of the target pixels on the LED modules of the irregularly shaped LED display, the target storage address of the target pixels in memory is calculated, and multiple target pixels are aggregated in a cache to obtain aggregated pixels. When the aggregated data volume of the aggregated pixels reaches a preset burst transmission length, the aggregated pixels are written to the target storage address in memory using a burst write method. The aggregated pixels are linearly read from memory, and end-map correction is performed on the aggregated pixels to obtain output data. Based on the output data, the irregularly shaped LED display is driven to display the corrected image. Implementing the technical solution provided in this application improves the image display quality.

Description

Technical Field

[0001] This application relates to the field of image display, specifically to an image correction method and system for irregularly shaped LED displays. Background Technology

[0002] With the rapid development of LED display technology and the continuous expansion of application scenarios, three-dimensional irregularly shaped LED displays (such as spherical screens, cylindrical screens, and circular screens) have been widely used in sports stadiums, exhibitions, stage performances, theme parks, and other fields. These irregularly shaped displays break through the limitations of traditional flat-panel displays, providing more stunning visual effects and immersive viewing experiences. However, when a two-dimensional video source designed for a standard flat-panel display is directly projected onto these three-dimensional irregularly shaped display surfaces, significant visual distortion occurs due to changes in projection geometry. For example, a horizontal straight line in a flat image will appear as an upward-convex arc when mapped onto the upper half of a spherical screen, compromising the visual fidelity of the original image.

[0003] Currently, the industry generally adopts a technical solution based on pre-calculated mapping relationships to solve the geometric distortion problem of irregularly shaped displays. This type of solution typically generates the correct pixel data for each physical pixel through real-time interpolation during video playback. While this method effectively achieves geometric correction, it introduces a new problem in practical applications. Specifically, at the receiver card, although the data stream is received sequentially, the physical positions of these pixels on the display module and the scanning driving order are often non-linear and discontinuous. To write this pixel data into the onboard memory for subsequent display, the receiver card has to perform frequent, small-volume random write operations based on their discrete physical addresses. This large number of discrete writes degrades the data writing efficiency of the memory, resulting in low memory bandwidth utilization and easily causing problems such as screen tearing or stuttering, leading to poor image quality. Summary of the Invention

[0004] This application provides an image correction method and system for irregularly shaped LED displays, which improves the image display quality.

[0005] A first aspect of this application provides an image correction method for an irregularly shaped LED display screen. The method includes: acquiring each physical pixel of the irregularly shaped LED display screen and calculating the mapping relationship between each physical pixel and the global display canvas of the irregularly shaped LED display screen to the original video canvas, generating correction mapping parameters; sending and storing the correction mapping parameters to a receiving card corresponding to the physical pixel; receiving a video pixel stream by the receiving card and using the correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels; calculating the target storage address of the target pixels in a memory according to the physical scanning order of the target pixels on the LED module of the irregularly shaped LED display screen, and aggregating multiple target pixels in a cache to obtain aggregated pixels; when the aggregated data volume of the aggregated pixels reaches a preset burst transmission length, writing the aggregated pixels to the target storage address of the memory in a burst write manner; linearly reading the aggregated pixels from the memory and performing end-map correction on the aggregated pixels to obtain output data; and driving the irregularly shaped LED display screen to display the corrected image based on the output data.

[0006] By adopting the above technical solution, and through pre-calculating and storing correction mapping parameters, the receiving card can perform geometric correction interpolation calculations in real time when receiving video pixel streams, generating corrected target pixels and achieving precise geometric correction of irregularly shaped LED displays. The target storage address is calculated based on the physical scanning order of the target pixels on the LED module, and multiple target pixels are aggregated into aggregate pixels, allowing the originally scattered pixel data to be reorganized according to the actual driving order. When the aggregated data volume reaches the preset burst transmission length, a burst write operation is triggered, efficiently writing the aggregated pixels into memory and significantly improving memory bandwidth utilization. By linearly reading out the aggregated pixels and performing end-map correction, it is ensured that the output data fully meets the timing requirements of the LED driver chip, ultimately driving the irregularly shaped LED display to show a geometrically correct and distortion-free corrected image. The entire processing flow achieves end-to-end optimization from video input to display output, solving the image distortion problem caused by irregular arrangement of irregularly shaped LED displays. This application achieves precise geometric correction by pre-calculating correction mapping parameters and sending them to the receiving card, combined with real-time interpolation calculations. It innovatively designs a target pixel storage address calculation and data aggregation mechanism, improving storage and transmission efficiency through pixel aggregation and burst writing and linear reading. End-point mapping correction ensures the stability and continuity of the image output. This solution effectively solves the problems of geometric distortion, low storage efficiency, and poor image quality in irregularly shaped LED displays, significantly improving the system's real-time performance, display smoothness, and stability, and has broad application value in complex dynamic scenarios.

[0007] Optionally, the step of calculating the mapping relationship of each physical pixel from the global display canvas of the irregularly shaped LED display to the original video canvas and generating correction mapping parameters specifically includes: dividing the global display canvas of the irregularly shaped LED display into a preset number of sub-regions according to the topology, with each sub-region corresponding to a logical address space of the receiving card; calculating the floating-point mapping coordinates of the physical coordinates of each physical pixel in each sub-region in the original video canvas according to the curved geometric characteristics of the irregularly shaped LED display; calculating the pixel index, sub-pixel offset, and interpolation weight coefficient corresponding to each physical pixel according to the floating-point mapping coordinates, and using the pixel index, sub-pixel offset, and interpolation weight coefficient as the correction mapping parameters.

[0008] By adopting the above technical solution, the global display canvas is divided into multiple sub-regions according to its topology. Each sub-region corresponds to the logical address space of a receiving card, realizing a distributed processing architecture for large-scale irregularly shaped LED displays and reducing the computational load of a single receiving card. Based on the curved geometric characteristics of the irregularly shaped LED display, the floating-point mapping coordinates of each physical pixel in each sub-region within the original video canvas are accurately calculated, ensuring the geometric accuracy of the curved display. By calculating pixel indices, sub-pixel offsets, and interpolation weight coefficients, complete correction mapping parameters are generated, providing a precise data foundation for subsequent real-time interpolation calculations. The introduction of sub-pixel offsets enables interpolation calculations to achieve sub-pixel level accuracy, effectively eliminating the jagged edges caused by pixel alignment errors. The pre-calculation of interpolation weight coefficients avoids redundant calculations during real-time processing, improving the processing efficiency of the receiving card and ensuring the real-time requirements of the video stream.

[0009] Optionally, the step of receiving the video pixel stream by the receiving card and performing interpolation calculations on the video pixel stream using the correction mapping parameters to generate a geometrically corrected target pixel specifically includes: the receiving card extracting the video pixel stream belonging to the load range of the receiving card from the high-speed video link; within the mapping engine of the receiving card, using a row buffer to temporarily store pixel data of the current processing row and adjacent rows of the current processing row to form an interpolation window; determining the target pixel index, target sub-pixel offset, and target interpolation weight coefficient corresponding to the current physical pixel based on the correction mapping parameters according to the current write counter value; locating neighboring pixels from the interpolation window according to the target pixel index, and performing a weighted summation of the neighboring pixels according to the target sub-pixel offset and the target interpolation weight coefficient to generate the target pixel.

[0010] By adopting the above technical solution, the receiving card accurately extracts the video pixel stream within its own load range from the high-speed video link, realizing parallel processing of the multi-receiving-card system and improving the overall system throughput. Using a row buffer to temporarily store pixel data of the current processing row and adjacent rows to form an interpolation window provides the necessary neighboring pixel data for multi-point interpolation calculations, ensuring the continuity of interpolation operations. Correction mapping parameters are dynamically obtained based on the write counter value, achieving precise synchronization between pixel stream processing and parameter reading, avoiding timing misalignment. Neighboring pixels are located using the target pixel index, and a weighted sum is performed based on the target sub-pixel offset and the target interpolation weight coefficient to generate target pixels with anti-aliasing characteristics, improving the display quality of irregularly shaped displays. The entire processing is completed in the mapping engine inside the receiving card, realizing hardware-level real-time interpolation calculation and meeting the performance requirements of high frame rate video display.

[0011] Optionally, the step of calculating the target storage address of the target pixel in the memory according to the physical scanning order of the target pixel on the LED module of the irregular LED display screen, and aggregating multiple target pixels in the cache to obtain aggregated pixels, specifically includes: obtaining the physical driving parameters of the LED module, and constructing a physical scanning order index table based on the physical driving parameters and the physical scanning order, wherein the physical driving parameters include the number of scan rows, the number of pixels per row, and the row scanning timing; based on the physical scanning order index table, parsing the physical driving row number and the offset position within the row to which the target pixel belongs; converting the physical driving row number and the offset position within the row into the form of a memory base address plus an offset using an address redirection algorithm, and calculating the target storage address; detecting whether the target storage addresses of multiple target pixels belong to the same physical driving row; and aggregating the target pixels belonging to the same physical driving row in the cache according to the physical scanning order to form the aggregated pixels.

[0012] By employing the above technical solutions, the physical driving parameters of the LED module are obtained and a physical scan sequence index table is constructed, establishing a precise mapping relationship between display coordinates and driving timing. This ensures that pixel data can be organized according to the actual scanning sequence of the LED driver chip. By parsing the physical driving row number and in-row offset of the target pixel, precise positioning of the pixel's physical location is achieved, providing an accurate basis for subsequent address calculation. The address redirection algorithm converts the physical driving location into a memory address, enabling pixels belonging to the same scan cycle to be mapped to contiguous storage space, thus optimizing the memory access mode. Detecting whether multiple target pixels belong to the same physical driving row and forming aggregated pixels in the cache for those meeting the criteria achieves ordered aggregation of discrete pixel data. This aggregation mechanism reorganizes the originally randomly distributed pixels into continuous data blocks suitable for burst transmission, laying the foundation for subsequent efficient memory writing.

[0013] Optionally, the step of writing the aggregated pixel to the target storage address of the memory in a burst write manner when the aggregated data volume of the aggregated pixel reaches a preset burst transmission length specifically includes: detecting whether the aggregated data volume of the aggregated pixel reaches the preset burst transmission length; generating a write trigger signal when it is determined that the aggregated data volume of the aggregated pixel reaches the preset burst transmission length; configuring the burst transmission parameters of the memory according to the write trigger signal and the target storage address, the burst transmission parameters including burst length and address increment mode; organizing the aggregated pixel into a transmission data format conforming to the memory interface specification based on the burst transmission parameters; and performing a burst write operation to the target storage address based on the transmission data format.

[0014] By employing the above technical solutions, the aggregated data volume of aggregated pixels is detected in real time, ensuring that write operations are triggered only when the preset burst transmission length is reached. This maximizes the data volume of each burst transmission and improves the utilization efficiency of the memory interface. Generating a write trigger signal and configuring the memory's burst transmission parameters, including burst length and address increment mode, ensures that burst write operations conform to the memory's timing specifications, avoiding transmission failures due to parameter errors. Organizing aggregated pixels into a transmission data format conforming to the memory interface specifications guarantees correct data transmission at the physical layer, improving system stability and reliability. Performing burst write operations to the target memory address completes the writing of multiple pixel data in a single transmission transaction, significantly reducing memory access counts and bus arbitration overhead compared to writing pixel by pixel. After the burst write is completed, the cache write pointer is updated and the cache space for written data is cleared, achieving efficient cache recycling and ensuring the system can continuously process newly arriving pixel data.

[0015] Optionally, the step of performing end-mapping correction on the aggregated pixels to obtain output data specifically includes: calculating the deviation between the order of each target pixel within the aggregated pixel and the original logical order, and generating an intra-packet reordering index based on the deviation; encapsulating the intra-packet reordering index and the aggregated pixels into a composite data block, and writing the composite data block into the target storage address of the memory; when reading the current composite data block from the memory, using the intra-packet reordering index to reconstruct subsequent composite data blocks after the current composite data block in real time, completing the end-mapping correction, and obtaining the output data.

[0016] By employing the above technical solution, the deviation between the order of each target pixel within the aggregated pixel and its original logical order is calculated, and an intra-packet reordering index is generated. This accurately records the pixel order changes caused by address redirection, providing necessary information for subsequent order recovery. Encapsulating the intra-packet reordering index and the aggregated pixel into a composite data block achieves unified storage of data and metadata, avoiding additional index storage overhead and improving storage space utilization. When reading the composite data block from memory, the intra-packet reordering index is used to reconstruct subsequent composite data blocks in real time, completing end-map correction and ensuring that the pixel order of the output data fully conforms to the scanning requirements of the LED driver chip. This delayed correction mechanism decomposes the complex address mapping problem into two stages: address redirection during writing and order reconstruction during reading, ensuring both writing efficiency and output correctness. The output data obtained through end-map correction can be directly sent to the LED driver chip without additional order adjustment, simplifying subsequent drive control logic.

[0017] Optionally, driving the irregularly shaped LED display screen to display the corrected image based on the output data specifically includes: acquiring the PCB wiring topology information of the LED module; identifying invalid data bits in the output data corresponding to unconnected physical LED beads according to the PCB wiring topology information; generating invalid data for filling based on the invalid data bits; and driving the irregularly shaped LED display screen to display the corrected image based on the output data and the invalid data.

[0018] By employing the above technical solution, the PCB wiring topology information of the LED module is obtained, providing a precise physical layer basis for data correction and ensuring the accuracy of subsequent identification and processing. Identifying invalid data bits in the output data based on the PCB wiring topology information enables precise positioning at the data stream level, directly locking down redundant data that does not correspond to any physical LED. Invalid data is generated to fill these invalid data bits, and the display screen is ultimately driven based on the output data and the invalid data. The core effect is that invalid data bits are filled in real-time in hardware at the final stage of data output to the driver chip. This solution achieves efficient, accurate, and lossless compatible driving of LED modules of any physical shape, ensuring the integrity and accuracy of the final displayed image.

[0019] Secondly, embodiments of this application provide an image correction system for irregularly shaped LED displays. This system includes a mapping calculation module, a parameter distribution module, an interpolation processing module, an address calculation module, a cache aggregation module, and an output correction module. The mapping calculation module acquires each physical pixel of the irregularly shaped LED display and calculates the mapping relationship between each physical pixel and the global display canvas of the irregularly shaped LED display to the original video canvas, generating correction mapping parameters. The parameter distribution module distributes and stores the correction mapping parameters in the receiving card corresponding to the physical pixel. The interpolation processing module receives the video pixel stream from the receiving card and uses the correction mapping parameters to perform correction on the video pixel stream. Interpolation calculations are performed to generate geometrically corrected target pixels. The address calculation module is used to calculate the target storage address of the target pixels in the memory according to the physical scanning order of the target pixels on the LED module of the irregularly shaped LED display screen, and to aggregate multiple target pixels in the cache to obtain aggregated pixels. The cache aggregation module is used to write the aggregated pixels to the target storage address of the memory in a burst write manner when the aggregated data of the aggregated pixels reaches a preset burst transmission length. The output correction module is used to linearly read the aggregated pixels from the memory and perform end mapping correction on the aggregated pixels to obtain output data. The output correction module is also used to drive the irregularly shaped LED display screen to display the corrected image based on the output data.

[0020] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. By generating and distributing correction mapping parameters, combined with real-time interpolation calculation and precise geometric correction at the receiving card, the display distortion problem caused by the special curved surface geometry of irregular LED displays is effectively solved, ensuring the visual fidelity of the image and the accuracy of the display effect, while improving the adaptability of the display in complex dynamic scenes.

[0021] 2. By establishing the target storage address based on the physical scanning order, a caching mechanism is introduced to aggregate target pixels, and a burst write method is adopted. This effectively avoids the waste of memory bandwidth caused by traditional random small batch writes, greatly improves data transmission and storage efficiency, and achieves efficient data processing and output synchronization, thereby improving the overall display performance of the system.

[0022] 3. By using end-map correction technology, combined with the intelligent skipping mechanism of packet reordering index and invalid data bits, the final output data maintains a strict logical order and spatial consistency. At the same time, the driving clock pulse has been optimized and adjusted, further improving the smoothness and stability of the image display of irregularly shaped LED displays, ensuring the image quality and the reliability of system operation. Attached Figure Description

[0023] Figure 1 This is a schematic flowchart of an image correction method for an irregularly shaped LED display screen disclosed in an embodiment of this application; Figure 2 This is another schematic flowchart of an image correction method for irregularly shaped LED displays disclosed in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an image correction system for an irregularly shaped LED display screen provided in an embodiment of this application.

[0024] Explanation of reference numerals in the attached diagram: 301, Mapping calculation module; 302, Parameter distribution module; 303, Interpolation processing module; 304, Address calculation module; 305, Cache aggregation module; 306, Output correction module; 400, Electronic device. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0026] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0027] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0028] This application provides an image correction method for irregularly shaped LED displays, referring to... Figure 1 , Figure 1 This is a flowchart illustrating an image correction method for an irregularly shaped LED display screen provided in an embodiment of this application. The method is applied to a system and includes steps S101 to S107, as follows: Step S101: Obtain each physical pixel of the irregularly shaped LED display screen, calculate the mapping relationship of each physical pixel from the global display canvas of the irregularly shaped LED display screen to the original video canvas, and generate correction mapping parameters.

[0029] In step S101, the irregular LED display screen refers to a display device with a non-planar physical form, such as a spherical screen or a cylindrical screen; physical pixel represents the independent light-emitting unit that constitutes the irregular LED display screen, i.e., LED lamp bead; global display canvas refers to the logical coordinate space after the three-dimensional physical surface of the entire irregular LED display screen is unfolded in two dimensions; original video canvas represents the coordinate space of the input standard two-dimensional planar video source; mapping relationship refers to the mathematical transformation rule that accurately associates the coordinates of any physical pixel on the global display canvas with specific floating-point coordinates on the original video canvas; correction mapping parameters refer to the specific set of values ​​calculated through the mapping relationship and used to guide subsequent correction calculations.

[0030] Specifically, the system performs offline static initialization in this step. First, the precise coordinates of each physical pixel on the irregularly shaped LED display screen in 3D space are obtained through 3D modeling software or physical measurement. Then, the system projects or unfolds the coordinates of all physical pixels to form a complete global display canvas. For each physical pixel on the global display canvas, the system calculates in reverse which position in the original video canvas the pixel should sample for correctly displaying the image content. Since the position of the physical pixel and the pixel grid of the video source are usually not perfectly aligned, the calculation result is a floating-point coordinate. The system decomposes this floating-point coordinate into a set of correction mapping parameters that can be directly used for hardware calculation. These correction mapping parameters include at least the pixel index for positioning, the floating-point offset for sub-pixel-level precise positioning, and the interpolation weight coefficients for smoothing, ultimately generating the correction mapping parameters corresponding to all physical pixels.

[0031] In one possible implementation, the mapping relationship of each physical pixel from the global display canvas of the irregularly shaped LED display to the original video canvas is calculated, and correction mapping parameters are generated. Specifically, this includes steps S1011-S1013, as follows: Step S1011: Divide the global display canvas of the irregular LED display screen into a preset number of sub-regions according to the topology, with each sub-region corresponding to the logical address space of a receiving card.

[0032] In step S1011, the topology refers to the physical connection relationship and data link structure between all receiving cards in the irregularly shaped LED display screen. A sub-region refers to a local canvas area obtained after the global display canvas is logically divided, matching the processing capability of a single receiving card. The logical address space refers to the virtual address range allocated to a single receiving card for identifying and managing the set of physical pixels it is responsible for.

[0033] Specifically, the system first analyzes the system wiring diagram and configuration information of the entire irregularly shaped LED display screen to determine the location of each receiving card and the range of the LED modules it drives, thus forming the topology of the display screen. Based on this topology, the system logically divides the global display canvas, representing all pixels of the entire display screen, into multiple non-overlapping sub-regions. The range and size of each sub-region correspond to the actual load capacity and physical jurisdiction of a receiving card. The system assigns a unique identifier to each sub-region and binds it to the network address or ID of the corresponding receiving card, thereby establishing a dedicated logical address space for each receiving card.

[0034] Step S1012: Based on the curved geometric characteristics of the irregular LED display screen, calculate the floating-point mapping coordinates of the physical coordinates of each physical pixel in each sub-region in the original video canvas.

[0035] In step S1012, the surface geometric characteristics refer to the precise geometric information of the irregularly shaped LED display screen in three-dimensional space, such as its shape, curvature, and size. Physical coordinates refer to the precise position coordinates of each physical pixel in the established global display canvas coordinate system. Floating-point mapped coordinates refer to the non-integer coordinate values ​​with decimal parts obtained when the physical coordinates are projected onto the original video canvas through an inverse geometric transformation.

[0036] Specifically, the system retrieves precise surface geometry data of the irregularly shaped LED display screen, obtained beforehand through 3D scanning or modeling. For each physical pixel assigned to a sub-region, the system first obtains the physical coordinates of that pixel on the global display canvas. Then, the system applies a reverse projection transformation algorithm, which simulates the process of projecting light rays backward from the physical pixel location onto the planar original video canvas. Because the physical surface of the irregularly shaped LED display screen is irregular, it is almost impossible for the landing point of this reverse projection to be precisely aligned with the integer pixel grid of the original video canvas; therefore, the calculation result is a floating-point mapped coordinate containing a decimal part.

[0037] Step S1013: Based on the floating-point mapping coordinates, calculate the pixel index, sub-pixel offset, and interpolation weight coefficient corresponding to each physical pixel, and use the pixel index, sub-pixel offset, and interpolation weight coefficient as correction mapping parameters.

[0038] In step S1013, the pixel index is used to locate the integer coordinates of the top-left reference pixel of the neighboring pixels required for interpolation calculation within the original video canvas. The sub-pixel offset is used to describe the precise decimal position of the floating-point mapped coordinates within the reference pixel cell determined by the pixel index. The interpolation weight coefficients are a set of values ​​pre-calculated based on the sub-pixel offset and a specific interpolation algorithm, used to assign to each neighboring pixel in the subsequent weighted summation operation.

[0039] Specifically, the system decomposes each floating-point mapping coordinate calculated in the previous step. The system extracts the integer part of the floating-point mapping coordinate and uses this integer part as a pixel index, which points to the top-left pixel of the neighborhood pixel matrix required for subsequent interpolation calculations. The system then extracts the decimal part of the floating-point mapping coordinate and uses this decimal part as a sub-pixel offset. Subsequently, according to the system-defined interpolation algorithm, such as bilinear interpolation, the system uses the sub-pixel offset to calculate the proportion of each neighboring pixel in the final color synthesis, thus obtaining a set of interpolation weight coefficients. Finally, the system packages and combines the pixel index, sub-pixel offset, and interpolation weight coefficients calculated for each physical pixel to form the final correction mapping parameters, ready for subsequent distribution to the receiving card.

[0040] Step S102: Send the correction mapping parameters and store them in the receiver card corresponding to the physical pixels.

[0041] In step S102, the receiving card refers to a distributed processing unit in the system that is responsible for receiving upstream video data and directly driving a portion of the physical pixels.

[0042] Specifically, the system sends all the calibration mapping parameters generated in step S101 to the transmitting card in the display system via the Gigabit Ethernet protocol or other data channels. Based on pre-defined global topology segmentation information, the transmitting card knows the physical pixel region driven by each receiving card. Therefore, the transmitting card distributes the complete set of calibration mapping parameters, precisely forwarding only the calibration mapping parameters corresponding to each physical pixel to the receiving card managing that physical pixel. Ultimately, each receiving card stores only the local calibration mapping parameters related to its own load area, forming a localized lookup table.

[0043] Step S103: The receiving card receives the video pixel stream and uses the correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels.

[0044] In step S103, the video pixel stream refers to the sequence of original pixel data continuously transmitted from the sending card to the receiving card via a high-speed bus such as a DP cable; interpolation calculation refers to the mathematical operation process of using the color values ​​and weight coefficients of multiple pixels around a pixel to jointly determine the final color of that pixel; the target pixel refers to the new pixel data generated after the original pixels in the video pixel stream have undergone interpolation calculation and geometric correction, and is ready to be written to the memory.

[0045] Specifically, the receiver card intercepts the video pixel stream from the high-speed bus in real time at the hardware level. For the data in the video pixel stream, the geometric correction mapping engine within the receiver card synchronously retrieves the corresponding correction mapping parameters from internal storage according to the current processing sequence. Using the pixel index and floating-point offset contained in the correction mapping parameters, the engine locates one or more original pixels in the video pixel stream and performs multi-point convolution interpolation operations on these original pixels, such as bilinear interpolation, using the interpolation weight coefficients contained in the parameters. This operation can eliminate geometric distortion and generate a smooth image with anti-aliasing effect. The final pixel color value obtained after the operation is the geometrically corrected target pixel. This process is completed in the physical path before the data is written to memory, integrated with the inherent buffer cycle of data transmission, and does not generate additional frame-level latency.

[0046] In one possible implementation, the receiving card receives the video pixel stream and uses correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels. Specifically, this includes steps S1031-S1034, as follows: Step S1031: The receiving card extracts the video pixel stream belonging to the load range of the receiving card from the high-speed video link.

[0047] In step S1031, the high-speed video link refers to the physical communication channel used for video data transmission, such as a DP, DVI, HDMI, or Ethernet interface. The load range refers to one or more specific rectangular areas from the original video canvas allocated to a single receiver card during system configuration; the receiver card only processes video data within this area.

[0048] Specifically, the receiver card continuously monitors data frames transmitted on the high-speed video link through its physical interface layer. These data frames contain not only video pixel data but also address or region identifier information, indicating which part of the original video canvas the data frame belongs to. The receiver card internally stores its own load range information. It compares the region identifier of a received data frame with its own load range. If the region identifier falls within the receiver card's load range, the receiver card captures and buffers the video pixel stream in that data frame; otherwise, if the data frame does not belong to its load range, the receiver card discards the data frame without processing it. In this way, each receiver card can accurately filter out the portion it needs to process from the entire video data deluge.

[0049] Step S1032: Inside the mapping engine of the receiving card, the pixel data of the current processing row and the adjacent rows of the current processing row are temporarily stored in the row buffer to form an interpolation window.

[0050] In step S1032, the mapping engine refers to the hardware processing unit inside the receiving card specifically designed for performing geometric correction core algorithms such as pixel coordinate transformation and interpolation calculation. The line buffer refers to a set of high-speed storage units located inside the mapping engine, used to temporarily store several lines of pixel data read from the video pixel stream. The current processing line refers to the video pixel line used as the reference during the interpolation calculation. Adjacent lines refer to the pixel data of the line immediately preceding and following the current processing line. The interpolation window is a small pixel matrix composed of a portion of the pixel data from the current processing line and adjacent lines, used for a single interpolation calculation.

[0051] Specifically, the video pixel stream extracted from the high-speed video link is sequentially fed into the mapping engine. Since subsequent bilinear or bicubic interpolation algorithms require simultaneous access to multiple raw pixels surrounding a target point, and these pixels may be distributed across different video lines, the mapping engine utilizes line buffering to address the dependency issue of line data access. For example, during bilinear interpolation, at least two lines of video data need to be buffered. The mapping engine sequentially stores the current processing line and the next line of the video pixel stream into the line buffer. This way, when the mapped coordinates of any target pixel to be calculated fall between the current processing line and the next line, all four neighboring pixels required to form the interpolation window are ready and can be read by the mapping engine at any time.

[0052] Step S1033: Based on the current write counter value, determine the target pixel index, target subpixel offset, and target interpolation weight coefficient corresponding to the current physical pixel based on the correction mapping parameters.

[0053] In step S1033, the current write counter is a counter operating inside the receiving card, and its count value corresponds one-to-one with the physical scanning order of the physical pixels on the LED module. The target pixel index, part of the correction mapping parameters, specifies the starting pixel coordinates in the original video canvas that constitute the neighboring pixels required for interpolation calculation. The target sub-pixel offset, also part of the correction mapping parameters, precisely describes the sub-pixel level position of the sampling point within the neighboring pixels determined by the target pixel index. The target interpolation weight coefficient, also part of the correction mapping parameters, is a set of multipliers pre-calculated based on the target sub-pixel offset, used for subsequent weighted summation calculations.

[0054] Specifically, the receiving card generates target pixels one by one according to the physical scanning order of the driving LED modules. The current write counter starts from zero and automatically increments by one for each target pixel generated. The mapping engine uses the current write counter value as an address or index to look up the correction mapping parameter table stored on the receiving card. This lookup operation accurately reads the unique set of correction mapping parameters corresponding to the current physical pixel. This set of parameters includes the target pixel index, the target sub-pixel offset, and the target interpolation weight coefficient. This set of read parameters is then sent to the arithmetic logic unit of the mapping engine to guide the next interpolation operation.

[0055] Step S1034: Based on the target pixel index, locate the neighboring pixels in the interpolation window, and perform a weighted summation of the neighboring pixels based on the target sub-pixel offset and the target interpolation weight coefficient to generate the target pixel.

[0056] In step S1034, the neighboring pixel refers to the multiple original video pixels located by the target pixel index and surrounding the subpixel sampling point in the interpolation window.

[0057] Specifically, the arithmetic logic unit of the mapping engine receives the target pixel index, target subpixel offset, and target interpolation weight coefficients from the previous step. First, based on the target pixel index, the arithmetic logic unit locates and reads all relevant neighboring pixels from the interpolation window formed by the line buffer, such as the color values ​​of the four pixels required for bilinear interpolation. Then, using the target interpolation weight coefficients, the arithmetic logic unit performs a weighted summation operation on each color component of these four neighboring pixels—the red, green, and blue components. For example, the red component value of the target pixel equals the red component value of the first neighboring pixel multiplied by the first weight coefficient, plus the red component value of the second neighboring pixel multiplied by the second weight coefficient, and so on. After all color components have undergone weighted summation calculations, the final geometrically corrected target pixel is generated.

[0058] Step S104: Calculate the target storage address of the target pixel in the memory according to the physical scanning order of the target pixel on the LED module of the irregular LED display, and aggregate multiple target pixels in the cache to obtain aggregated pixels.

[0059] In step S104, an LED module refers to a standardized PCB board unit that constitutes an irregularly shaped LED display screen, on which physical pixels and driving circuits are arranged; the physical scanning order refers to the fixed order in which the driving chips on the LED module light up the physical pixels; the memory refers to the high-speed dynamic random access memory on the receiving card used to cache image frame data, usually DDR; the target storage address refers to the physical address in the memory where the target pixel should be stored, calculated according to the physical scanning order; the cache refers to a small but extremely fast temporary storage space integrated inside the main control chip of the receiving card, outside of the memory; and the aggregated pixel refers to a collection of multiple target pixels that are temporarily collected and combined together in the cache.

[0060] Specifically, after generating the target pixel, the system does not write it to the memory address corresponding to the original video logical coordinates. Instead, the system calculates a completely new target memory address based on the physical scanning order of the physical pixels that the target pixel will eventually display on the LED module. This target memory address ensures that when data is linearly read from memory, its order directly corresponds to the refresh order of the driver chip. The calculated target pixel and its corresponding target memory address are sent together to a cache. The system continuously collects target pixels in the cache, combining multiple target pixels with consecutive or adjacent target memory addresses to form aggregated pixels.

[0061] In one possible implementation, the target storage address of the target pixel in the memory is calculated according to the physical scanning order of the target pixel on the LED module of the irregularly shaped LED display, and multiple target pixels are aggregated in the cache to obtain an aggregated pixel. Specifically, this includes steps S1041-S1045, as follows: Step S1041: Obtain the physical driving parameters of the LED module, and construct a physical scanning sequence index table based on the physical driving parameters and the physical scanning sequence. The physical driving parameters include the number of scan rows, the number of pixels per row, and the row scanning timing.

[0062] In step S1041, an LED module refers to the smallest physical display unit constituting an irregularly shaped LED display screen, typically containing a driving circuit and multiple LED pixels. Physical driving parameters are a set of core parameters describing the hardware scanning method of the LED module. The physical scanning order refers to the actual sequence in which all physical pixels on the LED module are illuminated. The physical scanning order index table is a pre-built data structure used to quickly map the linear indices in the physical scanning order to specific physical driving row and column positions. The number of scan rows indicates the number of rows that the LED module needs to activate sequentially in one complete refresh cycle. The number of pixels per row indicates the amount of pixel data that needs to be serially fed in when activating a single scan row. The row scan timing refers to the precise time sequence controlling operations such as scan row switching and data latching.

[0063] Specifically, the receiving card first reads the physical driving parameters of the LED module it drives from its own firmware or configuration information. These parameters define the underlying hardware operation of the LED module. Based on these physical driving parameters, especially the number of scan rows and the number of pixels per row, as well as the physical scan order determined by the hardware design, the receiving card creates a physical scan order index table in its internal memory. The index values ​​of this table start from 0 and increment in the physical scan order. Each index position stores the physical driving row number and the offset position within the row corresponding to the pixel in that order. This construction process is completed once during system initialization, providing an efficient lookup mechanism for subsequent address calculations.

[0064] Step S1042: Based on the physical scan order index table, parse the physical driving row number and in-row offset position of the target pixel.

[0065] In step S1042, the physical drive row number refers to the unique identifier of the scan row to which the target pixel belongs under the scanning drive mechanism of the LED module. The in-row offset position refers to the specific position index of the target pixel in the data chain of its respective physical drive row.

[0066] Specifically, after the receiving card generates a target pixel through interpolation, the generation order of the target pixel is consistent with the physical scanning order. The receiving card uses the sequence number of the current target pixel in the physical scanning order as an index to directly look up the physical scanning order index table constructed in the previous step. Through this table lookup operation, the receiving card can immediately obtain the precise driving coordinates of the target pixel on the LED module, that is, the physical driving row number to which the target pixel belongs and its in-row offset position in the data of that row.

[0067] Step S1043: Using an address redirection algorithm, the physical drive row number and the offset position within the row are converted into the form of memory base address plus offset, and the target memory address is calculated.

[0068] In step S1043, the address redirection algorithm refers to the calculation rules for converting two-dimensional physical drive row and column coordinates into one-dimensional linear memory addresses. The memory base address refers to the starting memory address allocated to each physical drive row in the frame buffer memory of the receiving card. The offset here is equivalent to the offset position within the row. The target memory address is the final and unique storage address of the target pixel's color data in the frame buffer memory.

[0069] Specifically, the receiver card pre-allocates a fixed memory base address for each physical drive row in the frame buffer memory. After obtaining the physical drive row number and in-row offset of the target pixel by looking up a table, the receiver card executes an address redirection algorithm. This algorithm first looks up the corresponding memory base address from an internal address mapping table based on the physical drive row number, and then performs an arithmetic addition operation between the memory base address and the in-row offset of the target pixel. The result of the operation is the absolute address of the target pixel in the frame buffer memory, i.e., the target memory address.

[0070] Step S1044: Detect whether the target storage addresses of multiple target pixels belong to the same physical drive row.

[0071] In step S1044, the cache refers to the high-speed storage area inside the receiving card used to temporarily store pixel data.

[0072] Specifically, after calculating the target memory address of the current target pixel, the receiving card does not immediately write the target pixel to the frame buffer memory. Instead, it temporarily stores the physical drive line number of the current target pixel. Then, the receiving card processes the next target pixel and similarly calculates its physical drive line number. The receiving card then compares the physical drive line numbers of these two consecutive target pixels. The purpose of this step is to identify multiple target pixels that are consecutive in the physical scan sequence and belong to the same physical drive line.

[0073] Step S1045: Aggregate target pixels belonging to the same physical drive row in the cache according to the physical scan order to form aggregated pixels.

[0074] In step S1045, cache refers to a memory area used to temporarily store and rearrange pixel data; aggregation refers to the process of collecting multiple target pixel data that are logically scattered but belong to the same row in physical drive together; aggregated pixel refers to a continuous data block formed in the cache, arranged in the physical scan order, representing all pixel data of an entire physical drive row.

[0075] Specifically, for all target pixels determined to belong to the same physical drive row in step S1044, the system writes the color data of these target pixels into a designated buffer. During the writing process, the system strictly follows the in-row offset position of each target pixel to place the pixel data into the corresponding position in the buffer. After this process is completed, an aggregated pixel data block is formed in the buffer, with a data sequence completely equivalent to the hardware physical scan order. This aggregated pixel can be directly and efficiently transmitted to the display driver hardware for row scanning and illumination.

[0076] Step S105: When the amount of aggregated data of the aggregated pixel reaches the preset burst transmission length, the aggregated pixel is written to the target storage address of the memory in a burst write mode.

[0077] In step S105, the aggregated data amount refers to the total number of data bits occupied by the aggregated pixels in the cache; the preset burst transmission length refers to the data block size preset to achieve the most efficient memory access, such as 128 bits or 256 bits; the burst write mode refers to the efficient transmission mode of writing an entire data block to a continuous address space of the memory at once.

[0078] Specifically, the system continuously monitors the amount of aggregated data in the cache. Once the amount of aggregated data of clustered pixels temporarily stored in the cache and with contiguous target storage addresses reaches the preset burst transfer length, the system triggers an atomic write operation to the memory. Through this operation, the entire clustered pixel data block is transferred from the cache to the corresponding contiguous target storage address in memory in a burst write manner. This step effectively merges the large number of discrete and random write requests to memory generated by the irregular mapping into a small number of continuous and sequential batch write requests, thereby maximizing the utilization of memory bus bandwidth.

[0079] In one possible implementation, when the amount of aggregated data of the aggregated pixel reaches a preset burst transmission length, the aggregated pixel is written to the target storage address of the memory in a burst write manner, specifically including steps S1051-S1055, as follows: Step S1051: Detect whether the aggregated data volume of the aggregated pixels has reached the preset burst transmission length.

[0080] In step S1051, the aggregated data volume refers to the total amount of data contained in the aggregated pixels currently formed in the cache, usually in bytes. The preset burst transmission length refers to the optimal data length for a single burst write operation, determined by the memory hardware characteristics, in order to achieve the most efficient memory write performance.

[0081] Specifically, the receiver card internally sets up a data volume counter. Whenever a target pixel is added to the aggregated pixels in the buffer, the receiver card increments the data size of that target pixel onto the data volume counter. Simultaneously, the receiver card continuously compares the current value of the data volume counter with a fixed, preset burst transmission length value. This preset burst transmission length value is pre-set based on the memory chip and bus protocol used, for example, set to 64 bytes.

[0082] Step S1052: When it is determined that the aggregated data volume of the aggregated pixel reaches the preset burst transmission length, a write trigger signal is generated.

[0083] In step S1052, the write trigger signal refers to a level or pulse signal generated by the control logic inside the receiver card, which is used to start a complete burst write process.

[0084] Specifically, when the comparison result in the previous step is true, meaning the aggregated data volume reaches or exceeds the preset burst transmission length, the receiver card's control logic immediately generates a high-level active write trigger signal. This signal is sent to the receiver card's memory interface control unit as an explicit instruction to perform a burst write operation.

[0085] Step S1053: Configure the burst transfer parameters of the memory according to the write trigger signal and the target memory address. The burst transfer parameters include burst length and address increment mode.

[0086] In step S1053, the burst transfer parameters refer to a set of configuration information required for the memory to perform burst operations. The burst length specifies the number of data units that need to be written consecutively in this burst write operation. The address increment mode is an operating mode that instructs the memory to automatically increment the storage address for each subsequent data unit after receiving the starting address.

[0087] Specifically, upon receiving a write trigger signal, the receiver card's memory interface control unit immediately performs configuration. The control unit uses the target memory address of the first target pixel in the aggregated pixels as the starting address for this burst write. Simultaneously, it loads the preset burst transmission length value into the burst length register and sets the address mode to linear increment mode. These burst transmission parameters are written to the corresponding configuration registers of the memory, preparing it to receive a continuous data stream.

[0088] Step S1054: Based on the burst transmission parameters, organize the aggregated pixels into a transmission data format that conforms to the memory interface specification.

[0089] In step S1054, the data transmission format refers to the rearrangement and encapsulation of aggregated pixel data to meet the requirements of the memory bus protocol, so that it can be correctly recognized and received by the memory interface.

[0090] Specifically, the data path logic of the receiving card reads the aggregated pixel data from the cache. If the memory interface data bus width is 32 bits and each pixel data is 24 bits, then the data path logic aligns and concatenates the aggregated pixel data stream, packaging it into a continuous 32-bit data word sequence. This process ensures that the data bit width and format sent to the data bus in each clock cycle of a burst write fully conform to the memory interface specification.

[0091] Step S1055: Perform a burst write operation to the target storage address based on the transmission data format.

[0092] In step S1055, the burst write operation refers to the process of writing the formatted aggregated pixel data block to the contiguous storage space pointed to by the target storage address at high speed and continuously via the memory bus.

[0093] Specifically, after the memory is configured and the data transmission format is ready, the receiver card's memory interface control unit initiates a burst write operation. The memory interface control unit first sends the starting target memory address to the address bus. Then, over multiple consecutive clock cycles, it sequentially places the organized aggregated pixel data in the transmission data format onto the data bus, and, in conjunction with the corresponding write enable and data valid signals, writes the data stream into the memory. The entire process, from sending the address until the last piece of data is written, does not require resending the address, achieving high-speed continuous data writing.

[0094] Step S106: Read the aggregated pixels linearly from the memory and perform end mapping correction on the aggregated pixels to obtain the output data.

[0095] In step S106, end mapping correction refers to the final real-time adjustment of the data stream based on the actual physical wiring and other conditions after the data is read from the memory and before it is sent to the driver chip; output data refers to the final data sequence whose format completely matches the requirements of the driver chip after end mapping correction.

[0096] Specifically, during display refresh, the system efficiently reads aggregated pixels arranged in physical scan order from memory in a linear streaming manner. In the data flow path to the driver chip, the system uses a real-time lookup table or logical judgment to perform end-map correction on the data stream. This correction includes: reordering minor out-of-order pixel issues within the same scan row that may be caused by aggregate writing; automatically skipping or masking invalid data bits connected to idle pins or invalid LED positions based on the PCB routing design; and dynamically adjusting the effective length and clock signal of each row of output data stream for two-dimensional irregular shapes with varying numbers of rows and columns, such as circular edges. After correction, output data that can directly drive physical pixels is obtained.

[0097] In one possible implementation, end-map correction is performed on the aggregated pixels to obtain output data, specifically including steps S1061-S1063, as follows: Step S1061: Calculate the deviation between the order of each target pixel within the aggregated pixel and the original logical order, and generate an intra-packet reordering index based on the deviation.

[0098] In step S1061, the original logical order refers to the original arrangement order of the target pixels in a standard two-dimensional image frame before any irregular screen mapping processing, typically a linear order from top to bottom and left to right. The deviation is used to represent the misalignment of the current arrangement order of the target pixels within the aggregated pixel relative to the original logical order. The intra-packet reordering index is a data structure used to record and describe how to restore the disordered target pixels within the aggregated pixel to the correct logical order or the final drive output order.

[0099] Specifically, while aggregating multiple target pixels into a single aggregated pixel, the receiving card also records the original logical order of these target pixels. Once an aggregated pixel is formed, the receiving card compares the correspondence between each target pixel within the aggregated pixel and its original logical order, thus calculating the deviation between the two. Based on this deviation, the receiving card generates an intra-packet reordering index. This index is essentially a mapping table that explicitly indicates that the data at position N in the current aggregated pixel should ultimately be placed at position M in the output data stream.

[0100] Step S1062: Encapsulate the reordering index and aggregated pixels within the packet into a composite data block, and write the composite data block to the target storage address of the memory.

[0101] In step S1062, a composite data block refers to a data unit that binds together the actual color data of aggregated pixels with an intra-packet reordering index used to correct the order of the data.

[0102] Specifically, after generating the intra-packet reordering index, the receiving card does not store the intra-packet reordering index separately from the aggregated pixels. Instead, the receiving card appends the intra-packet reordering index to the front or back of the corresponding aggregated pixel data in its internal cache, encapsulating the two into an indivisible composite data block. Subsequently, the receiving card writes the entire composite data block as a whole to the target memory address using the aforementioned burst write method. This ensures that the pixel data and the index information used to correct the order of the pixel data are closely associated in physical storage, facilitating subsequent reading and processing.

[0103] Step S1063: When the current composite data block is read from the memory, the subsequent composite data blocks after the current composite data block are reconstructed in real time using the intra-packet reordering index to complete the end mapping correction and obtain the output data.

[0104] In step S1063, the current composite data block refers to the composite data block being read from the memory during the data readout stage. The subsequent composite data block refers to the next composite data block that follows the current one and is about to be read. End-map correction refers to the process of real-time reordering of the pixel data stream using index information at the final stage of data output from memory to the LED driver circuit, ensuring the image is correctly displayed on the irregularly shaped display screen. The output data, after end-map correction, is in the correct order and can be directly sent to the final pixel data stream of the LED driver circuit.

[0105] Specifically, when the display engine of the receiver card needs to send frame data to the LED module, it begins to sequentially read composite data blocks from memory. When the display engine reads the current composite data block, it immediately extracts the intra-packet reordering index portion and uses this index to configure a data reconstruction unit. The intra-packet reordering index is used to configure the sorting logic of a data reconstruction unit on the fly, while the aggregated pixel data portion of the composite data block is sent to the data reconstruction unit. Based on the just-loaded index, the data reconstruction unit performs real-time position rearrangement of the currently input pixel data paired with that index, restoring the disordered pixels to the correct logical order. In this way, each composite data block is reordered using the intra-packet reordering index when it is read.

[0106] Please refer to Figure 2 In one possible implementation, based on the output data, the irregularly shaped LED display screen is driven to display the corrected image, specifically including steps S201-S204, as follows: Step S201: Obtain the PCB wiring topology information of the LED module; In step S201, PCB wiring topology information refers to circuit layout data that defines in detail the physical connection correspondence between each output pin of the driver chip and the physical LED on the printed circuit board of the LED module.

[0107] Specifically, during the initialization phase or before executing display tasks, the system loads and parses the PCB routing topology information of a specific LED module from a preset configuration file. This information precisely records whether each data output channel of the driver chip is connected to a valid physical LED, and which physical LED it is connected to. In some designs, to simplify wiring or use a general-purpose PCB board, some driver chip pins may be left floating, i.e., not connected to any physical LEDs; this information is also included in the PCB routing topology information.

[0108] Step S202: Based on the PCB wiring topology information, identify invalid data bits in the output data corresponding to unconnected physical LEDs; In step S202, invalid data bits refer to those data portions in the output data stream read from the memory that, based on the PCB wiring topology information, the corresponding driver chip pins are not connected to any physical LEDs.

[0109] Specifically, after the output data is linearly read from the memory, the data stream is processed before being sent to the driver chip. This processing logic compares the sequence of the output data stream with the PCB routing topology information obtained in step S201 in real time. By comparing, it can be calculated which positions in the data stream need to be inserted invalid data, so that the valid data can be accurately aligned to the pins on the driver chip connected to the physical LEDs.

[0110] Step S203: Generate invalid data for padding based on invalid data bits; In step S203, invalid data refers to specific data content generated by the system to fill or replace invalid data bits in the data stream, typically zero-value data representing a closed state.

[0111] Specifically, after identifying invalid data bits, invalid data is generated for padding. This invalid data is set to a value that will not light up the LED, such as all zeros. The generation of invalid data is a real-time hardware operation, ensuring that the padding action does not affect the overall data stream transmission rate.

[0112] Step S204: Based on the output data and invalid data, drive the irregularly shaped LED display screen to display the corrected image.

[0113] In step S204, driving the irregularly shaped LED display to display the corrected image refers to sending the processed final data stream, which contains valid pixel data and filled invalid data, out according to the timing required by the driver chip to control the physical LED beads to light up, thereby presenting a complete picture on the screen.

[0114] Specifically, the original, continuous output data stream is used as a foundation. Based on invalid data points determined by the PCB routing information, generated invalid data is inserted into designated positions within the data stream to obtain the final output data stream. The length and structure of this final output data stream perfectly match the physical pins of the driver chip. When this data stream is sent to the driver chip, the original valid pixel data accurately falls on the pins connected to the physical LEDs, illuminating the screen and ensuring the continuity of the final displayed image. The newly inserted invalid data fills the positions of corresponding floating pins, successfully skipping empty pins and avoiding any stray signals or image misalignment.

[0115] Step S107: Based on the output data, drive the irregularly shaped LED display screen to display the corrected image.

[0116] In step S107, the corrected image refers to the correct image that is ultimately presented to the observer on the three-dimensional irregular LED display screen without geometric distortion.

[0117] Specifically, the receiving card sends the output data generated in step S106 through physical pins, strictly following the data timing required by the driver chip. The driver chip, as the final execution terminal, receives the output data and parses it into control signals, precisely controlling the brightness and color of each physical pixel. Because the output data has undergone precise correction, rearrangement, and adjustment in all previous steps, the driver chip's actions enable the entire irregularly shaped LED display screen to function as a whole, stably and smoothly displaying the corrected image without geometric distortion.

[0118] Reference Figure 3This application also provides an image correction system for irregularly shaped LED displays. The system includes a mapping calculation module 301, a parameter distribution module 302, an interpolation processing module 303, an address calculation module 304, a cache aggregation module 305, and an output correction module 306. The mapping calculation module 301 is used to acquire each physical pixel of the irregularly shaped LED display and calculate the mapping relationship between each physical pixel and the global display canvas of the irregularly shaped LED display to the original video canvas, generating correction mapping parameters. The parameter distribution module 302 is used to distribute and store the correction mapping parameters to the receiving card corresponding to the physical pixel. The interpolation processing module 303 is used to receive the video pixel stream from the receiving card and use the correction mapping parameters to correct the video pixel stream. Interpolation calculations are performed to generate geometrically corrected target pixels; address calculation module 304 is used to calculate the target storage address of the target pixels in the memory according to the physical scanning order of the target pixels on the LED module of the irregular LED display, and aggregate multiple target pixels in the cache to obtain aggregated pixels; cache aggregation module 305 is used to write the aggregated pixels to the target storage address of the memory in a burst write mode when the aggregated data of the aggregated pixels reaches the preset burst transmission length; output correction module 306 is used to linearly read the aggregated pixels from the memory and perform end mapping correction on the aggregated pixels to obtain output data; output correction module 306 is also used to drive the irregular LED display to display the corrected image based on the output data.

[0119] In one possible implementation, the mapping calculation module 301 calculates the mapping relationship of each physical pixel from the global display canvas of the irregular LED display to the original video canvas, and generates correction mapping parameters. Specifically, the mapping calculation module 301 divides the global display canvas of the irregular LED display into a preset number of sub-regions according to the topology, and each sub-region corresponds to the logical address space of a receiving card; the mapping calculation module 301 calculates the floating-point mapping coordinates of the physical coordinates of each physical pixel in each sub-region in the original video canvas according to the curved geometric characteristics of the irregular LED display; the mapping calculation module 301 calculates the pixel index, sub-pixel offset and interpolation weight coefficient corresponding to each physical pixel according to the floating-point mapping coordinates, and uses the pixel index, sub-pixel offset and interpolation weight coefficient as correction mapping parameters.

[0120] In one possible implementation, the interpolation processing module 303 receives the video pixel stream from the receiving card and performs interpolation calculations on the video pixel stream using correction mapping parameters to generate a geometrically corrected target pixel. Specifically, the interpolation processing module 303 extracts the video pixel stream belonging to the load range of the receiving card from the high-speed video link; within the mapping engine of the receiving card, the interpolation processing module 303 temporarily stores the pixel data of the current processing row and the adjacent rows of the current processing row using a row buffer to form an interpolation window; based on the current write counter value, the interpolation processing module 303 determines the target pixel index, target sub-pixel offset, and target interpolation weight coefficient corresponding to the current physical pixel based on the correction mapping parameters; based on the target pixel index, the interpolation processing module 303 locates neighboring pixels from the interpolation window and performs a weighted summation of the neighboring pixels based on the target sub-pixel offset and the target interpolation weight coefficient to generate the target pixel.

[0121] In one possible implementation, the address calculation module 304 calculates the target storage address of the target pixel in the memory according to the physical scanning order of the target pixel on the LED module of the irregularly shaped LED display, and aggregates multiple target pixels in the cache to obtain aggregated pixels. Specifically, the address calculation module 304 obtains the physical driving parameters of the LED module and constructs a physical scanning order index table based on the physical driving parameters and the physical scanning order. The physical driving parameters include the number of scan rows, the number of pixels per row, and the row scanning timing. Based on the physical scanning order index table, the address calculation module 304 parses the physical driving row number and the offset position within the row to which the target pixel belongs. The address calculation module 304 converts the physical driving row number and the offset position within the row into the form of a memory base address plus an offset using an address redirection algorithm to calculate the target storage address. The address calculation module 304 detects whether the target storage addresses of multiple target pixels belong to the same physical driving row. The address calculation module 304 aggregates the target pixels belonging to the same physical driving row in the cache according to the physical scanning order to form aggregated pixels.

[0122] In one possible implementation, when the aggregated data volume of the aggregated pixels reaches a preset burst transmission length, the cache aggregation module 305 writes the aggregated pixels to the target storage address of the memory in a burst write manner. Specifically, this includes: the cache aggregation module 305 detecting whether the aggregated data volume of the aggregated pixels has reached the preset burst transmission length; when it is determined that the aggregated data volume of the aggregated pixels has reached the preset burst transmission length, the cache aggregation module 305 generates a write trigger signal; the cache aggregation module 305 configures the burst transmission parameters of the memory according to the write trigger signal and the target storage address, the burst transmission parameters including burst length and address increment mode; the cache aggregation module 305 organizes the aggregated pixels into a transmission data format conforming to the memory interface specification based on the burst transmission parameters; and the cache aggregation module 305 performs a burst write operation to the target storage address based on the transmission data format.

[0123] In one possible implementation, the output correction module 306 performs end-map correction on the aggregated pixels to obtain output data. Specifically, the output correction module 306 calculates the deviation between the order of each target pixel within the aggregated pixel and the original logical order, and generates an intra-packet reordering index based on the deviation; the output correction module 306 encapsulates the intra-packet reordering index and the aggregated pixels into a composite data block, and writes the composite data block to the target storage address of the memory; when the current composite data block is read from the memory, the output correction module 306 uses the intra-packet reordering index to reconstruct the subsequent composite data blocks after the current composite data block in real time, completes the end-map correction, and obtains the output data.

[0124] In one possible implementation, the output correction module 306 drives the irregularly shaped LED display screen to display the corrected image based on the output data. Specifically, the output correction module 306 acquires the PCB wiring topology information of the LED module; the output correction module 306 identifies invalid data bits in the output data corresponding to unconnected physical LEDs based on the PCB wiring topology information; invalid data is generated for filling based on the invalid data bits; and the output correction module 306 drives the irregularly shaped LED display screen to display the corrected image based on the output data and the invalid data.

[0125] It should be noted that the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

Claims

1. An image correction method for a special-shaped LED display screen, characterized in that, The method includes: Obtain each physical pixel of the irregularly shaped LED display screen, and calculate the mapping relationship of each physical pixel from the global display canvas of the irregularly shaped LED display screen to the original video canvas, and generate correction mapping parameters; The correction mapping parameters are sent out and stored in the receiving card corresponding to the physical pixel; The receiving card receives the video pixel stream and uses the correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels; Based on the physical scanning order of the target pixels on the LED module of the irregular LED display, the target storage address of the target pixel in the memory is calculated, and multiple target pixels are aggregated in the cache to obtain aggregated pixels; When the aggregated data of the aggregated pixel reaches the preset burst transmission length, the aggregated pixel is written to the target storage address of the memory in a burst write manner. The aggregated pixels are linearly read from the memory, and the end mapping of the aggregated pixels is corrected to obtain the output data; Based on the output data, the irregularly shaped LED display screen is driven to display the corrected image.

2. The method of claim 1, wherein, The calculation of the mapping relationship between each physical pixel and the global display canvas of the irregularly shaped LED display screen to the original video canvas, and the generation of correction mapping parameters, specifically includes: The global display canvas of the irregularly shaped LED display screen is divided into a preset number of sub-regions according to the topology, and each sub-region corresponds to a logical address space of the receiving card; Based on the curved geometric characteristics of the irregular LED display screen, the physical coordinates of each physical pixel in each sub-region are calculated as floating-point mapping coordinates in the original video canvas; Based on the floating-point mapping coordinates, the pixel index, sub-pixel offset, and interpolation weight coefficient corresponding to each physical pixel are calculated, and the pixel index, sub-pixel offset, and interpolation weight coefficient are used as the correction mapping parameters.

3. The method of claim 1, wherein, The step of receiving the video pixel stream from the receiving card and using the correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels specifically includes: The receiving card extracts the video pixel stream belonging to the load range of the receiving card from the high-speed video link; Inside the mapping engine of the receiving card, the pixel data of the current processing row and the adjacent rows of the current processing row are temporarily stored in the row buffer to form an interpolation window; Based on the current write counter value, the target pixel index, target sub-pixel offset, and target interpolation weight coefficient corresponding to the current physical pixel are determined based on the correction mapping parameters. Based on the target pixel index, neighboring pixels are located from the interpolation window, and the neighboring pixels are weighted and summed according to the target sub-pixel offset and the target interpolation weight coefficient to generate the target pixel.

4. The method of claim 1, wherein, The step of calculating the target storage address of the target pixel in the memory based on the physical scanning order of the target pixel on the LED module of the irregularly shaped LED display, and aggregating multiple target pixels in the cache to obtain aggregated pixels, specifically includes: The physical driving parameters of the LED module are obtained, and a physical scanning sequence index table is constructed based on the physical driving parameters and the physical scanning sequence. The physical driving parameters include the number of scan rows, the number of pixels per row, and the row scanning timing. Based on the physical scan order index table, the physical driving row number and in-row offset position of the target pixel are parsed. The physical drive row number and the offset position within the row are converted into the form of memory base address plus offset by an address redirection algorithm, and the target memory address is calculated. Detect whether the target storage addresses of multiple target pixels belong to the same physical drive row; Target pixels belonging to the same physical drive row are aggregated in the cache according to the physical scan order to form the aggregated pixels.

5. The method of claim 1, wherein, When the aggregated data volume of the aggregated pixel reaches a preset burst transmission length, the aggregated pixel is written to the target storage address of the memory in a burst write manner, specifically including: Detect whether the aggregated data volume of the aggregated pixels reaches the preset burst transmission length; When it is determined that the amount of aggregated data of the aggregated pixel reaches the preset burst transmission length, a write trigger signal is generated; Based on the write trigger signal and the target storage address, configure the burst transfer parameters of the memory, including burst length and address increment mode; Based on the burst transmission parameters, the aggregated pixels are organized into a transmission data format that conforms to the memory interface specification; Based on the transmitted data format, a burst write operation is performed to the target storage address.

6. The method of claim 1, wherein, The step of performing end-map correction on the aggregated pixels to obtain output data specifically includes: Calculate the deviation between the order of each target pixel within the aggregated pixel and the original logical order, and generate an intra-packet reordering index based on the deviation; The reordering index within the package and the aggregated pixel are encapsulated into a composite data block, and the composite data block is written to the target storage address of the memory. When the current composite data block is read from the memory, the subsequent composite data blocks after the current composite data block are reconstructed in real time using the intra-packet reordering index to complete the end-map correction and obtain the output data.

7. The method of claim 1, wherein, The step of driving the irregularly shaped LED display screen to display the corrected image based on the output data specifically includes: Obtain the PCB wiring topology information of the LED module; Based on the PCB wiring topology information, identify invalid data bits in the output data that correspond to unconnected physical LEDs; Based on the invalid data bits, generate invalid data for padding; Based on the output data and the invalid data, the irregularly shaped LED display screen is driven to display the corrected image.

8. An image correction system for irregularly shaped LED displays, characterized in that, The system includes a mapping calculation module (301), a parameter distribution module (302), an interpolation processing module (303), an address calculation module (304), a cache aggregation module (305), and an output correction module (306), wherein, The mapping calculation module (301) is used to obtain each physical pixel of the irregular LED display screen, calculate the mapping relationship of each physical pixel from the global display canvas of the irregular LED display screen to the original video canvas, and generate correction mapping parameters. The parameter sending module (302) is used to send the correction mapping parameters and store them in the receiving card corresponding to the physical pixel; The interpolation processing module (303) is used to receive the video pixel stream from the receiving card and use the correction mapping parameters to perform interpolation calculations on the video pixel stream to generate geometrically corrected target pixels. The address calculation module (304) is used to calculate the target storage address of the target pixel in the memory according to the physical scanning order of the target pixel on the LED module of the irregular LED display screen, and to aggregate multiple target pixels in the cache to obtain aggregated pixels; The cache aggregation module (305) is used to write the aggregated pixel to the target storage address of the memory in a burst write manner when the aggregated data amount of the aggregated pixel reaches the preset burst transmission length. The output correction module (306) is used to linearly read the aggregated pixel from the memory and perform end mapping correction on the aggregated pixel to obtain output data; The output correction module (306) is also used to drive the irregularly shaped LED display screen to display the corrected image based on the output data.

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