Array substrate, display panel and electronic device

Abstract

This application discloses an array substrate, a display panel, and an electronic device, relating to the field of display device technology. The array substrate includes: a pixel circuit and a driving circuit; a first signal line electrically connected to the pixel circuit, the first signal line transmitting a first signal for the pixel circuit; and a second signal line electrically connected to the driving circuit, the second signal line transmitting a second signal for the driving circuit. The first signal line and the second signal line are located in different film layers, and a first isolation layer is included between the first signal line and the second signal line, the first isolation layer transmitting a first voltage signal. This application can utilize the first isolation layer to reduce the interference of the second signal transmitted by the second signal line on the first signal line transmitted by the first signal line, improving the stability and reliability of the pixel circuit, thereby improving the image display quality of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to an array substrate, a display panel, and an electronic device. Background Technology

[0002] With the continuous development of display technology, high-resolution and high-refresh-rate display panels place increasingly higher demands on the signal transmission quality and display uniformity within the panel. The array substrate of a display panel typically contains pixel circuits and driving circuits. The pixel circuits control the light-emitting state of the light-emitting elements, while the driving circuits provide various control signals to the pixel circuits.

[0003] Pixel circuits are connected to the light-emitting elements in the display panel used for image display. The pixel circuits respond to control signals input from the driving circuit, controlling the light-emitting elements to display images. As the integration of display panels continues to increase, the signal traces between the pixel circuits and the driving circuits become increasingly dense, requiring the arrangement of various signal lines within a limited film layer space. Therefore, signals transmitted in the signal lines electrically connected to the pixel circuits are highly susceptible to interference from signals transmitted in the signal lines connected to the driving circuits, causing fluctuations in the signals transmitted in these lines. This affects the stability and reliability of the pixel circuits, thereby impacting image display quality. Summary of the Invention

[0004] In view of the above problems, this application provides an array substrate, a display panel, and an electronic device, the specific solutions of which are as follows:

[0005] The first aspect of this application provides an array substrate for a display panel, comprising:

[0006] Pixel circuits and driving circuits;

[0007] A first signal line electrically connected to the pixel circuit, the first signal line transmits a first signal to the pixel circuit;

[0008] The second signal line is electrically connected to the drive circuit, and the second signal line transmits the second signal to the drive circuit.

[0009] The first signal line and the second signal line are located in different film layers, and a first isolation layer is included between the first signal line and the second signal line. The first isolation layer transmits the first voltage signal.

[0010] Optionally, in the above array substrate, the first isolation layer includes an integral conductive region, and the conductive region transmits a first voltage signal;

[0011] In this configuration, in a direction perpendicular to the plane of the array substrate, the first isolation layer is located between the first signal line and the second signal line, and at least one of the first signal line and the second signal line overlaps with the conductive region.

[0012] Optionally, in the above array substrate, the conductive region has multiple mesh holes;

[0013] In a direction perpendicular to the plane, at least some of the mesh openings do not overlap with the first signal line; and / or, at least some of the mesh openings do not overlap with the second signal line.

[0014] Optionally, in the above array substrate, the pixel circuit includes a plurality of transistors located in the first circuit region; in a direction perpendicular to the plane of the array substrate, the first circuit region overlaps with the conductive region, but does not overlap with the first signal line and the second signal line.

[0015] In the first direction, there is a gap region between two adjacent first circuit regions; both the first signal line and the second signal line extend along the second direction; the second direction intersects the first direction and is parallel to the plane;

[0016] In a direction perpendicular to the plane, the portion of the conductive region opposite the gap region has a mesh; and within this portion, the first signal line and / or the second signal line do not overlap with the mesh.

[0017] Optionally, in the above array substrate, the conductive area is electrically connected to the pixel circuit to transmit a first voltage signal to the pixel circuit;

[0018] Alternatively, the conductive area is electrically connected to the driving circuit to transmit the first voltage signal to the driving circuit.

[0019] Optionally, in the array substrate described above, the pixel circuit receives at least a first power supply voltage, a second power supply voltage, and a reference voltage;

[0020] The driving circuit receives at least a start voltage signal, a high-level signal, and a low-level signal;

[0021] The first voltage signal is any one of the following: first power supply voltage, second power supply voltage, reference voltage, start voltage signal, high-level signal, and low-level signal.

[0022] Optionally, in the array substrate described above, the first isolation layer is insulated from both the pixel circuit and the driving circuit.

[0023] Optionally, in the above-mentioned array substrate, the pixel circuit receives at least a data voltage signal;

[0024] The drive circuit must receive at least a clock signal;

[0025] The first signal is the data voltage signal, and the second signal is the clock signal.

[0026] Optionally, in the above array substrate, the conductive region has multiple mesh holes;

[0027] The pixel circuit and the driving circuit are located on the same side of the first isolation layer, and the other side of the first isolation layer has a first connection line; the first connection line passes through the conductive area based on mesh insulation to be electrically connected to one of the pixel circuit and the driving circuit.

[0028] Optionally, in the above array substrate, the plurality of mesh holes include a first through hole, and the first through hole has a transition block that is insulated from the conductive area;

[0029] The first connection line is electrically connected to one of the pixel circuit and the driving circuit via a transition block.

[0030] Optionally, in the above array substrate, the plurality of mesh holes include first through holes;

[0031] The first connecting line is electrically connected to the anode of the light-emitting element, and the first connecting line is electrically connected to the transistor in the pixel circuit based on the first through hole;

[0032] Alternatively, the first connection line is electrically connected to a transistor in the drive circuit via a first through-hole.

[0033] Optionally, in the array substrate described above, at least a portion of the first via does not overlap with the active layer of the transistor in a direction perpendicular to the plane.

[0034] Optionally, in the above-mentioned array substrate, the pixel circuit includes a plurality of transistors located in the first circuit region; in a direction perpendicular to the plane of the array substrate, the first circuit region and the conductive region have an overlapping portion;

[0035] The multiple mesh holes include second through holes, which are filled with insulating material; in a direction perpendicular to the plane of the array substrate, the second through holes do not overlap with the first circuit area.

[0036] Optionally, in the above-mentioned array substrate, the driving circuit includes a plurality of transistors located in the second circuit region; in a direction perpendicular to the plane of the array substrate, the second circuit region and the conductive region have an overlapping portion;

[0037] The multiple mesh holes include a second through hole, which is filled with an insulating material; in a direction perpendicular to the plane of the array substrate, the second through hole overlaps with the second circuit area.

[0038] Optionally, in the array substrate described above, the pixel circuit includes a plurality of transistors located in the first circuit region; the first circuit region and the conductive region have an overlapping portion;

[0039] Multiple mesh openings include a third through-hole, which is filled with insulating material;

[0040] The pixel circuit includes multiple transistors, including a driving transistor and a storage capacitor. In a direction perpendicular to the plane, the third via does not overlap with either the driving transistor or the storage capacitor.

[0041] Optionally, in the array substrate described above, the first isolation layer further includes a third signal line insulated from the conductive region. The third signal line is electrically connected to one of the pixel circuit and the driving circuit for transmitting a second voltage signal, wherein the first voltage signal is different from the second voltage signal.

[0042] Optionally, in the above array substrate, the second signal is a periodic signal;

[0043] The number of level switching times of the first voltage signal within a set time period is less than the number of level switching times of the second signal;

[0044] The number of level switching times of the second voltage signal within the set time period is less than the number of level switching times of the second signal.

[0045] Optionally, in the above array substrate, the metal layer where the first signal line is located further includes a first isolation line and a fourth signal line, the fourth signal line being electrically connected to the pixel circuit or driving circuit.

[0046] The first isolation line, the first signal line, and the fourth signal line extend in the same direction; there is at least one first isolation line between adjacent first signal lines and fourth signal lines, and the first isolation line is electrically connected to the first isolation layer.

[0047] Optionally, in the above array substrate, the second metal layer where the second signal line is located further includes a second isolation line and a fifth signal line, the fifth signal line being electrically connected to the pixel circuit or driving circuit.

[0048] The second isolation line, the second signal line, and the fifth signal line extend in the same direction; there is at least one second isolation line between adjacent second signal lines and fifth signal lines, and the second isolation line is electrically connected to the first isolation layer.

[0049] Optionally, in the array substrate described above, the pixel circuit includes a plurality of transistors located in the first circuit region; the first circuit region and the conductive region have an overlapping portion;

[0050] The first isolation layer has multiple mesh openings;

[0051] The multiple meshes include a first portion of meshes and / or a second portion of meshes; in a direction perpendicular to the plane of the array substrate, the first portion of meshes does not overlap with the first circuit area, while the second portion of meshes overlaps with the first circuit area;

[0052] The first part of the mesh has the same area, or the first part of the mesh has the same spacing in the first direction, or the first part of the mesh has the same spacing in the second direction, and both the first and second directions are parallel to the plane and intersect.

[0053] The second part of the mesh has the same area, or the second part of the mesh has the same spacing in the first direction, or the second part of the mesh has the same spacing in the second direction.

[0054] Optionally, the array substrate further includes a second isolation layer disposed adjacent to the first isolation layer, the second isolation layer transmitting a third voltage signal; an insulating layer is provided between the first isolation layer and the second isolation layer.

[0055] Optionally, in the above array substrate, the first isolation layer and the second isolation layer constitute a composite isolation structure, the pixel circuit and the driving circuit are located on one side of the composite isolation structure, and the other side of the composite isolation structure has a first connection line;

[0056] Both the first and second isolation layers have multiple mesh holes. In a direction perpendicular to the plane of the array substrate, some mesh holes of the first and second isolation layers overlap, and the overlapping mesh holes are used to set the transition block. The first connecting line is electrically connected to one of the pixel circuit and the driving circuit through the transition block. Some mesh holes of the first and second isolation layers do not overlap, and the non-overlapping through holes are filled with insulating material.

[0057] Optionally, in the above array substrate, the first isolation layer includes a plurality of integral conductive regions distributed along a first direction; the conductive regions are respectively input with a first voltage signal;

[0058] Both the first signal line and the second signal line extend along the second direction;

[0059] The first and second directions intersect and are both parallel to the plane.

[0060] Optionally, in the above array substrate, the pixel circuit and the driving circuit are located on one side of the first isolation layer, and the other side of the first isolation layer has a first connection line;

[0061] The first isolation layer has multiple mesh holes; some of the mesh holes are first through holes, and the first connecting line is electrically connected to one of the pixel circuit and the driving circuit based on the first through holes; the first connecting line is insulated from the first isolation layer.

[0062] The other part of the mesh is filled with insulating material;

[0063] The metal layer containing the first signal line also has a first shielding block that is insulated from the first signal line; the first shielding block is disposed opposite to another part of the mesh and is electrically connected to the first isolation layer, and / or, the metal layer containing the second signal line also has a second shielding block that is insulated from the second signal line; the second shielding block is disposed opposite to another part of the mesh and is electrically connected to the first isolation layer.

[0064] A second aspect of this application provides a display panel, comprising:

[0065] An array substrate includes: a pixel circuit and a driving circuit; a first signal line electrically connected to the pixel circuit, the first signal line transmitting a first signal for the pixel circuit; and a second signal line connected to the driving circuit, the second signal line transmitting a second signal for the driving circuit; wherein the first signal line and the second signal line are located in different film layers, and a first isolation layer is provided between the first signal line and the second signal line.

[0066] The light-emitting element, which is electrically connected to the pixel circuit, displays images based on the driving current provided by the pixel circuit.

[0067] A third aspect of this application provides an electronic device, comprising:

[0068] The aforementioned display panel.

[0069] In the technical solution of this application, the first signal line transmitting the first signal and the second signal line transmitting the second signal are disposed on different film layers, and a first isolation layer transmitting the first voltage signal is disposed between them. This reduces the interference of the second signal transmitted by the second signal line on the first signal line, improves the stability and reliability of the pixel circuit, and thus improves the image display quality of the display panel. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0071] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0072] Figure 1This is a schematic diagram of the structure of an array substrate in a display panel;

[0073] Figure 2 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0074] Figure 3 A top view of an array substrate in a display panel provided in an embodiment of this application;

[0075] Figure 4a for Figure 3 The cross-sectional view of the array substrate along the A-A' direction is shown.

[0076] Figure 4b This application provides a schematic diagram of a structure in an array substrate that isolates a first signal line and a second signal line based on a first isolation layer.

[0077] Figure 5 This is a schematic diagram of the layout of a first isolation layer, a first signal line, and a second signal line in an array substrate provided in an embodiment of this application.

[0078] Figure 6 for Figure 5 The cross-sectional view of the array substrate shown in the B-B' direction;

[0079] Figure 7 This is a schematic diagram of another layout of the first isolation layer, the first signal line, and the second signal line in an array substrate provided in an embodiment of this application.

[0080] Figure 8 for Figure 7 The cross-sectional view of the array substrate shown in the C-C' direction;

[0081] Figure 9 This is a schematic diagram of the structure of an array substrate in another display panel provided in an embodiment of this application;

[0082] Figure 10 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0083] Figure 11 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0084] Figure 12 This application provides a schematic diagram of the structure of a pixel circuit in a display panel.

[0085] Figure 13 for Figure 12 The circuit layout of the pixel circuit shown;

[0086] Figure 14This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0087] Figure 15 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0088] Figure 16 for Figure 15 The cross-sectional view of the array substrate along the D-D' direction is shown.

[0089] Figure 17 for Figure 16 The diagram shows a cross-sectional view of the display panel along the E-E' direction;

[0090] Figure 18 A schematic diagram illustrating the layout of the active layer and the first via in the conductive region of a transistor in an array substrate, provided for an embodiment of this application;

[0091] Figure 19 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0092] Figure 20 A schematic diagram of a layout scheme for a first through hole and a second through hole in a conductive region provided in an embodiment of this application;

[0093] Figure 21 A schematic diagram of another layout scheme for the first through hole and the second through hole in a conductive region provided in an embodiment of this application;

[0094] Figure 22 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0095] Figure 23a This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0096] Figure 23b for Figure 13 The diagram shows the relative layout of the pixel circuit and the third via in the conductive area.

[0097] Figure 24 This is a schematic diagram of the graphic structure of a first isolation layer provided in an embodiment of this application;

[0098] Figure 25 A cross-sectional view of an array substrate provided in an embodiment of this application;

[0099] Figure 26 A cross-sectional view of another array substrate provided in an embodiment of this application;

[0100] Figure 27A schematic diagram illustrating the layout of mesh holes in a conductive area, provided for an embodiment of this application;

[0101] Figure 28 A cross-sectional view of another array substrate provided in an embodiment of this application;

[0102] Figure 29 A cross-sectional view of another array substrate provided in an embodiment of this application;

[0103] Figure 30 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application;

[0104] Figure 31 A cross-sectional view of another array substrate provided in an embodiment of this application;

[0105] Figure 32 A cross-sectional view of another array substrate provided in an embodiment of this application;

[0106] Figure 33 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0107] Figure 34 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0108] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0109] It should be noted that in the schematic diagrams of the array substrate and display panel in this application embodiment, the relative directional positions of the panel structure are shown based on the same three-dimensional Cartesian coordinate system. The positive directions of the three coordinate axes of this three-dimensional Cartesian coordinate system are, in order, the first direction X, the second direction Y, and the third direction Z. The plane containing the array substrate is parallel to the first direction X and the second direction Y, and the normal to the plane containing the array substrate is parallel to the third direction Z.

[0110] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an array substrate in a display panel. The array substrate 100 includes:

[0111] substrate 101;

[0112] The pixel circuit and driving circuit are located on the substrate 101. Both the pixel circuit and the driving circuit include multiple transistors 102. The transistors 102 include an active layer ACL. The active layer ACL can be low-temperature polysilicon or other semiconductor materials.

[0113] The first metal layer MT1, the capacitor metal layer MTc, the second metal layer MT2, the third metal layer MT3, and the fourth metal layer MT4 are stacked sequentially along the third direction Z. The third direction Z is perpendicular to the plane of the array substrate (i.e., the panel plane below) and faces the display side. An insulating layer is provided between adjacent metal layers.

[0114] The first metal layer MT1 is used to construct at least the gate of transistor 102, and also to construct the scan traces (including at least one of PAMS1, PAMS2, PAMK2, PWMS1, PWMS2 and PWMK1 hereinafter) to which the transistors are connected in the pixel circuit and the pulse width control voltage line Sweep hereinafter.

[0115] The second metal layer MT2 is used to construct at least the source and drain of transistor 102, and also to construct data traces (including D1 below).

[0116] The third metal layer MT3 is used at least to construct the control signal lines (including at least one of STV, VGL, VGH, CK, and XCK as described below) connected to the drive circuit, the positive power supply traces (including PVDD as described below) connected to the pixel circuit, and some data traces (including D2 as described below).

[0117] The fourth metal layer MT4 is used at least to construct the anode traces for connecting the pixel circuit to the light-emitting element.

[0118] Both the pixel circuitry and the driving circuitry include capacitive elements. The capacitor metal layer MTc is used at least to construct these capacitive elements.

[0119] Optionally, such as Figure 1 As shown, the array substrate 100 may also include a shielding metal layer MT0 located on the substrate 100 and the shielding metal layer MT0 having an overlap portion with the active layer ACL of at least one transistor 102 in the third direction Z, for electromagnetic shielding and / or light shielding.

[0120] For display panels where the light-emitting element is a miniature LED, such as Figure 1 As shown, the array substrate 100 may further include a fifth metal layer MT5, a sixth metal layer MT6, and a seventh metal layer MT7 sequentially stacked on a fourth metal layer MT4 along a third direction Z. The fifth metal layer MT5 is used at least to construct the negative power supply trace and the pads for soldering the light-emitting element. The sixth metal layer MT6 is another metal film layer. The seventh metal layer MT7 is the soldering metal between the electrodes of the light-emitting element and the pads. The micro LED can be a Micro LED or a Mini LED.

[0121] In the array substrate 100, there are insulating layers 106 between the active layer ACL and adjacent metal layers, and between adjacent metal layers. The array substrate 100 includes multiple insulating layers 106. Each insulating layer 106 can be designed as a single organic material insulating layer, a single inorganic material insulating layer, or a stacked structure formed by at least one organic material insulating layer and at least one inorganic material insulating layer, based on its layout requirements in the array substrate 100.

[0122] like Figure 1 As shown, the array substrate 100 has multiple insulating layers 106. Along the third direction Z, the multiple insulating layers 106 include, in sequence: an insulating layer 106a located between the shielding metal layer MT0 and the active layer ACL; an insulating layer 106b located between the active layer ACL and the first metal layer MT1; an insulating layer 106c located between the first metal layer MT1 and the capacitor metal layer MTc; an insulating layer 106d located between the capacitor metal layer MTc and the second metal layer MT2; an insulating layer 106e located between the second metal layer MT2 and the third metal layer MT3; an insulating layer 106f located between the third metal layer MT3 and the fourth metal layer MT4; an insulating layer 106g located between the fourth metal layer MT4 and the fifth metal layer MT5; an insulating layer 106h located between the fifth metal layer MT5 and the sixth metal layer MT6; an insulating layer 106i located between the sixth metal layer MT6 and the seventh metal layer MT7; and an insulating layer 106j located on the surface of the seventh metal layer MT7.

[0123] In the array substrate, the pixel circuit is directly electrically connected to the light-emitting element and is used to control the light-emitting element to display images. Therefore, the voltage stability of the signal lines connected to the pixel circuit is particularly important for the image display quality. In the array substrate 100, the signals transmitted in the signal lines connected to the pixel circuit are easily interfered with by the signals transmitted in the signal lines connected to the driving circuit. For example, the clock signals input to the driving circuit (including CK and XCK hereinafter) require high-frequency high-low level switching, resulting in large voltage fluctuations, which will seriously affect the data voltage input to the pixel circuit (including PWM_DATA hereinafter), thereby affecting the image display quality. To solve the above problems, embodiments of this application provide an array substrate, which includes:

[0124] Pixel circuits and driving circuits;

[0125] A first signal line electrically connected to the pixel circuit, the first signal line transmits a first signal to the pixel circuit;

[0126] The second signal line is electrically connected to the drive circuit, and the second signal line transmits the second signal to the drive circuit.

[0127] The first signal line and the second signal line are located in different film layers, and a first isolation layer is included between the first signal line and the second signal line. The first isolation layer transmits the first voltage signal.

[0128] In the technical solution of this application embodiment, the first signal line transmitting the first signal and the second signal line transmitting the second signal are disposed on different film layers, and a first isolation layer transmitting the first voltage signal is disposed between them. The first isolation layer can be used to shield the electromagnetic interference between the first signal line and the second signal line, reduce the interference of the second signal transmitted by the second signal line on the first signal line, improve the stability and reliability of the pixel circuit, and thus improve the image display quality of the display panel.

[0129] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments described in this application are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The terminology used in the embodiments of this application is only used to explain the specific embodiments of this application and is not intended to limit this application.

[0130] refer to Figure 2 , Figure 2 This application provides a schematic diagram of the structure of an array substrate in a display panel, showing the array substrate 100 comprising:

[0131] Pixel circuit 103 and driving circuit 104;

[0132] The first signal line SL1 is electrically connected to the pixel circuit 103, and the first signal line SL1 transmits the first signal to the pixel circuit 103.

[0133] The second signal line SL2 is electrically connected to the drive circuit 104, and the second signal line SL2 transmits the second signal to the drive circuit 104.

[0134] The first signal line SL1 and the second signal line SL2 are located in different film layers, and a first isolation layer 105 is included between the first signal line SL1 and the second signal line SL2. The first isolation layer 105 transmits the first voltage signal.

[0135] In the technical solution of this application embodiment, the first signal line SL1 that transmits the first signal and the second signal line SL2 that transmits the second signal are disposed on different film layers, and a first isolation layer 105 that transmits the first voltage signal is disposed between them. The first isolation layer 105 can be used to shield the electromagnetic interference between the first signal line SL1 and the second signal line SL2, reduce the interference of the second signal transmitted by the second signal line SL2 on the first signal transmitted by the first signal line SL1, improve the stability and reliability of the pixel circuit 103, and thus improve the image display quality of the display panel.

[0136] Optionally, the array substrate 100 includes a substrate 101, which can be a rigid substrate made of materials such as glass, or a flexible substrate made of materials such as polyimide. The pixel circuit 103 and the driving circuit 104 are located on the same side of the substrate 101. The first signal line SL1 and the second signal line SL2 can be disposed on the side of the pixel circuit 103 and the driving circuit 104 away from the substrate 101.

[0137] As described below, both the pixel circuit 103 and the driving circuit 104 include multiple transistors. The active layers of all transistors in the pixel circuit 103 and the driving circuit 104 can be disposed on the same layer, such as all transistors having their active layers located on the same semiconductor layer. Alternatively, the active layers of at least some transistors in the same circuit can be located on different semiconductor film layers. Alternatively, some transistors in the pixel circuit 103 and some transistors in the driving circuit 104 can be located on different semiconductor film layers. If the active layers of two transistors are located on different semiconductor film layers, one semiconductor film layer can be LTPS (Low Temperature Polycrystalline Silicon), and the other semiconductor film layer can be IGZO (Indium Gallium Zinc Oxide).

[0138] exist Figure 2 In the illustrated configuration, the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are located on the surfaces of different insulating layers 106, and these two film layers are stacked in the third direction Z. For example, combined with Figure 1 and Figure 2 As shown, the first signal line SL1 can be located on the second metal layer MT2, the first isolation layer 105 can be located on the third metal layer MT3, and the second signal line SL2 can be located on the fourth metal layer MT4. In this case, the film layer containing the first signal line SL1 is located on the surface of the insulating layer 106d, while the film layer containing the second signal line SL2 is located on the surface of the insulating layer 106f. Along the third direction Z, the first signal line SL1 and the second signal line SL2 have different distances from the substrate 101. At this time, the first isolation layer 105 is disposed between the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2. In this configuration, the first signal line SL1 and the second signal line SL2 are isolated in the third direction Z by the first isolation layer 105.

[0139] When the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are stacked in the third direction Z, along the third direction Z, the film layer containing the first signal line SL1, the first isolation layer 105, and the film layer containing the second signal line SL2 can be as follows: Figure 1 The array substrate 100 shown has any three conductive layers, not limited to the second metal layer MT2, the third metal layer MT3, and the fourth metal layer MT4. The conductive layers include metal layers and the active layer ACL.

[0140] When the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are stacked in the third direction Z, at least one of the first signal line SL1 and the second signal line SL2 overlaps with the first isolation layer 105 in the third direction Z. This causes the first isolation layer 105 to shield at least a portion of the first signal line SL1 and / or at least a portion of the second signal line SL2, so as to isolate the first signal line SL1 and the second signal line SL2 in the third direction Z by the first isolation layer 105, thereby reducing the interference of the signal transmitted in the second signal line SL2 to the signal transmitted in the first signal line SL1.

[0141] refer to Figure 3 and Figure 4a , Figure 3 This is a top view of an array substrate in a display panel provided in an embodiment of this application. Figure 4a for Figure 3 The diagram shows a cross-sectional view of the array substrate along the A-A' direction. In this configuration, the film layer of the first signal line SL1 and the film layer of the second signal line SL2 are located on the surface of the same insulating layer 106, and the two film layers are coplanar in the third direction Z. Along the third direction Z, the distance between the first signal line SL1 and the second signal line SL2 and the substrate 101 is the same. At this time, the first isolation layer 105 is located on the surface of the insulating layer 106 and between the first signal line SL1 and the second signal line SL2. In this configuration, the first signal line SL1 and the second signal line SL2 are isolated by the first isolation layer 105 in a direction parallel to the panel plane.

[0142] like Figure 3 As shown, the first signal line SL1 and the second signal line SL2 can both extend along the second direction Y, and a first isolation layer 105 is coplanarly disposed between them.

[0143] When the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are coplanar, the first signal line SL1 and the second signal line SL2 extend in the same direction, and at least one of them overlaps with the first isolation layer 105, so that the first isolation layer 105 shields at least a portion of the first signal line SL1 and / or at least a portion of the second signal line SL2, so as to isolate the first signal line SL1 and the second signal line SL2 in the extension direction through the first isolation layer 105, thereby reducing the interference of the signal transmitted in the second signal line SL2 on the signal transmitted in the first signal line SL1.

[0144] like Figure 2 or Figure 4a As shown, in the array substrate 100, the first signal line SL1 can be electrically connected to the corresponding transistor in the pixel circuit 103 through the corresponding conductive hole Via. The second signal line SL2 can be electrically connected to the corresponding transistor in the driving circuit 104 through the corresponding conductive hole Via.

[0145] like Figure 2 or Figure 4a As shown, the lower end of the conductive via Via can be directly electrically connected to the corresponding transistor electrode. In other methods, the lower end of the conductive via Via can also be electrically connected to the transistor electrode through a trace in the conductive layer containing the transistor electrode. For example... Figure 2 or Figure 4a As shown, the upper end of the via (Via) is directly electrically connected to the signal line. In other methods, the upper end of the via (Via) can also be electrically connected to the signal line through a trace on the conductive layer containing the signal line.

[0146] As can be seen from the description, in the embodiments of this application, such as Figure 2 As shown, the first signal line SL1 and the second signal line SL2 can be stacked along the third direction Z, and the two film layers are isolated by the first isolation layer 105 in the third direction Z; or as shown Figure 3 and Figure 4a As shown, the first signal line SL1 and the second signal line SL2 can be coplanar in a direction parallel to the panel plane, and are isolated from each other by a first isolation layer 105 that is coplanar.

[0147] refer to Figure 4b , Figure 4b This is a schematic diagram of an array substrate with a first isolation layer isolating a first signal line and a second signal line, as provided in an embodiment of this application. In this configuration, the first signal line SL1 and the second signal line SL2 are located in different film layers. The first signal line SL1 and the second signal line SL2 are arranged in parallel and have a lateral spacing in the third direction Z. The first isolation layer 105 is located between this lateral spacing, and the first isolation layer 105 and the first signal line SL1 are located in the same metal layer.

[0148] Such as combination Figure 1 and Figure 4b As shown, the first signal line SL1 can be located in the second metal layer MT2, and the second signal line SL2 can be located in the third metal layer MT3.

[0149] exist Figure 4b Based on the method shown, in other methods, the first isolation layer 105 may also be on the same layer as the second signal line SL2 and located within the lateral spacing between the first signal line SL1 and the second signal line SL2; or, the first isolation layer 105 may be located within the lateral spacing between the first signal line SL1 and the second signal line SL2, and the film layer on which the first isolation layer 105 is located may be located between the film layer on which the first signal line SL1 is located and the film layer on which the second signal line SL2 is located.

[0150] In this embodiment, the film material of the first signal line SL1 and the film material of the second signal line SL2 can be the same or different. When the film layers of the first signal line SL1 and the second signal line SL2 are coplanar, the two film layers can be prepared separately using different processes, or they can be prepared simultaneously by the same process and located on different regions of the same insulating layer 106.

[0151] The second signal is a periodic signal, which has multiple level switching during the working cycle of the pixel circuit 103. The level switching of the second signal line will interfere with the first signal, causing fluctuations in the first signal, thereby affecting the stability and reliability of the pixel circuit 103.

[0152] The number of level transitions of the first voltage signal within a set time period is less than the number of level transitions of the second signal. This set time period can be one operating cycle of the pixel circuit 103, or a fixed duration, such as 1 second, 0.10 seconds, or 0.01 seconds. For example, the first voltage signal can be a fixed voltage signal, which will not undergo level transitions, equivalent to its level transition count being 0 within the set time period. Alternatively, within the set time period, the number of level transitions of the first voltage signal is greater than 0 and less than the number of level transitions of the second signal.

[0153] In this embodiment, compared to the first signal, the first voltage signal has fewer level switching times within a set time period. This allows for better reduction of interference between the second signal transmitted on the second signal line SL2 and the first signal transmitted on the first signal line SL1 through the first isolation layer 105. Specifically, for the same signal, the rising edge and falling edge each correspond to one level switching time.

[0154] refer to Figure 5 and Figure 6 , Figure 5This is a schematic diagram illustrating the layout of a first isolation layer, a first signal line, and a second signal line in an array substrate according to an embodiment of this application. Figure 6 for Figure 5 The diagram shows a cross-sectional view of the array substrate along the B-B' direction. Based on other embodiments, Figure 5 and Figure 6 In the array substrate 100 shown, along the third direction Z, the first signal line SL1 and the second signal line SL2 are respectively disposed on both sides of the first isolation layer 105.

[0155] like Figure 5 and Figure 6 As shown, the first isolation layer 105 includes an integral conductive region 107, which transmits a first voltage signal. In a direction perpendicular to the panel plane (i.e., the third direction Z), the first isolation layer 105 is located between a first signal line SL1 and a second signal line SL2, and at least one of the first signal line SL1 and the second signal line SL2 overlaps with the conductive region 107. When the first signal line SL1 and the conductive region 107 overlap in the third direction Z, their vertical projections onto the plane of the array substrate 100 at least partially overlap. When the second signal line SL2 and the conductive region 107 overlap in the third direction Z, their vertical projections onto the panel plane at least partially overlap.

[0156] When the first voltage signal is input, the conductive region 107 of the integrated structure is in a state of approximately equal potential, avoiding voltage differences at different locations of the conductive region 107 at the same time, which would affect the electromagnetic shielding effect. For large-area conductive regions, in order to avoid uneven voltage distribution caused by their own voltage drop affecting the electromagnetic shielding effect, the first voltage signal can be input at multiple different locations of the conductive region 107 to reduce the voltage drop at different locations of the conductive region 107 and improve the voltage uniformity of different areas of the conductive region 107.

[0157] In order to better shield the interference of the second signal transmitted by the second signal line SL2 on the first signal line SL1 through the first isolation layer 105, such as Figure 5 and Figure 6 As shown, both the first signal line SL1 and the second signal line SL2 overlap with the conductive region 107 in the third direction Z. In other configurations, one of the first signal line SL1 and the second signal line SL2 may overlap with the conductive region 107 in the third direction Z, while the other may not overlap with the conductive region 107 in the third direction Z.

[0158] When the first signal line SL1 overlaps with the conductive region 107 in the third direction Z, preferably, within the display area of ​​the display panel, the first signal line SL1 can completely overlap with the conductive region 107, that is, the vertical projection of the first signal line SL1 onto the panel plane is completely within the vertical projection of the conductive region 107 onto the panel plane. In this manner, within the display area, the conductive region 107 can completely block the first signal line SL1, thereby minimizing the interference of the second signal on the first signal.

[0159] In other ways, within the display area, the first signal line SL1 may also overlap with the conductive area 107 in the third direction Z, that is, the portion of the first signal line SL1 projected vertically onto the panel plane is located within the vertical projection of the conductive area 107 onto the panel plane.

[0160] When the second signal line SL2 overlaps with the conductive region 107 in the third direction Z, preferably, within the display area of ​​the display panel, the second signal line SL2 can completely overlap with the conductive region 107, that is, the vertical projection of the second signal line SL2 onto the panel plane is completely within the vertical projection of the conductive region 107 onto the panel plane. In this manner, within the display area, the conductive region 107 can completely block the second signal line SL2, thereby minimizing the interference of the second signal on the first signal.

[0161] In other methods, within the display area, the second signal line SL can also overlap with the conductive area 107 in the third direction Z, that is, the portion of the second signal line SL projected vertically onto the panel plane is located within the vertical projection of the conductive area 107 onto the panel plane.

[0162] In this embodiment of the application, when the film layer of the first signal line SL1 and the film layer of the second signal line SL2 are stacked in the third direction Z, it is possible to Figure 2 or Figure 6 As shown, the first signal line SL1 is positioned on the side of the first isolation layer 105 facing the pixel circuit 103, and the second signal line SL2 is positioned on the side of the first isolation layer 105 away from the pixel circuit 103. Alternatively, the second signal line SL2 can be positioned on the side of the first isolation layer 105 facing the pixel circuit 103, and the first signal line SL1 can be positioned on the side of the first isolation layer 105 away from the pixel circuit 103.

[0163] refer to Figure 7 and Figure 8 , Figure 7 This is a schematic diagram illustrating another layout of the first isolation layer, the first signal line, and the second signal line in an array substrate provided in an embodiment of this application. Figure 8 for Figure 7 The diagram shows a cross-sectional view of the array substrate along the C-C' direction. Based on other embodiments, Figure 7 and Figure 8 In the array substrate 100 shown, the conductive region 107 has a plurality of mesh holes 108; in the third direction Z, at least some of the mesh holes 108 do not overlap with the first signal line SL1; and / or, at least some of the mesh holes 108 do not overlap with the second signal line SL2. The mesh holes 108 penetrate the conductive region 107.

[0164] The mesh 108 is used for venting the insulating layer 106 of the organic material below the conductive region 107, and / or for insulating the conductive hole Via that passes through the signal line electrically connecting the conductive region 107 above the conductive region 107 and the circuit below the conductive region 107. The side below the conductive region 107 faces the pixel circuit 103 and the driving circuit 104, while the side above the conductive region 107 faces away from the pixel circuit 103 and the driving circuit 104.

[0165] The insulating layers 106 between the metal layers in the array substrate 100 are sometimes made of organic materials and sometimes of inorganic materials. For organic insulating layers 106, gases may volatilize during some high-temperature processes in the array substrate 100. The integral conductive region 107 has a large coverage area; if the gas between the conductive region 107 and the adjacent organic insulating layer 106 below cannot be discharged in time, the accumulated gas can cause film peeling between the conductive region 107 and the adjacent organic insulating layer 106 below, and may even cause the conductive region 107 to crack. In this embodiment, by providing through-holes 108 in the conductive region 107, the gas between the conductive region 107 and the adjacent organic insulating layer 106 below can be discharged in time, avoiding film peeling and cracking of the conductive region 107.

[0166] In the array substrate 100, the pixel circuit 103 and the driving circuit 104 are located below the conductive region 107. One of the first signal line SL1 and the second signal line SL2 is located above the conductive region 107, and the other is located below it. Therefore, for the first signal line SL1 and the second signal line SL2, the one located above the conductive region 107 needs to be electrically connected to the circuit below through a conductive via Via. If the second signal line SL2 is located above the conductive region 107, then the second signal line SL2 needs to be electrically connected to the driving circuit 104 below the conductive region 107 through a corresponding conductive via Via. In this case, if the corresponding conductive via Via is opposite to the overlapping portion of the second signal line SL2 and the conductive region 107, the corresponding conductive via Via needs to be insulated through a corresponding mesh 108 to achieve the electrical connection between the upper signal line and the lower circuit. If the first signal line SL1 is located above the conductive area, the first signal line SL1 needs to be electrically connected to the pixel circuit 103 below the conductive area 107 through the corresponding conductive hole Via. At this time, if the corresponding conductive hole Via is opposite to the overlapping part of the first signal line SL1 and the conductive area 107, the corresponding conductive hole Via needs to be insulated through a corresponding mesh 108 to realize the electrical connection between the upper signal line and the lower circuit.

[0167] When a mesh 108 is provided on a large conductive area 107 for venting and / or insulation through the conductive hole, the mesh 108 becomes an electric field leakage area in the conductive area 107. The electric field generated by the second signal transmitted in the second signal line SL2 will leak through the mesh 108 to the other side of the conductive area 107, thereby interfering with the first signal in the first signal line SL1.

[0168] like Figure 7 As shown, in the array substrate 100, at least some mesh holes 108 are provided that do not overlap with the first signal line SL1. The electric field leaked by the at least some mesh holes 108 cannot perpendicularly interfere with the first signal line SL1, thereby reducing the degree of interference of the electric field leaked by the part of the mesh holes 108 on the first signal transmitted in the first signal line SL1.

[0169] like Figure 7 As shown, in the array substrate 100, at least a portion of the mesh 108 is provided so that it does not overlap with the second signal line SL2. The electric field generated by the transmission of the second signal in the second signal line SL2 cannot leak directly to the other side of the conductive region 108 through the at least a portion of the mesh 108. This can reduce the extent to which the electric field generated by the transmission of the second signal in the second signal line SL2 leaks to the other side of the conductive region 107 through the at least a portion of the mesh 108, or prevent the electric field from leaking to the other side of the conductive region 107 through the at least a portion of the mesh 108, thereby reducing or avoiding the degree of interference to the first signal transmitted in the first signal line SL1 due to electric field leakage.

[0170] If the first signal line SL1 is located above the conductive region 107, the conductive aperture Via connecting the first signal line SL1 and the pixel circuit 103 can be positioned outside the overlapping portion of the first signal line SL1 and the conductive region 107. This allows the conductive aperture Via to electrically connect the first signal line SL1 and the pixel circuit 103 outside the overlapping portion, without requiring insulation through the mesh 108. This ensures that all meshes 108 do not overlap with the first signal line SL1, minimizing the interference of the electric field leaked from the mesh 108 on the first signal line SL1. Alternatively, the conductive aperture Via connecting the first signal line SL1 and the pixel circuit 103 can be located within the overlapping portion of the first signal line SL1 and the conductive region 107. In this case, only the mesh 108 passing through the conductive aperture Via overlaps with the first signal line SL1, while all other meshes 108 do not overlap, minimizing the interference of the first signal line SL1 from the electric field leaked from the vertically opposite meshes 108.

[0171] When the first signal line SL1 is located above the conductive region 107, since the second signal line SL2 and the driving circuit 104 are both located below the conductive region 107, the conductive hole Via connecting the two does not need to be insulated through the mesh Via, regardless of whether it is opposite to the overlapping part between the second signal line SL2 and the driving circuit 104. Therefore, all meshes 108 can be set to not overlap with the second signal line SL2, thereby minimizing the degree to which the electric field formed by the transmission of the second signal in the second signal line SL2 leaks to the conductive region 107 based on the mesh 108, and minimizing the interference of the electric field leaked by the mesh 108 with the first signal transmitted in the first signal line SL1.

[0172] If the second signal line SL2 is located above the conductive region 107, the conductive hole Via that electrically connects the second signal line SL2 and the driving circuit 104 can be located outside the overlapping portion of the second signal line SL2 and the conductive region 107. In this way, the conductive hole Via can electrically connect the second signal line SL2 and the driving circuit 104 in the area outside the overlapping portion without the need for insulation through the mesh 108. This ensures that all meshes 108 do not overlap with the second signal line SL2, which can minimize the leakage of the electric field formed by the second signal to the lower part of the conductive region through the mesh 108, thereby minimizing the interference of the electric field leaked by the mesh 108 with the first signal line SL1. Alternatively, the conductive hole Via that electrically connects the second signal line SL2 to the drive circuit 104 is located within the overlapping portion of the second signal line SL2 and the conductive region 107. In this case, only the mesh for passing through the conductive hole Via overlaps with the second signal line SL1, while all other meshes 108 do not overlap with the second signal line SL2, so as to minimize the leakage of the electric field formed by the second signal through the meshes 108 to the bottom of the conductive region.

[0173] When the second signal line SL2 is located above the conductive region 107, since the first signal line SL1 and the pixel circuit 103 are both located below the conductive region 107, the conductive hole Via connecting the two does not need to be insulated through the mesh Via, regardless of whether it is opposite to the overlapping part between the first signal line SL1 and the pixel circuit 103. Therefore, all meshes 108 can be set to not overlap with the first signal line SL1, thereby completely avoiding interference from the electric field leaked by the vertically opposite mesh 108 on the first signal line SL1, and minimizing the interference of the electric field leaked by the mesh 108 on the first signal line SL1.

[0174] refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of an array substrate in another display panel provided in this application embodiment. Based on other embodiments, Figure 9 In the array substrate shown, the pixel circuit 103 includes a plurality of transistors 102 located in the first circuit region 109; in the third direction Z, the first circuit region 109 overlaps with the conductive region 107, but does not overlap with the first signal line SL1 and the second signal line SL2; in the first direction X, there is a gap region 110 between two adjacent first circuit regions 109; the first signal line SL1 and the second signal line SL2 both extend along the second direction Y; the second direction Y intersects the first direction X and is parallel to the panel plane; in the third direction Z, the portion of the conductive region 107 opposite to the gap region 110 has a mesh 108; and within this portion, the first signal line SL1 and / or the second signal line SL2 do not overlap with the mesh 108.

[0175] exist Figure 9 In the configuration shown, the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are stacked along the third direction Z layer. Figure 9 The illustration uses an example where the first signal line SL1 is located below the conductive region 107 and the second signal line SL2 is located above the conductive region 107. Obviously, it is also possible to configure the second signal line SL2 to be above the conductive region 107 and the first signal line SL1 to be below the conductive region 107.

[0176] When the film layer containing the first signal line SL1 and the film layer containing the second signal line SL2 are stacked along the third direction Z layer, it can be as follows: Figure 9 As shown, the first signal line SL1 and the second signal line SL2 do not overlap in the third direction Z, and they are spaced apart in the lateral direction. In other configurations, they can be configured to overlap at least partially in the third direction Z.

[0177] On the third direction Z, the first circuit region 109 and the conductive region 107 have an overlapping portion, which can be as follows: Figure 9 As shown, the entire first circuit region 109 overlaps with the conductive region 107. At this time, all transistors 102 of the pixel circuit 103 in the first circuit region 109 are blocked by the conductive region 107. That is, the vertical projection of all transistors 102 of the pixel circuit 103 on the panel plane is located within the vertical projection of the conductive region 107 on the panel plane.

[0178] In other ways, on the third direction Z, the first circuit region 109 and the conductive region 107 may have an overlapping portion, which means that a part of the first circuit region 109 overlaps with the conductive region 107. In this case, within the first circuit region 109, a part of the transistors 102 of the pixel circuit 103 is blocked by the conductive region 107. That is, the vertical projection of the part of the transistors 102 of the pixel circuit 103 on the panel plane is located within the vertical projection of the conductive region 107 on the panel plane.

[0179] In this embodiment, since the first circuit region 109 and the conductive region 107 have an overlapping portion, the first circuit region 109 can be electromagnetically shielded by the conductive region 107 in the overlapping portion to avoid electromagnetic interference from the signal transmitted in the signal line above the conductive region 107.

[0180] exist Figure 9 In the illustrated configuration, within the portion of the conductive region 107 opposite to the gap region 110, both the first signal line SL1 and the second signal line SL2 do not overlap with the mesh 108, thereby minimizing the interference of the second signal on the first signal. In other configurations, one of the signal lines SL1 and SL2 may also be configured not to overlap with the mesh 108.

[0181] like Figure 9As shown, in the portion of the conductive region 107 opposite to the gap region 110, all mesh holes 108 within this portion can be configured to not overlap with the first signal line SL1. In other configurations, depending on the drilling conditions of the process space, some mesh holes 108 can be configured to not overlap with the first signal line SL1, while some mesh holes 108 can overlap with the first signal line SL1.

[0182] like Figure 9 As shown, in the portion of conductive region 107 opposite to gap region 110, all mesh holes 108 within this portion can be configured to not overlap with the second signal line SL2. This portion can correspond to a defined pixel region range within which all mesh holes 108 do not overlap with the second signal line SL2. This defined pixel region range can include at least a 2×2 pixel circuit group, or for example, it can be... Figure 9 The diagram shows a 4×2 pixel band group. In other methods, depending on the hole-cutting conditions of the process space, some meshes 108 may not overlap with the second signal line SL2, while some meshes 108 may overlap with the second signal line SL2.

[0183] refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 10 In the array substrate 100 shown, the conductive region 107 is electrically connected to the pixel circuit 103 to transmit a first voltage signal to the pixel circuit 103.

[0184] exist Figure 10 In the illustrated configuration, the pixel circuit 103 includes multiple transistors 102. A first signal line SL1 is electrically connected to one of the transistors 102 in the pixel circuit 103 to transmit a first signal to that transistor 102. A conductive region 107 is electrically connected to another transistor 102 in the pixel circuit 103 to transmit a first voltage signal to that transistor 102. In this configuration, the first voltage signal is an operating voltage of the pixel circuit 103. The conductive region 102 serves not only as a shielding structure between the first signal line SL1 and the second signal line SL2, but also as a means of transmitting the first voltage signal to the pixel circuit 103.

[0185] refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 11 In the array substrate 100 shown, the conductive region 107 is electrically connected to the driving circuit 104 to transmit a first voltage signal to the driving circuit 104.

[0186] exist Figure 11In the illustrated configuration, the driving circuit 104 includes multiple transistors 102. A second signal line SL2 is electrically connected to one of the transistors 102 in the driving circuit 104 to transmit a second signal to that transistor 102. A conductive region 107 is electrically connected to another transistor 102 in the driving circuit 104 to transmit a first voltage signal to that transistor 102. In this configuration, the first voltage signal is an operating voltage of the driving circuit 104. The conductive region 102 serves not only as a shielding structure between the first signal line SL1 and the second signal line SL2, but also as a means of transmitting the first voltage signal to the driving circuit 104.

[0187] like Figure 10 The first voltage signal can be the operating voltage of the pixel circuit 103, and the conductive area 107 is equivalent to the signal line connected to the pixel circuit 103, or as... Figure 11 As shown, the first voltage signal is the operating voltage of the driving circuit 104, and the conductive region 107 is equivalent to the signal line connected to the driving circuit 104. At this time, the conductive region 107, the first signal line SL1, and the second signal line SL2 can be fabricated based on the three metal layers already present in the array substrate 100, without the need to add additional metal layers.

[0188] like Figure 10 or Figure 11 As shown, the conductive region 107 can be electrically connected to one of the pixel circuit 103 and the driving circuit 104, and is insulated from the other. In this case, the first voltage signal input to the conductive region 107 can be an operating voltage of either the pixel circuit 103 or the driving circuit 104, and can also be used for electromagnetic isolation between the first signal line SL1 and the second signal line SL2. In this configuration, the integrally structured conductive region 107 has a large area, significantly reducing the transmission line impedance of the first voltage signal compared to conventional routing schemes that provide the first voltage signal to the pixel circuit 103 or the driving circuit 104.

[0189] refer to Figure 12 and Figure 13 , Figure 12 This is a schematic diagram of the pixel circuit in a display panel provided in an embodiment of this application. Figure 13 for Figure 12 The diagram shows the circuit layout of the pixel circuit. The pixel circuit 103 shown includes a pulse width modulation unit 11 and an amplitude modulation unit 12. The pulse width modulation unit 11 includes transistors M1 to M6 and a capacitor C1. The amplitude modulation unit 12 includes a driver transistor M0, transistors M7 to M12, and a capacitor C2.

[0190] In the pulse width modulation unit 11, the first terminal of transistor M6 is electrically connected to the second reference voltage line Vref2, and the second terminal of transistor M6 is electrically connected to the gate of transistor M2, the first terminal of transistor M4, and the second terminal of capacitor C1. The gate of transistor M6 is electrically connected to the first pulse width scan control signal line PWMS1. The first terminal of capacitor C1 is electrically connected to the pulse width control voltage line Sweep. The pulse width control voltage line Sweep is used to transmit a linearly decreasing voltage. The first terminal of transistor M2 is electrically connected to the second terminals of transistors M3 and M5, and the second terminal of transistor M2 is electrically connected to the second terminal of transistor M4 and the first terminal of transistor M1. The first terminal of transistor M3 is electrically connected to the first data voltage line D1, and the gate of transistor M3 is electrically connected to the second pulse width scan control signal line PWMS2. The first terminal of transistor M5 is electrically connected to the turn-off voltage line Voff, and the gate of transistor M5 is electrically connected to the first light emission control signal line PWMK1. The second terminal of transistor M1 is electrically connected to the gate of driving transistor M0 in amplitude modulation unit 12, and the gate of transistor M1 is electrically connected to the first light emission control signal line PWMK1.

[0191] Specifically, the first pulse width scan control signal line PWMS1 inputs the first pulse width scan control signal; the second pulse width scan control signal line PWMS2 inputs the second pulse width scan control signal; the pulse width control voltage line Sweep inputs the pulse width control voltage; the second reference voltage line Vref2 inputs the second reference voltage; the first light emission control signal line PWMK1 inputs the first light emission control signal; the turn-off voltage line Voff inputs the turn-off voltage; and the first data voltage line D1 inputs the first data voltage.

[0192] In amplitude modulation unit 12, the first terminal of transistor M7 is electrically connected to the first reference voltage line Vref1, and the second terminal of transistor M7 is electrically connected to the gate of driving transistor M0, the second terminal of transistor M8, and the second terminal of capacitor C2. The gate of transistor M7 is electrically connected to the first amplitude scan control signal line PAMS1. The first terminal of transistor M8 is electrically connected to the second terminal of driving transistor M0, and the gate of transistor M8 is electrically connected to the second amplitude scan control signal line PAMS2. The first terminal of capacitor C2 is electrically connected to the first power supply voltage line PVDD. The first terminal of transistor M9 is electrically connected to the second data voltage line D2, the second terminal of transistor M9 is electrically connected to the first terminal of driving transistor M0, and the gate of transistor M9 is electrically connected to the second amplitude scan control signal line PAMS2. The first terminal of transistor M10 is electrically connected to the first power supply voltage line PVDD, the second terminal of transistor M10 is electrically connected to the first terminal of driving transistor M0, and the gate of transistor M10 is electrically connected to the second light emission control signal line PAMK2. The first terminal of transistor M11 is electrically connected to the second terminal of driving transistor M0, the second terminal of transistor M11 is electrically connected to the anode of light-emitting element 30, and the gate of transistor M11 is electrically connected to the second light-emitting control signal line PAMK2. The first terminal of transistor M12 is electrically connected to the first reference voltage line Vref1, the second terminal of transistor M12 is electrically connected to the anode of light-emitting element 30, and the gate of transistor M12 is electrically connected to the second amplitude scanning control signal line PAMS2.

[0193] The cathode of the light-emitting element 30 is connected to the second power supply voltage line PVEE. The first power supply voltage line PVDD receives the first power supply voltage (positive voltage); the second power supply voltage line PVEE receives the second power supply voltage (negative voltage); the first amplitude scan control signal line PAMS1 receives the first amplitude scan control signal; the second amplitude scan control signal line PAMS2 receives the second amplitude scan control signal; the first reference voltage line Vref1 receives the first reference voltage; the second light emission control signal line PAMK2 receives the second light emission control signal; and the second data voltage line D2 receives the second data voltage.

[0194] In this embodiment, one of the first and second terminals of the transistor is the source, and the other is the drain. Optionally, transistors M4, M6, M7, and M8 can be dual-gate transistors to improve the transistor response speed and enhance the performance of the pixel circuit 103.

[0195] In the pixel circuit 103, all transistors and driving transistors M0 are thin-film transistors (TFTs). Optionally, such as... Figure 12 As shown, each transistor in the pixel circuit 103 can be a PMOS.

[0196] The driving circuit includes a vertical shift register (VSR). The array substrate 100 includes multiple VSR circuit groups, each containing multiple cascaded VSRs. Within the same VSR circuit group, the output signal of the preceding VSR serves as the input signal for the following VSR. The input signal of the first-stage VSR is a set start signal. The output of the VSR is connected to the scan trace, providing control signals to the gates of the corresponding transistors 102 in the pixel circuit 103. For example, for the first pulse width scan control signal, the array substrate sequentially provides the first pulse width scan control signal to each row of pixel circuits 102 through a VSR circuit group. The gate of transistor M6 in the same row of pixel circuits 103 is connected to the output of the same-stage VSR in that VSR circuit group, and the gates of transistor M6 in pixel circuits 103 of different rows are connected to the outputs of different-stage VSRs in that VSR circuit group. The VSR circuit structure can be as follows: Figure 14 As shown.

[0197] refer to Figure 14 , Figure 14 This is a schematic diagram of a shift register provided in an embodiment of this application. The driving circuit 104 shown is a 10T3C structure, including transistors T1 to T10 and capacitors C3 to C5.

[0198] The first terminal of transistor T1 is electrically connected to the high-level signal line VGH, the first terminal of capacitor C3, the first terminal of transistor T3, and the first terminal of transistor T7. The second terminal of transistor T1 is electrically connected to the output terminal OUT and the first terminal of transistor T2. The gate of transistor T1 is electrically connected to the second terminals of capacitor C3, transistor T3, and transistor T4. The second terminal of transistor T2 is electrically connected to the low-level signal line VGL. The gate of transistor T2 is electrically connected to the second terminal of capacitor C4, the gate of transistor T3, the gate of transistor T6, the second terminal of transistor T8, and the first terminal of transistor T9. The first terminal of transistor T4 is electrically connected to the second terminal of capacitor C5 and the first terminal of transistor T5. The gate of transistor T4 is electrically connected to the first terminal of capacitor C4, the second terminal of transistor T5, and the first clock signal line XCK. The gate of transistor T5 is electrically connected to the first terminal of capacitor C5, the first terminal of transistor T6, the gate of transistor T7, and the first terminal of transistor T10. The second terminal of transistor T6 is electrically connected to the second clock signal line CK, the gate of transistor T9, and the gate of transistor T10. The second terminal of transistor T7 is electrically connected to the first terminal of transistor T8. The gate of transistor T8 is electrically connected to the first clock signal line XCK. The second terminal of transistor T9 is electrically connected to the input signal line IN. The second terminal of transistor T10 is electrically connected to the low-level signal line VGL.

[0199] In this configuration, if the VSR is the first stage, its input signal line IN is the start signal line STV. If the VSR is not the first stage, its input signal line IN is connected to the output terminal OUT of the previous stage VSR. The start signal line STV receives the start signal. The first clock signal line XCK receives the first clock signal; the second clock signal line CK receives the second clock signal; the high-level signal line VGH receives a high-level signal; and the low-level signal line VGL receives a low-level signal.

[0200] In the driving circuit 104, each transistor is a thin-film transistor (TFT). Optionally, such as... Figure 13 As shown, each transistor in the driving circuit 104 can be a PMOS.

[0201] It should be noted that, in the embodiments of this application, Figure 12 and Figure 13 This application only provides one implementation of the pixel circuit 103 and the VSR. The pixel circuit 103 and the VSR can also adopt other circuit structures. This application does not limit the specific circuit structure of the two.

[0202] like Figure 12 As shown, the pixel circuit 103 receives at least a first power supply voltage, a second power supply voltage, and a reference voltage (including the aforementioned first and second reference voltages); as Figure 14 As shown, the driving circuit 104 receives at least a start voltage signal, a high-level signal, and a low-level signal. In some embodiments of this application, the first voltage signal is any one of a first power supply voltage, a second power supply voltage, a reference voltage, a start voltage signal, a high-level signal, and a low-level signal. The first voltage signal, including the first power supply voltage, the second power supply voltage, the reference voltage, the start voltage signal, the high-level signal, and the low-level signal, are all DC constant voltage signals. During the operating cycle of the pixel circuit 103, these signals do not undergo level switching and can be multiplexed as the first voltage signal input to the first isolation layer 105. Reliable electromagnetic isolation between the first signal line SL1 and the second signal line SL2 can be achieved without adding an additional voltage signal.

[0203] Preferably, the first voltage signal is a first power supply voltage. As described above, the conductive area 107 of the large-area integrated structure has low impedance, which can effectively reduce the impedance of the line where the first voltage signal is located, thereby increasing the current. When the first voltage signal is the first power supply voltage, the first power supply voltage is the power supply voltage used for light emission control in the pixel circuit. Lower impedance can achieve a larger current, which can improve the display brightness of the light-emitting element 30. Therefore, this solution can reduce the operating voltage at the same display brightness, thereby reducing power consumption, or it can increase the display brightness at the same operating voltage.

[0204] In other embodiments, the first isolation layer 105 is insulated from both the pixel circuit 103 and the driving circuit 104. In this approach, it is not necessary to reuse the input signals of the pixel circuit 103 and the driving circuit 104; a separate voltage signal can be used as the first voltage signal, such as a device ground signal. In this approach, the first isolation layer 105 can be fabricated using an existing metal layer in the display panel, or by adding an additional metal layer.

[0205] like Figure 12 As shown, the pixel circuit 103 receives at least a data voltage signal, which includes either the first data voltage or the second data voltage described above; the driving circuit 104 receives at least a clock signal, which includes either the first clock signal or the second clock signal described above. In some embodiments of this application, the first signal is a data voltage signal and the second signal is a clock signal.

[0206] Among the multiple signals input to the pixel circuit 103, the voltage stability of the data voltage has a significant impact on image display quality. In the driving circuit 104, the clock signal is a high-frequency switching square wave signal with a high level switching frequency, which can easily interfere with other signals. In this embodiment, the first signal includes a data voltage signal, and the second signal includes a clock signal, which can effectively reduce the interference of the high-frequency clock signal input to the driving circuit 104 on the data voltage input to the pixel circuit 103.

[0207] The first data voltage relies on pulse timing and duty cycle to carry grayscale information. It has a higher signal switching frequency and steeper edge jumps, making it extremely sensitive to alternating electric field coupling interference generated by the high-frequency clock input to the VSR in the low-drive circuit 104. The second data voltage, on the other hand, relies on voltage amplitude modulation and has stronger anti-interference capabilities compared to the first data voltage. Therefore, in some embodiments of this application, the first signal is preferentially set as the first data voltage.

[0208] refer to Figures 15-17 , Figure 15 This is a schematic diagram of the structure of an array substrate in a display panel provided in an embodiment of this application. Figure 16 for Figure 15 The cross-sectional view of the array substrate along the D-D' direction is shown. Figure 17 for Figure 16 The diagram shows a cross-sectional view of the display panel along the E-E' direction.

[0209] Based on other implementation methods Figures 15-17In the array substrate 100 shown, the pixel circuit 103 includes a plurality of transistors 102, and the plurality of transistors 102 in the pixel circuit 103 are located in the first circuit region 109; the driving circuit 104 includes a plurality of transistors 102, and the plurality of transistors 102 in the driving circuit 104 are located in the second circuit region 112. The first circuit region 109 can be determined based on the active layer ACL of all transistors 102 in the pixel circuit 103. For example, the opposite two edges of the first circuit region 109 in the first direction X can be... Figure 13 The left and right edges of the active layer ACL in the circuit board layout shown, and the opposite sides of the first circuit region 109 in the second direction Y can be Figure 13 The circuit board layout shown shows the top and bottom edges of the active layer ACL.

[0210] Similarly, the second circuit region 112 can be identified based on the active layer ACL of all transistors 102 in the VSR circuit board layout. The two opposite edges of the second circuit region 112 in the first direction X can be the left and right edges of the active layer ACL in the VSR circuit board layout, and the two opposite edges of the second circuit region 112 in the second direction Y can be the upper and lower edges of the active layer ACL in the VSR circuit board layout.

[0211] In some embodiments, on the third direction Z, the first circuit region 109 and the conductive region 107 have an overlapping portion, so that the conductive region 107 at least blocks a portion of the transistors and connected lines of the pixel circuit 103 to prevent interference from signals transmitted in the signal lines above the conductive region 107 to the transistors and connected lines. A portion of the first circuit region 109 may overlap with the conductive region 107, with the conductive region 107 blocking a portion of the first circuit region 109 and exposing another portion of the first circuit region 109; or as... Figure 15 As shown, the entire first circuit region 109 overlaps with the conductive region 107, and the conductive region 107 completely blocks the first circuit region 109.

[0212] In some embodiments, on the third direction Z, the second circuit region 112 overlaps with the conductive region 107 to at least shield a portion of the transistors and connected lines of the drive circuit 104 through the conductive region 107, thereby preventing interference from signals transmitted in the signal lines above the conductive region 107 to these transistors and connected lines. A portion of the second circuit region 112 may overlap with the conductive region 107, with the conductive region 107 shielding a portion of the second circuit region 112 and exposing another portion of the second circuit region 112; or as... Figure 15 As shown, the second circuit region 112 overlaps entirely with the conductive region 107, and the conductive region 107 completely blocks the second circuit region 112.

[0213] like Figure 15As shown, the conductive region 107 has multiple mesh openings 108; as Figure 16 As shown, pixel circuit 103 and driving circuit 104 are located on the same side of first isolation layer 105; the other side of first isolation layer 105 has a first connection line 111, which is insulated through conductive region 107 based on mesh 108, to be electrically connected to one of pixel circuit 103 and driving circuit 104, and insulated from the other. Figures 15-17 In the illustrated configuration, the first connection line 111 is electrically connected to the pixel circuit 103. The first connection line 111 can be electrically connected to the transistor 102 in the pixel circuit 103 below the conductive region 107 via the corresponding mesh 108. In other configurations, the first connection line 111 can be electrically connected to the driving circuit 105.

[0214] The array substrate 100 includes an active layer ACL, a first metal layer MT1, a capacitor metal layer MTc, a second metal layer MT2, a third metal layer MT3, a fourth metal layer MT4, and a fifth metal layer MT5, which are stacked sequentially along the third direction Z. The transistor 102 is located on the first metal layer MT1, with its source and drain located on the second metal layer MT2, and its channel located on the active layer ACL.

[0215] like Figure 17 As shown, the first isolation layer 105 is located on the third metal layer MT3. The first signal line SL1 is located below the conductive region 107, such as on the second metal layer MT2; the second signal line SL2 is located above the conductive region 107, such as on the fourth metal layer MT4. In other configurations, the second signal line SL2 may be located on the second metal layer MT2, and the first signal line SL1 may be located on the fourth metal layer MT4.

[0216] In this embodiment of the application, if the wiring in the panel needs to place the first connecting line 111, which is electrically connected to the pixel circuit 103 or the driving circuit 104, above the conductive area 107, the circuit interconnection can be achieved through the mesh in the conductive area 107, so that the first connecting line 111 above the conductive area 107 is electrically connected to the pixel circuit 103 or the driving circuit 104 below.

[0217] In one embodiment of this application, such as Figure 15 and Figure 16 As shown, the plurality of meshes 108 in the conductive region 107 include a first through-hole TH1, and a first connecting line 111 passes through the conductive region 107 through the first through-hole TH1 with insulation, so as to be electrically connected to the pixel circuit 103 or the driving circuit below.

[0218] In one embodiment, the first via TH1 has a transition block 113 insulated from the conductive region 107; the first connecting line 111 is electrically connected to one of the pixel circuit 103 and the driving circuit 104 through the transition block 113. Optionally, the transition block 113 may be located on the same metal layer as the conductive region 107. In this embodiment, the first connecting line 111 located above the conductive region 107 can be electrically connected to the transition block 113 through a conductive via Via, and the transition block 113 is then electrically connected to the corresponding circuit below through a conductive via Via. The electrical connection between the first connecting line 111 and the circuit below is achieved through two separately formed conductive vias Via, which avoids the direct electrical connection between the first connecting line 111 and the circuit below through a conductive via Via of considerable depth, thereby reducing the fabrication difficulty of the conductive via Via.

[0219] In other methods, the first connecting line 111 and the circuit below can be directly and vertically electrically connected through an integrated conductive hole Via.

[0220] The first through hole TH1 is a transition hole, which can be used not only for venting the organic material film layer below the conductive area 107, but also for insulating the electrical connection structure between the first connecting line 111 and the circuit below. The electrical connection structure includes an integral conductive hole Via or transition block 113.

[0221] like Figure 15 and Figure 16 As shown, the upper surface of the array substrate 100 has multiple pads (PADs). These pads are used for soldering the light-emitting elements 30. Each pad includes a negative pad soldered to the cathode of the light-emitting element 30 and a positive pad soldered to the anode of the light-emitting element 30. For ease of illustration, Figure 15 The diagram shows the positive electrode pads PADR+ for multiple red light-emitting elements, PADG+ for multiple green light-emitting elements, and PADB+ for multiple blue light-emitting elements. The negative electrode pads for these three types of light-emitting elements are not shown. Figure 16 The image shows the cross-sectional positions corresponding to the positive pad PADR+ and negative pad PADR- of a red light-emitting element.

[0222] like Figure 16 As shown, the pad (PAD) can be located on the fifth metal layer MT5. A sixth metal layer MT6 and a seventh metal layer MT7 can also be sequentially stacked on the fifth metal layer MT5. The seventh metal layer MT7 may include a solder metal layer that is in direct electrical contact with the pad (PAD).

[0223] When the first connecting line 111 is electrically connected to the pixel circuit 104, the first connecting line 111 can be electrically connected to the anode of the light-emitting element, and the first connecting line 111 is electrically connected to the transistor in the pixel circuit 103 through the first through-hole TH1; in this mode, the first connecting line 111 is Figure 12 The anode connection line between the second terminal of transistor M11 and the second terminal of transistor M12 in the pixel circuit 103 shown and the anode of the light-emitting element 30.

[0224] like Figure 16 As shown, the anode flying wire connecting the light-emitting element 30 in the pixel circuit 103 is placed on the side of the conductive region 107 away from the pixel circuit 103. This facilitates the layout of the pixel circuit 103 and the connected pad PAD. For example, it can be arranged as follows: Figure 15 The pixel circuit 103 and the pad PAD are staggered in the second direction Y, which increases the layout flexibility of the pixel circuit 103 and the connected traces in the panel. On the other hand, the anode flying wire and the driving circuit 104 are respectively set on both sides of the conductive area 107, which reduces the interference of the circuit structure in the driving circuit 104 on the signal transmitted in the anode flying wire, so as to ensure the image display stability and reliability of the light-emitting element 30 directly connected to the anode flying wire.

[0225] When the first connection line 111 is electrically connected to the driving circuit 104, the first connection line 111 is electrically connected to the transistor 102 in the driving circuit 104 through the first through-hole TH1. The first connection line 111 and the second signal line SL2 can be any two different from the input signal line IN, the first clock signal line XCK, the second clock signal line CK, the high-level signal line VGH, and the low-level signal line VGL. This method places the driving circuit 104 and the connected first connection line 111 on opposite sides of the conductive area 107, so that the extension path of the first connection line 111 is not limited by the layout constraints of the driving circuit 104 with a large number of transistors 102, increasing the layout flexibility of the driving circuit 104 and the connected traces in the panel.

[0226] refer to Figure 18 , Figure 18 This application provides a schematic diagram of the layout of the active layer and the first via in the conductive region of a transistor in an array substrate. Based on other embodiments, Figure 18 In the illustrated configuration, at least a portion of the first via TH1 does not overlap with the active layer ACL of the transistor 102 in the third direction Z. That is, at least a portion of the vertical projection of the first via TH1 onto the panel plane is located outside the vertical projection of the active layer ACL onto the panel plane in the third direction Z.

[0227] The active layer ACL of transistor 102 includes the channel region of transistor 102. The active layer ACL can be a patterned low-temperature polysilicon layer. Its patterned structure can be designed according to the circuit layout of each transistor 102 in pixel circuit 103. Figure 18This is only a partial schematic diagram of an active layer ACL and does not represent the specific graphical structure of an active layer ACL. The embodiments of this application do not limit the specific graphical structure of an active layer ACL.

[0228] As described above, the mesh 108 leaks an electric field, causing electromagnetic interference to occur in the circuit structures above and below the conductive region 107. Therefore, the electric field generated by the signals transmitted in the first connecting line 111 and other nearby signal lines will leak through the first via TH1, interfering with the channel region of the transistor in the pixel circuit 103 and thus affecting the reliability and stability of the pixel circuit 103. To solve this problem, in this embodiment, in the third direction Z, when at least a portion of the first via TH1 does not overlap with the active layer ACL of the transistor 102, the interference of the leaked electric field of the first via TH1 below the conductive region 107 on the channel region of the transistor 102 in the pixel circuit 103 can be reduced, improving the reliability and stability of the pixel circuit 103 and thus improving the image display quality.

[0229] Figure 18 In this configuration, the first via TH1 completely does not overlap with the active layer ACL of transistor 102. The vertical projection of the first via TH1 onto the panel plane is completely outside the vertical projection of the active layer ACL onto the panel plane, with no overlap between the two. This minimizes the interference of the leakage electric field of the first via TH1 below the conductive region 107 on the channel region of transistor 102 in pixel circuit 103. Alternatively, the first via TH1 may partially overlap with the active layer ACL of transistor 102, with one part of the vertical projection of the first via TH1 onto the panel plane outside the vertical projection of the active layer ACL onto the panel plane, and the other part within the vertical projection of the active layer ACL onto the panel plane.

[0230] refer to Figure 19 , Figure 19 This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 19 In the array substrate 100 shown, multiple mesh holes 108 include second through holes TH2, which are filled with insulating material; in the third direction Z, the second through holes TH2 do not overlap with the first circuit region 109. The insulating material is the material of the insulating layer 106 above the conductive region 107.

[0231] The second through hole TH2 is a non-transfer hole used for venting of the organic material film layer below the conductive area 107. There is no electrical connection structure in the second through hole TH2 that simultaneously connects the upper and lower lines.

[0232] exist Figure 19In the conductive region 107, a first through-hole TH1 and a second through-hole TH2 are simultaneously provided. For ease of illustration, the first through-hole TH1 is depicted as a square hole and the second through-hole TH2 as a round hole. In actual products, the shapes of the first through-hole TH1 and the second through-hole TH2 may be the same or different. Optionally, in the third direction Z, the shape of the mesh 108 includes at least one of the following: circular, elliptical, regular polygon (such as triangle, quadrilateral, and pentagon), and irregular polygon.

[0233] In one approach, such as Figure 19 As shown, the second through-hole TH2 is completely filled with insulating material. This method can completely remove the conductive material inside the second through-hole TH2, facilitating the formation of the second through-hole TH2 in the conductive region 107.

[0234] When the conductive region 107 is provided with a second through hole TH2, it can be as follows: Figure 19 As shown, at least a portion of the second via TH2 is configured not to overlap with the second region 102 in the third direction Z, so as to reduce the interference of the leakage electric field of the at least a portion of the second via TH2 on the transistor 102 and its connected lines in the drive circuit 104.

[0235] refer to Figure 20 , Figure 20 This is a schematic diagram of a layout scheme for a first through-hole and a second through-hole in a conductive region, provided by an embodiment of this application. In this scheme, the second through-hole TH2 has a conductive block 114. Optionally, the conductive block 114 can be located in the same metal layer as the conductive region 107. An insulating gap 115 is provided between the conductive block 114 and the sidewall of the second through-hole TH2, and the insulating gap 115 is filled with insulating material.

[0236] The conductive block 114 can reduce the cutout area of ​​the second through hole TH2, reduce the degree of electric field leakage, and reduce the interference of the electric field formed by the electrical signal on one side of the conductive region 107 to the circuit on the other side of the conductive region 107; the conductive block 114 can also compensate for the cutout area and reduce the reflection difference between the through hole area and the non-through hole area.

[0237] exist Figure 20In the illustrated configuration, a gap can completely surround the conductive block 114 between the conductive block 114 and the sidewall of the second through-hole TH2. In this case, the second through-hole TH2 is insulated from the conductive region 107. In this configuration, the second through-hole TH2 can have the same shape as the first through-hole TH1, and the conductive block 114 can have the same shape as the transition block 113. The difference between the first through-hole TH1 and its internal transition block 113 and the second through-hole TH2 and its internal conductive block 114 is that the conductive block 114 within the second through-hole TH2 is not simultaneously connected to the upper and lower lines. Therefore, the first through-hole TH1 and its internal transition block 113 and the second through-hole TH2 and its internal conductive block 114 can be fabricated based on the same process parameters. When shaping the mesh 108 within the conductive region 107, all mesh 108 have the same pattern structure, eliminating the need for differentiated design of the first through-hole TH1 and the second through-hole TH2, thus facilitating the patterned fabrication of the conductive region 107.

[0238] refer to Figure 21 , Figure 21 This is a schematic diagram of another layout scheme for the first and second through holes in the conductive region provided in an embodiment of this application. In this scheme, a local edge of the conductive block 114 is electrically connected to the conductive region 107. The conductive block 114 and the conductive region 107 are an integral structure. In this scheme, the conductive block 114 can also reduce the impedance of the conductive region 107, thereby improving the voltage uniformity of the conductive region 107 in different regions.

[0239] refer to Figure 22 , Figure 22 This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 22 In the array substrate 100 shown, the second via TH2 and the second circuit region 112 have an overlapping portion in the third direction Z.

[0240] like Figure 22As shown, each of the second circuit regions 112 overlaps with at least one second via TH2. In the third direction, at the overlap of the conductive region 107 and the second circuit region 112, the organic insulating layer 106 between the overlapping portions can be vented through the second via TH2 above the second circuit region 112, avoiding problems such as film peeling and breakage of the conductive region 107 caused by the lack of venting vias above the larger second circuit region 112. In addition, compared with the data voltage signal transmitted in the pixel circuit 103, the signal transmission signal in the driving circuit 104 has stronger anti-interference capability, and since the driving circuit 104 is not directly connected to the light-emitting element 103 like the pixel circuit 103, its signal fluctuations have less impact on the image display effect of the light-emitting element 30. Providing the second via TH2 above the second circuit region 112 where the driving circuit 104 is located not only facilitates the venting of the organic insulating layer 106 in this area, but also has less impact on the image display effect.

[0241] refer to Figure 23a , Figure 23a This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 23a In the array substrate 100 shown, the pixel circuit 103 includes multiple transistors located in the first circuit region; the first circuit region overlaps with the conductive region 107. The conductive region 107 has multiple mesh holes, and the multiple mesh holes 108 include a third through hole TH3. The third through hole TH3 is filled with insulating material and is a non-transfer hole for venting. Its implementation can be the same as the second through hole TH2, which will not be described in detail here.

[0242] Combination Figure 12 , Figure 13 and Figure 23a As shown, the pixel circuit 103 includes multiple transistors 102, including a driving transistor M0. The pixel circuit 103 also includes a storage capacitor (i.e., the second capacitor C2 mentioned above). In the third direction Z, the third via TH3 does not overlap with either the driving transistor M0 or the storage capacitor. The vertical projection of the third via TH3 onto the panel plane does not overlap with the vertical projection of the driving transistor M0 onto the panel plane, nor with the vertical projection of the storage capacitor onto the panel plane.

[0243] refer to Figure 23b , Figure 23b for Figure 13The diagram shows the circuit layout of the pixel circuit and the relative position of the third via in the conductive region. In the pixel circuit 103, the driving transistor M0 and the second capacitor C2 are key display control nodes in the amplitude modulation unit 12. To prevent the leakage electric field of the third via TH3 from interfering with the electrode voltage (including gate voltage, source voltage, and drain voltage) of the driving transistor M0 and the plate voltage of the second capacitor C2, the third via TH3 is designed to not overlap with the driving transistor M0 and the storage capacitor. This can improve the voltage stability of the key display control nodes in the amplitude modulation unit 12 and ensure the image display quality.

[0244] Optionally, in the XY plane, the minimum distance between the critical display control node in the pixel circuit 103 and the third via TH3 is greater than a set threshold, including: the minimum distance between the channel region or gate of the driving transistor M0 and the third via TH3 is greater than the set threshold, and / or, the minimum distance between the second capacitor C2 and the third via TH3 is greater than the set threshold, so as to reduce the interference of the leakage electric field of the third via TH3 on the critical display control node in the pixel circuit 103. The larger the set threshold, the weaker the interference of the leakage electric field of the third via TH3 on the critical display control node in the pixel circuit 103. Optionally, the set threshold is not less than 1 μm.

[0245] In some implementations, the first signal line SL1 includes at least one of a first data voltage signal line D1 and a second data voltage signal line D2. For example... Figure 23b As shown, along the third direction Z, the third via TH3 can have no overlap with either the first data voltage signal line D1 or the second data voltage signal line D2, thereby reducing the interference of the leakage electric field of the third via TH3 on the data voltage signal transmitted in the data voltage signal line below. In other configurations, along the third direction Z, the third via TH3 can have no overlap with either the first data voltage signal line D1 or the second data voltage signal line D2.

[0246] Optionally, in the third direction Z, the third via TH3 does not overlap with transistor M2 in the pulse width modulation unit 11. Transistor M2 is equivalent to the driving transistor of the pulse width modulation unit 11 and is a key display control node in the pulse width modulation unit 11. Based on this, when the third via TH3 does not overlap with transistor M2 in the pulse width modulation unit 11, the voltage stability of the key display control node in the pulse width modulation unit 11 can be improved to ensure image display quality. In the XY plane, the minimum distance between the key display control node in the pixel circuit 103 and the third via TH3 is greater than a set threshold, including: the minimum distance between transistor M2 and the third via TH3 is greater than a set threshold.

[0247] Combination Figure 23a and Figure 23bAs shown, a first through-hole TH1, a second through-hole TH2, and a third through-hole TH3 can be simultaneously provided in the conductive region 107. The third through-hole TH3 is provided in the overlapping area of ​​the conductive region 107 and the first circuit region 109. As mentioned above, the distance between the third through-hole TH3 and the key display control node of the pixel circuit 103 is greater than a set threshold. In a direction parallel to the panel plane, this set threshold is not less than the distance between the channel region of the driving transistor M0 in the pixel circuit 103 and the channel regions of other adjacent transistors 102. In some embodiments, the set threshold is not less than the distance in the XY plane between the channel region of the driving transistor M0 or the second capacitor C2 and the first through-hole TH1.

[0248] It should be noted that when the conductive area 107 includes multiple mesh holes 108, the multiple mesh holes 108 can be configured to include any one of the first through hole TH1, the second through hole TH2, and the third through hole TH3, depending on the through hole layout space; or the multiple mesh holes 108 can include any two of the first through hole TH1, the second through hole TH2, and the third through hole TH3; or the multiple mesh holes 108 can simultaneously include the first through hole TH1, the second through hole TH2, and the third through hole TH3.

[0249] When the conductive region 107 is provided with both a first through hole TH1 and a second through hole TH2, the diameters of the two through holes can be the same, or the diameter of the first through hole TH1 can be larger than the diameter of the second through hole TH2, so that an electrical connection structure for connecting the upper and lower lines can be set within the first through hole TH1. Similarly, when the conductive region 107 is provided with both a first through hole TH1 and a third through hole TH3, the diameters of the two through holes can be the same, or the diameter of the first through hole TH1 can be larger than the diameter of the third through hole TH3, so that an electrical connection structure for connecting the upper and lower lines can be set within the first through hole TH1.

[0250] refer to Figure 24 , Figure 24 This is a schematic diagram of the graphic structure of a first isolation layer provided in an embodiment of this application. Based on other implementation methods... Figure 24 The first isolation layer 105 also includes a third signal line SL3 insulated from the conductive region 107. The third signal line SL3 is electrically connected to one of the pixel circuit 103 and the driving circuit 104 for transmitting a second voltage signal, which is different from the first voltage signal. In this configuration, the first isolation layer 105 can not only have an integral conductive region 107 for isolating the first signal line SL1 and the second signal line SL2, but also have a third signal line SL3 for inputting the second voltage signal to one of the pixel circuit 103 and the driving circuit 104. This reduces the wiring space of other metal layers in the array substrate 100, facilitating wiring within the panel.

[0251] Optionally, the conductive region 107 and the third signal line SL3 are located in the same metal layer and there is a gap between them, which is used to achieve insulation between them.

[0252] The second voltage signal has fewer level switching times within a set time period than the second signal. Since the second voltage signal has fewer level switching times than the second signal, the first signal line SL1 and the second signal line SL2 can be electromagnetically isolated by the third signal line SL3.

[0253] Optionally, the second voltage signal transmitted in the third signal line SL3 can be any one of the following: the first voltage signal (a first power supply voltage, a second power supply voltage, a reference voltage, a start voltage signal, a high-level signal, and a low-level signal), and is different from the first voltage signal. As described above, these signals are all DC constant voltage signals, so placing the third signal line SL3 in the first isolation layer 105 also provides electromagnetic isolation for the first signal line SL1 and the second signal line SL2.

[0254] like Figure 24 As shown, there is a gap between the conductive region 107 and the third signal line SL3 to provide insulation between them. The width of this gap is smaller than the line width of the third signal line SL3 to reduce the area of ​​the hollowed-out region in the first isolation layer 105 and reduce the signal interference caused by the leakage electric field of the gap.

[0255] refer to Figure 25 , Figure 25 This is a cross-sectional view of an array substrate provided in an embodiment of this application. Based on other embodiments, Figure 25 In the array substrate 100 shown, the metal layer containing the first signal line SL1 also includes a first isolation line EIL1 and a fourth signal line SL4. The fourth signal line SL4 is electrically connected to one of the pixel circuit 103 and the driving circuit 104, and is insulated from the other. The first isolation line EIL1, the first signal line SL1, and the fourth signal line SL4 extend in the same direction. At least one first isolation line EIL1 is present between adjacent first signal lines SL1 and fourth signal lines SL4, and the first isolation line EIL1 is electrically connected to the first isolation layer 105. In this configuration, the metal layer can simultaneously fabricate the first signal line SL1 and the fourth signal line SL4, saving wiring space in other metal layers of the panel and facilitating wiring in the panel. Furthermore, by setting the first isolation line EIL1 between the first signal line SL1 and the fourth signal line SL4, electromagnetic isolation between the first signal line SL1 and the fourth signal line SL4 is achieved, reducing electromagnetic interference between them.

[0256] If the fourth signal line SL4 is electrically connected to the pixel circuit 103, the fourth signal line SL4 and the first signal line SL1 are used to input different signals to the pixel circuit 103. If the fourth signal line SL4 is electrically connected to the driving circuit 104, the fourth signal line SL4 and the second signal line SL2 are used to input different signals to the driving circuit 104.

[0257] like Figure 25 As shown, the first isolation line EIL1 can be electrically connected to the first isolation layer 105 through at least one conductive via Via. Because the first isolation line EIL1 is electrically connected to the first isolation layer 105, it can receive a first voltage signal, preventing the potential of the first isolation line EIL from floating, thus achieving better electromagnetic isolation. Furthermore, the first isolation line EIL1 can reduce the resistance of the line containing the first voltage signal, reduce the voltage drop of the first voltage signal, and improve its uniformity. The first isolation line EIL1 can also work in conjunction with the first isolation layer 105 to achieve electromagnetic isolation in different dimensions. While achieving electromagnetic isolation between the first signal line SL1 and the second signal line SL2 on different layers, it can also achieve isolation between the first signal line SL1 and the fourth signal line SL4 on the same layer, providing more comprehensive electromagnetic protection for the first signal line SL1 and better ensuring the stability of the first signal transmitted by the first signal line SL1. This method can simultaneously provide electromagnetic protection for multiple different signal lines in the panel, effectively improving the stability of the pixel circuit 103 and the driving circuit 104.

[0258] refer to Figure 26 , Figure 26 This is a cross-sectional view of another array substrate provided in an embodiment of this application, based on other implementations. Figure 26 In the array substrate 100 shown, the metal layer containing the second signal line SL2 also includes a second isolation line EIL2 and a fifth signal line SL5. The fifth signal line SL5 is electrically connected to one of the pixel circuit 103 and the driving circuit 104, and is insulated from the other. The second isolation line EIL2, the second signal line SL2, and the fifth signal line SL5 extend in the same direction. At least one second isolation line EIL2 is present between adjacent second signal lines SL2 and fifth signal lines SL5, and the second isolation line EIL2 is electrically connected to the first isolation layer 105. In this configuration, the metal layer can simultaneously fabricate the second signal line SL2 and the fifth signal line SL5, saving wiring space in other metal layers of the panel and facilitating wiring in the panel. Furthermore, by setting the second isolation line EIL2 between the second signal line SL2 and the fifth signal line SL5, electromagnetic isolation between them is achieved, reducing electromagnetic interference between them.

[0259] If the fifth signal line SL5 is electrically connected to the pixel circuit 103, the fifth signal line SL5 and the first signal line SL1 are used to input different signals to the pixel circuit 103. If the fifth signal line SL5 is electrically connected to the driving circuit 104, the fifth signal line SL5 and the second signal line SL2 are used to input different signals to the driving circuit 104.

[0260] like Figure 26 As shown, the second isolation line EIL2 can be electrically connected to the first isolation layer 105 through at least one conductive via Via. Because the second isolation line EIL2 is electrically connected to the first isolation layer 105, it can receive a first voltage signal, preventing the potential of the second isolation line EIL2 from floating, thus achieving better electromagnetic isolation. Furthermore, the second isolation line EIL2 can reduce the resistance of the line containing the first voltage signal, reduce the voltage drop of the first voltage signal, and improve its uniformity. The second isolation line EIL2 can also work in conjunction with the first isolation layer 105 to achieve electromagnetic isolation in different dimensions. While achieving electromagnetic isolation between the first signal line SL1 and the second signal line SL2 on different layers, it can also achieve isolation between the second signal line SL2 and the fifth signal line SL5 on the same layer, simultaneously providing electromagnetic protection for multiple different signal lines in the panel, effectively improving the stability of the pixel circuit 103 and the driving circuit 104.

[0261] refer to Figure 27 , Figure 27 This is a schematic diagram illustrating the layout of mesh holes in a conductive region according to an embodiment of this application. Based on other embodiments, the pixel circuit 103 includes multiple transistors located in the first circuit region 109. The circuit connection and layout of each transistor in the pixel circuit 103 include, but are not limited to, [the following]. Figure 12 and Figure 13 As shown.

[0262] like Figure 27 As shown, the first circuit region 109 and the conductive region 107 overlap, so that the conductive region 107 can shield the first circuit region 109 opposite to the overlapping portion, thus providing electromagnetic protection for the pixel circuit 103 within the first circuit region 109. Preferably, the entire first circuit region 109 overlaps with the conductive region 108, so that the conductive region 107 can completely shield the first circuit region 109, thereby maximizing the electromagnetic protection of the pixel circuit 103 provided by the conductive region 107.

[0263] exist Figure 27In the illustrated configuration, the first isolation layer 105 has a plurality of mesh openings 108; the plurality of mesh openings 108 include a first portion of mesh opening P1 and a second portion of mesh opening P2; in the third direction Z, the first portion of mesh opening P1 does not overlap with the first circuit region 109, and the second portion of mesh opening P2 overlaps with the first circuit region 109. In other configurations, the plurality of mesh openings 108 may also include one of the first portion of mesh opening P1 and the second portion of mesh opening P2. The first portion of mesh opening P1 includes the second through-hole TH2 mentioned above. The second portion of mesh opening P2 includes the first through-hole TH1 and / or the third through-hole TH3 mentioned above.

[0264] When the plurality of meshes 108 in the conductive region 107 include the first portion of meshes P1, within the conductive region 107, such as Figure 27 As shown, the areas of the first portion of mesh holes P1 are the same, or the spacing of the first portion of mesh holes P1 in the first direction X is the same, or the spacing of the first portion of mesh holes P1 in the second direction Y is the same. The first direction X and the second direction Y are both parallel to the panel plane and intersect. In this method, at least one of the area of ​​the first portion of mesh holes P1, the spacing in the first direction X, and the spacing in the second direction Y is the same, which allows it to be adapted to each first circuit area 109 for layout, and also facilitates the layout of all first portion of through holes P1 based on the same process parameters.

[0265] When the plurality of meshes 108 in the conductive region 107 include the second portion of meshes P2, within the conductive region 107, such as Figure 27 As shown, the second portion of the mesh P2 has the same area, or the second portion of the mesh P2 has the same spacing in the first direction X, or the second portion of the mesh P2 has the same spacing in the second direction Y. In this method, at least one of the area of ​​the second portion of the mesh P2, the spacing in the first direction X, and the spacing in the second direction Y is the same, which facilitates the layout of all the first portion of the through holes P1 based on the same process parameters.

[0266] refer to Figure 28 , Figure 28 This is a cross-sectional view of another array substrate provided in the embodiments of this application, based on other implementations. Figure 28 The array substrate 100 shown also includes a second isolation layer 116 disposed adjacent to the first isolation layer 105, the second isolation layer 116 transmitting a third voltage signal; an insulating layer 106 is provided between the first isolation layer 105 and the second isolation layer 116.

[0267] The third voltage signal has fewer level switching times within a set time period than the second signal, so that the first signal line SL1 and the second signal line SL2 can be electromagnetically isolated by the second isolation layer 116.

[0268] exist Figure 28In this design, the first signal line SL1 and the second signal line SL2 can be electromagnetically isolated by two layers of isolation, achieving better electromagnetic isolation and significantly reducing the interference of the second signal on the first signal.

[0269] In one embodiment, the second isolation layer 116 and the first isolation layer 105 are electrically connected through a conductive via. In this case, the third voltage signal is the same as the first voltage signal, and both isolation layers receive the same voltage signal, which simplifies the signal line structure of the isolation layers in the dual-isolation layer design. In other embodiments, the first isolation layer 105 is insulated from the second isolation layer 116, and the first and third voltage signals can be different fixed voltage signals. The design scheme of the third voltage signal can be the same as that of the first voltage signal, which will not be described in detail in this embodiment.

[0270] refer to Figure 29 , Figure 29 This is a cross-sectional view of another array substrate provided in this application embodiment. Based on the above-described embodiment, the first isolation layer 105 and the second isolation layer constitute a composite isolation structure. The pixel circuit 103 and the driving circuit 104 are located on one side of the composite isolation structure, and the other side of the composite isolation structure has a first connecting line 111. Both the first isolation layer 105 and the second isolation layer 116 have multiple mesh holes 108. In the third direction Z, some of the mesh holes 108 of the first isolation layer 105 and the second isolation layer 116 are overlapped. The overlapped mesh holes 108 are used to set the transition block 113. The first connecting line 111 is electrically connected to one of the pixel circuit 103 and the driving circuit 104 through the transition block 113. Some of the mesh holes 108 of the first isolation layer 105 and the second isolation layer 116 are not overlapped, and the non-overlapping through holes are filled with insulating material.

[0271] like Figure 29 As shown, the left mesh 108 in the first isolation layer 105 and the left mesh 108 in the second isolation layer 116 are perpendicularly opposite each other. Both meshes 108 are transition holes, each containing a transition block 113. The first connecting line 111 is electrically connected to the pixel circuit 103 through the transition blocks 113 within these two meshes 108. The right mesh 108 in the first isolation layer 105 and the right mesh 108 in the second isolation layer 116 do not overlap in the third direction Z.

[0272] In this embodiment, similar to the scheme where multiple holes 108 are provided on the first isolation layer 105, the second isolation layer 116 includes multiple mesh holes 108. The mesh holes 108 in the second isolation layer 116 are used for venting of the organic material insulating layer 106 below the second isolation layer 116 and for electrical connection of the upper and lower circuits of the two isolation layers. In the third direction Z, some of the mesh holes 108 in the first isolation layer 105 and the second isolation layer 116 overlap, used for electrical connection of the first connecting line 111 to the lower circuit, while other mesh holes 108 do not overlap. The non-overlapping mesh holes 108 in the two isolation layers allow the leaked electric field from the mesh holes 108 in one isolation layer to be isolated by the other isolation layer, thereby effectively solving the problem of electric field leakage from the mesh holes 108 when there is only one isolation layer.

[0273] refer to Figure 30 , Figure 30 This is a schematic diagram of the structure of an array substrate in a display panel provided in another embodiment of this application. Based on other implementation methods... Figure 30 In the array substrate 100 shown, the first isolation layer 105 includes a plurality of integral conductive regions 107 distributed along the first direction X; the conductive regions 107 are respectively input with a first voltage signal; the first signal line SL1 and the second signal line SL2 both extend along the second direction Y.

[0274] If the first isolation layer 105 isolates all the first signal lines SL1 and the second signal lines SL2 through a conductive region 109, due to the large area of ​​the conductive region 109, large voltage drops will form at different locations, resulting in uneven voltage distribution within the conductive region 109. To solve this problem, Figure 30 In the illustrated configuration, the first isolation layer 105 is divided into multiple conductive regions 109 distributed along the first direction X. The first signal line SL1 and the second signal line SL2 extend along the second direction Y. This not only allows the first signal line SL1 and the second signal line SL2 to form a large area of ​​shielding through their corresponding conductive regions 107, achieving better electromagnetic isolation, but also improves the voltage uniformity of the conductive regions 107 by allowing independent input of the first voltage signal through the multiple separate conductive regions 107, thus enhancing the electromagnetic isolation effect. This method can improve the stability of the first voltage signal. When the first voltage signal is used as the pixel circuit 103, it can improve the stability of the pixel circuit 103. Alternatively, when the first voltage signal is used as the input signal of the driving circuit 104, it can improve the stability of the driving circuit 104.

[0275] refer to Figure 31 , Figure 31This is a cross-sectional view of another array substrate provided in this application embodiment. Based on other embodiments, the pixel circuit 103 and the driving circuit 104 are located on one side of the first isolation layer 105, and the other side of the first isolation layer 105 has a first connecting line 111. The first isolation layer 105 has a plurality of mesh holes 108. A portion of the mesh holes 108 are first through holes TH1, which are transition holes. The first connecting line 111 is electrically connected to one of the pixel circuit 103 and the driving circuit 104 based on the first through holes TH1. This method is exemplified by the connection of the first connecting line 111 to the pixel circuit 103. The first connecting line 111 is insulated from the first isolation layer 105. Another portion of the mesh holes 108 is filled with insulating material, and this portion of the mesh holes is not a transition hole. The metal layer where the first signal line SL1 is located also has a first shielding block 117 that is insulated from the first signal line SL1. The first shielding block 117 is disposed opposite to the other portion of the mesh holes 108 and is electrically connected to the first isolation layer 105.

[0276] exist Figure 31 In the illustrated configuration, by shielding the non-transfer holes in the first isolation layer 105 with the first shielding block 117 on the same layer as the first signal line SL1, the electromagnetic interference of the leakage electric field from the non-transfer holes to the first signal line SL1 can be reduced. The first shielding block 117 is electrically connected to the first isolation layer 105, ensuring they are at the same potential, preventing the points from floating and improving the electromagnetic isolation effect. It also reduces the resistance of the first isolation layer 105 transmitting the first voltage signal, lowering the line impedance and improving the stability of the first voltage signal. Furthermore, the first shielding block 117 and the first isolation layer 105 on different layers can work together to achieve electromagnetic isolation in different dimensions, further enhancing the electromagnetic isolation effect.

[0277] In this embodiment of the application, when the second signal line SL2 is located above the first isolation layer 105, the first connecting line 111 may be located in the same metal layer as the second signal line SL2, or in a different metal layer. When the first signal line SL1 is located above the first isolation layer 105, the first connecting line 111 may be located in the same metal layer as the first signal line SL1, or in a different metal layer.

[0278] refer to Figure 32 , Figure 32 A cross-sectional view of another array substrate provided in an embodiment of this application, in Figure 31In the illustrated configuration, the metal layer containing the second signal line SL2 also has a second shielding block 118 that is insulated from the second signal line SL2. The second shielding block 118 is disposed opposite to the other portion of the mesh 108 and is electrically connected to the first isolation layer 105. In this configuration, the electrical connection between the second shielding block 118 and the first isolation layer 105 allows it to be at the same potential as the first isolation layer 105, preventing the point from floating and improving its electromagnetic isolation effect. It can also reduce the resistance of the first isolation layer 105 that transmits the first voltage signal, reduce the line impedance, and improve the stability of the first voltage signal. The second shielding blocks 118 and the first isolation layer 105 in different layers can also work together to achieve electromagnetic isolation in different dimensions, improving the electromagnetic isolation effect.

[0279] It should be noted that the array substrate 100 may include either the first shielding block 117 or the second shielding block 118, or both the first shielding block 117 and the second shielding block 118 may be provided simultaneously; it is not limited to this configuration. Figure 31 and Figure 32 As shown.

[0280] Based on the above embodiments, another embodiment of this application also provides a display panel, the structure of which can be as follows: Figure 33 As shown.

[0281] refer to Figure 33 , Figure 33 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel 119 includes:

[0282] Array substrate 100, the structure of array substrate 100 can be as follows Figure 2 As shown, the array substrate 100 includes: a pixel circuit 103 and a driving circuit 104; a first signal line SL1 electrically connected to the pixel circuit 103, the first signal line SL1 transmitting a first signal for the pixel circuit 103; and a second signal line SL2 connected to the driving circuit 104, the second signal line SL2 transmitting a second signal for the driving circuit 104; wherein the first signal line SL1 and the second signal line SL2 are located in different film layers, and a first isolation layer 105 is provided between the first signal line SL1 and the second signal line SL2.

[0283] The light-emitting element 30, which is electrically connected to the pixel circuit 103, displays images based on the driving current provided by the pixel circuit 103.

[0284] Based on the above embodiments, another embodiment of this application also provides an electronic device, the structure of which is as follows: Figure 33 As shown.

[0285] refer to Figure 34 , Figure 34This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device includes a display panel 119 as provided in the above embodiment.

[0286] The display panel and electronic device and array substrate 100 disclosed in the above embodiments have the same or corresponding beneficial effects, and will not be described again here to avoid repetition.

[0287] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0288] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for understanding and ease of description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0289] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0290] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0291] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An array substrate for a display panel, characterized in that, include: Pixel circuits and driving circuits; A first signal line electrically connected to the pixel circuit, wherein the first signal line transmits a first signal to the pixel circuit; A second signal line electrically connected to the drive circuit, wherein the second signal line transmits a second signal to the drive circuit; The first signal line and the second signal line are located in different film layers, and a first isolation layer is included between the first signal line and the second signal line. The first isolation layer transmits a first voltage signal.

2. The array substrate of claim 1, wherein, The first isolation layer includes an integral conductive region, which transmits the first voltage signal; In a direction perpendicular to the plane of the array substrate, the first isolation layer is located between the first signal line and the second signal line, and at least one of the first signal line and the second signal line overlaps with the conductive region.

3. The array substrate of claim 2, wherein, The conductive area has multiple mesh openings; In a direction perpendicular to the plane, at least a portion of the mesh openings do not overlap with the first signal line; and / or, at least a portion of the mesh openings do not overlap with the second signal line.

4. The array substrate of claim 3, wherein, The pixel circuit includes a plurality of transistors located in the first circuit region; in a direction perpendicular to the plane of the array substrate, the first circuit region overlaps with the conductive region, but does not overlap with the first signal line and the second signal line; In a first direction, there is a gap region between two adjacent first circuit regions; both the first signal line and the second signal line extend along a second direction; the second direction intersects the first direction and is parallel to the plane; In a direction perpendicular to the plane, the portion of the conductive region opposite the gap region has the mesh; and within this portion, the first signal line and / or the second signal line do not overlap with the mesh.

5. The array substrate of claim 2, wherein, The conductive area is electrically connected to the pixel circuit to transmit the first voltage signal to the pixel circuit; Alternatively, the conductive area may be electrically connected to the driving circuit to transmit the first voltage signal to the driving circuit.

6. The array substrate of claim 5, wherein, The pixel circuit receives at least a first power supply voltage, a second power supply voltage, and a reference voltage; The driving circuit receives at least a start voltage signal, a high-level signal, and a low-level signal; The first voltage signal is any one of the first power supply voltage, the second power supply voltage, the reference voltage, the starting voltage signal, the high-level signal, and the low-level signal.

7. The array substrate of claim 1, wherein, The first isolation layer is insulated from both the pixel circuit and the driving circuit.

8. The array substrate of claim 1, wherein, The pixel circuit receives at least a data voltage signal; The driving circuit receives at least a clock signal; The first signal is the data voltage signal, and the second signal is the clock signal.

9. The array substrate of claim 2, wherein, The conductive area has multiple mesh openings; The pixel circuit and the driving circuit are located on the same side of the first isolation layer, and the other side of the first isolation layer has a first connecting line; the first connecting line passes through the conductive area based on the mesh insulation to be electrically connected to one of the pixel circuit and the driving circuit.

10. The array substrate of claim 9, wherein, The plurality of mesh openings include a first through-hole, the first through-hole having a transition block insulated from the conductive area; The first connection line is electrically connected to one of the pixel circuit and the driving circuit through the adapter block.

11. The array substrate of claim 9, wherein, The plurality of mesh openings includes a first through-hole; The first connecting line is electrically connected to the anode of the light-emitting element, and the first connecting line is electrically connected to the transistor in the pixel circuit through the first through hole; Alternatively, the first connection line may be electrically connected to a transistor in the driving circuit via the first via.

12. The array substrate of claim 11, wherein, In a direction perpendicular to the plane, at least a portion of the first via does not overlap with the active layer of the transistor.

13. The array substrate of claim 9, wherein, The pixel circuit includes a plurality of transistors located in the first circuit region; in a direction perpendicular to the plane of the array substrate, the first circuit region and the conductive region have an overlapping portion; The plurality of mesh holes include a second through hole, which is filled with an insulating material; in a direction perpendicular to the plane of the array substrate, the second through hole does not overlap with the first circuit area.

14. The array substrate of claim 9, wherein, The driving circuit includes a plurality of transistors located in the second circuit region; in a direction perpendicular to the plane of the array substrate, the second circuit region and the conductive region have an overlapping portion; The plurality of mesh holes include a second through hole, which is filled with an insulating material; in a direction perpendicular to the plane of the array substrate, the second through hole overlaps with the second circuit area.

15. The array substrate of claim 9, wherein, The pixel circuit includes a plurality of transistors located in a first circuit region; the first circuit region and the conductive region have an overlapping portion. The plurality of mesh openings include a third through-hole, the third through-hole being filled with insulating material; The pixel circuit includes multiple transistors, including driving transistors, and also includes a storage capacitor. In a direction perpendicular to the plane, the third via does not overlap with either the driving transistors or the storage capacitor.

16. The array substrate of claim 2, wherein, The first isolation layer further includes a third signal line insulated from the conductive region. The third signal line is electrically connected to one of the pixel circuit and the driving circuit for transmitting a second voltage signal, wherein the first voltage signal is different from the second voltage signal.

17. The array substrate of claim 16, wherein, The second signal is a periodic signal; The number of level switching times of the first voltage signal within a set time period is less than the number of level switching times of the second signal; The number of level switching times of the second voltage signal within the set time period is less than the number of level switching times of the second signal.

18. The array substrate of claim 1, wherein, The metal layer containing the first signal line also includes a first isolation line and a fourth signal line, wherein the fourth signal line is electrically connected to the pixel circuit or the driving circuit. The first isolation line, the first signal line, and the fourth signal line extend in the same direction; there is at least one first isolation line between adjacent first signal lines and fourth signal lines, and the first isolation line is electrically connected to the first isolation layer.

19. The array substrate of claim 1, wherein, The second metal layer on which the second signal line is located also includes a second isolation line and a fifth signal line, wherein the fifth signal line is electrically connected to the pixel circuit or the driving circuit; The second isolation line, the second signal line, and the fifth signal line extend in the same direction; there is at least one second isolation line between adjacent second signal lines and the fifth signal line, and the second isolation line is electrically connected to the first isolation layer.

20. The array substrate according to claim 2, characterized in that, The pixel circuit includes a plurality of transistors located in a first circuit region; the first circuit region and the conductive region have an overlapping portion. The first isolation layer has multiple mesh openings; The plurality of mesh openings includes a first portion of mesh openings and / or a second portion of mesh openings; In a direction perpendicular to the plane of the array substrate, the first portion of the mesh does not overlap with the first circuit area, while the second portion of the mesh overlaps with the first circuit area. The first portion of the mesh has the same area, or the first portion of the mesh has the same spacing in the first direction, or the first portion of the mesh has the same spacing in the second direction, and both the first direction and the second direction are parallel to the plane and intersect. The second portion of the mesh has the same area, or the second portion of the mesh has the same spacing in the first direction, or the second portion of the mesh has the same spacing in the second direction.

21. The array substrate of claim 1, wherein, It also includes a second isolation layer disposed adjacent to the first isolation layer, the second isolation layer transmitting a third voltage signal; an insulating layer is provided between the first isolation layer and the second isolation layer.

22. The array substrate of claim 21, wherein, The first isolation layer and the second isolation layer constitute a composite isolation structure. The pixel circuit and the driving circuit are located on one side of the composite isolation structure, and the other side of the composite isolation structure has a first connection line. Both the first isolation layer and the second isolation layer have multiple mesh holes; in a direction perpendicular to the plane of the array substrate, some of the mesh holes of the first isolation layer and the second isolation layer overlap, and the overlapping mesh holes are used to set a transition block. The first connecting line is electrically connected to one of the pixel circuit and the driving circuit through the transition block; some of the mesh holes of the first isolation layer and the second isolation layer do not overlap, and the non-overlapping through holes are filled with insulating material.

23. The array substrate of claim 1, wherein, The first isolation layer includes a plurality of integral conductive regions distributed along a first direction; the first voltage signal is respectively input to each conductive region. Both the first signal line and the second signal line extend along the second direction; The first direction and the second direction intersect and are both parallel to the plane.

24. The array substrate of claim 1, wherein, The pixel circuit and the driving circuit are located on one side of the first isolation layer, and the other side of the first isolation layer has a first connection line; The first isolation layer has multiple mesh openings; a portion of the mesh openings are first through-holes, and the first connecting line is electrically connected to one of the pixel circuit and the driving circuit based on the first through-holes; the first connecting line is insulated from the first isolation layer; The other part of the mesh is filled with insulating material; The metal layer containing the first signal line also has a first shielding block that is insulated from the first signal line; the first shielding block is disposed opposite to the other part of the mesh and is electrically connected to the first isolation layer, and / or, the metal layer containing the second signal line also has a second shielding block that is insulated from the second signal line; the second shielding block is disposed opposite to the other part of the mesh and is electrically connected to the first isolation layer.

25. A display panel comprising: include: An array substrate includes: a pixel circuit and a driving circuit; a first signal line electrically connected to the pixel circuit, the first signal line transmitting a first signal for the pixel circuit; and a second signal line connected to the driving circuit, the second signal line transmitting a second signal for the driving circuit; wherein the first signal line and the second signal line are located in different film layers, and a first isolation layer is provided between the first signal line and the second signal line. The light-emitting element, which is electrically connected to the pixel circuit, displays an image based on the driving current provided by the pixel circuit.

26. An electronic device, comprising: include: The display panel as described in claim 25.

Images