Balanced scheduling and scattering display method, electronic device, chip and storage medium

Abstract

This disclosure provides a balanced scheduling and scattered display method, an electronic device, a chip, and a storage medium. The balanced scheduling and scattered display method includes: determining the subfield in which each display partition is displayed within I subfields of a display frame, wherein each subfield includes N display time slots, and each display time slot corresponds to one display partition; dividing the display duration of the display frame into at least one subfield period sequence, wherein a subfield period sequence includes M subfield periods set in chronological order, each subfield period includes one display time slot of J different subfields, and the display time slots within each subfield period are arranged in a predetermined order, wherein M, N, I, and J are positive integers, and J is less than or equal to I; within the M subfield periods of each subfield period sequence, each display partition is displayed in the display time slot of the corresponding subfield.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a balanced scheduling and scattering display method, electronic device, chip, and storage medium. Background Technology

[0002] Currently, in the field of light-emitting diode (LED) displays (including small-pitch LED displays, Mini-LED displays, Micro-LED displays, etc.), PWM (Pulse Width Modulation) driving technology is commonly used to achieve multi-grayscale display. This technology divides a frame of image into multiple sub-fields in time, and achieves different grayscale levels by combining the lighting / off states of each sub-field.

[0003] Display control using Pulse Width Modulation (PWM) typically drives the display row by row, completing one display cycle for each subfield. This means the next subfield begins displaying only after all rows have finished. However, the subfields corresponding to lower grayscale levels (e.g., grayscale 1-15) are concentrated at the beginning, resulting in a significantly lower effective refresh rate for lower grayscale levels compared to higher grayscale levels. Therefore, in PWM digital drive technology, the output sequence of subfields suffers from insufficient refresh rate for lower grayscale levels.

[0004] Therefore, improving the effective refresh rate and refresh uniformity of low grayscale images and enhancing their display quality is an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a balanced scheduling and scattering display method, an electronic device, a chip, and a storage medium.

[0006] According to a first aspect of the present disclosure, a balanced scheduling and distribution display method is proposed, applied to a display device, wherein the display device includes N display partitions, and the method includes: Determine the subfield in which each display partition is displayed within the I subfields of a display frame, where each subfield includes N display time slots and each display time slot corresponds to one display partition; The display duration of the display frame is divided into at least one subfield cycle sequence. A subfield cycle sequence includes M subfield cycles set in chronological order. Each subfield cycle includes one display time slot of J different subfields. The display time slots in each subfield cycle are arranged in a predetermined order. M, N, I, and J are positive integers, and J is less than or equal to I. Within each of the M sub-field cycles in each sub-field cycle sequence, each display partition is displayed in the corresponding sub-field display time slot.

[0007] In some embodiments, within M subfield cycles in each subfield cycle sequence, each display partition is displayed in the corresponding subfield display time slot, including: Within each subfield cycle, the correspondence between the subfield corresponding to the current display slot and the currently scanned display partition is determined sequentially based on the predetermined scanning order of the N display partitions, with the display slot as the scanning time interval unit for each display partition. In response to the subfield corresponding to the current display slot and the display partition currently being scanned, the currently scanned display partition is displayed.

[0008] In some embodiments, the method further includes: If the subfield corresponding to the current display time slot does not correspond to the display partition being scanned, no display will be made in the current display time slot.

[0009] In some embodiments, each subfield cycle includes J subfield sequence numbers that cycle through adjacent subfields and each corresponding display time slot, and the J display time slots in each subfield cycle are set according to the subfield sequence number order of the corresponding J adjacent subfields.

[0010] In some embodiments, the subfield number corresponding to the first display slot among the J display slots in each subfield cycle is determined using one of the following methods: The subfield number corresponding to the first display slot in the J display slots within each subfield cycle is represented by the following expression:

[0011] Where m represents the subfield cycle number, X represents the subfield sequence number of the first display time slot in the J display time slots within the m-th subfield cycle, M represents the total number of subfield cycles, and k represents the interval step size between the subfield sequence numbers of the first display time slot in the J display time slots corresponding to two adjacent subfield cycles, where k is a positive integer. The subfield number of the first display time slot in the J display time slots within each subfield cycle is randomly set, and the subfield number of the first display time slot in the J display time slots within each subfield cycle is different; The M subfield periods correspond to the subfield number of the first display time slot in the J display time slots, and are respectively the bit inversion values ​​of the sequentially arranged subfield numbers of the I subfields.

[0012] In some embodiments, the display frame satisfies a first condition, k=1, wherein the first condition includes: the proportion of pixels in the display frame whose grayscale value is less than or equal to a low grayscale threshold is greater than a first proportion, k=1; Alternatively; the display frame satisfies the second condition, k=4, wherein the second condition includes: the proportion of pixels with grayscale values ​​greater than the low grayscale threshold in the display frame is greater than the second proportion, k=4; Alternatively; the display frame does not satisfy the first condition and the second condition, k=2.

[0013] In some embodiments, one display time slot includes multiple grayscale clocks, and one grayscale clock is used to display one grayscale value; The method further includes: The grayscale value of the display frame is divided by the number of grayscale clock cycles of the display time slot, and the remainder is used to determine the first grayscale value of the remainder portion of the grayscale value of the display frame. One grayscale value is displayed for each display time slot. For the second grayscale value other than the remainder portion of the grayscale value of the display frame, Y grayscale values ​​are displayed in one display time slot, where Y is the number of grayscale clocks contained in the display time slot.

[0014] According to a second aspect of the present disclosure, a display device is provided, the display device including a display area, a control device, and a cascaded group of display driving devices respectively connected to the display area and the control device; the cascaded group of display driving devices includes one or more cascaded display driving devices. The control device is used to implement the balanced scheduling and scattered display method described in the first aspect; The multiple display partitions in the display area constitute a display cluster; the display area includes one or more display clusters. Each of the display drivers is connected to at least one of the display partitions, such that the display drivers are cascaded together to connect the plurality of display partitions; and are used to drive the display of the display partitions.

[0015] In some embodiments, each of the display driving devices is connected to at least one of the display partitions in a preset manner according to the physical location distribution of the plurality of display partitions in the display area.

[0016] According to a third aspect of the present disclosure, a chip or chip system is provided for driving the display of a display screen, comprising: A memory storing instructions; and a processor configured to execute the instructions to implement the balanced scheduling scatter display method as described in the first aspect.

[0017] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided that stores computer instructions or programs that, when executed on a computer, cause the balanced scheduling and scattering display method described in the first aspect to be executed.

[0018] This disclosure provides a balanced scheduling and scattered display method, an electronic device, a chip, and a storage medium. The balanced scheduling and scattered display method includes: determining the subfield corresponding to each display partition in I subfields of a display frame, wherein each subfield includes N display time slots, and each display time slot corresponds to one display partition; dividing the display duration of the display frame into at least one subfield period sequence, wherein one subfield period sequence includes M subfield periods arranged in chronological order, each subfield period including one display time slot in J different subfields, the display time slots within each subfield period being arranged in a predetermined order, wherein M, N, I, and J are positive integers, and J is less than or equal to I; within the M subfield periods of each subfield period sequence, each display partition is displayed in the display time slot of the corresponding subfield. Thus, by distributing the display time slots in a subfield to different subfield periods and displaying them in the display time slots of the corresponding subfields of the display area, the temporal domain position of grayscale display is scattered, thereby improving the effective refresh rate and refresh uniformity of low grayscale, and improving the display effect of low grayscale images. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an LED progressive scan display; Figure 2 This is a schematic diagram of a single-line grayscale scan display; Figure 3 This is a schematic diagram of a grayscale 2-line scan display; Figure 4 This is a schematic diagram of the balanced scheduling and scattering display method according to an embodiment; Figure 5 This is a schematic diagram of grayscale dispersion shown in the embodiment. Figure 1 ; Figure 6 This is a schematic diagram of grayscale dispersion shown in the embodiment. Figure 2 ; Figure 7 This is a schematic diagram of grayscale dispersion shown in the embodiment. Figure 3 ; Figure 8 This is a schematic diagram of grayscale dispersion shown in the embodiment. Figure 4 ; Figure 9 This is a schematic diagram of a grayscale clock in a display time slot, as shown in the embodiment. Figure 1 ; Figure 10 This is a schematic diagram of a grayscale clock in a display time slot, as shown in the embodiment. Figure 2 ; Figure 11 This is an exemplary schematic block diagram of a display device according to an embodiment; Figure 12This is a schematic diagram illustrating an exemplary operating scenario of a chip or chip system according to an embodiment. Figure 13 This is an exemplary principle block diagram of a chip or chip system shown according to an embodiment. Detailed Implementation

[0020] To make the technical solution and beneficial effects of the present invention more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0021] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0022] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0023] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0024] In this disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular or a plural expression.

[0025] In the embodiments disclosed herein, "multiple" refers to two or more.

[0026] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0027] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, both A and B are executed. The same applies when there are more branches such as A, B, C, etc.

[0028] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, selective execution from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, and C.

[0029] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0030] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0031] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0032] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0033] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0034] The principle of LED display is as follows: Figure 1 During the display process, the LEDs are scanned line by line. In this process, a display frame is divided into multiple subfields in the time domain, and the grayscale is adjusted by changing the display duration of each line in each subfield.

[0035] Taking 8 rows (i.e., 8 display zones) and 16 sub-fields as an example, the display method when the grayscale is 1 is as follows: Figure 2 As shown (where the horizontal numbers represent subfield numbers and the vertical numbers represent row numbers). There are 16 subfields (subfields 0 to 15 are arranged in chronological order). Each subfield includes 8 display slots, and each display slot is used for displaying exactly one row. For example, if subfield 0 has 8 display slots, during row scanning, all 8 rows can be displayed in the 8 display slots of subfield 0. The remaining 15 subfields will not be displayed. Similarly, as... Figure 2 As shown (where the horizontal numbers represent subfield numbers and the vertical numbers represent row numbers), when the grayscale is 2, the image can be displayed in the first two of the 16 subfields, while it is not displayed in the remaining 14 subfields. Higher grayscale images can be displayed in all 16 subfields. Clearly, the effective refresh rate of lower grayscale images is lower than that of higher grayscale images, thus affecting the display effect of lower grayscale images.

[0036] This disclosure proposes a balanced scheduling and distribution display method for a display device, wherein the display device includes N display partitions, such as... Figure 4 As shown, the balanced scheduling and distribution method specifically includes the following steps: Step 401: Determine the subfield in which each display partition is displayed within the I subfields of a display frame, where each subfield includes N display time slots and each display time slot corresponds to 1 display partition; Step 402: Divide the display duration of the display frame into at least one sub-field period sequence, wherein a sub-field period sequence includes M sub-field periods set in chronological order, each sub-field period includes one display time slot of J different sub-fields, and the display time slots in each sub-field period are arranged in a predetermined order, wherein M, N, I and J are positive integers, and J is less than or equal to I; Step 403: Within the M sub-field cycles in each sub-field cycle sequence, each display partition displays in the corresponding sub-field display time slot.

[0037] A display device can be a hardware device capable of displaying images or video content, such as an LED display screen or LED backlight. This device typically consists of multiple independent display units to achieve the overall display of the image. A display zone can be a physical area unit within the display device used for independently controlling the displayed content.

[0038] In one possible implementation, a display partition may include a row of display units. For example, in an LED display, a display partition may include a row of LEDs, or an area controlled by a single driver module. N display partitions indicate that the display device is logically or physically divided into N independently addressable and / or controllable areas.

[0039] A subfield can be a subdivided unit of a display frame in time. In pulse width modulation (PWM) driving technology, different grayscale levels can be achieved by combining different subfields to turn on and off. I subfields represent a display frame being divided into I time subunits.

[0040] The display partition corresponds to a subfield, which can be one of I subfields. A specific display partition is determined as the subfield that needs to be displayed. Each display partition may be activated in a different subfield to display its content.

[0041] In one possible implementation, a subfield can correspond to multiple display partitions. For example... Figure 2 As shown, rows 1 to 8 are all displayed in subfield 0.

[0042] In one possible implementation, a display partition can correspond to a subfield. For example... Figure 3As mentioned above, row 1 is displayed in subfield 0 and subfield 1.

[0043] A display time slot can be a time window allocated to a display partition within a subfield. Each subfield contains N display time slots, meaning that within a subfield, N display partitions can be allocated time for display sequentially or in parallel. Each display time slot corresponds one-to-one with a display partition.

[0044] A subfield cycle sequence can be a set of multiple time segments into which the overall display duration of a display frame is divided according to certain rules. A subfield cycle sequence contains M subfield cycles arranged in chronological order, and these subfield cycles together constitute a complete display cycle. For example, a display frame may include one subfield cycle sequence or multiple subfield cycle sequences.

[0045] Each subfield cycle includes one display slot for J different subfields, and the display slots are arranged in a predetermined order within the subfield cycle. J is less than or equal to I, indicating that the number of subfield types included in a subfield cycle does not exceed the total number of subfields. Within the I subfields of a display frame, it can be determined which subfields each display partition will display in. This determination process can be based on the grayscale information of the displayed content. For example, for a display partition, if it needs to display a specific grayscale value, the subfields in which the display partition is activated are determined according to the subfield combination corresponding to that grayscale value. This determination can be performed by the control unit of the display device according to a preset grayscale-subfield mapping table, or it can be obtained through real-time calculation. Figure 2 As shown, the display frame has a grayscale of 1, and rows 1 to 8 are all assigned to subfield 0 for display. Figure 3 As shown, the display frame has a grayscale of 2, and rows 1 to 8 are all assigned to subfield 0 and subfield 1 for display, with each subfield displaying one grayscale.

[0046] To achieve grayscale dispersion, the overall display duration of a display frame is logically divided into one or more sub-field cycle sequences. Each sub-field cycle sequence consists of M sub-field cycles, which can be performed sequentially in time. Within each sub-field cycle, there are J display time slots from different sub-fields. The display time slots are arranged in a predetermined order within the current sub-field cycle. For example, a sub-field cycle can contain display time slots from sub-field 0, sub-field 1, and sub-field 2, and be set in the order of display time slots from sub-field 0, sub-field 1, and sub-field 2. The order of display time slots within a sub-field cycle is determined based on the sub-field order of the display time slots.

[0047] In one possible implementation, within a subfield period sequence, the subfields corresponding to the time slots in each subfield period are not entirely the same. For example, subfield period 1 includes the display time slots for subfield 0, subfield 1, and subfield 2; subfield period 2 includes the display time slots for subfield 1, subfield 2, and subfield 3; and subfield period 3 includes the display time slots for subfield 2, subfield 3, and subfield 4.

[0048] In one possible implementation, within a subfield period sequence, at least two of the M subfield periods correspond to different subfields. For example, subfield period 1 includes the display time slots for subfield 0, subfield 1, and subfield 2; subfield period 2 includes the display time slots for subfield 1, subfield 2, and subfield 3; and subfield period 3 includes the display time slots for subfield 0, subfield 1, and subfield 2. The subfields corresponding to subfield period 1 and subfield period 3 are the same, but different from the subfields corresponding to subfield period 2.

[0049] In one possible implementation, the product of M and J is equal to the product of N and I.

[0050] The product of M and J equals the product of N and I, ensuring a balanced distribution of display opportunities across all subfields throughout the entire subfield cycle sequence. This reduces the over- or under-scheduling of certain subfields or subfields. J less than or equal to I indicates that a subfield cycle will not contain duplicate subfield types, and the number of subfield types it contains will not exceed the total number of subfields.

[0051] Within M subfield cycles, each display partition is displayed only within the display time slot corresponding to the subfield it is assigned to. That is, a subfield cycle contains multiple display time slots, and a specific display partition is only activated within the display time slot of its assigned subfield. For example, if display partition A is assigned to subfield 0, then within a given subfield cycle, display partition A will only be driven to display when it is the turn of the display time slot corresponding to subfield 0. This scheduling method allows for precise control of display resources, thereby achieving efficient and accurate image display.

[0052] In one possible implementation, the N display partitions are scanned and displayed sequentially in a predetermined scanning order. For example, the first display partition is scanned during the first display gap of a subfield cycle. If the subfield of the first display gap is the subfield to which the first display partition was assigned, then the first display partition is displayed during that first display gap.

[0053] In one possible implementation, J can be equal to N.

[0054] For example, such as Figure 2 As shown, a display device has N=8 display partitions (rows), and a display frame is divided into I=16 subfields (e.g., subfield 0 to subfield 15). Rows 1 to 8 in the display frame are all assigned to subfield 0 for display.

[0055] The display duration of the display frame is divided into multiple sub-field periodic sequences. For example... Figure 5 As shown, a subfield cycle sequence contains M=16 subfield cycles. Each subfield cycle is designed to contain display time slots of J=8 different subfields, and these display time slots are arranged in the order of their respective subfields. For example, the first subfield cycle may contain display time slots of subfields 0 to 7 in sequence; the second subfield cycle may contain display time slots of subfields 1 to 8 in sequence; and so on.

[0056] In one possible implementation, J may not be equal to N.

[0057] like Figure 2 As shown, a display device has N=8 display partitions (rows), and a display frame is divided into I=16 subfields (e.g., subfield 0 to subfield 15). Rows 1 to 8 in the display frame are all assigned to subfield 0 for display.

[0058] like Figure 6 As shown, a subfield cycle sequence contains M=8 subfield cycles. Each subfield cycle is designed to contain J=16 display time slots for different subfields, and these display time slots are arranged in the order of their respective subfields. For example, the first subfield cycle may contain display time slots for subfields 0 to 15 in sequence; the second subfield cycle may contain display time slots for subfields 1 to 0 in sequence; and so on.

[0059] When entering the M subfield cycles in the subfield cycle sequence, each row is displayed only within the display time slot corresponding to the subfield determined to be displayed. Specifically, within each subfield cycle, the display control device (or control device) can scan the rows sequentially at display time slot intervals based on the predetermined scanning order of the rows. Figure 5 As shown, in the first subfield cycle, the display control scans the first line in the first display time slot, and the subfield of the first display time slot is subfield 0. Figure 1 The first row is assigned to subfield 0 for display, so it can be controlled to be displayed in the first display time slot. The display control device scans the second row in the second display time slot, where the subfield is subfield 1. Figure 1 If the second row is assigned to subfield 0 for display, then the second display slot will not be used for display. This process continues, with the display control cyclically scanning the display rows. Only when a display row matches (corresponds to) a display slot will it be displayed.

[0060] like Figure 1 As shown, when the grayscale is 1, all 8 rows are displayed in 8 adjacent display time slots. After adopting the balanced scheduling and scattering display method in this embodiment, the 8 rows are scattered in 8 sub-field cycles, thereby realizing grayscale scattering.

[0061] In this way, by distributing the display time slots in a subfield to different subfield cycles and displaying them in the display time slots of the corresponding subfields in the display area, the temporal domain position of grayscale display is broken up, thereby improving the effective refresh rate and refresh uniformity of low grayscale and improving the display effect of low grayscale images.

[0062] In some embodiments, within M subfield cycles in each subfield cycle sequence, each display partition is displayed in the corresponding subfield display time slot, including: Within each subfield cycle, the correspondence between the subfield corresponding to the current display slot and the currently scanned display partition is determined sequentially based on the predetermined scanning order of the N display partitions, with the display slot as the scanning time interval unit for each display partition. In response to the subfield corresponding to the current display slot and the display partition currently being scanned, the currently scanned display partition is displayed.

[0063] In one possible implementation, the display partition may include display rows, and the predetermined scan order may include a forward row order. For example, as... Figure 2 As shown, the predetermined scan order can include a forward row order of row 1, row 2, row 3, etc.

[0064] In one possible implementation, the display partition may include display rows, and the predetermined scan order may include a reverse row order. For example, the predetermined scan order may include a reverse row order of row 8, row 7, row 6, etc.

[0065] In one possible implementation, the predetermined scan order of each subfield cycle in the subfield cycle sequence can be the same or different.

[0066] In one possible implementation, the predetermined scan order can be determined based on the subfield number corresponding to the first display slot of the subfield cycle. For example, if the subfield number corresponding to the first display slot is odd, then the predetermined scan order for that subfield cycle is forward row order; if the subfield number corresponding to the first display slot is even, then the predetermined scan order for that subfield cycle is reverse row order. Alternatively, if the subfield number corresponding to the first display slot is even, then the predetermined scan order for that subfield cycle is forward row order; if the subfield number corresponding to the first display slot is odd, then the predetermined scan order for that subfield cycle is reverse row order.

[0067] For example, if the subfield number corresponding to the first display slot is odd, then the subfield cycle can be scanned forward in the order of row 1 → row 2 → ... → row 8; if the subfield number corresponding to the first display slot is even, then the subfield cycle can be scanned backward in the order of row 8 → row 7 → ... → row 1.

[0068] In different subfield cycles, the line scanning direction alternates (round-trip scanning), and the initial conditions for precharging the lines differ: During forward scanning (line 1 → line N), line 1 is scanned first, and the voltage accumulated by the parasitic capacitance during frame blanking is the highest, resulting in the greatest precharging side effect. During reverse scanning (line N → line 1), line N is scanned first, but the parasitic capacitance of line 1 has already been discharged by the intermediate lines, reducing the precharging side effect. Thus, round-trip scanning ensures that each line experiences the "first line condition" once and the "last line condition" once in two adjacent subfield cycles, and the color cast effect caused by precharging is naturally balanced after averaging the two.

[0069] Specifically, the display controller can be configured to trigger a scan operation at the beginning of each display time slot, thereby ensuring that the scanning process of the display partition is strictly aligned with the display time slot.

[0070] In each display time slot, the controller identifies the display partition currently being scanned according to the predetermined scanning order and determines the subfield to which the current display time slot belongs, in order to determine whether the expected correspondence exists.

[0071] In one possible implementation, the controller can also pre-calculate and store a detailed timing control sequence, which includes which display partition is scanned in each display time slot, and the corresponding subfields in the display time slot and display partition. At runtime, the controller reads and executes the sequence one by one to efficiently determine the correspondence.

[0072] The subfield corresponding to the current display time slot corresponds to the display partition being scanned. This can include situations where the subfield corresponding to the current display time slot and the display partition being scanned are assigned to the same subfield. Here, the subfield can be identified using a subfield number.

[0073] The subfield corresponding to the current display slot corresponds to the currently scanned display partition, and only the currently scanned display partition will be displayed. Here, displaying the display partition may include the controller controlling the display driver to drive the display partition.

[0074] For example, such as Figure 2 As shown, assume a display device has N=8 display partitions (rows), and a display frame is divided into I=16 subfields (e.g., subfield 0 to subfield 15). Rows 1 to 8 in the display frame are all assigned to subfield 0 for display.

[0075] The display duration of the display frame is divided into multiple sub-field periodic sequences. Figure 5 As shown, a subfield period sequence contains M=16 subfield periods. Each subfield period is designed to contain J=8 display time slots for different subfields, and these display time slots are arranged in the order of their respective subfields.

[0076] The controller scans one row in each display time slot in the row scanning order of row 1, row 2, row 3… That is, row 1 is scanned in the first display time slot of the first subfield cycle, and the subfield of the first display time slot is subfield 0. Figure 2 Row 1 is assigned to subfield 0 for display, so the two correspond to each other, and the controller can display row 1 in one of the first display slots.

[0077] In some embodiments, the method further includes: If the subfield corresponding to the current display time slot does not correspond to the display partition being scanned, no display will be made in the current display time slot.

[0078] The subfield corresponding to the current display time slot does not correspond to the display partition being scanned. This can include situations where the subfield corresponding to the current display time slot is different from the subfield assigned to the display partition being scanned. Here, the subfield can be identified using a subfield number.

[0079] For example, with Figure 5 For example, the controller scans one row in each display time slot in the row scanning order of row 1, row 2, row 3, etc.

[0080] The controller scans line 2 in the second display time slot of the first subfield cycle. The subfield of the second display time slot is subfield 1. Figure 2 Row 2 is assigned to subfield 0 for display. The second display time slot is a subfield that does not correspond to the first one. The controller can choose not to display in the second display time slot.

[0081] In this way, the display device can achieve precise control over the display process of multiple display zones and multiple subfields. By using the display time slot as the unit of scanning time interval and dynamically determining the correspondence between the subfield corresponding to the current display time slot and the currently scanned display zone based on a predetermined scanning order, each display zone can be displayed only within its assigned specific subfield and time slot.

[0082] In some embodiments, each subfield cycle includes J subfield sequence numbers that cycle through adjacent subfields and each corresponding display time slot, and the J display time slots in each subfield cycle are set according to the subfield sequence number order of the corresponding J adjacent subfields.

[0083] Specifically, the J cyclically adjacent subfields can be selected from all I (e.g., 16) subfields, arranged according to their subfield numbers (e.g., from 0 to I-1), by choosing J subfields that are consecutive in number or consecutive in a cyclic sense. Cyclic adjacency means that if the subfield number reaches the maximum value I-1 (e.g., 15), the next adjacent subfield is number 0.

[0084] The J subfields can be determined by a starting subfield number (or first subfield number) and a step size. For example, if the starting subfield number is X, then the J subfields can be X, X+1, X+2, ..., X+J-1; where % represents modulo. Alternatively, a lookup table for subfield numbers can be predefined, which specifies a set of J cyclically adjacent subfield numbers for each subfield cycle.

[0085] The arrangement order of the J display time slots is determined by the ascending (or descending) order of the subfield numbers of the J subfields they correspond to. For example, if the subfield numbers of the J subfields are X, X+1, X+2, ..., X+J-1, then within a subfield cycle, the display time slot order is to first display the display time slot corresponding to subfield X, then the display time slot corresponding to subfield X+1, and so on.

[0086] For ease of understanding, the I subfields can be viewed as a circular sequence, and the J subfields contained in each subfield cycle can be a continuous segment of this circular sequence. The arrangement order of the J display time slots within each subfield cycle is directly determined based on the subfield sequence number of their corresponding J cyclically adjacent subfields.

[0087] For example, such as Figure 5 As shown, a subfield periodic sequence contains M=16 subfield periods. Each subfield period is designed to contain J=8 display slots for different subfields. Figure 5 As shown, the subfields of the J display time slots within each subfield cycle are arranged in order of subfield number. Furthermore, from the 1st subfield cycle to the 16th subfield cycle, the subfield numbers of the J display time slots are cyclically shifted.

[0088] In some embodiments, the subfield sequence number corresponding to the first display time slot among the J display time slots in each subfield cycle includes: The subfield number corresponding to the first display slot in the J display slots within each subfield cycle is represented by the following expression (1): (1) Where m represents the subfield cycle number, X represents the subfield sequence number of the first display time slot in the J display time slots within the m-th subfield cycle, M represents the total number of subfield cycles, and k represents the interval step size between the subfield sequence numbers of the first display time slot in the J display time slots corresponding to two adjacent subfield cycles, where k is a positive integer.

[0089] By using the modulo operation of expression (1), the calculated subfield number X always falls within the range of valid subfield numbers, thus realizing the cyclical use of subfield numbers. The subfield number of the first display slot exhibits a regular and predictable jumping pattern within M subfield cycles.

[0090] When k is 1, it is possible to achieve cyclic shifting of J display time slots within M subfield cycles, with the starting subfield number of the J display time slots in each subfield cycle increasing sequentially. In this way, the starting subfields are shifted regularly between each subfield cycle, and the subfield sequence of different subfield cycles forms a cyclically increasing relationship.

[0091] For example, such as Figure 5 As shown, I is 8, J is 8, M is 16, and N is 16. In the 16 subfield cycles, the sequence number of each subfield is used as the starting subfield sequence number of the J display time slots in each subfield cycle, thereby achieving uniform dispersion of the subfields and thus dispersion of low grayscale.

[0092] like Figure 5 As shown, I is 8, J is 16, M is 8, and N is 16. In the 8 subfield cycles, the sequence number of the 8 subfields is used as the starting subfield sequence number of the J display time slots in each subfield cycle, thereby realizing the dispersion of subfields and thus the dispersion of low grayscale.

[0093] Here, the interval step size can be set based on actual needs. The smaller k is, the higher the uniformity of grayscale dispersion; the larger k is, the smaller the timing switching overhead.

[0094] In this way, by adjusting the subfield period corresponding to the subfield sequence number of the display time slot in the subfield period, the uniformity of grayscale dispersion can be adjusted based on actual needs to meet the requirements of different scenarios.

[0095] In some embodiments, the display frame satisfies a first condition, k=1, wherein the first condition includes: the proportion of pixels in the display frame whose grayscale value is less than or equal to a low grayscale threshold is greater than a first proportion, k=1; Alternatively; the display frame satisfies the second condition, k=4, wherein the second condition includes: the proportion of pixels with grayscale values ​​greater than the low grayscale threshold in the display frame is greater than the second proportion, k=4; Alternatively; the display frame does not satisfy the first condition and the second condition, k=2.

[0096] The step size k is a parameter used to determine the subfield number of the first display time slot in the J display time slots within each subfield cycle. When k=1, it means that the subfield number corresponding to the first display time slot in adjacent subfield cycles increases continuously, which can improve the uniformity of grayscale dispersion. When k=4, it means that the subfield number corresponding to the first display time slot in adjacent subfield cycles increases in leaps (modulo M), which can reduce timing switching and reduce overhead. When k=2, it means that the step size is 2, achieving a balance between dispersion uniformity and timing switching overhead.

[0097] The controller can select different k values ​​based on the grayscale distribution characteristics of the display frame.

[0098] In one possible implementation, the low grayscale threshold can be 15, and the first and second ratios can both be 70%.

[0099] Therefore, when the displayed frame is mainly low grayscale (the proportion of pixels with a grayscale value ≤ 15 is > 70%): choose k=1 (smallest step size, most uniform dispersion); when the displayed frame has a uniform grayscale distribution: choose k=2; when the displayed frame is mainly high grayscale (the proportion of pixels with a grayscale value > 15 is > 70%): choose k=4 (larger step size, reduces dispersion overhead).

[0100] In an exemplary implementation, the following steps can be taken: select the step size k and display it.

[0101] Step A1: Calculate the grayscale distribution of the current display frame.

[0102] Step A2: Select the cyclic shift step size k based on the grayscale distribution.

[0103] Step A3: Determine the subfield output order according to the selected step size k. For example, the starting subfield of the kth subfield cycle is (m-1)×k mod N.

[0104] Step A4: Control the display panel to drive the display according to the determined sub-field sequence.

[0105] By using adaptive step size configuration, the cyclic shifting and scattering scheme can achieve the best display effect in different grayscale distribution scenarios. In low grayscale scenarios, step size k=1 ensures the maximum scattering uniformity, while in high grayscale scenarios, step size k=4 reduces unnecessary timing switching and lowers overhead.

[0106] For example, let's illustrate the subfield with a step size k=2 for the subfield cycle (taking 8 display time slots / subfield cycle and 16 subfield cycles as examples). Cyclic shift formula: The starting subfield number X of the m-th subfield cycle is X = (m-1) × 2 mod 16. Within the cycle, take 8 consecutive subfield numbers starting from the starting subfield (if it exceeds 15, return to 0 for shifting cycle).

[0107] The subfield output order of the 16 subfield cycles is shown in Table 1: Table 1

[0108] When k=2, the initial subfield set is {0, 2, 4, 6, 8, 10, 12, 14} (even-numbered only). The pattern repeats every 8 cycles, and is completely repeated twice within 16 cycles. Compared to the 16 different starting points with k=1, k=2 has only 8 different starting points, resulting in lower uniformity of dispersion, but a corresponding reduction in timing switching overhead. It is suitable for scenes with relatively uniform grayscale distribution.

[0109] The subfield with a step size k=2 is used to explain the subfield cycle (taking 8 display time slots / subfield cycle and 16 subfield cycles as examples). Cyclic shift formula: The starting subfield number X of the m-th subfield cycle is X = (m-1) × 4 mod 16. Within the cycle, take 8 consecutive subfield numbers starting from the starting subfield (if it exceeds 15, return to 0 for shifting cycle).

[0110] The subfield output order of the 16 subfield cycles is shown in Table 2: Table 2

[0111] When k=4, the initial subfield set is only {0, 4, 8, 12} (4 starting points), and the pattern repeats every 4 cycles, repeating completely 4 times within 16 cycles. It achieves the lowest uniformity of dispersion but also the lowest hardware timing switching overhead. It is suitable for scenes where the image is predominantly high grayscale (pixels with grayscale > 15 account for > 70%), where the proportion of low grayscale subfields is small, eliminating the need for extreme dispersion and prioritizing lower hardware overhead.

[0112] Table 3 shows a comparison of the uniformity of grayscale dispersion and the overhead when the interval step size k is 1, 2, and 4 respectively.

[0113] Table 3

[0114] Therefore, the larger k is, the sparser the initial subfield distribution, the shorter the repetition period, and the lower the uniformity of dispersion, but the lower the hardware overhead. By adaptively selecting the step size, the optimal balance between display effect and hardware overhead can be achieved in different grayscale distribution scenarios.

[0115] In some embodiments, the subfield number of the subfield corresponding to the first display time slot in the J display time slots within each subfield period is determined by: randomly setting the subfield number of the subfield corresponding to the first display time slot in the J display time slots within each subfield period, and the subfield number of the subfield corresponding to the first display time slot in the J display time slots within each subfield period being different.

[0116] Within each subfield cycle, the subfield number corresponding to the first display time slot out of the J display time slots is randomly set, ensuring that the subfield numbers corresponding to the first display time slot out of the J display time slots within each subfield cycle are different from each other. This ensures that the starting subfield number of each subfield cycle does not follow a fixed pattern, while guaranteeing that each subfield cycle has a unique starting subfield number within the M subfield cycles.

[0117] In some embodiments, the subfield number corresponding to the first display time slot in the J display time slots within each subfield period is adopted as follows: the subfield number corresponding to the first display time slot in the J display time slots for each of the M subfield periods is the bit inversion value of the subfield number of the I subfields arranged in sequence.

[0118] Bit reversal is an operation that inverts the bits of a binary number. For example, a 3-bit binary number 0001 (decimal 1) becomes 1110 (decimal 8) after reversal. Applying this operation to subfield indices can produce a non-linear but deterministic sequence, causing the subfield indices to be distributed in a specific, dispersed manner over M subfield periods. This further improves the uniformity of grayscale dispersion.

[0119] Taking 16 subfields and 16 subfield cycles as an example, after bit reversal, the subfield sequence number corresponding to the first display slot of each subfield cycle within the 16 subfield cycles is shown in Table 4 after bit reversal.

[0120] Table 4

[0121] Figure 7 This is a diagram illustrating the display positions of grayscale 1 in each row when the bit-inverted value after bit inversion using the subfield sequence number is used as the subfield sequence number corresponding to the first display slot of each subfield cycle. Compared to... Figure 5 , Figure 7 The grayscale is dispersed more evenly.

[0122] Figure 8 The diagram illustrates the display positions of each row of grayscale 1 when the subfield number is used as the bit-inverted value after bit inversion for the first display slot of each subfield period, which is divided into 16 subfields and 8 subfield periods (16 display gaps in each subfield period).

[0123] The specific steps of the low gray field dispersion driving method include: Step B1: Divide a display frame into 16 subfields in time (subfield 0 to subfield 15).

[0124] Step B2: Use 8 display time slots as 1 subfield cycle to form a total of 16 subfield cycles.

[0125] Step B3: Under the round-trip scanning sequence of line 1 → line 8 → line 1, determine the subfield output order of each subfield cycle according to the cyclic shift rule (the subfield order of different subfield cycles is cyclically shifted, and the starting subfield number is also increased as the subfield cycle number increases).

[0126] The subfield output order for the m-th subfield cycle is: subfield (m-1) mod 16, subfield ((m-1)+1) mod 16, ..., subfield ((m-1)+7) mod 16. m = 1, 2, ..., 16.

[0127] Step B4: For the determined 16 subfield cycles, shuffle the order of the starting subfields in each subfield cycle (e.g., by using a random method or by using bit reversal), thereby shuffling the 16 subfield cycles.

[0128] Step B5: Control the display panel to scan and drive the display according to the sub-field sequence determined by the cycle of each sub-field.

[0129] By using bit reversal values, the display time slots within the subfield can be further broken down, thereby breaking down the grayscale and improving the display effect of the display frame.

[0130] In some embodiments, one display time slot includes multiple grayscale clocks, and one grayscale clock is used to display one grayscale value; The method further includes: The grayscale value of the display frame is divided by the number of grayscale clock cycles of the display time slot, and the remainder is used to determine the first grayscale value of the remainder portion of the grayscale value of the display frame. One grayscale value is displayed for each display time slot. For the second grayscale value other than the remainder portion of the grayscale value of the display frame, Y grayscale values ​​are displayed in one display time slot, where Y is the number of grayscale clocks contained in the display time slot.

[0131] A display time slot is a unit of time within a display frame allocated to a specific display area for display. To achieve grayscale display, a display time slot can be further subdivided into multiple smaller clock cycles, known as grayscale clocks. Each grayscale clock is designed to control the duration for which a display unit is lit at a specific brightness level, thus representing one grayscale level. For example, a display time slot can contain eight grayscale clocks, each corresponding to one grayscale level of display.

[0132] Figure 9 for Figure 7 Enlarged views of neutron field period 1 and subfield period 4. (See attached image.) Figure 9 As shown, a display time slot can have multiple grayscale clocks (one grayscale clock is shown as arrow A or B), each grayscale clock is used to display one grayscale value. When the grayscale value is 1, row 1 can be displayed in a grayscale clock in the first display time slot (subfield number 0) of subfield period 1, and row 5 can be displayed in a grayscale clock in the middle display time slot (subfield number 0) of subfield period 4.

[0133] Figure 10 for Figure 8 Enlarged views of neutron field period 1 and subfield period 2. (See attached image.) Figure 10 As shown, a display time slot can have multiple grayscale clocks (one grayscale clock is shown as arrow C or D), and each grayscale clock is used to display one grayscale value. When the grayscale value is 1, row 1 can be displayed in a grayscale clock in the first display time slot (subfield number 0) of subfield period 1, and row 5 can be displayed in a grayscale clock in the middle display time slot (subfield number 0) of subfield period 2.

[0134] Figure 9 and Figure 10 When the grayscale value of the display frame is not 1, multiple grayscale clocks can be used to display it within one display time slot. For example, when the grayscale value is 2, two grayscale clocks can be used, so that the display of one line can be completed within one time slot.

[0135] When the display frame is a low grayscale, such as a grayscale value less than or equal to 15, a single display time slot can be used with only one grayscale clock. For example, when the grayscale value is 2, only one grayscale value can be displayed in one subfield periodic sequence, while two grayscale values ​​can be displayed through two subfield periodic sequences. Figure 5 As shown, within this subfield periodic sequence, row 1 displays only one grayscale value, and the other grayscale value of row 1 is displayed in the next subfield periodic sequence.

[0136] When the display frame is a high grayscale (e.g., grayscale greater than 15), if the grayscale value is greater than the number of grayscale clocks in a display time slot, multiple grayscale clocks can be used in one display time slot to display multiple grayscale values.

[0137] For example, if the number of grayscale clocks in a display slot is Y, the grayscale value of the display frame can be divided by the number of grayscale clocks Y in the display slot, and the remainder can be taken. The remainder can be considered as a low grayscale, and low grayscales can be displayed one grayscale value per display slot. Grayscale values ​​that are divisible by the number of grayscale clocks Y but not by the remainder can be considered as high grayscales, and high grayscales can be displayed multiple grayscale values ​​per display slot. For example, Y grayscale values ​​can be displayed per display slot. Furthermore, multiple sub-field periodic sequences can be used to display high grayscale values, with each sub-field periodic sequence displaying Y grayscale values.

[0138] Taking a grayscale value of 218 as an example, where one display slot comprises 13 grayscale clock cycles, the grayscale value of the display frame divided by the number of grayscale clock cycles Y in the display slot yields a quotient of 16 and a remainder of 10. The high grayscale value (13*16=208) is displayed sequentially across 16 sub-field cycles occupying 13 clock cycles, while the low grayscale value (10) is displayed sequentially across 16 sub-field cycles occupying 1 clock cycle. Here, for the high grayscale value, each sub-field cycle sequence can display 13 grayscale values, using 16 sub-field cycle sequences to complete the high grayscale display. For the low grayscale value, each sub-field cycle sequence can display 1 grayscale value, using 10 sub-field cycle sequences to complete the high grayscale display. In this way, the grayscale is dispersed across multiple sub-field cycle sequences within a single display frame, improving the grayscale dispersion effect.

[0139] This application embodiment also provides a display device for displaying dynamic and / or static images within the display area of ​​a display device, comprising: a control module, the control module being used for: Determine the subfield in which each display partition is displayed within the I subfields of a display frame, where each subfield includes N display time slots and each display time slot corresponds to one display partition; The display duration of the display frame is divided into at least one subfield cycle sequence. A subfield cycle sequence includes M subfield cycles set in chronological order. Each subfield cycle includes one display time slot of J different subfields. The display time slots in each subfield cycle are arranged in a predetermined order. M, N, I and J are positive integers, and J is less than or equal to I. Within each of the M sub-field cycles in each sub-field cycle sequence, each display partition is displayed in the corresponding sub-field display time slot.

[0140] In the described embodiments, the specific implementation of the control module can be found in the corresponding steps of the above method embodiments, and will not be repeated here.

[0141] This application also provides a display device, which is a chip-based display device capable of displaying partitioned spaces based on chip fragmentation. Figure 11 An exemplary schematic block diagram illustrating a display device according to one or more embodiments is provided. (Refer to...) Figure 11 The display device 1000 includes a display area 1001, a control device 1002, and a cascaded array of display driving devices connected to the display area 1001 and the control device 1002 respectively; the cascaded array of display driving devices includes one or more cascaded display driving devices 1003. The control device 1002 is used to implement the balanced scheduling and scattered display method as described in the above embodiments; The multiple display partitions in the display area 1001 constitute a display cluster; the display area includes one or more display clusters. Each of the display driver devices 1003 is connected to at least one of the display partitions, such that the display driver devices are cascaded together to connect the plurality of display partitions; and is used to drive the display of the display partitions.

[0142] In some examples, the display driver may be called by different names, such as display driver chip, chip, driver IC, etc. There is no restriction on the name here.

[0143] In this way, by using the display driver under the control of the control device, the display time slots in a subfield are distributed into different subfield cycles, and the display is performed in the display time slots of the corresponding subfield in the display area. This disperses the temporal position of the grayscale display, thereby improving the effective refresh rate and refresh uniformity of low grayscale, and improving the display effect of low grayscale images.

[0144] In one alternative embodiment, each of the display driving devices is connected to at least one of the display partitions in a preset manner according to the physical location distribution of the plurality of display partitions in the display area.

[0145] As a specific example, a row of display partitions within the display area corresponds to a segment of a cascaded string group of display drivers.

[0146] In the described embodiments, the control device 1002 can be implemented as a hardware circuit. Exemplarily, it can be gate circuits, logic circuits, etc., implemented on an integrated circuit, and / or various modules or units implemented in one or more processors. In one implementation, the processor can be a circuit with instruction reading, interpretation, execution, and processing capabilities, such as a Central Processing Unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a type of microprocessor), or a digital signal processor (DSP). In another implementation, the processor can implement certain functions through the logical relationships of the hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to achieve the above functions. In addition, a processor can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a Neural Network Processing Unit (NPU), a Tensor Processing Unit (TPU), a Deep Learning Processing Unit (DPU), etc.

[0147] In other examples, the control device 1002 can be implemented in a combination of hardware, firmware, and software. For instance, it can be implemented by a computer program instructing the relevant hardware. This computer program can be stored in a non-volatile computer-readable storage medium. The computer program includes computer instructions, and when a processor reads the computer program from the computer-readable storage medium, the processor executes the computer instructions to implement the functions of the control device described above.

[0148] In the described embodiments, the connection between the control device 1002 and the cascaded group of the display driver device can be a single-line or dual-line communication method, which can be configured according to actual needs.

[0149] This application also provides a display control device, which may also be referred to as a chip or chip system. Figure 12 Exemplary operating scenario diagrams illustrating a chip or chip system according to one or more embodiments. References Figure 12 The chip or chip system 8000 is used to drive the display of the display screen 9000 (the pattern shown on the display screen 9000 is not intended to limit this application, but is only an example of a display pattern of the display screen 9000), including: A memory storing instructions; and a processor configured to execute the instructions to implement the balanced scheduling and scattering display method as described in the above embodiments.

[0150] In the illustrated embodiments, the operating system running on the chip system 8000 may include, but is not limited to, Android, iOS, HarmonyOS, Linux, Windows, UnionTech UOS, Galaxy Kylin, Dragon Lizard, Zhongke Fangde, etc.

[0151] Display screen 9000 can display dynamic and / or static images based on the balanced scheduling and distribution display method described in the above embodiments. Display screen 9000, processor, etc., are as described above and will not be repeated here.

[0152] In some examples, Figure 13 This describes exemplary schematic block diagrams of a chip or chip system according to one or more embodiments. (Reference) Figure 13 The chip or chip system 8000 includes a processor, memory, network interface, display, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface of the chip or chip system is used for communication with external terminals (such as cascaded display drivers). The display of the chip or chip system can be a liquid crystal display (LCD) or an electronic ink display. The input devices can be a touch layer covering the display, buttons, a trackball, or a touchpad mounted on the chip or chip system casing, or an external keyboard, touchpad, or mouse.

[0153] Understandable, Figure 13 The structures shown are merely block diagrams of some structures related to the embodiments of this application and do not constitute a limitation on the chips or chip systems applied thereto in the embodiments of this application. Specific chips or chip systems may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0154] This application also provides a computer-readable storage medium storing computer instructions or programs that, when executed on a computer, cause the balanced scheduling and scattering display method described in the above embodiments to be executed.

[0155] The computer instructions or programs may also be in the form of, for example Figure 13 The chip or chip system shown operates on the device. The memory of the chip or chip system contains various program modules that make up the apparatus corresponding to the above-described balanced scheduling and scattering display method. When the computer program composed of these program modules is executed, it can perform the functions corresponding to the various steps in the balanced scheduling and scattering display method described in the above embodiments.

[0156] The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions may be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; or an optical medium, such as a digital video optical disc; or a semiconductor medium, such as a solid-state drive.

[0157] This application also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the balanced scheduling and distribution display method provided in the various implementations described above.

[0158] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory.

[0159] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in this application. Various modifications and changes can be made to the above embodiments without departing from the scope of this application. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A balanced scheduling and scattering display method, characterized in that, Applied to a display device, wherein the display device includes N display partitions, the method includes: Determine the subfield in which each display partition is displayed within the I subfields of a display frame, where each subfield includes N display time slots and each display time slot corresponds to one display partition; The display duration of the display frame is divided into at least one subfield cycle sequence. A subfield cycle sequence includes M subfield cycles set in chronological order. Each subfield cycle includes one display time slot of J different subfields. The display time slots in each subfield cycle are arranged in a predetermined order. M, N, I and J are positive integers, and J is less than or equal to I. Within each of the M sub-field cycles in each sub-field cycle sequence, each display partition is displayed in the corresponding sub-field display time slot.

2. The balanced scheduling and scattering display method according to claim 1, characterized in that, Within each of the M subfield cycles in each subfield cycle sequence, each display partition displays within the corresponding subfield's display time slot, including: Within each subfield cycle, the correspondence between the subfield corresponding to the current display slot and the currently scanned display partition is determined sequentially based on the predetermined scanning order of the N display partitions, with the display slot as the scanning time interval unit for each display partition. In response to the subfield corresponding to the current display slot and the display partition currently being scanned, the currently scanned display partition is displayed.

3. The balanced scheduling and scattering display method according to claim 2, characterized in that, The method further includes: If the subfield corresponding to the current display time slot does not correspond to the display partition being scanned, no display will be made in the current display time slot.

4. The balanced scheduling and scattering display method according to any one of claims 1 to 3, characterized in that, Each subfield cycle includes J subfield numbers that cycle through adjacent subfields and each corresponding to a display time slot. The J display time slots within each subfield cycle are set in order based on the subfield numbers of the corresponding J adjacent subfields.

5. The balanced scheduling and scattering display method according to claim 4, characterized in that, The subfield number corresponding to the first display time slot among the J display time slots in each subfield cycle is determined by one of the following: The subfield number corresponding to the first display slot in the J display slots within each subfield cycle is represented by the following expression: ； Where m represents the subfield cycle number, X represents the subfield sequence number of the first display time slot in the J display time slots within the m-th subfield cycle, M represents the total number of subfield cycles, and k represents the interval step size between the subfield sequence numbers of the first display time slot in the J display time slots corresponding to two adjacent subfield cycles, where k is a positive integer. The subfield number of the first display time slot in the J display time slots within each subfield cycle is randomly set, and the subfield number of the first display time slot in the J display time slots within each subfield cycle is different; The M subfield periods correspond to the subfield number of the first display time slot in the J display time slots, and are respectively the bit inversion values ​​of the sequentially arranged subfield numbers of the I subfields.

6. The balanced scheduling and scattering display method according to claim 5, characterized in that, The display frame satisfies a first condition, k=1, wherein the first condition includes: the proportion of pixels in the display frame whose grayscale value is less than or equal to the low grayscale threshold is greater than a first proportion, k=1; Alternatively; the display frame satisfies the second condition, k=4, wherein the second condition includes: the proportion of pixels with grayscale values ​​greater than the low grayscale threshold in the display frame is greater than the second proportion, k=4; Alternatively; the display frame does not satisfy the first condition and the second condition, k=2.

7. The balanced scheduling and scattering display method according to any one of claims 1 to 3, characterized in that, One of the display time slots includes multiple grayscale clocks, with one grayscale clock used to display one grayscale value; The method further includes: The grayscale value of the display frame is divided by the number of grayscale clock cycles of the display time slot, and the remainder is used to determine the first grayscale value of the remainder portion of the grayscale value of the display frame. One grayscale value is displayed for each display time slot. For the second grayscale value other than the remainder portion of the grayscale value of the display frame, Y grayscale values ​​are displayed in one display time slot, where Y is the number of grayscale clocks contained in the display time slot.

8. A display device, characterized in that, The display device includes a display area, a control device, and a cascaded group of display driver devices connected to the display area and the control device respectively; the cascaded group of display driver devices includes one or more cascaded display driver devices. The control device is used to implement the balanced scheduling and scattered display method as described in any one of claims 1-7; The multiple display partitions in the display area constitute a display cluster; the display area includes one or more display partitions. Show cluster; Each of the display drivers is connected to at least one of the display partitions, such that the display drivers are cascaded. The group connects the multiple display partitions; And it is used to drive the display of the display partition.

9. A chip or chip system, characterized in that, The chip or chip system is used to drive the display on the display screen, including: Memory, which stores instructions; and A processor configured to execute the instructions to implement the balanced scheduling and scattering display method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions or programs that, when executed on a computer, cause the balanced scheduling and scattering display method as described in any one of claims 1-7 to be performed.

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