Display panel and driving method

Abstract

This application provides a display panel and a driving method. The display panel includes pixel circuits and a multiplexing circuit. The pixel circuits are located in the display area, and the multiplexing circuit is located in the non-display area. The multiplexing circuit includes a first control module and a second control module. The input terminal of the first control module receives a multiplexed signal, the first control terminal of the first control module receives a first control signal, the second control terminal of the first control module receives a second control signal, the output terminal of the first control module is electrically connected to the input terminal of the second control module, the first control terminal of the second control module receives a third control signal, the second control terminal of the second control module receives a fourth control signal, and the first output terminal and the second output terminal of the second control module transmit the multiplexed signal to different pixel circuits through signal transmission lines. This application reduces the number of transistors in the pixel circuit by setting up a multiplexing circuit, thereby improving the PPI.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and driving method. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a display panel and a driving method, which aims to improve the performance of the display panel.

[0005] This application provides a display panel, including a display area and a non-display area surrounding at least a portion of the display area. The display panel includes a pixel circuit and a multiplexing circuit. The pixel circuit is located in the display area, and the multiplexing circuit is located in the non-display area. The multiplexing circuit is electrically connected to the pixel circuit through a signal transmission line.

[0006] The multiplexing circuit includes a first control module and a second control module. The input terminal of the first control module is connected to a multiplexed signal, the first control terminal of the first control module is connected to a first control signal, the second control terminal of the first control module is connected to a second control signal, the output terminal of the first control module is electrically connected to the input terminal of the second control module, the first control terminal of the second control module is connected to a third control signal, the second control terminal of the second control module is connected to a fourth control signal, and the first output terminal and the second output terminal of the second control module transmit the multiplexed signal to different pixel circuits through signal transmission lines, respectively.

[0007] In one specific embodiment, the third control terminal of the second control module is connected to the fifth control signal, and the first output terminal, the second output terminal, and the third output terminal of the second control module transmit the multiplexed signal to different pixel circuits through signal transmission lines.

[0008] In one specific embodiment, a plurality of pixel circuit arrays are arranged, and the plurality of pixel circuits include at least a first pixel circuit, a second pixel circuit, and a third pixel circuit, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are in the same row but different columns; The second control module is turned on in response to the third control signal, and the first output terminal of the second control module transmits the multiplexed signal to the first pixel circuit through the signal transmission line. And / or, The second control module is turned on in response to the fourth control signal, and the second output terminal of the second control module transmits the multiplexed signal to the second pixel circuit through the signal transmission line. And / or, The second control module is turned on in response to the fifth control signal, and the third output terminal of the second control module transmits the multiplexed signal to the third pixel circuit through the signal transmission line.

[0009] In one specific embodiment, the first control module includes a first selection unit and a second selection unit; The first terminal of the first selection unit is connected to a multiplexed signal, the second terminal of the first selection unit is electrically connected to the first node, and the control terminal of the first selection unit is connected to a first control signal; the first terminal of the second selection unit is connected to a multiplexed signal, the second terminal of the second selection unit is electrically connected to the first node, and the control terminal of the second selection unit is connected to a second control signal. The second control module includes a first transmission unit, a second transmission unit, and a third transmission unit; The first end of the first transmission unit, the first end of the second transmission unit, and the first end of the third transmission unit are all electrically connected to the first node. The second end of the first transmission unit transmits the multiplexed signal to the first pixel circuit through a signal transmission line. The control end of the first transmission unit is connected to a third control signal. The second end of the second transmission unit transmits the multiplexed signal to the second pixel circuit through a signal transmission line. The control end of the second transmission unit is connected to a fourth control signal. The second end of the third transmission unit transmits the multiplexed signal to the third pixel circuit through a signal transmission line. The control end of the third transmission unit is connected to a fifth control signal. Further, the first selection unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the first selection unit, the second electrode of the first transistor serving as the second terminal of the first selection unit, and the gate of the first transistor serving as the control terminal of the first selection unit; the second selection unit includes a second transistor, the first electrode of the second transistor serving as the first terminal of the second selection unit, the second electrode of the second transistor serving as the second terminal of the second selection unit, and the gate of the second transistor serving as the control terminal of the second selection unit; the first transmission unit includes a third transistor, the first electrode of the third transistor serving as the first terminal of the first transmission unit, the second electrode of the third transistor serving as the second terminal of the first transmission unit, and the gate of the third transistor serving as the control terminal of the first transmission unit; the second transmission unit includes a fourth transistor, the first electrode of the fourth transistor serving as the first terminal of the second transmission unit, the second electrode of the fourth transistor serving as the second terminal of the second transmission unit, and the gate of the fourth transistor serving as the control terminal of the second transmission unit; the third transmission unit includes a fifth transistor, the first electrode of the fifth transistor serving as the first terminal of the third transmission unit, the second electrode of the fifth transistor serving as the second terminal of the third transmission unit, and the gate of the fifth transistor serving as the control terminal of the third transmission unit.

[0010] In one specific embodiment, the waveform of the first control signal is the same as the waveform of the second control signal, and the end time of the conduction level of the first control signal is earlier than the start time of the conduction level of the second control signal. The third, fourth, and fifth control signals all include a first conduction level and a second conduction level. The first conduction level is located before the second conduction level. The pulse widths of the first conduction level of the third control signal, the fourth control signal, and the fifth control signal are the same and overlap. The pulse widths of the second conduction level of the third control signal, the fourth control signal, and the fifth control signal are the same, do not overlap, and are sequentially shifted. Furthermore, the pulse width of the first conduction level is greater than the pulse width of the second conduction level; Furthermore, the conduction level pulse width of the first control signal or the conduction level pulse width of the second control signal is the same as and overlaps with the first conduction level pulse width; Furthermore, the conduction level of the second control signal overrides the second conduction level.

[0011] In one specific embodiment, the pixel circuit includes a sixth transistor, a first capacitor, a second capacitor, a seventh transistor, and a light-emitting device; The first terminal of the first capacitor is electrically connected to the gate of the sixth transistor; the second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor at the second node; the second terminal of the second capacitor is electrically connected to the first terminal of the sixth transistor; the first terminal of the seventh transistor is electrically connected to the signal transmission line; the second terminal of the seventh transistor is electrically connected to the second node; the gate of the seventh transistor is connected to the second scan signal; and the first terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting device. Furthermore, the conduction level of the second scan signal covers the conduction level of the first control signal, the conduction level of the second control signal, the first conduction level, and the second conduction level.

[0012] In one specific embodiment, the pixel circuit further includes an eighth transistor, a ninth transistor, and a tenth transistor; The first terminal of the eighth transistor is electrically connected to the gate of the sixth transistor, the second terminal of the eighth transistor is electrically connected to the second terminal of the sixth transistor, and the gate of the eighth transistor is connected to a third scan signal; the first terminal of the ninth transistor is connected to a first power supply voltage, the second terminal of the ninth transistor is electrically connected to the second terminal of the sixth transistor, and the gate of the ninth transistor is connected to a light-emitting control signal; the first terminal of the tenth transistor is connected to a second initialization signal, the second terminal of the tenth transistor is electrically connected to the first terminal of the light-emitting device, and the gate of the tenth transistor is connected to the first scan signal; the second terminal of the light-emitting device is connected to a second power supply voltage. Furthermore, the conduction level pulse width of the first scan signal is the same as that of the second scan signal, and the start and end times of the conduction level of the first scan signal are the same as those of the second scan signal.

[0013] In one specific embodiment, the multiplexed signal includes a first initialization signal and a data voltage. During the on-level of the first control signal or during the first on-level period, the multiplexed signal is the first initialization signal; during the on-level of the second control signal or during the second on-level period, the multiplexed signal is the data voltage.

[0014] This application embodiment also provides a driving method for driving the pixel circuit and multiplexing circuit in the above-mentioned display panel, the method including: In the first and second stages, the multiplexing circuit transmits the first initialization signal to different pixel circuits simultaneously, and the first initialization signal initializes the second node of different pixel circuits simultaneously. In the third stage, the multiplexing circuit transmits the data voltage sequentially to different pixel circuits. The data voltage is written to the second node of the pixel circuit and coupled to the gate of the sixth transistor through the first capacitor.

[0015] In one specific embodiment, the method further includes: In the first stage, the first power supply voltage initializes the gate of the sixth transistor, and the second initialization signal initializes the first electrode of the light-emitting device. In the second stage, the gate potential of the sixth transistor discharges to the second initialization signal to perform threshold compensation on the sixth transistor.

[0016] The technical solution provided in this application embodiment controls the input of data voltage and first initialization signal through a multiplexing circuit, and places the multiplexing circuit in the non-display area, so that the pixel circuit in the display area only needs one signal transmission line and one transistor to control the input of multiple signals. As a result, the number of transistors in the pixel circuit is reduced, the layout space is optimized, more pixel circuits can be set, which is beneficial to improving the pixel density (PPI) of the display panel.

[0017] It should be understood that the description in this section is not intended to identify key or important features of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a pixel circuit in the prior art; Figure 2 This is another pixel circuit in the prior art; Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is as follows; Figure 4 This is a schematic diagram of a display panel structure according to an embodiment of this application; Figure 5 This is a diagram of a multiplexing circuit architecture according to an embodiment of this application; Figure 6 This is another multiplexing circuit architecture diagram according to an embodiment of this application; Figure 7 This is another multiplexing circuit architecture diagram according to an embodiment of this application; Figure 8 This is a diagram of a multiplexing circuit structure according to an embodiment of this application; Figure 9 This is a pixel circuit structure diagram according to an embodiment of this application; Figure 10 This is a timing diagram of a write frame driver according to an embodiment of this application; Figure 11 This is a timing diagram for holding frame driving according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0023] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0024] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Moreover, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor is turned on when its gate is connected to a high level and turned off when its gate is connected to a low level.

[0025] With the continuous development of display panel technology, the types and methods of display panels are becoming increasingly diverse, and people's demands for display panels in various scenarios are also increasing. In a display panel, pixel circuits provide driving current to the light-emitting devices. The pixel circuits can be... Figure 1 The pixel circuit shown is a typical 2T1C pixel circuit, including a driving transistor M1, a data writing transistor M2, a storage capacitor C, and a light-emitting device. The first terminal of the driving transistor M1 is connected to the power supply voltage Vdd, the second terminal of the driving transistor M1 is electrically connected to the anode of the light-emitting device, the cathode of the light-emitting device is connected to the power supply voltage VSS, the gate of the driving transistor M1 is electrically connected to the first terminal of the data writing transistor M2, the second terminal of the data writing transistor M2 is connected to the data voltage Vdata, and the gate of the data writing transistor M2 is connected to the first scan signal scan1. The first terminal of the storage capacitor C is electrically connected to the gate of the driving transistor M1, and the second terminal of the storage capacitor C is connected to the power supply voltage Vdd. The driving transistor M1 generates a driving current based on the data voltage Vdata at its gate to drive the light-emitting device to emit light.

[0026] However, the 2T1C pixel circuit lacks threshold compensation, resulting in poor display quality. Therefore, the 7T1C pixel circuit with threshold compensation was further developed, such as... Figure 2As shown, the pixel circuit 7T1C includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a gate reset transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, an anode reset transistor M7, a storage capacitor C, and a light-emitting device. The first terminal of the first light-emitting control transistor M5 is connected to the power supply voltage Vdd. The second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M1. The second terminal of the driving transistor M1 is electrically connected to the first terminal of the second light-emitting control transistor M6. The second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device. The gates of both the first and second light-emitting control transistors are connected to the control signal em. The cathode of the light-emitting device is connected to the power supply voltage VSS. The first terminal of the data writing transistor M2 is connected to the data voltage Vdata. The second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M1. The gate of the data writing transistor M2 is connected to the first scan signal scan1. The first terminal of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor M1. The second terminal of threshold compensation transistor M3 is electrically connected to the second terminal of driving transistor M1. The gate of threshold compensation transistor M3 is connected to the first scan signal scan1. The first terminals of gate reset transistor M4 and anode reset transistor M7 are both connected to the reset voltage vref. The second terminal of gate reset transistor M4 is electrically connected to the gate of driving transistor M1. The second terminal of anode reset transistor M7 is electrically connected to the anode of the light-emitting device. The gate of gate reset transistor M4 is connected to the second scan signal scan2. The gate of anode reset transistor M7 is connected to the first scan signal scan1. The first terminal of storage capacitor C is electrically connected to the gate of driving transistor M1. The second terminal of storage capacitor C is connected to the power supply voltage vdd. Driving transistor M1 generates a driving current according to the data voltage vdata of its gate to drive the light-emitting device to emit light.

[0027] Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is illustrated below. The operation process of the pixel circuit is described as follows: Initial stage P0: This stage is the light-emitting stage of the previous display frame. The second scan signal scan2 and the first scan signal scan1 are both at high level, the control signal em is at low level, the driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, and the other transistors are turned off. The driving transistor M1 generates a driving current to drive the light-emitting device to emit light.

[0028] Reset Phase P1: Control signal em and the first scan signal scan1 are both high, the second scan signal scan2 is low, gate reset transistor M4 is turned on, the gate of driving transistor M1 is reset, and the potential V of the gate of driving transistor M1... G=vref; During the writing and compensation phase P2: the control signal em and the second scan signal scan2 are both high, the first scan signal scan1 is low, the anode reset transistor M7 is turned on, the anode of the light-emitting device is reset, and the anode potential V of the light-emitting device is... Anode =vref, the driving transistor M1, the data writing transistor M2, and the threshold compensation transistor M3 are turned on. The data voltage signal vdata passes sequentially through the data writing transistor M2, the driving transistor M1, and the threshold compensation transistor M3, charging the gate of the driving transistor M1 until the potential V of the gate of the driving transistor M1 is reached. G =vdata+Vth, and this potential is stored in the storage capacitor C.

[0029] Light-emitting stage P3: This stage is the light-emitting stage of the current display frame. The second scan signal scan2 and the first scan signal scan1 are both high, and the control signal em is low. Driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, while the remaining transistors are turned off, driving the light-emitting device to emit light. At this time, the light-emitting current... I OLED =(1 / 2) μ Cox (W / L) [(vdata+Vth)-vdd-Vth] 2 =(1 / 2) μ Cox (W / L) (vdata-vdd) 2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0030] However, the large number of transistors in the pixel circuit described above makes it difficult to meet users' demands for high PPI. Therefore, this application provides the following solution.

[0031] This application provides a display panel. Figure 4 This is a schematic diagram of a display panel structure according to an embodiment of this application, such as... Figure 4As shown, the display panel 400 includes a display area AA and a non-display area NA surrounding at least a portion of the display area AA. In this embodiment, the non-display area NA completely surrounds the display area AA. The display panel 400 includes a pixel circuit 100 and a multiplexing circuit 200. The pixel circuit 100 is located in the display area AA and is used to generate drive current. The multiplexing circuit 200 is located in the non-display area and is electrically connected to different pixel circuits 100 through a signal transmission line 300.

[0032] In one embodiment, Figure 5 This is a diagram of a multiplexing circuit architecture according to an embodiment of this application, such as... Figure 5 As shown, the multiplexing circuit 200 includes a first control module 201 and a second control module 202. The input terminal of the first control module 201 is connected to a multiplexed signal. In this embodiment, the multiplexed signal represents a different signal at different times; that is, the signal lines electrically connected to the input terminal of the first control module 201 transmit different signals in a time-division multiplexing manner. The first control terminal of the first control module 201 is connected to a first control signal MUX11, and the second control terminal of the first control module 201 is connected to a second control signal MUX22. The output terminal of the first control module 201 is electrically connected to the input terminal of the second control module 202. Under the control of the first control signal MUX11 and the second control signal MUX22, the first control module 201 transmits different multiplexed signals in a time-division multiplexing manner. The first control terminal of the second control module 202 is connected to the third control signal MUX1. Under the control of the third control signal MUX1, the second control module 202 outputs the multiplexed signal through the first output terminal to the signal transmission line 300, and then transmits it to the pixel circuit 100. The second control terminal of the second control module 202 is connected to the fourth control signal MUX2. Under the control of the fourth control signal MUX2, the second control module 202 outputs the multiplexed signal through the second output terminal to the signal transmission line 300, and then transmits it to another pixel circuit 100. In this embodiment, the selection input of different multiplexed signals is placed in the non-display area NA by the multiplexing circuit 200. The display area AA only needs one signal transmission line 300 and one transistor to control the input of different multiplexed signals, which reduces the number of transistors in the pixel circuit 100, optimizes the layout space, and allows for the setting of more pixel circuits 100, which is beneficial to improving the pixel density (PPI) of the display panel 400.

[0033] In one embodiment, the second control module 202 further includes a third control terminal and a third output terminal, such as... Figure 6As shown, the third control terminal of the second control module 202 is connected to the fifth control signal MUX3. Under the control of the fifth control signal MUX3, the second control module 202 outputs the multiplexed signal to the signal transmission line 300 through the third output terminal, and then transmits it to the third pixel circuit 100. It should be noted that in this embodiment, the three pixel circuits 100 electrically connected to the first output terminal, second output terminal, and third output terminal of the second control module 202 are located in the same row (X direction in the figure) but different columns (Y direction in the figure) in the array layout of the display panel 400. By setting the third control terminal and the third output terminal, this embodiment allows one multiplexer circuit 200 to output multiplexed signals to more pixel circuits 100, which helps to reduce the number of multiplexer circuits 200.

[0034] Continue to refer to Figure 4 The display area AA has multiple pixel circuits 100 arranged in an array. Every three consecutive columns (Y-direction in the diagram) of pixel circuits 100 form a group. The three columns of pixel circuits 100 are arranged sequentially in the row direction (X-direction in the diagram) as the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100. That is, each row in a group of pixel circuits 100 includes the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100. A multiplexer circuit 200 is electrically connected to the three columns of pixel circuits 100 via three signal transmission lines 300. The number of columns in each group of pixel circuits 100 varies with the number of output terminals of the second control module 202, and the number of columns in each group of pixel circuits 100 remains consistent with the number of output terminals of the second control module 202.

[0035] Specifically, the second control module 202 is turned on in response to the third control signal MUX1, and the first output terminal of the second control module 202 transmits the multiplexed signal to the first pixel circuit 100 through the signal transmission line 300. And / or, The second control module 202 is turned on in response to the fourth control signal MUX2, and the second output terminal of the second control module 202 transmits the multiplexed signal to the second pixel circuit 100 through the signal transmission line 300. And / or, The second control module 202 is turned on in response to the fifth control signal MUX3, and the third output terminal of the second control module 202 transmits the multiplexed signal to the third pixel circuit 100 through the signal transmission line 300.

[0036] Each pixel circuit 100 is independent of the others. The display area AA only needs one signal transmission line 300 and one transistor to control the input of different multiplexed signals, which reduces the number of transistors in the pixel circuit 100 and optimizes the layout space.

[0037] In one embodiment, Figure 7This is another multiplexing circuit architecture diagram according to an embodiment of this application, such as... Figure 7 As shown, the first control module 201 includes a first selection unit 2011 and a second selection unit 2012. The first terminal of the first selection unit 2011 is connected to a multiplexed signal, and the second terminal of the first selection unit 2011 is electrically connected to the first node M. The control terminal of the first selection unit 2011 is connected to a first control signal MUX11. The first terminal of the second selection unit 2012 is connected to a multiplexed signal, and the second terminal of the second selection unit 2012 is electrically connected to the first node M. The control terminal of the second selection unit 2012 is connected to a second control signal MUX22. The conduction times of the first selection unit 2011 and the second selection unit 2012 do not overlap.

[0038] Further, the second control module 202 includes a first transmission unit 2021, a second transmission unit 2022, and a third transmission unit 2023. The first end of the first transmission unit 2021, the first end of the second transmission unit 2022, and the first end of the third transmission unit 2023 are all electrically connected to the first node M. The second end of the first transmission unit 2021 transmits the multiplexed signal to the first pixel circuit 100 through the signal transmission line 300. The control end of the first transmission unit 2021 is connected to the third control signal MUX1. The second end of the second transmission unit 2022 transmits the multiplexed signal to the second pixel circuit 100 through the signal transmission line 300. The control end of the second transmission unit 2022 is connected to the fourth control signal MUX2. The second end of the third transmission unit 2023 transmits the multiplexed signal to the third pixel circuit 100 through the signal transmission line 300. The control end of the third transmission unit 2023 is connected to the fifth control signal MUX3.

[0039] In one embodiment, Figure 10 This is a timing diagram of a write frame driven according to an embodiment of this application, such as... Figure 10 As shown, the waveform of the first control signal MUX11 is the same as the waveform of the second control signal MUX22, and the end time of the conduction level of the first control signal MUX11 is earlier than the start time of the conduction level of the second control signal MUX22. That is, the first selection unit 2011 is turned on before the second selection unit 2012, and the conduction time of the first selection unit 2011 and the conduction time of the second selection unit 2012 do not overlap, so as to avoid mutual interference when transmitting different multiplexed signals.

[0040] Continue to refer to Figure 10The third control signal MUX1, the fourth control signal MUX2, and the fifth control signal MUX3 all include a first conduction level and a second conduction level. The first conduction level is located before the second conduction level. The pulse widths of the first conduction level of the third control signal MUX1, the fourth control signal MUX2, and the fifth control signal MUX3 are the same and overlap. The pulse widths of the second conduction level of the third control signal MUX1, the fourth control signal MUX2, and the fifth control signal MUX3 are the same, do not overlap, and are sequentially shifted. In a single write frame, the first transmission unit 2021, the second transmission unit 2022, and the third transmission unit 2023 are all turned on twice. The first turn-on time and duration of the first transmission unit 2021, the second transmission unit 2022, and the third transmission unit 2023 are all the same, allowing the multiplexed signal to be transmitted simultaneously to the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100 respectively. In addition, the duration of the second turn-on of the first transmission unit 2021, the second transmission unit 2022, and the third transmission unit 2023 is the same, but the second turn-on time of the first transmission unit 2021, the second transmission unit 2022, and the third transmission unit 2023 are different. This is a sequential delay shift setting, which realizes time-division multiplexing of the multiplexed signal to the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100 respectively, and the multiplexed signals transmitted to the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100 can be different from each other.

[0041] Continue to refer to Figure 10 The pulse width of the first conduction level is greater than the pulse width of the second conduction level. The pulse width of the conduction level of the first control signal MUX11 or the pulse width of the conduction level of the second control signal MUX22 is the same as and overlaps with the pulse width of the first conduction level. The conduction level of the second control signal MUX22 covers the second conduction level. Through the coordination of the conduction levels of the first control signal MUX11, the second control signal MUX22, the third control signal MUX1, the fourth control signal MUX2, and the fifth control signal MUX3, the multiplexing circuit 200 can transmit different multiplexed signals to different pixel circuits 100 simultaneously or in a time-division manner. This reduces the number of transistors in the pixel circuit 100, optimizes the layout space, and allows for the placement of more pixel circuits 100, which is beneficial for improving the pixel density (PPI) of the display panel 400.

[0042] In one embodiment, Figure 8 This is a diagram of a multiplexing circuit structure according to an embodiment of this application, such as... Figure 8As shown, the first selection unit 2011 includes a first transistor T1, the first electrode of the first transistor T1 serving as the first terminal of the first selection unit 2011, the second electrode of the first transistor T1 serving as the second terminal of the first selection unit 2011, and the gate of the first transistor T1 serving as the control terminal of the first selection unit 2011; the second selection unit 2012 includes a second transistor T2, the first electrode of the second transistor T2 serving as the first terminal of the second selection unit 2012, the second electrode of the second transistor T2 serving as the second terminal of the second selection unit 2012, and the gate of the second transistor T2 serving as the control terminal of the second selection unit 2012; the first transmission unit 2021 includes a third transistor T3, the first electrode of the third transistor T3 serving as the first terminal of the first transmission unit 2021, and the third… The second terminal of transistor T3 serves as the second terminal of the first transmission unit 2021, and the gate of the third transistor T3 serves as the control terminal of the first transmission unit 2021. The second transmission unit 2022 includes a fourth transistor T4, the first terminal of which serves as the first terminal, the second terminal of which serves as the second terminal, and the gate of which serves as the control terminal. The third transmission unit 2023 includes a fifth transistor T5, the first terminal of which serves as the first terminal, the second terminal of which serves as the second terminal, and the gate of which serves as the control terminal. For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors, and the semiconductor materials of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 all include p-Si (low-temperature polycrystalline silicon).

[0043] In this embodiment, the multiplexed signal includes a first initialization signal Vini and a data voltage Vdata, which can be provided by the chip IC. During the on-level of the first control signal MUX11 or during the first on-level, the multiplexed signal is the first initialization signal Vini; during the on-level of the second control signal MUX22 or during the second on-level, the multiplexed signal is the data voltage Vdata. Specifically, when the first transistor T1 is turned on in response to the first control signal MUX11, the first transistor T1 transmits the first initialization signal Vini to the first node M. At the same time, the third transistor T3 is turned on in response to the first on-level of the third control signal MUX1, and the third transistor T3 transmits the first initialization signal Vini to the first pixel circuit 100. The fourth transistor T4 is turned on in response to the first on-level of the fourth control signal MUX2, and the fourth transistor T4 transmits the first initialization signal Vini to the second pixel circuit 100. The fifth transistor T5 is turned on in response to the first on-level of the fifth control signal MUX3, and the fifth transistor T5 transmits the first initialization signal Vini to the third pixel circuit 100. When the second transistor T2 is turned on in response to the second control signal MUX22, it transmits the data voltage Vdata to the first node M. During this period, the third transistor T3 is turned on first in response to the second conduction level of the third control signal MUX1, and transmits the first data voltage Vdata to the first pixel circuit 100. The fourth transistor T4 is turned on next in response to the second conduction level of the fourth control signal MUX2, and transmits the second data voltage Vdata to the second pixel circuit 100. The fifth transistor T5 is turned on last in response to the second conduction level of the fifth control signal MUX3, and transmits the third data voltage Vdata to the third pixel circuit 100. In this embodiment, the first data voltage Vdata, the second data voltage Vdata, and the third data voltage Vdata can be the same or different.

[0044] In one embodiment, Figure 9 This is a pixel circuit structure diagram according to an embodiment of this application, such as... Figure 9As shown, the pixel circuit 100 includes a sixth transistor T6, a first capacitor C1, a second capacitor C2, a seventh transistor T7, and a light-emitting device, wherein the sixth transistor T6 is a driving transistor. The first terminal of the first capacitor C1 is electrically connected to the gate of the sixth transistor T6, the second terminal of the first capacitor C1 is electrically connected to the first terminal of the second capacitor C2 at the second node N, the second terminal of the second capacitor C2 is electrically connected to the first terminal of the sixth transistor T6, the first terminal of the seventh transistor T7 is electrically connected to the signal transmission line 300, the second terminal of the seventh transistor T7 is electrically connected to the second node N, and the gate of the seventh transistor T7 is connected to the second scan signal S2; the first terminal of the sixth transistor T6 is electrically connected to the first terminal of the light-emitting device. For example, both the sixth transistor T6 and the seventh transistor T7 are N-type transistors, and the semiconductor materials of both the sixth transistor T6 and the seventh transistor T7 include metal oxides, such as IGZO (indium gallium zinc oxide) and IZO (indium zinc oxide).

[0045] In this embodiment, the first initialization signal Vini and the data voltage Vdata are transmitted in a time-division manner through a signal transmission line 300 and a seventh transistor T7. This reduces the number of transistors connected to the second node N in the pixel circuit 100, optimizes the layout space, and allows for the setting of more pixel circuits 100, which is beneficial to improving the pixel density (PPI) of the display panel 400.

[0046] In this embodiment, the conduction level of the second scan signal S2 covers the conduction level of the first control signal MUX11, the conduction level of the second control signal MUX22, the first conduction level, and the second conduction level. That is, whether it is the transmission of data voltage Vdata or the first initialization signal Vini, it needs to be carried out during the conduction period of the seventh transistor T7.

[0047] Continue to refer to Figure 9The pixel circuit 100 also includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The first terminal of the eighth transistor T8 is electrically connected to the gate of the sixth transistor T6, and the second terminal of the eighth transistor T8 is electrically connected to the second terminal of the sixth transistor T6. The gate of the eighth transistor T8 is connected to a third scan signal Re. The first terminal of the ninth transistor T9 is connected to a first power supply voltage VDD, and the second terminal of the ninth transistor T9 is electrically connected to the second terminal of the sixth transistor T6. The gate of the ninth transistor T9 is connected to a light emission control signal EM. The first terminal of the tenth transistor T10 is connected to a second initialization signal Vref, and the second terminal of the tenth transistor T10 is electrically connected to the first terminal of the light-emitting device. The gate of the tenth transistor T10 is connected to a first scan signal S1. The second terminal of the light-emitting device is connected to a second power supply voltage VSS, and the voltage value of the second power supply voltage VSS is less than the voltage value of the first power supply voltage VDD. For example, the light-emitting device includes an OLED device. The eighth transistor T8 is an N-type transistor, and the semiconductor material of the eighth transistor T8 includes metal oxides, such as IGZO (indium gallium zinc oxide) and IZO (indium zinc oxide). The ninth transistor T9 and the tenth transistor T10 are both P-type transistors, and the semiconductor materials of the ninth transistor T9 and the tenth transistor T10 both include p-Si (low-temperature polycrystalline silicon). In this embodiment, the gate of the sixth transistor T6 is electrically connected to only one eighth transistor T8, and the second node N is also electrically connected to only one seventh transistor T7. This can effectively reduce the parasitic capacitance of the gate of the sixth transistor T6 and the second node N, and improve crosstalk and brightness uniformity.

[0048] In this embodiment, the conduction level pulse width of the first scan signal S1 is the same as that of the second scan signal S2, and the start and end times of the conduction level of the first scan signal S1 are the same as those of the second scan signal S2. This allows the second node N and the first electrode (anode) of the light-emitting device to be initialized for a sufficient amount of time, which helps to reduce image retention.

[0049] In this embodiment, the pixel circuit 100 includes only five transistors and two capacitors, which reduces the number of transistors in the pixel circuit 100, optimizes the array layout space, and is beneficial for achieving high PPI.

[0050] The following is combined Figure 10 right Figure 9 and Figure 8 The working process of the circuit in the diagram is described below: Phase 1 (t11): This is the initialization phase. The first control signal MUX11 is low, and the third, fourth, and fifth control signals MUX1, MUX2, and MUX3 are all at the first conduction level (low). The second control signal MUX22 is high, and the first transistor T1 is turned on, transmitting the first initialization signal Vini to the first node M. The third, fourth, and fifth transistors T3, T4, and T5 are simultaneously turned on, transmitting the first initialization signal Vini to the first pixel circuit 100, the second pixel circuit 100, and the third pixel circuit 100. The second scan signal S2 is high, and the seventh transistor T7 is turned on. The first initialization signal Vini initializes the second node N through the seventh transistor T7. N =Vini, the light emission control signal EM and the first scan signal S1 are both low, the third scan signal Re is high, the eighth transistor T8 and the ninth transistor T9 are turned on, the first power supply voltage VDD is transmitted to the gate of the sixth transistor T6 to initialize the gate of the sixth transistor T6, V g =VDD, the tenth transistor T10 is turned on, and the second initialization signal Vref is transmitted to the first electrode of the light-emitting device to initialize the first electrode of the light-emitting device. V anode =V s =Vref, the initialization time at this stage is adjustable to avoid generating additional power consumption.

[0051] Phase 2 t12: This is the threshold compensation phase. The light emission control signal EM jumps to a high level, the ninth transistor T9 is turned off, and the eighth transistor T8, the sixth transistor T6, and the tenth transistor T10 remain on. The gate potential of the sixth transistor T6 discharges to the second initialization signal Vref through the eighth transistor T8, the sixth transistor T6, and the tenth transistor T10, performing threshold compensation on the sixth transistor T6 until the gate potential V of the sixth transistor T6 is reached. g =Vref+Vth, the sixth transistor T6 stops conducting, the gate potential of the sixth transistor T6 stops discharging, the threshold compensation is completed, and the time of this stage is adjustable within one line time (the time for each pixel circuit to write the data voltage Vdata within one frame), improving brightness uniformity.

[0052] Phase 3 (t13): This is the data writing phase. The first control signal MUX11 is high, the second control signal MUX22 is low, and the second transistor T2 is turned on, transmitting the data voltage Vdata to the first node M. The third control signal MUX1, the fourth control signal MUX2, and the fifth control signal MUX3 sequentially switch to the second on-level (low level). The third transistor T3, the fourth transistor T4, and the fifth transistor T5 sequentially turn on. The third transistor T3 transmits the first data voltage Vdata to the first pixel circuit 100, the fourth transistor T4 transmits the second data voltage Vdata to the second pixel circuit 100, and the fifth transistor T5 transmits the third data voltage Vdata to the third pixel circuit 100. The third scan signal Re switches to low, the eighth transistor T8 is turned off, and the seventh transistor T7 remains on. The data voltage Vdata is transmitted to the second node N through the seventh transistor T7, and the potential of the second node N becomes V. N =Vdata, the potential difference ΔV at the second node N is Vdata-Vini, and the gate potential of the sixth transistor T6 is determined through the coupling effect of the first capacitor C1. V g =Vref+Vth+△V= Vref+Vth+ Vdata-Vini, at this time the tenth transistor T10 remains in the on state, V anode =V s =Vref, from which we can know the gate-source voltage difference V of the sixth transistor T6. gs = V g - V s = Vref+Vth+ Vdata-Vini- Vref= Vdata-Vini+Vth.

[0053] Phase 4 (t14): This is the light-emitting stage. The light-emitting control signal EM, the second scan signal S2, and the third scan signal Re are all low, while the remaining signals are high. The sixth transistor T6 and the ninth transistor T9 are turned on, and the light-emitting device emits light. The light-emitting current is... I OLED =(1 / 2) μ Cox (W / L) (V) gs -Vth) 2 =(1 / 2) μ Cox (W / L) (Vdata-Vini+Vth-Vth) 2 =(1 / 2) μ Cox (W / L) (Vdata-Vini) 2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0054] It should be noted that in this embodiment, the sum of the times of the first stage t11, the second stage t12, the third stage t13, and the fourth stage t14 is less than one row time. To ensure sufficient threshold compensation time for the sixth transistor T6, the time of the second stage t12 can be extended and the time of the third stage t13 can be shortened. Additionally, the time of the first stage t11 can be reduced to decrease the short-circuit loss between the first power supply voltage VDD and the second initialization signal Vref, thereby reducing power consumption.

[0055] The display panel 400 in this embodiment can display at high frequency or low frequency. When displaying at high frequency, the timing of each display frame is as follows: Figure 10 As shown; during low-frequency display, each display frame includes one write frame and at least one hold frame, and the timing of the write frame is as follows. Figure 10 As shown, the timing of the preserved frames is as follows Figure 11 As shown, Figure 11 This is a timing diagram of a hold-frame driving embodiment of the present application, which is described below in conjunction with... Figure 11 right Figure 9 and Figure 8 The working process of the circuit in the diagram is described below: Phase 1 t21: This is the initialization phase. The light emission control signal EM and the first scan signal S1 are high-frequency signals. The light emission control signal EM jumps to a high level, and the first scan signal S1 jumps to a low level. The remaining signals are low-frequency signals, maintaining the timing of the light emission phase when writing the frame. The ninth transistor T9 is turned off, and the tenth transistor T10 is turned on. The second initialization signal Vref is transmitted to the first electrode of the light-emitting device to initialize the first electrode of the light-emitting device. At this time, the voltage difference between the gate of the sixth transistor T6 and the first electrode of the sixth transistor T6 is relatively large, which is beneficial to adjust the threshold voltage of the sixth transistor T6 and can also improve the afterimage and flickering problems at low frequencies or frequency switching.

[0056] Second stage t22: This stage is the light emission stage. The light emission control signal EM jumps to a low level, the first scan signal S1 jumps to a high level, and the other signals remain unchanged. The sixth transistor T6 and the ninth transistor T9 are turned on, and the light emission device emits light. Its light emission current is consistent with the light emission current of the written frame.

[0057] This application embodiment also provides a driving method for driving the pixel circuit 100 and multiplexer circuit 200 in the above embodiments, the method comprising: In the first stage t11 and the second stage t12, the multiplexing circuit 200 simultaneously transmits the first initialization signal Vini to different pixel circuits 100, and the first initialization signal Vini simultaneously initializes the second node N of different pixel circuits 100. In the third stage t13, the multiplexing circuit 200 sequentially transmits the data voltage Vdata to different pixel circuits 100. The data voltage Vdata is written to the second node N of the pixel circuit 100 and coupled to the gate of the sixth transistor T6 through the first capacitor C1.

[0058] Furthermore, in the first stage t11, the first power supply voltage VDD initializes the gate of the sixth transistor T6, and the second initialization signal Vref initializes the first electrode of the light-emitting device. In the second stage t12, the potential of the gate of the sixth transistor T6 discharges to the second initialization signal Vref, and threshold compensation is performed on the sixth transistor T6.

[0059] The specific working process of this embodiment can be referred to Figure 8 and Figure 9 The operation of the circuit in the embodiment will not be described again here.

[0060] In this embodiment, the multiplexing circuit 200 controls the input of the data voltage Vdata and the first initialization signal Vini. The multiplexing circuit 200 is placed in the non-display area NA, so that the pixel circuit 100 in the display area AA only needs one signal transmission line 300 and one transistor to control the input of multiple signals. As a result, the number of transistors in the pixel circuit 100 is reduced, the layout space is optimized, and more pixel circuits 100 can be set, which is beneficial to improving the pixel density (PPI) of the display panel 400.

[0061] The display panel 400 of this application embodiment can be applied to mobile phones, or to any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets / watches, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This application embodiment does not make any special limitations on this.

[0062] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0063] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel comprising a display area and a non-display area surrounding at least a portion of the display area, characterized in that, The display panel includes a pixel circuit and a multiplexing circuit. The pixel circuit is located in the display area, and the multiplexing circuit is located in the non-display area. The multiplexing circuit is electrically connected to the pixel circuit through a signal transmission line. The multiplexing circuit includes a first control module and a second control module. The input terminal of the first control module is connected to a multiplexed signal, the first control terminal of the first control module is connected to a first control signal, the second control terminal of the first control module is connected to a second control signal, the output terminal of the first control module is electrically connected to the input terminal of the second control module, the first control terminal of the second control module is connected to a third control signal, the second control terminal of the second control module is connected to a fourth control signal, and the first output terminal and the second output terminal of the second control module respectively transmit the multiplexed signal to different pixel circuits through the signal transmission line.

2. The display panel according to claim 1, characterized in that, The third control terminal of the second control module is connected to the fifth control signal, and the first output terminal, the second output terminal, and the third output terminal of the second control module respectively transmit the multiplexed signal to different pixel circuits through the signal transmission line.

3. The display panel according to claim 2, characterized in that, The pixel circuit array is arranged in a plurality of ways, and the plurality of pixel circuits include at least a first pixel circuit, a second pixel circuit, and a third pixel circuit, wherein the first pixel circuit, the second pixel circuit, and the third pixel circuit are in the same row but different columns. The second control module is turned on in response to the third control signal, and the first output terminal of the second control module transmits the multiplexed signal to the first pixel circuit through the signal transmission line; And / or, The second control module is turned on in response to the fourth control signal, and the second output terminal of the second control module transmits the multiplexed signal to the second pixel circuit through the signal transmission line; And / or, The second control module is turned on in response to the fifth control signal, and the third output terminal of the second control module transmits the multiplexed signal to the third pixel circuit through the signal transmission line.

4. The display panel according to claim 3, characterized in that, The first control module includes a first selection unit and a second selection unit; The first terminal of the first selection unit is connected to the multiplexed signal, the second terminal of the first selection unit is electrically connected to the first node, and the control terminal of the first selection unit is connected to the first control signal; the first terminal of the second selection unit is connected to the multiplexed signal, the second terminal of the second selection unit is electrically connected to the first node, and the control terminal of the second selection unit is connected to the second control signal. The second control module includes a first transmission unit, a second transmission unit, and a third transmission unit; The first end of the first transmission unit, the first end of the second transmission unit, and the first end of the third transmission unit are all electrically connected to the first node. The second end of the first transmission unit transmits the multiplexed signal to the first pixel circuit through the signal transmission line. The control end of the first transmission unit is connected to the third control signal. The second end of the second transmission unit transmits the multiplexed signal to the second pixel circuit through the signal transmission line. The control end of the second transmission unit is connected to the fourth control signal. The second end of the third transmission unit transmits the multiplexed signal to the third pixel circuit through the signal transmission line. The control end of the third transmission unit is connected to the fifth control signal. Preferably, the first selection unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the first selection unit, the second electrode of the first transistor serving as the second terminal of the first selection unit, and the gate of the first transistor serving as the control terminal of the first selection unit; the second selection unit includes a second transistor, the first electrode of the second transistor serving as the first terminal of the second selection unit, the second electrode of the second transistor serving as the second terminal of the second selection unit, and the gate of the second transistor serving as the control terminal of the second selection unit; the first transmission unit includes a third transistor, the first electrode of the third transistor serving as the first terminal of the first transmission unit, the second electrode of the third transistor serving as the second terminal of the first transmission unit, and the gate of the third transistor serving as the control terminal of the first transmission unit; the second transmission unit includes a fourth transistor, the first electrode of the fourth transistor serving as the first terminal of the second transmission unit, the second electrode of the fourth transistor serving as the second terminal of the second transmission unit, and the gate of the fourth transistor serving as the control terminal of the second transmission unit; the third transmission unit includes a fifth transistor, the first electrode of the fifth transistor serving as the first terminal of the third transmission unit, the second electrode of the fifth transistor serving as the second terminal of the third transmission unit, and the gate of the fifth transistor serving as the control terminal of the third transmission unit.

5. The display panel according to claim 2, characterized in that, The waveform of the first control signal is the same as the waveform of the second control signal, and the end time of the conduction level of the first control signal is earlier than the start time of the conduction level of the second control signal. The third control signal, the fourth control signal, and the fifth control signal all include a first conduction level and a second conduction level. The first conduction level is located before the second conduction level. The pulse widths of the first conduction level of the third control signal, the fourth control signal, and the fifth control signal are the same and overlap. The pulse widths of the second conduction level of the third control signal, the fourth control signal, and the fifth control signal are the same, do not overlap, and are sequentially shifted. Preferably, the pulse width of the first conduction level is greater than the pulse width of the second conduction level; Preferably, the conduction level pulse width of the first control signal or the conduction level pulse width of the second control signal is the same as and overlaps with the first conduction level pulse width; Preferably, the conduction level of the second control signal covers the second conduction level.

6. The display panel according to claim 5, characterized in that, The pixel circuit includes a sixth transistor, a first capacitor, a second capacitor, a seventh transistor, and a light-emitting device; The first terminal of the first capacitor is electrically connected to the gate of the sixth transistor; the second terminal of the first capacitor is electrically connected to the first terminal of the second capacitor at the second node; the second terminal of the second capacitor is electrically connected to the first terminal of the sixth transistor; the first terminal of the seventh transistor is electrically connected to the signal transmission line; the second terminal of the seventh transistor is electrically connected to the second node; and the gate of the seventh transistor is connected to the second scan signal. The first terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting device. Preferably, the on-level of the second scanning signal covers the on-level of the first control signal, the on-level of the second control signal, the first on-level, and the second on-level.

7. The display panel according to claim 6, characterized in that, The pixel circuit also includes an eighth transistor, a ninth transistor, and a tenth transistor; The first terminal of the eighth transistor is electrically connected to the gate of the sixth transistor, and the second terminal of the eighth transistor is electrically connected to the second terminal of the sixth transistor. The gate of the eighth transistor is connected to a third scan signal. The first terminal of the ninth transistor is connected to a first power supply voltage, and the second terminal of the ninth transistor is electrically connected to the second terminal of the sixth transistor. The gate of the ninth transistor is connected to a light-emitting control signal. The first terminal of the tenth transistor is connected to a second initialization signal, and the second terminal of the tenth transistor is electrically connected to the first terminal of the light-emitting device. The gate of the tenth transistor is connected to the first scan signal. The second terminal of the light-emitting device is connected to a second power supply voltage. Preferably, the conduction level pulse width of the first scan signal is the same as the conduction level pulse width of the second scan signal, and the start time and end time of the conduction level of the first scan signal are the same as the start time and end time of the conduction level of the second scan signal.

8. The display panel according to claim 5, characterized in that, The multiplexed signal includes a first initialization signal and a data voltage. During the on-level of the first control signal or during the first on-level, the multiplexed signal is the first initialization signal. During the on-level period of the second control signal or the second on-level period, the multiplexed signal is a data voltage.

9. A driving method for driving the pixel circuit and multiplexing circuit in the display panel according to any one of claims 1-8, characterized in that, The method includes: In the first and second stages, the multiplexing circuit simultaneously transmits the first initialization signal to different pixel circuits, and the first initialization signal simultaneously initializes the second nodes of different pixel circuits. In the third stage, the multiplexing circuit sequentially transmits the data voltage to different pixel circuits, writes the data voltage to the second node of the pixel circuit, and couples the voltage containing the data voltage information to the gate of the sixth transistor through the first capacitor.

10. The driving method according to claim 9, characterized in that, The method further includes: In the first stage, the first power supply voltage initializes the gate of the sixth transistor, and the second initialization signal initializes the first electrode of the light-emitting device. In the second stage, the potential of the gate of the sixth transistor discharges to the second initialization signal to perform threshold compensation on the sixth transistor.

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