Display panel and display device

Abstract

This invention provides a display panel and display device, solving the problem of increased bezel width caused by the need for wiring around the perimeter due to the presence of a hole area in the prior art. The display panel provided in this disclosure has multiple cascaded first shift registers and multiple cascaded second shift registers arranged in the non-display areas on both sides of the display area along a first direction. The output terminals of each first shift register and each second shift register are connected to at least one row of pixel circuits on the same side. Therefore, for the pixel circuits surrounding the hole area, the necessary scanning signals can be directly obtained from the first and second shift registers on their respective sides, eliminating the need for signal wiring across the hole area and thus reducing the bezel width of the hole area.

Description

Technical Field

[0001] This invention relates to display panels, and more specifically to a display panel and a display device. Background Technology

[0002] In the field of display device technology, especially in display panels with punch-hole areas, how to minimize bezel width and optimize driving timing while implementing the driving control required by pixel driving circuits has always been a core requirement of the industry.

[0003] Current display panels often require a large number of traces to be laid out in the hole area to electrically connect the drive circuits located on both sides of the hole area, making it difficult to reduce the bezel size of the hole area. Summary of the Invention

[0004] In view of this, embodiments of the present invention aim to provide a display panel and a display device.

[0005] In a first aspect, the present invention provides a display panel including an aperture region, a display region, and a non-display region, wherein the non-display region at least partially surrounds the display region, the display region at least partially surrounds the aperture region, and the display region has a first side and a second side disposed opposite to each other in a first direction; the display panel further includes: a pixel circuit located within the display region, comprising a plurality of transistors; a plurality of cascaded first shift registers simultaneously arranged in the non-display regions located on the first and second sides of the display region, wherein the pixel circuit located on the first side of the aperture region is electrically connected to the first shift register located on the first side of the aperture region, and the pixel circuit located on the second side of the aperture region is electrically connected to the first shift register located on the second side of the aperture region; and a plurality of cascaded second shift registers simultaneously arranged in the non-display regions located on the first and second sides of the display region, wherein the pixel circuit located on the first side of the aperture region is electrically connected to the second shift register located on the first side of the aperture region, and the pixel circuit located on the second side of the aperture region is electrically connected to the second shift register located on the second side of the aperture region; wherein the first shift registers and the second shift registers respectively provide scanning signals to different transistors in the pixel circuit.

[0006] In some implementations, the first shift register is used to provide a scan signal to at least one row of pixel circuits; for example, the first-level first shift register simultaneously provides scan signals to at least one transistor in the Nth row of pixel circuits and at least one transistor in the N+1th row of pixel circuits, where N is an integer greater than or equal to 1.

[0007] In some embodiments, the pixel circuit includes: a driving transistor and a light-emitting device connected between a first power line and a second power line, wherein a first terminal of the driving transistor is connected to the first power line, a gate of the driving transistor is connected to a first node, and a second terminal of the light-emitting device is connected to the second power line; a storage capacitor, a first terminal of which is connected to the first power line, and a second terminal of which is connected to the first node; a threshold compensation transistor, a first terminal of which is connected to the second terminal of the driving transistor, and a second terminal of which is connected to the first node; a first initialization transistor, a first terminal of which is connected to a first initialization signal line, and a second terminal of which is connected to the first node; a second initialization transistor, a first terminal of which is connected to a second initialization signal line, and a second terminal of which is connected to the first terminal of the light-emitting device; and a data writing transistor, a first terminal of which is connected to a data line, and a second terminal of which is connected to the first terminal of the driving transistor.

[0008] In some implementations, the scan signal includes a first scan signal, a second scan signal, and a third scan signal; the output of the Nth-stage first shift register simultaneously provides the third scan signal to the gate of the second initialization transistor in the (N-2)th row pixel circuit, the second scan signal to the gate of the data write transistor and the gate of the threshold compensation transistor in the (N-1)th row pixel circuit, and the first scan signal to the gate of the first initialization transistor in the Nth row pixel circuit, where N is an integer greater than or equal to 3; exemplarily, the first-stage first shift register simultaneously provides the third scan signal to the gate of the second initialization transistor in multiple rows of pixel circuits; exemplarily, the scan signal further includes a fourth scan signal; the pixel circuit also includes a third initialization transistor, the first terminal of which is connected to the third initialization signal line, and the second terminal of which is connected to the first terminal of the driving transistor or the second terminal of the driving transistor; the output of the Nth-stage first shift register also simultaneously provides the fourth scan signal to the gate of the third initialization transistor in the (N-2)th row pixel circuit.

[0009] In some embodiments, the scan signal includes a first scan signal, a second scan signal, and a third scan signal; the pixel circuit further includes a third initialization transistor, the first terminal of which is connected to a third initialization signal line, and the second terminal of which is connected to the first terminal of a driving transistor, the second terminal of a driving transistor, or the first terminal of a light-emitting device; the output of the Nth-stage first shift register simultaneously provides a fourth scan signal to the gate of the third initialization transistor in the (N-2)th row pixel circuit, a second scan signal to the gate of the data writing transistor and the gate of the threshold compensation transistor in the (N-1)th row pixel circuit, a third scan signal to the gate of the second initialization transistor in the (N-1)th row pixel circuit, and a first scan signal to the gate of the first initialization transistor in the Nth row pixel circuit, wherein N is an integer greater than or equal to 3; exemplaryly, the output of the Nth-stage first shift register also simultaneously provides a fourth scan signal to the gate of the third initialization transistor in the (N-3)th row and at least one row of pixel circuits before the (N-3)th row, wherein N is an integer greater than or equal to 4.

[0010] In some implementations, the scan signal comprises at least three valid pulses within a display cycle.

[0011] In some embodiments, the pixel circuit further includes a light-emitting control transistor, and a second shift register is used to provide a light-emitting control signal to the gate of the light-emitting control transistor; exemplaryly, the light-emitting control transistor includes a first light-emitting control transistor and a second light-emitting control transistor, the first terminal of the first light-emitting control transistor is connected to a first power supply signal line, and the second terminal of the first light-emitting control transistor is connected to the first terminal of a driving transistor; the first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the light-emitting device; the second shift register is used to provide a light-emitting control signal to the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor.

[0012] In some implementations, a first-level second shift register is used to provide a light emission control signal to a row pixel circuit; within a display cycle, the time period corresponding to an invalid pulse of the light emission control signal covers the time periods corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the row pixel circuit; exemplarily, the time period corresponding to an invalid pulse of the light emission control signal is less than or equal to 10 times the row time.

[0013] In some implementations, a first-level second shift register is used to provide a light emission control signal to two adjacent rows of pixel circuits; within a display cycle, the time period corresponding to an invalid pulse of the light emission control signal covers the time period corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the two adjacent rows of pixel circuits; exemplarily, the time period corresponding to an invalid pulse of the light emission control signal is less than or equal to 10 times the row time.

[0014] The display panel disclosed herein comprises a plurality of cascaded first shift registers and a plurality of cascaded second shift registers in the non-display areas on both sides of the display area along a first direction. The output of each first shift register and the output of each second shift register are connected to at least one row of pixel circuits on the same side. Therefore, for the pixel circuits surrounding the aperture area, the necessary scanning signals can be directly obtained from the first and second shift registers on their respective sides, eliminating the need for signal routing across the aperture area and thus reducing the bezel width of the aperture area. Attached Figure Description

[0015] Figure 1 The figure shown is a plan view of a display panel provided in an embodiment of this disclosure.

[0016] Figure 2 The diagram shown is a structural diagram of a pixel circuit in a display panel according to an embodiment of this disclosure.

[0017] Figure 3A The diagram shown is a structural schematic of a display panel.

[0018] Figure 3B The diagram shows the driving timing of a pixel circuit in a display panel.

[0019] Figure 4 The diagram shown is a first structural schematic of a display panel provided in an embodiment of this disclosure.

[0020] Figure 5 The diagram shown is a structural diagram of another pixel circuit in a display panel according to an embodiment of this disclosure.

[0021] Figure 6 The diagram shown is a structural diagram of another pixel circuit in a display panel according to an embodiment of the present disclosure.

[0022] Figure 7 The diagram shown is a schematic diagram of the driving timing of a pixel circuit in a display panel according to an embodiment of this disclosure.

[0023] Figure 8 The diagram shown is a structural diagram of another pixel circuit in a display panel according to an embodiment of the present disclosure.

[0024] Figure 9 The diagram shown is a second structural schematic of a display panel provided in an embodiment of this disclosure.

[0025] Figure 10 The diagram shown is a driving timing diagram of a pixel circuit in a display panel according to an embodiment of this disclosure.

[0026] Figure 11 The diagram shown is a third structural schematic of a display panel provided in one embodiment of this disclosure.

[0027] Figure 12 The diagram shown is a driving timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0028] Figure 13 The diagram shown is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0032] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, the view of various elements parallel to the plane containing the X and Y directions is called the top view.

[0033] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element located in the Z direction, while "below" or "under" is used when describing an element located in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent but also the state where they are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0034] In active matrix organic light-emitting diode (OLED) display devices, in order to achieve image display, pixel circuits and driving circuits are usually used in combination. The driving circuit provides signals to the pixel circuits line by line to complete the compensation, writing and light emission operations of each row of pixels.

[0035] refer to Figure 1 The display panel typically includes a display area AA and a non-display area NA located around the display area AA. The pixel circuit 10 is located within the display area AA, and the driving circuit is located within the non-display area NA.

[0036] refer to Figure 2 Taking the 8T1C pixel circuit as an example, the pixel circuit 10 includes a data writing transistor T2, a driving transistor T1, a light-emitting device EL, a storage capacitor C1, a threshold compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, a third initialization transistor T8, a first light-emitting control transistor T5, and a second light-emitting control transistor T6.

[0037] A driving transistor T1 and a light-emitting device EL are connected between a first power line ELVDD and a second power line ELVSS. The driving transistor T1 can drive the light-emitting device EL to pass current according to the voltage of its gate. The first terminal of the driving transistor T1 is connected to the first power line ELVDD, and the gate of the driving transistor T1 is connected to the first node N1. The second terminal of the light-emitting device EL is connected to the second power line ELVSS. The first terminal of the storage capacitor C1 is connected to the first power line ELVDD, and the second terminal of the storage capacitor C1 is connected to the first node N1. A threshold compensation transistor T3 is connected between the second terminal of the driving transistor T1 and the first node N1 to compensate for the threshold voltage of the driving transistor T1.

[0038] The first initialization transistor T4 is connected between the first initialization signal line V1 and the first node N1, and is used to write the voltage on the first initialization signal line V1 into the gate of the driving transistor T1. The gate of the first initialization transistor T4 is connected to the first scan signal line S1.

[0039] The second initialization transistor T7 is connected between the second initialization signal line V2 and the first terminal of the light-emitting device EL, and is used to write the voltage on the second initialization signal line V2 into the first terminal of the light-emitting device EL. The gate of the second initialization transistor T7 is connected to the third scan signal line S3.

[0040] The first terminal of the data writing transistor T2 is connected to the data signal line Data, and the second terminal of the data writing transistor T2 is connected to the first terminal of the driving transistor T1. The gate of the data writing transistor T2 is connected to the second scan signal line S2.

[0041] The first light-emitting control transistor T5 is connected between the first power supply line ELVDD and the first terminal of the driving transistor T1. The second light-emitting control transistor T6 is connected between the second terminal of the driving transistor T1 and the light-emitting device EL. The gates of both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM.

[0042] The first terminal of the third initialization transistor T8 is connected to the first terminal of the driving transistor T1, and the second terminal of the third initialization transistor T8 is connected to the third initialization signal line V3 to initialize the voltage at the first terminal of the driving transistor T1. The gate of the third initialization transistor T8 is connected to the fourth scan signal line G.

[0043] The driving circuit includes a scan driving circuit 201, a light emission control driving circuit 202, and a high-frequency reset driving circuit 203. The scan driving circuit 201 provides scan signals to the first scan signal line S1 and the second scan signal line S2. The light emission control driving circuit 202 provides a light emission control signal to the light emission control signal line EM. The high-frequency reset driving circuit 203 simultaneously provides scan signals to the third scan signal line S3 and the fourth scan signal line G.

[0044] refer to Figure 1 and Figure 3A The scanning drive circuit 201 is disposed in the non-display area NA on both sides of the display area AA along the first direction (i.e., the X direction). The light emission control drive circuit 202 and the high-frequency reset drive circuit are respectively disposed in the non-display area NA on both sides of the display area AA along the first direction. That is, the light emission control drive circuit 202 is located in the non-display area NA on one side of the display area AA along the first direction, and the high-frequency reset drive circuit 203 is located in the non-display area NA on the other side of the non-display area NA along the first direction. In this way, only two rows of drive circuits are arranged in the non-display area NA on one side along the first direction, which can effectively reduce the width of the non-display area NA.

[0045] The arrangement of this driving circuit dictates that one unit in a light-emitting control driving circuit 202 needs to be electrically connected to all the pixel circuits 10 in at least one row. Simultaneously, one unit in a high-frequency reset driving circuit 203 needs to be electrically connected to all the pixel circuits 10 in at least one row.

[0046] However, when a display panel has a hole area HA, such as a partial hole formed in the display area AA to accommodate a camera or sensor, this traditional single-sided driving scheme faces a contradiction. The originally continuous signal lines around the hole area HA are forced to be interrupted. In order to pass the driving signal located on one side of the hole area HA around the hole area HA to the pixel circuit 10 on the other side, a long jumper wire needs to be arranged along the edge of the hole area HA. ​​This directly leads to the need for additional wiring space within the bezel of the hole area HA. ​​However, due to the presence of the hole area HA, the design requirement of the bezel to converge inward makes the available space very limited, creating a conflict between "the space required for wiring" and "the goal of a narrow bezel". Specifically, in a smart mobile terminal display panel containing a hole area HA, if all pixel circuits 10 are to be provided with signals by the driving circuit on the same side, the scanning signal lines of the hole area HA in the first direction must be routed around the edge of the hole area HA, thereby forcing an increase in the bezel width on both sides of the hole area HA, making it impossible to achieve a narrower bezel.

[0047] Additionally, refer to Figure 3B Within one display cycle, the scan signal output by the scan drive circuit 201 includes three valid pulses, for example, a low-level pulse. In the first initialization phase t1, the first scan signal line S1 is connected to a low-level signal, the first initialization transistor T4 is turned on, and the first node N1 is initialized, keeping the first node N1 at a low voltage.

[0048] During the threshold compensation and data writing stage t2, the second scan signal line S2 is connected to a low-level signal, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, the data signal on the data signal line is written to the first node N1 and stored in the storage capacitor C1.

[0049] During the reset phase t3, the third scan signal line S3 and the fourth scan signal line G are connected to a low-level signal, and the second initialization transistor T7 and the third initialization transistor T8 are turned on to initialize the first terminal of the driving transistor T1 and the first terminal of the light-emitting device EL.

[0050] During the light-emitting stage t4, since the light-emitting control signal line EM is at a low level, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The light-emitting element EL selects whether to turn on the driving transistor T1 to emit light based on the level signal stored in the storage capacitor C1. If the signal stored in the storage capacitor C1 is a low level signal, the driving transistor T1 is turned on to make the light-emitting element EL emit light; if the signal stored in the storage capacitor C1 is a high level signal, the driving transistor T1 is turned off and the light-emitting element EL does not emit light.

[0051] Specifically, the width of the effective pulse in the scan signals input to the third scan signal line S3 and the fourth scan signal line G is at least twice the width of the effective pulse in the scan signal input to the first scan signal line S1, to ensure the reliability of initializing the first electrode of the driving transistor T1. Simultaneously, in the initial phase of a display cycle, the scan signals input to the third scan signal line S3 and the fourth scan signal line G also include an effective pulse to initialize the first electrode of the driving transistor T1 before the first initialization phase t1.

[0052] It should be noted that within a display cycle, the time period corresponding to the invalid pulses of the light emission control signal must cover the time period corresponding to the valid pulses of the scan signals provided by the scan driving circuit 201, the light emission control driving circuit 202, and the high-frequency reset driving circuit 203 received by a row of pixel circuits. In other words, during the time period when the scan signals provided by the scan driving circuit 201, the light emission control driving circuit 202, and the high-frequency reset driving circuit 203 received by a row of pixel circuits have valid pulses, the light emission control signal consists of continuous invalid pulses.

[0053] The total time required to complete the scanning of one pixel circuit line is called the line time. The line time is related to the panel's refresh rate; the shorter the line time, the higher the refresh rate. One unit of line time is denoted as 1H. Within one display cycle, the time period required for the two pixel driving circuits to receive all scan signals (such as the scan signals connected to the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line G) is 10H. The time period corresponding to an invalid pulse of the light emission control signal must be greater than or equal to 10H.

[0054] To overcome the aforementioned contradictions, this invention proposes a solution. The core concept involves cascading multiple first shift registers and multiple cascading second shift registers within the non-display areas on both sides of the display area along a first direction. The output of each first shift register and the output of each second shift register are connected to at least one row of pixel circuits on the same side. Thus, for pixel circuits surrounding the aperture area, the necessary scanning signals can be directly obtained from the driving transistors on their respective sides, eliminating the need for signal routing across the aperture area. In other words, a dual-sided driving architecture is provided to solve the problem of increased bezel width caused by routing around the aperture area, achieving the technical effect of no routing around the aperture area while maintaining a narrow bezel on both sides.

[0055] The display panel provided in this application will be described below with reference to some specific implementation methods.

[0056] This application provides a display panel. A display panel is an electronic device used to display images, and it can be an organic light-emitting diode (OLED) display panel, a liquid crystal display panel, a micro light-emitting diode (Micro LED) display panel, or a quantum dot light-emitting diode (QLED) display panel, etc.

[0057] refer to Figure 1 A display panel typically includes an aperture area HA, a display area AA, and a non-display area NA. At least a portion of the non-display area NA surrounds the display area AA, and at least a portion of the display area AA surrounds the aperture area HA. ​​The display area AA, as referred to in this application, corresponds to the area used to arrange light-emitting pixels and actually display images. The non-display area NA surrounds the display area AA and is used to arrange traces, driving circuits, sealing structures, etc. The non-display area NA includes a bezel area NA1 and a dummy area NA2. The bezel area NA1 generally refers to the non-display area NA at the edge of the display panel and is used for encapsulation and trace connections. The dummy area NA2 is located between the bezel area NA1 and the display area AA, or near the interior of the display area AA, and is often used to place display driving-related circuit structures, such as shift registers and multiplexers. The circuitry in the dummy area NA2 may occupy the width of the bezel in a conventional layout.

[0058] The aperture area HA is the area inside the display area AA that is hollowed out or designed to be transparent, allowing light to pass through in order to place optical components such as cameras and sensors. The display area AA has a first side and a second side that are arranged opposite to each other in the first direction (i.e., the X direction). The display area AA is divided in the first direction into a display portion located on the first side of the aperture area HA and a display portion located on the second side of the aperture area HA.

[0059] refer to Figure 4 The display panel includes a pixel circuit 10, a plurality of first shift registers 20 and a plurality of second shift registers 30.

[0060] The pixel circuit 10 is located within the display area AA. The pixel circuit 10 includes multiple transistors, such as driving transistors, storage capacitors, data writing transistors, threshold compensation transistors, initialization transistors, and light-emitting control transistors. These transistors work together to generate a precise driving current.

[0061] Multiple first shift registers 20 are cascaded with each other, and multiple second shift registers 30 are cascaded with each other. Cascading means that multiple shift registers are connected in series according to the shift signal sequence, and the output or shift signal of the previous stage is passed to the next stage, thereby generating scan signals for each row in sequence. The first shift registers 20 and the second shift registers 30 are shift register units in digital circuits, which can be composed of multiple latches or flip-flops, etc., cascaded together. Under the control of the clock signal, they sequentially pass the input pulse edge to the next stage, thereby generating sequentially shifted output pulses. In this application, the circuit structure of the first shift registers 20 or the second shift registers 30 is not required, as long as it can perform the shifting and passing of the output signal according to the clock signal. Any circuit structure in the known technology can be used, and will not be described in detail in this application.

[0062] Both the first shift register 20 and the second shift register 30 are circuits that generate and output scan signals, but the scan signals provided by the first shift register 20 and the second shift register 30 to the pixel circuit 10 are used for different transistors. For example, the first shift register 20 typically outputs a scan signal to control data writing, threshold compensation, and some initialization operations; in this case, the first shift register 20 can act as a scan driving unit. For example, the second shift register 30 typically outputs a light emission control signal to provide a light emission control signal to the light emission control transistor to control the light emission element during the light emission period after the drive current is established; in this case, the second shift register 30 can act as a light emission control unit.

[0063] In the display panel provided in this application, the cascaded multiple first shift registers 20 are not only arranged in the dummy area NA2 on one side of the display area AA, but are simultaneously arranged in the two dummy areas NA2 located on the first and second sides of the display area AA. That is, a sequence of first shift registers 20 is provided in both the left and right dummy areas NA2 of the display area AA, and both sequences include several cascaded first shift registers 20. The pixel circuit 10 located on the first side of the aperture area HA is electrically connected to the first shift register 20 located on the first side of the aperture area HA, thereby obtaining the corresponding scan signal from the shift register on the same side. Similarly, the pixel circuit 10 located on the second side of the aperture area HA is electrically connected to the first shift register 20 located on the second side of the aperture area HA.

[0064] For the second shift register 30, the same dual-sided arrangement strategy is adopted, that is, multiple cascaded second shift registers 30 are simultaneously arranged in the dummy area NA2 on the first and second sides of the display area AA. The pixel circuit 10 located on the first side of the aperture area HA is electrically connected to the second shift register 30 located on that side, and the pixel circuit 10 located on the second side of the aperture area HA is also electrically connected to the second shift register 30 located on that side.

[0065] At this time, the pixel circuit 10 located on the first side of the aperture region HA receives scanning signals from the first shift register 20 and the second shift register 30 located on the first side, and the pixel circuit 10 located on the second side of the aperture region HA receives scanning signals from the first shift register 20 and the second shift register 30 located on the second side. Since the pixel circuits 10 located on both sides of the aperture region HA obtain scanning signals from the shift registers located close to themselves, the display panel does not need to be connected across the aperture region HA, which is beneficial for realizing the narrow bezel design of the aperture region HA, and shortens the signal delay and improves the integrity of the signal waveform. In addition, compared with the arrangement of the driving circuit in related technologies, this application uses the first shift register 20 to replace the driving unit of the high-frequency reset driving circuit and the driving unit of the scanning driving circuit, and uses the saved space to arrange the second shift register 30 without increasing the width of the bezel, thus optimizing the compactness of the display panel.

[0066] In some examples, the first-stage shift register 20 is used to provide scan signals to at least one row of pixel circuits 10. For example, the Nth-stage first-stage shift register 20 simultaneously provides scan signals to at least one transistor in the Nth row of pixel circuits 10 and at least one transistor in the (N+1)th row of pixel circuits 10. Here, N is an integer greater than or equal to 1. The scan signal is a pulse voltage signal that turns on the connected transistors within a specific time window to achieve corresponding initialization, data writing, or compensation functions. The significance of the first-stage first-stage shift register 20 simultaneously driving multiple rows of pixel circuits is that the load of the scan signal generated by the shift register is shared by multiple rows of pixel circuits, thus reducing the total number of stages of the shift registers in the same column, which is equivalent to driving more pixel rows with fewer shift registers. This helps to reduce the size of the overall driving circuit, reduce the integrated circuit area, and reduce dynamic power consumption.

[0067] In some examples, the first-level second shift register 30 is used to provide illumination control signals to at least one row of pixel circuits 10. For example, the first-level second shift register 30 provides illumination control signals to one row of pixel circuits 10. Another example is that the M-th level first shift register 20 provides illumination control signals to the pixel circuits 10 in rows 2M-1 and 2M. Here, M is an integer greater than or equal to 1.

[0068] In some possible implementations, refer to Figure 5The pixel circuit includes a data writing transistor T2, a driving transistor T1, a light-emitting device EL, a storage capacitor C1, a threshold compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, and a light-emitting control transistor. For example, the light-emitting control transistor includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6.

[0069] A driving transistor T1 and a light-emitting device EL are connected between a first power line ELVDD and a second power line ELVSS. The driving transistor T1 can drive the light-emitting device EL to pass current according to the voltage of its gate. The first terminal of the driving transistor T1 is connected to the first power line ELVDD, and the gate of the driving transistor T1 is connected to the first node N1. The second terminal of the light-emitting device EL is connected to the second power line ELVSS.

[0070] The first terminal of the storage capacitor C1 is connected to the first power line ELVDD, and the second terminal of the storage capacitor C1 is connected to the first node N1.

[0071] The first terminal of threshold compensation transistor T3 is connected to the second terminal of driving transistor T1, and the second terminal of threshold compensation transistor T3 is connected to the first node N1. Threshold compensation transistor T3 is used to compensate for the threshold voltage of driving transistor T1. The gate of threshold compensation transistor T3 is connected to the second scan signal line S2. For example, there are two threshold compensation transistors T3 connected in series, and the gates of both threshold compensation transistors T3 are connected to the second scan signal line S2.

[0072] The first terminal of the first initialization transistor T4 is connected to the first initialization signal line V1, and the second terminal of the first initialization transistor T4 is connected to the first node N1. The first initialization transistor T4 is used to write the voltage on the first initialization signal line V1 to the gate of the driving transistor T1. The gate of the first initialization transistor T4 is connected to the first scan signal line S1.

[0073] The first terminal of the second initialization transistor T7 is connected to the second initialization signal line V2, and the second terminal of the second initialization transistor T7 is connected to the first terminal of the light-emitting device EL. The second initialization transistor T7 is used to write the voltage on the second initialization signal line V2 into the first terminal of the light-emitting device EL. The gate of the second initialization transistor T7 is connected to the third scan signal line S3.

[0074] The first terminal of the data writing transistor T2 is connected to the data line Data, and the second terminal of the data writing transistor T2 is connected to the first terminal of the driving transistor T1. The gate of the data writing transistor T2 is connected to the second scan signal line S2. The second scan signal line S2 connected to the gate of the data writing transistor T2 and the second scan signal line S2 connected to the gate of the threshold compensation transistor T3 can be connected at the same location.

[0075] The first light-emitting control transistor T5 is connected between the first power supply line ELVDD and the first terminal of the driving transistor T1. The first terminal of the first light-emitting control transistor T5 is connected to the first power supply signal line ELVDD, and the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T1. The second light-emitting control transistor T6 is connected between the second terminal of the driving transistor T1 and the light-emitting device EL. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T1, and the second terminal of the second light-emitting control transistor T6 is connected to the first terminal of the light-emitting device EL. The gates of both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM, and the light-emitting control signal is provided through the second shift register 30.

[0076] The scanning signals include a first scanning signal, a second scanning signal, a third scanning signal, and a fourth scanning signal. The first scanning signal line S1 is connected to the first scanning signal, the second scanning signal line S2 is connected to the second scanning signal, the third scanning signal line S3 is connected to the third scanning signal, and the fourth scanning signal line G is connected to the fourth scanning signal.

[0077] In some examples, reference Figure 4 The output of the Nth-stage first shift register 20 simultaneously provides a third scan signal to the gate of the second initialization transistor T7 in the (N-2)th row pixel circuit 10, a second scan signal to the gate of the data write transistor T2 and the threshold compensation transistor T3 in the (N-1)th row pixel circuit 10, and a first scan signal to the gate of the first initialization transistor T4 in the Nth row pixel circuit 10. Here, N is an integer greater than or equal to 3.

[0078] In other words, the output of the first shift register 20 of the Nth stage simultaneously provides a second scan signal to the second scan signal line S2 in the (N-1)th row pixel circuit 10, provides a second scan signal to the first scan signal line S1 in the Nth row pixel circuit 10, and provides a third scan signal to the third scan signal line S3 in the (N-2)th row pixel circuit 10.

[0079] It should be noted that the Nth level first shift register 20 corresponds to the Nth row of pixel circuits 10. Considering that a row of pixel circuits 10 needs to receive different scan signals (such as the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal) provided by multiple levels of first shift registers 20 within one display cycle, the number of levels of the first shift registers 20 is greater than the number of rows of pixel circuits 10 in order to ensure that each row of pixel circuits 10 can receive different scan signals provided by multiple levels of first shift registers 20.

[0080] In this example, reference Figure 6Within one display cycle, the scan signal comprises at least three valid pulses. For example, a valid pulse is a low-level pulse.

[0081] Specifically, in the initialization phase t1, the scan signal line S1 is connected to a low-level signal, the first initialization transistor T4 is turned on, and the first node N1 is initialized, keeping the first node N1 at a low voltage. In the threshold compensation and data writing phase t2, the scan signal line S2 is connected to a low-level signal, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, and the data signal on the data signal line is written to the first node N1 and stored in the storage capacitor C1. In the reset phase t3, the second initialization transistor T7 is turned on, resetting the first terminal of the light-emitting element EL. In the light-emitting phase t4, since the light-emitting control signal line EM is in a low-level state, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The light-emitting element EL selects whether to turn on the driving transistor T1 to make the light-emitting element EL emit light based on the level signal stored in the storage capacitor C1. If the signal stored in the storage capacitor C1 is a low-level signal, the driving transistor T1 is turned on to make the light-emitting element EL emit light; if the signal stored in the storage capacitor C1 is a high-level signal, the driving transistor T1 is turned off, and the light-emitting element EL does not emit light.

[0082] For example, the first shift register 20 can simultaneously provide a scan signal to the gate of the second initialization transistor T7 of the multi-row pixel circuit 10 to reset the pixel circuits 10 of different rows.

[0083] For example, refer to Figure 2 and Figure 7 The pixel circuit also includes a third initialization transistor T8, the first terminal of which is connected to the first terminal of the driving transistor T1 (e.g., ...). Figure 2 ) or the second terminal of the driving transistor T1 (such as Figure 7 The second terminal of the third initialization transistor T8 is connected to the third initialization signal line V3 to initialize the voltage at the first terminal of the driving transistor T1. The gate of the third initialization transistor T8 is connected to the fourth scan signal line G.

[0084] refer to Figure 4 The output of the Nth-stage first shift register 20 also simultaneously provides a fourth scan signal to the gate of the third initialization transistor T8 (i.e., the fourth scan signal line G) in the (N-2)th row pixel circuit 10 to initialize the voltage in the (N-2)th row pixel circuit 10. At this time, the gate of the third initialization transistor T8 and the gate of the second initialization transistor T7 are connected at one point, that is, they share the same scan signal. In other words, the third scan signal and the fourth scan signal are the same signal.

[0085] In other examples, refer to Figure 2 , Figure 7 and Figure 8 In the case where the pixel circuit 10 also includes a third initialization transistor T8, the first terminal of the third initialization transistor T8 is connected to the third initialization signal line, and the second terminal of the third initialization transistor T8 is connected to the first terminal of the driving transistor T1 (e.g., ...). Figure 2 ), the second electrode of driving transistor T1 (such as Figure 7 ) or the first electrode of the light-emitting device EL (such as Figure 8 ).

[0086] refer to Figure 9 The output of the Nth-stage first shift register 20 simultaneously provides a fourth scan signal to the gate of the third initialization transistor T8 in the (N-2)th row pixel circuit 10, a second scan signal to the gates of the data write transistor T2 and the threshold compensation transistor T3 in the (N-1)th row pixel circuit 10, a third scan signal to the gate of the second initialization transistor T7 in the (N-1)th row pixel circuit 10, and a first scan signal to the gate of the first initialization transistor T4 in the Nth row pixel circuit 10. Here, N is an integer greater than or equal to 3.

[0087] In other words, the output of the first shift register 20 of the Nth stage simultaneously provides a fourth scan signal to the fourth scan signal line G in the (N-2)th row pixel circuit 10, a second scan signal to the second scan signal line S2 and a third scan signal to the third scan signal line S3 in the (N-1)th row pixel circuit 10, and a first scan signal to the first scan signal line S1 in the Nth row pixel circuit 10. At this time, the second scan signal and the third scan signal are the same scan signal, that is, the waveform and timing are exactly the same.

[0088] It should be noted that the Nth level first shift register 20 corresponds to the Nth row pixel circuit 10.

[0089] In this example, reference Figure 10 Within one display cycle, the scan signal comprises at least three valid pulses. For example, a valid pulse is a low-level pulse.

[0090] Specifically, in the initialization phase t1, the scan signal line S1 is connected to a low-level signal, the first initialization transistor T4 is turned on, and the first node N1 is initialized, keeping the first node N1 at a low voltage. In the threshold compensation and data writing phase t2, the scan signal line S2 is connected to a low-level signal, the data writing transistor T2 and the threshold compensation transistor T3 are turned on, and the data signal on the data signal line is written to the first node N1 and stored in the storage capacitor C1. In addition, in this phase, the scan signal line S3 is connected to a low-level signal, the second initialization transistor T7 is turned on, and the first terminal of the light-emitting element EL is reset. In the reset phase t3, the third initialization transistor T8 is turned on, and the first terminal of the driving transistor T1, the second terminal of the driving transistor T1, or the first terminal of the light-emitting element EL is reset. In the light-emitting phase t4, since the light-emitting control signal line EM is in a low-level state, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting element EL selects whether to turn on the driving transistor T1 to emit light according to the level signal stored in the storage capacitor C1. If the signal stored in the storage capacitor C1 is a low-level signal, the driving transistor T1 is turned on, causing the light-emitting element EL to emit light; if the signal stored in the storage capacitor C1 is a high-level signal, the driving transistor T1 is turned off, and the light-emitting element EL does not emit light.

[0091] For example, the output of the first shift register 20 of the Nth stage simultaneously provides a fourth scan signal to the gate of the third initialization transistor T8 in the pixel circuit 10 of row N-3 and preceding row N-3. Here, N is an integer greater than or equal to 4. At this time, in the reset phase t3, the first shift register 20 of the Nth row can also simultaneously reset the pixel circuit 10 of row N-3 and preceding row N-3.

[0092] In some implementations, the first-level second shift register 30 is used to provide a light-emitting control signal to one or two rows of pixel circuits 10. The light-emitting control signal is continuously activated during the time period when the pixel circuit 10 receives the scan signal, and the duration of the light-emitting control signal is the level width. The light-emitting control signal can be either a high-level signal or a low-level signal, depending on the type of light-emitting control transistor.

[0093] For example, refer to Figure 11 The first-level second shift register 30 provides a light-emitting control signal to the row pixel circuit 10. (Reference) Figure 12 Within a display cycle, the time period corresponding to the invalid pulse of the light emission control signal covers the time periods corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the row pixel circuit 10.

[0094] In other words, during the period when the first scan signal, second scan signal, third scan signal and fourth scan signal received by the row pixel circuit 10 have valid pulses, the light emission control signal is a continuous invalid pulse.

[0095] To more clearly illustrate the contents of this disclosure, a definition of line time is introduced. Line time refers to the total time required to complete the scanning of one pixel circuit line. Line time is related to the refresh rate of the panel; the shorter the line time, the higher the refresh rate. If the display panel includes N pixel circuit lines, then N... t represents the time required for the display panel to scan once from top to bottom, which is also the time required for the panel to refresh one frame, i.e., one frame time. One unit of line time is denoted as 1H. The duration of a single valid pulse among the first, second, third, and fourth scan signals is 1H. Within the timing sequence, some valid pulses from the first, second, third, and fourth scan signals overlap in timing; in this case, it can be considered that the pixel circuit of that line simultaneously receives valid pulses from different scan signals within the same line time.

[0096] Understandably, reference Figure 12 Although there is an interval between the first valid pulse connected to the first scan signal line S1 and the first valid pulse connected to the second scan signal line S2 in the diagram, this is because the scan signal waveform has been simplified. In reality, a valid pulse also has a rising edge and a falling edge. The interval between the first valid pulse connected to the first scan signal line S1 and the first valid pulse connected to the second scan signal line S2 is actually the rising edge of the first valid pulse connected to the first scan signal line S1 and the falling edge of the first valid pulse connected to the second scan signal line S2.

[0097] Within one display cycle, the time required for the row pixel circuit 10 to receive the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal is 7H (i.e., 7 times the row time), and the time period corresponding to the invalid pulse of the light emission control signal needs to be greater than or equal to 7H. For example, the time period corresponding to the invalid pulse of the light emission control signal is less than or equal to 10H (i.e., 10 times the row time), such as 10H, 9H, 8H, or 7H.

[0098] At this point, compared with the driving circuit in related technologies, the present invention can reduce the duration of invalid pulses in the light emission control signal, which helps to reduce the requirements for the light emission control signal traces.

[0099] It should be noted that, in this disclosure, the fourth scan signal line G includes at least three valid pulses within one display cycle, which can turn on the third initialization transistor T8 multiple times to initialize the pixel circuit. Therefore, it is not necessary to increase the pulse width of the scan signal provided to the fourth scan signal line G, and the reliability of initializing the pixel circuit can still be guaranteed.

[0100] For example, refer to Figure 9 The second shift register 30 provides light emission control signals to the two-row pixel circuit 10. (Reference) Figure 10 Within a display cycle, the time period corresponding to the invalid pulse of the light emission control signal covers the time periods corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the adjacent two rows of pixel circuits 10.

[0101] In other words, during the period when the first scan signal, second scan signal, third scan signal and fourth scan signal received by the two-row pixel circuit 10 have valid pulses, the light emission control signal is a continuous invalid pulse.

[0102] Within one display cycle, the time required for the two-line pixel circuit 10 to receive the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal is 8H (i.e., 8 times the line time), and the time period corresponding to the invalid pulse of the light emission control signal needs to be greater than or equal to 8H. For example, the time period corresponding to the invalid pulse of the light emission control signal is less than or equal to 10H (i.e., 10 times the line time), such as 10H, 9H, or 8H.

[0103] At this point, compared with the driving circuit in related technologies, the present invention can reduce the duration of invalid pulses in the light emission control signal, which helps to reduce the requirements for the light emission control signal traces.

[0104] In some possible implementations, refer to Figure 13 This application also provides a display device, which includes the display panel described in this application. The display device may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, automotive displays, wearable devices, etc. Because this display device includes the display panel described in this application, the electronic device has higher reliability.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized by, It includes a hole area, a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, the display area at least partially surrounds the hole area, and the display area has a first side and a second side disposed opposite to each other in a first direction; The display panel also includes: A pixel circuit, located within the display area, includes multiple transistors; Multiple cascaded first shift registers are simultaneously arranged in the non-display area located on the first side and the second side of the display area. The pixel circuit located on the first side of the hole area is electrically connected to the first shift register located on the first side of the hole area, and the pixel circuit located on the second side of the hole area is electrically connected to the first shift register located on the second side of the hole area. Multiple cascaded second shift registers are simultaneously arranged in the non-display area located on the first side and the second side of the display area. The pixel circuit located on the first side of the hole area is electrically connected to the second shift register located on the first side of the hole area, and the pixel circuit located on the second side of the hole area is electrically connected to the second shift register located on the second side of the hole area. The first shift register and the second shift register respectively provide scanning signals to different transistors in the pixel circuit.

2. The display panel of claim 1, wherein, The first shift register is used to provide a scan signal to at least one row of the pixel circuitry; Preferably, the first shift register of the first stage simultaneously provides the scan signal to at least one transistor in the pixel circuit of the Nth row and at least one transistor in the pixel circuit of the N+1th row, wherein N is an integer greater than or equal to 1.

3. The display panel according to claim 1, characterized in that, The pixel circuit includes: A driving transistor and a light-emitting device are connected between a first power line and a second power line, wherein the first electrode of the driving transistor is connected to the first power line, the gate of the driving transistor is connected to a first node, and the second electrode of the light-emitting device is connected to the second power line. A storage capacitor, wherein the first terminal of the storage capacitor is connected to the first power line, and the second terminal of the storage capacitor is connected to the first node; A threshold compensation transistor, wherein the first terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the threshold compensation transistor is connected to the first node; A first initialization transistor, wherein the first terminal of the first initialization transistor is connected to a first initialization signal line, and the second terminal of the first initialization transistor is connected to the first node; A second initialization transistor, wherein the first terminal of the second initialization transistor is connected to a second initialization signal line, and the second terminal of the second initialization transistor is connected to the first terminal of the light-emitting device; A data writing transistor is provided, wherein the first terminal of the data writing transistor is connected to a data line, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor.

4. The display panel of claim 3, wherein, The first shift register is used to provide scan signals to at least one row of pixel circuits, the scan signals including a first scan signal, a second scan signal and a third scan signal; The output of the first shift register in the Nth stage simultaneously provides the third scan signal to the gate of the second initialization transistor in the pixel circuit in the (N-2)th row, provides the second scan signal to the gate of the data write transistor and the gate of the threshold compensation transistor in the pixel circuit in the (N-1)th row, and provides the first scan signal to the gate of the first initialization transistor in the pixel circuit in the Nth row, where N is an integer greater than or equal to 3. Preferably, the first shift register of the first stage simultaneously provides the third scan signal to the gate of the second initialization transistor in the multiple rows of pixel circuits; Preferably, the scan signal further includes a fourth scan signal; the pixel circuit further includes a third initialization transistor, the first terminal of the third initialization transistor is connected to the third initialization signal line, and the second terminal of the third initialization transistor is connected to the first terminal of the driving transistor or the second terminal of the driving transistor; the output terminal of the first shift register of the Nth stage also simultaneously provides the fourth scan signal to the gate of the third initialization transistor in the pixel circuit of the (N-2)th row at least.

5. The display panel of claim 3, wherein, The first shift register is used to provide scan signals to at least one row of pixel circuits, the scan signals including a first scan signal, a second scan signal and a third scan signal; The pixel circuit further includes a third initialization transistor, the first terminal of which is connected to a third initialization signal line, and the second terminal of which is connected to the first terminal of the driving transistor, the second terminal of the driving transistor, or the first terminal of the light-emitting device; The output of the first shift register in the Nth stage simultaneously provides the fourth scan signal to the gate of the third initialization transistor in the pixel circuit in the (N-2)th row, provides the second scan signal to the gate of the data write transistor and the gate of the threshold compensation transistor in the pixel circuit in the (N-1)th row, provides the third scan signal to the gate of the second initialization transistor in the pixel circuit in the (N-1)th row, and provides the first scan signal to the gate of the first initialization transistor in the pixel circuit in the Nth row, where N is an integer greater than or equal to 3; Preferably, the output of the first shift register of the Nth stage also simultaneously provides the fourth scan signal to the gate of the third initialization transistor in the pixel circuit of the (N-3)th row and at least one row before the (N-3)th row, where N is an integer greater than or equal to 4.

6. The display panel of any one of claims 4 or 5, wherein, Within one display cycle, the scan signal comprises at least three valid pulses.

7. The display panel of claim 6, wherein, The pixel circuit also includes a light-emitting control transistor, and the second shift register is used to provide a light-emitting control signal to the gate of the light-emitting control transistor; Preferably, the light-emitting control transistor includes a first light-emitting control transistor and a second light-emitting control transistor. The first terminal of the first light-emitting control transistor is connected to the first power signal line, and the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor. The first terminal of the second light-emitting control transistor is connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control transistor is connected to the first terminal of the light-emitting device. The second shift register is used to provide light-emitting control signals to the gates of the first light-emitting control transistor and the second light-emitting control transistor.

8. The display panel of claim 7, wherein, The first-level second shift register is used to provide light emission control signals to the row pixel circuit; Within a display cycle, the time period corresponding to the invalid pulse of the light emission control signal covers the time periods corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the row pixel circuit; Preferably, the time period corresponding to the invalid pulse of the light emission control signal is less than or equal to 10 times the line time.

9. The display panel of claim 7, wherein, The second shift register in the first stage is used to provide light emission control signals to the adjacent two rows of pixel circuits; Within a display cycle, the time period corresponding to the invalid pulse of the light emission control signal covers the time periods corresponding to at least three valid pulses of the first scan signal, at least three valid pulses of the second scan signal, at least three valid pulses of the third scan signal, and at least three valid pulses of the fourth scan signal received by the adjacent two rows of pixel circuits. Preferably, the time period corresponding to the invalid pulse of the light emission control signal is less than or equal to 10 times the line time.

10. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1 to 9.

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