Field sequential backlight driving circuit, backlight module and display device

Abstract

This invention proposes a field-sequential backlight driving circuit, a backlight module, and a display device. The field-sequential backlight driving circuit includes a multiplexer, a switch array, a delay control network, and a voltage generation circuit. The multiplexer sequentially outputs multiple backlight enable signals based on a global enable signal and a channel switching signal. The switch array turns on the corresponding backlight LED strings in a time-division manner according to the backlight enable signals. The first delay control network of the delay control network provides a preset delay amount. The voltage generation circuit obtains a control voltage based on the partitioned brightness signal. The control voltage controls the second delay control network to provide a variable delay amount. The variable delay amount changes positively with the brightness represented by the partitioned brightness signal, realizing precise and controllable adjustment of the backlight signal delay. A simple timing logic architecture is built through the multiplexer, reducing circuit complexity and mass production costs. At the same time, it solves the problem of poor adaptability of existing fixed parameter compensation modes and improves the adaptability of compensation modes.

Description

Technical Field

[0001] This invention belongs to the field of field-sequence display technology, and particularly relates to a field-sequence backlight driving circuit, a backlight module, and a display device. Background Technology

[0002] Field-sequential display abandons the traditional spatial color mixing principle and adopts a time-multiplexed, time-division color mixing imaging method. The principle is based on the persistence of vision in the human eye, using high-speed temporal switching of red, green, and blue monochrome backlights to output monochrome images at different time dimensions, which are then superimposed and synthesized into a complete color image in the human visual system. Compared to traditional display technologies, field-sequential display eliminates the color filter film and sub-pixel segmentation structure within pixels. Each pixel is a complete and independent light-transmitting unit, eliminating the need for a filter film for color separation and significantly reducing light occlusion loss. The backlight utilization rate can be increased from the traditional 5% to 20%, resulting in significant energy-saving advantages. Simultaneously, the elimination of the need for a three-sub-pixel structure design allows for a significant increase in the effective pixel count of a screen of the same size, theoretically improving the display effect by three times. This easily achieves ultra-high pixel density displays, making it suitable for high-end automotive displays, virtual reality micro-displays, high-definition commercial large screens, and other high-end application scenarios, possessing broad market development prospects.

[0003] The imaging quality of field-sequence displays is highly dependent on the timing control precision and brightness adjustment consistency of the backlight driving system. As the control unit, the backlight driving circuit directly determines the switching sequence, conduction duration, and luminous brightness of the three-color backlight, which is crucial for ensuring uniformity and color accuracy in field-sequence displays. Currently, the mainstream field-sequence backlight driving solutions in the industry are mainly divided into two categories, but both types of solutions have obvious technical defects and cannot simultaneously achieve control precision, circuit cost, and image display stability.

[0004] The first type is a general voltage divider adjustment drive scheme. This scheme uses a single drive circuit to provide a unified drive voltage for the red, green, and blue backlight LED strings. Limited single-channel brightness adjustment is achieved only by connecting variable resistors in series in each LED string branch. This circuit has a simple structure, low hardware cost, and does not require a dedicated control chip, making it suitable for mass production applications in low-end display devices. However, this scheme shares the same voltage drive source for all three backlights, making independent voltage control of the three colors impossible. Brightness can only be fine-tuned by changing the resistance of passive components, resulting in extremely low adjustment precision. Furthermore, the adjustment range of the variable resistors is fixed, making it unsuitable for dynamic adjustment needs in different display zones and different screen brightness scenarios.

[0005] The second type is the application-specific integrated circuit (ASIC) driving solution. This solution uses a dedicated ASIC control chip to achieve independent driving and brightness control of the red, green, and blue backlights, effectively improving the brightness adjustment accuracy of the three-color backlights and alleviating color shift problems. However, the high hardware cost of ASICs significantly increases the mass production cost of display devices, hindering the large-scale popularization of the technology.

[0006] In addition to the aforementioned circuit architecture defects, existing field-sequence backlight driving technologies generally suffer from rigid timing compensation mechanisms, further hindering the improvement of display quality. In actual operation, the inherent differences in the luminescent materials, driving impedance, and response characteristics of the red, green, and blue LED strings lead to variations in the activation response speed and signal transmission delay of the three backlights. This inherent response difference causes a misalignment in the emission timing of the three backlights, resulting in an imbalance in the emission duration ratio of the three colors within a single frame. This, in turn, causes problems such as white balance shift, dynamic color fringing, and color distortion. Especially in scenarios with high screen refresh rates and drastic changes in screen brightness and contrast, the timing misalignment problem is amplified, severely damaging the consistency and purity of the displayed image.

[0007] To address the aforementioned timing discrepancy issue, existing technologies generally employ a fixed delay parameter compensation mode or a fixed PWM duty cycle adjustment mode, pre-setting a fixed signal delay amount to offset the response differences of the three-color LEDs. However, this compensation method has significant limitations; the preset delay parameter is a fixed constant, which can only adapt to a single fixed brightness condition and cannot adapt to the dynamic working scenarios of field-sequence displays with zone dimming.

[0008] In summary, current field-sequential backlight driving technologies suffer from numerous technical shortcomings, including low circuit control precision, high hardware costs, rigid timing compensation, poor adaptability of zoned brightness, and insufficient color consistency and stability. These limitations make it difficult to meet the application requirements of high-end field-sequential display devices, which demand high-precision timing control, adaptive dynamic compensation, and low-cost integration. Therefore, this paper proposes a field-sequential backlight timing adjustment method and circuit based on zoned brightness. Through a novel circuit architecture design, it achieves precise time-division driving of the three-color backlight and adaptive timing compensation for zoned brightness, effectively addressing the various shortcomings of existing technologies and improving the overall image quality and device compatibility of field-sequential displays. Summary of the Invention

[0009] The purpose of this invention is to provide a field-sequence backlight driving circuit, which aims to solve the problems of low control accuracy, high cost and low adaptability of timing compensation in traditional backlight driving schemes.

[0010] A first aspect of this invention provides a field-sequence backlight driving circuit, comprising: The multiplexer is configured to receive a global enable signal and a channel switching signal, and to sequentially output multiple backlight enable signals within the effective window of the global enable signal according to the channel switching signal. A switch array is connected to a multi-channel backlight string and the multiplexer. The switch array is used to turn on the corresponding backlight string in a time-division manner according to the multi-channel backlight enable signals received in sequence. A voltage generation circuit is configured to receive a partition brightness signal representing the brightness of a display partition, and convert the partition brightness signal into a control voltage, the amplitude of which is negatively correlated with the brightness represented by the partition brightness signal. The delay control network includes a first delay control network and a second delay control network. The first delay control network is connected to the voltage generation circuit and is used to provide a preset delay for the passing control voltage. The second delay control network is connected in series in at least one of the transmission paths of the backlight enable signal in the switch array. The second delay control network is used to provide a variable delay amount that is negatively correlated with the received control voltage for the passing backlight enable signal, so that the variable delay amount changes in a positive correlation with the brightness represented by the partition brightness signal.

[0011] Optionally, the switch array includes multiple switch circuits corresponding to multiple backlight strings. The control terminal of each switch circuit is connected to one output terminal of the multiplexer. Each switch circuit is connected in series in the power supply circuit of the corresponding backlight string to turn on the corresponding backlight string in a time-division manner according to the received backlight enable signal.

[0012] Optionally, in a static state, when the global enable signal is low, all the multiplexer backlight enable signals are set to low. When the global enable signal is high, the multiplexer enters the working state. Within the effective window when the global enable signal remains high, each edge transition of the channel switching signal triggers the multiplexer to perform a state transition, sequentially setting one backlight enable signal high to drive the corresponding switch circuit to conduct and light up the corresponding backlight string.

[0013] Optionally, the multiple backlight strings include red, green and blue light strings; The multi-channel backlight enable signal includes a red enable signal, a green enable signal, and a blue enable signal; The transmission paths of the red enable signal, the green enable signal, and the blue enable signal are respectively connected in series with the delay control network corresponding to the color channel; The first delay control network corresponding to each color channel includes a first resistor and a first capacitor; The first end of the first resistor is connected to the output end of the voltage generation circuit, the second end of the first resistor is connected to the first end of the first capacitor to form the output end of the first delay control network, and the second end of the first capacitor is grounded. Wherein, the first resistance in the red enable signal path is less than the first resistance in the green enable signal path, and the first resistance in the green enable signal path is less than the first resistance in the blue enable signal path.

[0014] Optionally, the second delay control network for each color channel includes a variable resistance transistor and a second capacitor; The variable resistance transistor operates in the linear region. The gate of the variable resistance transistor is connected to the output terminal of the voltage generation circuit. The drain of the variable resistance transistor is connected to the output terminal of the first delay control network corresponding to the color channel. The source of the variable resistance transistor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

[0015] Optionally, the voltage generation circuit includes: A low-pass filter, the input of which is used to receive the partition brightness signal, the partition brightness signal being a PWM signal whose duty cycle represents the brightness of the display partition, and the low-pass filter being used to convert the PWM signal into a DC voltage signal whose amplitude is positively correlated with the duty cycle of the PWM signal; An inverting amplifier is connected to the output of the low-pass filter. The inverting amplifier is used to receive the first reference voltage and the DC voltage signal, and output an intermediate voltage signal whose amplitude changes negatively with the DC voltage signal. The voltage conditioning circuit includes a voltage follower connected in series and a bidirectional clamping network. The voltage follower is used to isolate the inverting amplifier from the subsequent load, and the bidirectional clamping network is used to clamp the intermediate voltage signal within a preset voltage range defined by a second reference voltage and a third reference voltage to form the control voltage. The preset voltage range corresponds to the gate voltage range of the linear operating region of the variable resistor transistor.

[0016] Optionally, in the second delay control network corresponding to each color channel, the control terminal of the variable resistor transistor receives an independently biased control voltage.

[0017] Optionally, in the voltage generation circuit corresponding to each color channel, the first reference voltage and / or amplification factor of the inverting amplifier are different, so that different color channels generate control voltages with different amplitudes under the same partition brightness input, in order to compensate for the response time drift of backlight strings of different colors under different brightness.

[0018] A second aspect of the present invention provides a backlight module including a plurality of backlight units, each of the backlight units including multiple backlight LED strings and a field-sequence backlight driving circuit as described above, wherein the field-sequence backlight driving circuit is connected to the multiple backlight LED strings.

[0019] A third aspect of the present invention provides a display device, including a display panel and a backlight module as described above, wherein the display panel and the backlight module are disposed opposite to each other.

[0020] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned field-sequence backlight driving circuit includes a multiplexer, a switch array, a delay control network, and a voltage generation circuit. The multiplexer sequentially outputs multiple backlight enable signals according to the global enable signal and the channel switching signal. The switch array turns on the corresponding backlight lamp string in a time-division manner according to the backlight enable signal. The first delay control network of the delay control network provides a preset delay amount. The voltage generation circuit obtains a control voltage according to the partition brightness signal. The control voltage controls the second delay control network to provide a variable delay amount. The variable delay amount changes positively with the brightness represented by the partition brightness signal, realizing precise and controllable adjustment of the backlight signal delay. A simple timing logic architecture is built through the multiplexer, reducing circuit complexity and mass production costs. At the same time, it solves the technical defects of poor adaptability and low compensation accuracy of the existing fixed parameter compensation mode, and improves the adaptability of the compensation mode. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the field-sequence backlight driving circuit provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the field-sequence backlight driving circuit provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the signal waveform of the multiplexer provided in Embodiment 2 of the present invention; Figure 4 This is a circuit diagram of the switch array and backlight string provided in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the voltage generation circuit provided in Embodiment 2 of the present invention; Figure 6 This is a circuit diagram of the voltage generation circuit and delay control network provided in Embodiment 2 of the present invention; Figure 7This is a schematic diagram of the backlight module provided in Embodiment 3 of the present invention; Figure 8 This is a schematic diagram of the structure of the display device provided in Embodiment 3 of the present invention.

[0022] 1. Backlight unit; 2. Backlight module; 3. Display panel; 100. Field-sequence backlight drive circuit; 200. Backlight string; 10. Multiplexer; 20. Switch array; 30. Delay control network; 40. Voltage generation circuit; 50. Boost circuit; 21. Switching circuit; 31. First delay control network; 32. Second delay control network; 41. Low-pass filter; 42. Inverting amplifier; 43. Voltage conditioning circuit; 431. Voltage follower; 432. Bidirectional clamping network; Q1, First electronic switch transistor; Q2, Second electronic switch transistor; Q3, Third electronic switch transistor; Qd, Variable resistor transistor; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; L1, Inductor; D1, First diode; D2, Second diode; D3, Third diode; Rled, Red LED string; Bled, Blue LED string; Gled, Green LED string; U1, Operational amplifier; STV1, Global Enable Signal; STV2, Channel Switching Signal; EN, Backlight Enable Signal; Ctr1, Zone Brightness Signal; Vctr, Control Voltage; Ren, Red Enable Signal; Gen, Green Enable Signal; Ben, Blue Enable Signal; Ctr2, Boost Control Signal; VIN, Input Voltage; Vref1, First Reference Voltage; Vref2, Second Reference Voltage; Vref3, Third Reference Voltage. Detailed Implementation

[0023] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0024] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] Example 1 A first aspect of the present invention provides a field-sequence backlight driving circuit 100.

[0026] like Figure 1 As shown, in this embodiment, the field-sequence backlight driving circuit 100 includes: The multiplexer 10 is configured to receive the global enable signal STV1 and the channel switching signal STV2, and output multiple backlight enable signals EN sequentially within the effective window of the global enable signal STV1 according to the channel switching signal STV2. Switch array 20 is connected to multiple backlight string 200 and multiplexer 10. Switch array 20 is used to turn on the corresponding backlight string 200 in a time-division manner according to the multiple backlight enable signals EN received in sequence. The voltage generation circuit 40 is configured to receive the partition brightness signal Ctr1, which represents the brightness of the display partition, and convert the partition brightness signal Ctr1 into a control voltage Vctr. The amplitude of the control voltage Vctr is negatively correlated with the brightness represented by the partition brightness signal Ctr1. The delay control network 30 includes a first delay control network 31 and a second delay control network 32. The first delay control network 31 is connected to the voltage generation circuit 40 and is used to provide a preset delay amount for the passing control voltage Vctr. The second delay control network 32 is connected in series in the transmission path of at least one backlight enable signal EN of the switch array 20. The second delay control network 32 is used to provide a variable delay amount that is negatively correlated with the received control voltage Vctr for the passing backlight enable signal EN, so that the variable delay amount changes positively correlated with the brightness characterized by the partition brightness signal Ctr1.

[0027] In this embodiment, the multiplexer 10 serves as a timing control module, responsible for backlight channel switching and enable signal output. The multiplexer 10 is externally connected to two types of control signals: a global enable signal STV1 and a channel switching signal STV2. These two signals work together to complete the timing logic control of the three-color backlight.

[0028] The global enable signal STV1 acts as the master control switch for the entire backlight module 2, determining its overall start / stop state. Only within the time window when the global enable signal STV1 is active will the multiplexer 10 perform channel switching and signal output operations, ensuring the integrity and standardization of the backlight module 2's operating timing and preventing circuit malfunctions caused by invalid signal outputs. The channel switching signal STV2 is a state trigger signal used to drive the multiplexer 10 to complete channel state transitions, enabling polling and activation of different backlight channels.

[0029] The working logic of the multiplexer 10 is as follows: within the effective working window range defined by the global enable signal STV1, it continuously responds to the trigger action of the channel switching signal STV2. According to the level transition state of the channel switching signal STV2, it sequentially outputs multiple independent backlight enable signals EN. Each backlight enable signal EN drives an independent backlight string 200, ensuring that multiple backlight strings 200 are turned on in turn according to the preset timing, and there will be no crosstalk problem of multiple strings lighting up at the same time. This conforms to the imaging principle of time-division color mixing in field sequence display. Each color backlight string 200 is composed of multiple LED devices of the same color connected in series and parallel.

[0030] The switch array 20 is the execution driver module of this circuit. It is directly electrically connected to the multi-channel backlight string 200 and the multiplexer 10, serving as a bridge between the timing control module and the backlight emission module. The switch array 20 contains multiple independent switch units, each corresponding to one of the multiple output terminals of the multiplexer 10 and the multi-channel backlight string 200. It can accurately receive the backlight enable signals EN output by the multiplexer 10 and perform conduction and deactivation actions based on the level of the enable signals. During operation, the switch array 20 sequentially activates the corresponding backlight string 200 according to the output timing of the received multi-channel backlight enable signals EN, achieving orderly rotation of red, green, and blue backlights and providing stable hardware support for time-division multiplexing.

[0031] To address the issues of rigid timing compensation and inability to adapt to dynamic changes in partition brightness, a dual delay control mechanism and a voltage generation circuit 40 are added to the signal transmission path of the multi-channel switch array 20. The voltage generation circuit 40 serves as a signal conversion unit for adaptive dynamic compensation and is electrically connected to the delay control network 30. The voltage generation circuit 40 receives the partition brightness signal Ctr1, representing the brightness of each display partition on the screen, in real time at its input terminal. It converts the partition brightness signal Ctr1, representing the brightness level, into a continuously adjustable analog control voltage Vctr. The amplitude of the control voltage Vctr exhibits a negative correlation with the partition brightness represented by the partition brightness signal Ctr1; the higher the partition brightness value, the smaller the amplitude of the output control voltage Vctr; conversely, the lower the partition brightness value, the larger the amplitude of the output control voltage Vctr.

[0032] The delay control network 30 integrates two-level compensation units, namely the first delay control network 31 and the second delay control network 32. The two-level networks have distinct functions and independent signal links, and work together to complete static basic delay compensation and dynamic brightness-related delay compensation.

[0033] The first delay control network 31 is directly connected to the voltage generation circuit 40. The function of the first delay control network 31 is to apply a fixed preset delay amount to the transmission path of the control voltage Vctr. The preset delay amount is pre-calibrated based on the inherent response differences of the red, green and blue LED strings, and is used to eliminate the static timing offset caused by the different colored LED devices themselves, so as to provide a unified timing reference for subsequent dynamic compensation.

[0034] The second delay control network 32 is connected in series within the transmission path of at least one backlight enable signal EN in the switch array 20. The second delay control network 32 receives the control voltage Vctr after being calibrated by the first delay control network 31, and adjusts its own equivalent impedance according to the amplitude of the control voltage Vctr, thereby changing the transmission delay time of the backlight enable signal EN.

[0035] The variable delay provided by the second delay control network 32 is negatively correlated with the amplitude of the input control voltage Vctr. A larger Vctr amplitude results in a smaller variable delay, and vice versa. Combining the negatively correlated delay characteristics of the second delay control network 32, a positive correlation between the variable delay and the brightness of the display zones can be achieved. The variable delay corresponding to the high-brightness zones is larger, effectively compensating for timing deviations caused by increased LED driving current and exacerbated response drift under high-brightness conditions. The variable delay corresponding to the low-brightness zones is smaller, avoiding overcompensation issues associated with fixed delay compensation. This enables precise adaptive timing compensation across the entire brightness range and all display zones, completely resolving the technical shortcomings of existing fixed-parameter compensation modes, such as poor adaptability and low compensation accuracy.

[0036] The field-sequence backlight driver circuit 100 abandons the traditional single-voltage-source voltage divider adjustment architecture and avoids the high-cost and complex architecture of dedicated ASIC chips. It uses a multiplexer 10 to build a simple timing logic architecture, reducing the number of external circuit components and lowering circuit complexity and mass production costs. At the same time, it adopts a dual compensation mechanism of fixed delay plus dynamic variable delay to separately compensate for the inherent static deviation of the device and the dynamic drift deviation of brightness. This ensures the stability of the basic timing and realizes adaptive adaptation to dynamic operating conditions, solving the problems of inconsistent field-sequence backlight timing, color distortion, and uneven brightness, thus improving the display effect.

[0037] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The field sequence backlight driving circuit 100 mentioned above includes a multiplexer 10, a switch array 20, a delay control network 30, and a voltage generation circuit 40. The multiplexer 10 outputs multiple backlight enable signals EN in sequence according to the global enable signal STV1 and the channel switching signal STV2. The switch array 20 turns on the corresponding backlight lamp string 200 in a time-division manner according to the backlight enable signal EN. The first delay control network 31 of the delay control network 30 provides a preset delay amount. The voltage generation circuit 40 obtains the control voltage Vctr according to the partition brightness signal Ctr1. The control voltage Vctr controls the second delay control network 32 to provide a variable delay amount. The variable delay amount changes positively with the brightness represented by the partition brightness signal Ctr1, realizing precise and controllable adjustment of the backlight signal delay. A simple timing logic architecture is built through the multiplexer 10, reducing circuit complexity and mass production costs. At the same time, it solves the technical defects of poor adaptability and low compensation accuracy of the existing fixed parameter compensation mode, and improves the adaptability of the compensation mode.

[0038] Example 2 The switch array 20 is composed of corresponding switching devices, such as in an optional embodiment. Figure 2 As shown, the switch array 20 includes multiple switch circuits 21 corresponding to the multi-channel backlight string 200. The control terminal of each switch circuit 21 is connected to one output terminal of the multiplexer 10. Each switch circuit 21 is connected in series in the power supply circuit of the corresponding backlight string 200 so as to turn on the corresponding backlight string 200 in a time-division manner according to the received enable signal.

[0039] In this embodiment, the switch array 20 specifically includes multiple switch circuits 21 that correspond one-to-one with the number of backlight strings 200. The number of switch circuits 21 and the channel parameters are perfectly matched with the number of backlight channels, so as to realize independent control of a single channel, with no channel crosstalk and no signal interference.

[0040] Each switch circuit 21 has an independent control terminal, and the control terminals of all switch circuits 21 are electrically connected one-to-one to the signal output terminals of the multiplexer 10, ensuring that each switch circuit 21 only responds to the backlight enable signal EN of the corresponding channel, achieving independence and precision in channel control. Each switch circuit 21 is arranged in series within the power supply circuit of the corresponding backlight string 200, directly intervening in the power supply path of the backlight string 200. The on and off states of the switch circuit 21 directly determine the power supply on and off of the corresponding backlight string 200, thereby controlling the lighting and off states of the backlight string 200.

[0041] In operation, the multiplexer 10 sequentially outputs high-level valid backlight enable signals EN to each switching circuit 21 according to a preset timing logic. When the control terminal of a switching circuit 21 of a certain channel receives a valid backlight enable signal EN, the switching circuit 21 immediately switches from the off state to the on state, the power supply circuit of the corresponding backlight string 200 is connected, the backlight string 200 is powered on and illuminates, outputting a monochrome backlight of the corresponding color. When the backlight enable signal EN of that channel fails, the switching circuit 21 automatically turns off, and the corresponding backlight string 200 is powered off and extinguished. The multiple switching circuits 21 are alternately turned on in a time-division manner without interfering with each other, precisely coordinating with the timing output logic of the multiplexer 10 to achieve the time-division orderly illumination of multiple backlight strings 200, matching the working mechanism of three-time time-division color display of a single frame of the field sequence display.

[0042] This switch array 20 adopts a single-channel independent switch control architecture. Compared with the traditional resistor divider synchronous control architecture, it solves the problems of mutual interference between multi-channel brightness and the inability to independently control timing. The conduction time and conduction duration of each backlight channel can be independently and precisely controlled, greatly improving the timing matching accuracy of the three-color backlight. At the same time, the discrete switch circuit 21 has a faster response speed, which can adapt to the working requirements of ultra-high refresh rates of field sequence displays, effectively avoiding the signal response lag problem under high refresh conditions and ensuring the stability of high-frequency timing switching.

[0043] The switching circuit 21 may employ a corresponding switching device; in an optional embodiment, such as... Figure 4 As shown, the switching circuit 21 includes a second resistor R2, a first electronic switch Q1, and a second electronic switch Q2; The control terminal of the first electronic switch Q1 and the first terminal of the second resistor R2 are connected to form the control terminal of the switch circuit 21. The second terminal of the first electronic switch Q1 and the second terminal of the second resistor R2 are grounded. The first terminal of the first electronic switch Q1 is connected to the control terminal of the second electronic switch Q2. The first terminal of the second electronic switch Q2 is connected to the power output terminal of the boost circuit 50. The second terminal of the second electronic switch Q2 is connected to the first terminal of the corresponding backlight string 200. The second terminal of the backlight string 200 can be grounded.

[0044] When the backlight enable signal EN is high, the first electronic switch Q1 and the second electronic switch Q2 are turned on, transmitting power to the corresponding backlight string 200, which then lights up and outputs a monochrome backlight of the corresponding color. When the backlight enable signal EN is low, the first electronic switch Q1 and the second electronic switch Q2 are turned off, and the corresponding backlight string 200 is powered off and turns off.

[0045] The boost circuit 50 can be a corresponding buck-boost circuit, as in an optional embodiment, such as... Figure 4As shown, the boost circuit 50 includes an inductor L1, a first diode D1, a third electronic switch Q3, and a sixth resistor R6. The third electronic switch Q3 performs boost conversion according to the received boost control signal Ctr2, and boosts the input voltage VIN to output the supply voltage. The supply voltage is output to the input terminal of each switch circuit 21, and is transmitted to the corresponding backlight string 200 when the switch circuit 21 is turned on.

[0046] The multiplexer 10 switches the output of the corresponding level signal according to the global enable signal STV1. In an optional embodiment, when the global enable signal STV1 is low, all multiplexer backlight enable signals EN are set to low level in the static state. When the global enable signal STV1 is high, the multiplexer 10 enters the working state. Within the effective window when the global enable signal STV1 is high, each edge transition of the channel switching signal STV2 triggers the multiplexer 10 to perform a state transition, sequentially setting one backlight enable signal EN high, driving the corresponding switch circuit 21 to conduct and light up the corresponding backlight string 200.

[0047] In this embodiment, the multiplexer 10 has two operating states: static standby and dynamic operation. The two states are precisely switched by the level of the global enable signal STV1. The state switching logic is clear and the operation is stable, which can effectively avoid the problems of invalid signal output and backlight false triggering in the standby state.

[0048] When the device is in standby steady state and the backlight display function is not activated, the global enable signal STV1 remains at a low level. At this time, the multiplexer 10 enters a locked standby mode, blocking the trigger requests of all channel switching signals STV2. Regardless of how the channel switching signal STV2 changes, all output ports of the multiplexer 10 continuously output a low-level invalid backlight enable signal EN. All switching circuits 21 remain in the off state, and all backlight LED strings 200 are in the off state, with no invalid backlight output, reducing the device's standby power consumption and avoiding circuit signal disorder in the standby state.

[0049] When the device starts its display function and enters normal operating mode, the global enable signal STV1 transitions from low to high, and the multiplexer 10 unlocks from standby mode and officially enters the triggerable operating state. During the complete effective time window in which the global enable signal STV1 remains high, the multiplexer 10 continuously monitors the level change of the channel switching signal STV2, using each edge transition of the channel switching signal STV2 as the state transition trigger condition to complete the channel switching action step by step.

[0050] The specific timing logic is as follows: after the global enable signal STV1 is pulled high, as follows: Figure 3As shown, the first edge transition of the channel switching signal STV2 triggers multiplexer 10 to switch to the first channel, corresponding to the first channel's backlight enable signal EN going high, while the enable signals of the other channels remain low, illuminating the first color's backlight string 200. The second edge transition of the channel switching signal STV2 triggers a state transition of multiplexer 10, turning off the first channel and turning on the second channel, turning on the second channel's backlight enable signal EN high, illuminating the second color's backlight string 200. The third edge transition of the channel switching signal STV2 completes the channel switching again, turning on the third channel and turning off the second channel, illuminating the third color's backlight string 200. After a single cycle, it waits for the next global enable signal STV1 cycle to start, repeating the above channel switching logic to form a periodic cyclical timing output.

[0051] Through a precise edge-triggered timing control mechanism, the three-color backlight can be lit up sequentially in strict accordance with the preset order within the display cycle of each frame. This ensures that a single frame is accurately split into three monochrome sub-frames. Relying on the persistence of vision of the human eye, a complete color image is synthesized. The timing switching accuracy can match the working requirements of ultra-high refresh rate field sequence panels, avoiding color mixing and timing misalignment problems from the timing logic level.

[0052] The multiplexer 10 can use logic gate circuits such as AND gates and NOT gates, and the specific structure is not limited.

[0053] The backlight string 200 can be an LED string of a corresponding color. In an optional embodiment, such as... Figure 4 As shown, the multi-channel backlight string 200 includes a red light string Rled, a green light string Gled, and a blue light string Bled; The multi-channel backlight enable signal EN includes the red enable signal Ren, the green enable signal Gen, and the blue enable signal Ben; In the transmission paths of the red enable signal Ren, the green enable signal Gen, and the blue enable signal Ben, a delay control network 30 corresponding to the color channel is connected in series. like Figure 6 As shown, the first delay control network 31 corresponding to each color channel includes a first resistor R1 and a first capacitor C1; The first end of the first resistor R1 is connected to the output end of the voltage generation circuit 40, the second end of the first resistor R1 is connected to the first end of the first capacitor C1 to form the output end of the first delay control network 31, and the second end of the first capacitor C1 is grounded. Among them, the first resistor R1 in the path of the red enable signal Ren is less than the first resistor R1 in the path of the green enable signal Gen, and the first resistor R1 in the path of the green enable signal Gen is less than the first resistor R1 in the path of the blue enable signal Ben.

[0054] In this embodiment, the multi-channel backlight string 200 is divided into three independent light-emitting channels: a red string (Rled), a green string (Gled), and a blue string (Bled). These three strings output red monochromatic backlight, green monochromatic backlight, and blue monochromatic backlight, respectively, providing a three-primary-color light source for field-sequence time-based color mixing. Correspondingly, the multi-channel backlight enable signal EN is divided into three independent control signals: a red enable signal (Ren), a green enable signal (Gen), and a blue enable signal (Ben). These three signals respectively control the conduction timing of the red string (Rled), the green string (Gled), and the blue string (Bled).

[0055] The red enable signal Ren, the green enable signal Gen, and the blue enable signal Ben each have their own independent signal transmission paths. These three paths do not share delay devices. Each transmission path contains a dedicated delay control network 30 for its corresponding color channel. Each delay control network 30 includes independent first delay control network 31 and second delay control network 32. The three-color channel delay compensation architecture is completely independent, allowing for individual setting of compensation parameters for the response characteristics and brightness drift characteristics of red, green, and blue LEDs, thus solving the problem that a unified compensation architecture cannot adapt to the inherent differences between the three color devices.

[0056] Each color channel's first delay control network 31 consists of a first resistor R1 and a first capacitor C1, forming a passive RC delay unit. The first terminal of the first resistor R1 receives the control voltage Vctr after partitioned brightness conversion; the second terminal of the first resistor R1 is connected to the first terminal of the first capacitor C1, and this connection node also serves as the output terminal of the first delay control network 31, transmitting the control voltage Vctr after fixed delay calibration to the subsequent second delay control network 32; the second terminal of the first capacitor C1 is grounded, forming an RC charging and discharging delay loop together with the first resistor R1, applying a base delay of a fixed duration to the control voltage Vctr.

[0057] To compensate for the inherent difference in response speed of the three-color LEDs, the resistance values ​​of the first resistor R1 in the three channels are set differently. The resistance values ​​are such that the first resistor R1 in the path of the red enable signal Ren is less than the first resistor R1 in the path of the green enable signal Gen, and the first resistor R1 in the path of the green enable signal Gen is less than the first resistor R1 in the path of the blue enable signal Ben.

[0058] The underlying logic of this differentiated resistance design stems from the inherent response characteristics of LED devices. The blue LED string (Bled) has the fastest light-emitting response speed, making it prone to premature turn-on and light emission duration exceeding the standard range. Therefore, the blue channel is configured with the largest first resistor, R1, to increase the fixed delay of the control voltage Vctr transmission, thus delaying the blue backlight triggering time. The green LED string (Gled) has a moderate response speed, matched with a medium-value first resistor R1 to achieve a moderate degree of fixed delay compensation. The red LED string (Rled) has the slowest light-emitting response speed, prone to turn-on lag and insufficient light emission duration. Therefore, the red channel is configured with the smallest first resistor, R1, to minimize the fixed delay of the control voltage Vctr and prevent the cumulative delay from further exacerbating the red light timing lag. Through the differentiated configuration of the first resistor R1 parameter, the basic timing alignment of the three-color backlight is completed during the control voltage Vctr transmission stage, eliminating static timing deviations caused by device materials and driving paths, and establishing a unified timing reference for the dynamic brightness compensation of the second delay control network 32.

[0059] The second delay control network 32 can select a matching delay unit according to the control voltage Vctr and the delay mode. In an optional embodiment, such as... Figure 6 As shown, the second delay control network 32 for each color channel includes a variable resistor transistor Qd and a second capacitor C2; The variable resistor transistor Qd operates in the linear region. The gate of the variable resistor transistor Qd is connected to the output terminal of the voltage generation circuit 40. The drain of the variable resistor transistor Qd is connected to the output terminal of the first delay control network 31 corresponding to the color channel. The source of the variable resistor transistor Qd is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is grounded.

[0060] In this embodiment, based on the above-mentioned fixed delay compensation architecture, the second delay control network 32 corresponding to each color channel is a dynamically adjustable RC delay structure. The components are a variable resistor transistor Qd and a second capacitor C2. Relying on the variable impedance characteristics of the transistor's linear region, the delay amount can be continuously and dynamically adjusted to meet the dynamic change requirements of the partition brightness.

[0061] The variable resistor transistor Qd is the control device of this network. It operates in the linear operating range. Within the linear operating range, the on-resistance of the transistor can be continuously and precisely adjusted by the gate control voltage Vctr. There is no gap when switching between levels, which can realize smooth stepless adjustment of the delay amount, ensuring the continuity and stability of timing compensation, and avoiding screen flickering and color jump problems caused by level adjustment.

[0062] In the specific operation, the control voltage Vctr, calibrated by the first delay control network 31, is directly input to the gate of the variable resistor transistor Qd. The backlight control signal completes secondary dynamic delay adjustment through the RC delay circuit composed of the equivalent variable resistance of the variable resistor transistor Qd and the second capacitor C2. When the control voltage Vctr received by the gate of the variable resistor transistor Qd changes, the on-resistance of the linear region of the variable resistor transistor Qd changes synchronously, and the charging and discharging time of the RC circuit changes accordingly, ultimately realizing the dynamic adjustment of the enable signal transmission delay. This structure is simple, reliable, and has a fast response speed. It can perform timing compensation adjustment in real time following the changes in the brightness of the partitions, and can accurately match the dynamic switching rhythm of the screen partition brightness.

[0063] The voltage generation circuit 40 can adopt a corresponding amplifier, filter circuit, or other structure. In an optional embodiment, such as... Figure 5 As shown, the voltage generation circuit 40 includes: The low-pass filter 41 has an input terminal for receiving the partition brightness signal Ctr1. The partition brightness signal Ctr1 is a PWM signal whose duty cycle represents the brightness of the display partition. The low-pass filter 41 is used to convert the PWM signal into a DC voltage signal whose amplitude is positively correlated with the duty cycle of the PWM signal. The inverting amplifier 42 is connected to the output of the low-pass filter 41. The inverting amplifier 42 is used to receive the first reference voltage Vref1 and the DC voltage signal, and output an intermediate voltage signal whose amplitude changes negatively with the DC voltage signal. The voltage conditioning circuit 43 includes a voltage follower 431 connected in series and a bidirectional clamping network 432. The voltage follower 431 is used to isolate the inverting amplifier 42 from the subsequent load. The bidirectional clamping network 432 is used to clamp the intermediate voltage signal within a preset voltage range defined by the second reference voltage Vref2 and the third reference voltage Vref3 to form a control voltage Vctr. The preset voltage range corresponds to the gate voltage range of the linear operating region of the variable resistor transistor Qd.

[0064] In this embodiment, the voltage generation circuit 40 is a module that realizes adaptive matching between partition brightness and timing delay. It can accurately convert the screen partition brightness signal Ctr1 into a stable, controllable analog control voltage Vctr that is compatible with the working range of transistors. The overall circuit consists of three parts: a low-pass filter 41, an inverting amplifier 42, and a voltage conditioning circuit 43. The three-stage circuit processes the signal step by step to ensure the accuracy, stability, and adaptability of the output control voltage Vctr.

[0065] The first part is a low-pass filter 41. The input of the low-pass filter 41 is used to receive the partition brightness signal Ctr1, which represents the brightness of the display partition, in real time. In an optional embodiment, the partition brightness signal Ctr1 is a PWM signal. The duty cycle of the signal directly corresponds to the real-time brightness of the display partition. The larger the duty cycle, the higher the partition brightness; the smaller the duty cycle, the lower the partition brightness. The PWM signal is a pulsed digital signal, and its voltage amplitude fluctuates at high frequency. It cannot be directly used for analog voltage control and needs to be converted by the low-pass filter 41. Figure 6 As shown, the low-pass filter 41 consists of an RC filter structure composed of a third resistor R3 and a third capacitor C3. The first end of the third resistor R3 is used to input the partition brightness signal Ctr1. The second end of the third resistor R3 is connected to the first end of the third capacitor C3 to form the output end of the low-pass filter 41. The second end of the third capacitor C3 is grounded.

[0066] The RC filter structure can filter out high-frequency pulse fluctuations in the PWM signal, converting the discontinuous pulse signal into a continuous and smooth DC voltage signal. The amplitude of the generated DC voltage signal is strictly positively correlated with the duty cycle of the PWM signal, accurately restoring the true value of the partition brightness and providing accurate signal input for subsequent voltage conversion.

[0067] The second part is an inverting amplifier 42. The input of the inverting amplifier 42 is connected to the output of the low-pass filter 41, receiving the DC voltage signal output by the low-pass filter 41. Simultaneously, it is connected to the first reference voltage Vref1 as a reference control voltage. The inverting amplifier 42 has dual functions of signal inversion and proportional amplification. It can perform inverse proportional calculation on the input DC voltage signal, and the amplitude of the final output intermediate voltage signal is strictly negatively correlated with the amplitude of the input DC voltage signal. By adjusting the ratio of the feedback resistor to the input resistor of the inverting amplifier 42, the voltage Vctr amplification factor can be precisely controlled. Simultaneously, with the reference calibration of the first reference voltage Vref1, the output range of the intermediate voltage can be precisely limited, achieving a negative correlation mapping match between the brightness signal and the control voltage Vctr, laying the foundation for the subsequent positive correlation adaptation of the variable delay. The specific operational logic can be precisely adjusted through the resistor ratio and the reference voltage, allowing for flexible adaptation to different screen specifications and LED device parameters, making it highly versatile.

[0068] In an alternative embodiment, such as Figure 6 As shown, the inverting amplifier 42 includes a fourth resistor R4, a fifth resistor R5, and an operational amplifier U1. The first end of the fourth resistor R4 is connected to the output of the low-pass filter 41. The second end of the fourth resistor R4, the inverting input of the operational amplifier U1, and the first end of the fifth resistor R5 are connected. The non-inverting input of the operational amplifier U1 is used to input the first reference voltage Vref1. The second end of the fifth resistor R5 is connected to the output of the operational amplifier U1.

[0069] The third part is the voltage conditioning circuit 43, which consists of a voltage follower 431 and a bidirectional clamping network 432 connected in series. Its main functions are signal isolation, voltage stabilization, and range limiting, ensuring that the output control voltage Vctr stably adapts to the linear operating range of the variable resistor transistor Qd. The input terminal of the voltage follower 431 is connected to the output terminal of the inverting amplifier 42 to receive the intermediate voltage signal output by the inverting amplifier 42. The voltage follower 431 has high input impedance and low output impedance, effectively isolating the pre-amplifier circuit from the load of the subsequent delay network, avoiding voltage drift and signal distortion caused by changes in the impedance of the subsequent load, and ensuring the stability and accuracy of the control voltage Vctr output.

[0070] The bidirectional clamping network 432 is connected to the output of the voltage follower 431. Its function is to strictly clamp the conditioned intermediate voltage signal within a preset voltage range. This preset voltage range is precisely calibrated and corresponds exactly to the gate voltage range required for the linear operating region of the variable resistor transistor Qd. This ensures that the output control voltage Vctr can continuously maintain the transistor in the linear range, preventing the transistor from entering the saturation region or cutoff region due to excessively high or low voltage, thus losing its variable impedance regulation capability.

[0071] like Figure 6 As shown, the bidirectional clamping network 432 consists of a second diode D2 and a third diode D3 forming a bidirectional clamping structure, which, together with the second reference voltage Vref2 and the third reference voltage Vref3, defines the upper and lower voltage thresholds. When the conditioned voltage is within the preset range, both diodes are in the off state, and the control voltage Vctr is output normally. When the voltage is lower than the preset lower threshold, the corresponding third diode D3 turns on, pulling the voltage up to the lower threshold. When the voltage is higher than the preset upper threshold, the second diode D2 turns on, pulling the voltage down to the upper threshold. Through the bidirectional clamping mechanism, the range locking of the control voltage Vctr is achieved, ensuring the stability and reliability of dynamic delay adjustment.

[0072] To achieve independent control, in an optional embodiment, in the second delay control network 32 corresponding to each color channel, the control terminal of the variable resistor transistor Qd receives an independently biased control voltage Vctr.

[0073] In the second delay control network 32 corresponding to the red, green and blue backlight channels in this invention, the gate control terminal of each variable resistor transistor Qd independently receives the control voltage Vctr of the bias parameter. The control voltage Vctr of the three color channels is independent of each other and does not share the same voltage, so as to realize independent dynamic timing compensation of a single channel.

[0074] Traditional field-sequence backlight timing compensation technology generally uses a uniform control voltage Vctr to regulate the three color channels. The delay adjustment parameters of all color channels are exactly the same, which cannot adapt to the different brightness drift characteristics of the three-color LED devices. Under the same brightness conditions, backlight strings of different colors have inherent differences in the amount of drift and delay deviation in response speed. The uniform voltage regulation mode cannot achieve accurate differential compensation, and color deviation and timing misalignment problems will still remain.

[0075] This invention employs a multi-channel independent bias control architecture, configuring an independent control voltage Vctr output for each color channel. The voltage bias parameters of each channel can be individually adjusted based on the device characteristics and response drift patterns of the LEDs in each channel. Under the condition that the brightness of each screen partition is the same, the three color channels can output control voltages Vctr of different amplitudes, thereby generating different dynamic delays. This precisely matches the timing deviation characteristics of each color channel, achieving one-to-one accurate compensation. It completely eliminates the problems of insufficient compensation accuracy and poor color consistency caused by unified compensation across multiple channels, significantly improving the alignment accuracy of the three-color backlight timing and the stability of the image color.

[0076] In another optional embodiment, the first reference voltage Vref1 and / or amplification factor of the inverting amplifier 42 in the voltage generation circuit 40 corresponding to each color channel are different, so that different color channels generate control voltages Vctr with different amplitudes under the same partition brightness input, in order to compensate for the response time drift of backlight strings of different colors under different brightness.

[0077] Based on the generation of multi-channel independent control voltage Vctr, the voltage generation circuit 40 corresponding to each color channel can be configured with differentiated parameters. Specifically, the voltage output of different color channels can be differentiated by adjusting the value of the first reference voltage Vref1 of each channel's inverting amplifier 42 or adjusting the voltage amplification factor of each channel's inverting amplifier 42.

[0078] The specific parameter configuration logic is as follows: For the different response characteristics and brightness drift characteristics of the red LED string (Rled), green LED string (Gled), and blue LED string (Bled), the optimal reference voltage and amplification parameters for each channel are calibrated one by one. The red LED string (Rled) has a slow response speed and a large high-brightness drift, so a corresponding reference voltage and amplification factor are matched to enhance the delay compensation under high-brightness conditions. The blue LED string (Bled) has a fast response speed and a significant low-brightness deviation, so the adaptation parameters are optimized to improve the timing compensation effect in the low-brightness range. The green LED string (Gled) has moderate parameters, and neutral parameters are used to ensure stable output under normal operating conditions.

[0079] Through this differentiated parameter configuration method, under the same brightness input conditions in each screen zone, the voltage generation circuit 40 of the three color channels can output precise control voltages Vctr with different amplitudes. This drives the second delay control network 32 of each channel to generate differentiated dynamic delay amounts, accurately compensating for the response time drift of different color LED strings under different brightness conditions. This design can comprehensively cover the timing deviation problem of the entire brightness range and all color channels, completely solving the technical shortcomings of traditional technologies that cannot adapt to multi-channel differentiated drift. It further improves the color purity, timing consistency, and visual uniformity of the field sequence display, effectively eliminating display defects such as color fringing, color shift, and local color difference in dynamic images.

[0080] Example 3 A second aspect of the present invention provides a backlight module 2, such as... Figure 7 As shown, the backlight module 2 includes multiple backlight units 1, and each backlight unit 1 includes multiple backlight LED strings 200 and a field-sequence backlight driving circuit 100. The specific structure of the field-sequence backlight driving circuit 100 is as described in the above embodiments. Since this backlight module 2 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The field-sequence backlight driving circuit 100 is connected to the multiple backlight LED strings 200.

[0081] In this embodiment, the backlight module 2 is composed of an array of multiple independent backlight units 1, which can be adapted to field sequence display screens of different sizes and resolutions, and meet the display requirements of local dimming. Each backlight unit 1 includes an independent multi-channel backlight string 200 and a field sequence backlight driving circuit 100. Each backlight unit 1 forms an independent control system, which can independently complete the backlight timing control and brightness adjustment of its own area. Each backlight unit 1 does not interfere with each other and works independently.

[0082] Multiple backlight strings 200 are evenly arranged in an array inside the backlight module 2. Red LED strings (Rled), green LED strings (Gled), and blue LED strings (Bled) are evenly and alternately distributed to ensure the uniformity of backlight emission and avoid brightness and color difference problems caused by local monochromatic accumulation. Each backlight unit 1 has a corresponding field sequence backlight drive circuit 100 that independently matches the LED string parameters of its unit. It can receive the brightness signal of the corresponding display zone of its unit independently and independently complete fixed delay calibration and dynamic delay adaptive compensation, realizing precise timing control at the pixel level and zone level.

[0083] Multiple backlight units 1 work together to achieve independent timing control of the backlight in different zones of the entire screen. Precise timing compensation can be obtained for different bright and dark areas of the screen, solving the problem that traditional overall backlight driving solutions cannot adapt to zone dimming and cannot correct local timing deviations.

[0084] Example 4 A third aspect of the present invention provides a display device, such as... Figure 8 As shown, the display device includes a display panel 3 and a backlight module 2. The specific structure of the backlight module 2 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. The display panel 3 and the backlight module 2 are arranged opposite to each other.

[0085] In this embodiment, the display panel 3 and the backlight module 2 are assembled and fixed in a relatively fitted manner. The backlight module 2 is located on the backlight side of the display panel 3, providing the display panel 3 with an RGB time-division backlight source that is accurate in timing, uniform in color, and stable in brightness. The display panel 3 is located on the visible side, completing the grayscale image display and human eye imaging output.

[0086] Display panel 3 is a field-sequence dedicated color filter-free LCD panel. Compared to traditional LCD panels, this panel eliminates the RGB color filter film, black matrix, and sub-pixel segmentation structure. Each pixel is a complete light-transmitting unit, responsible only for the accurate display of grayscale images, and no longer undertakes the function of spectral color rendering. Color synthesis is entirely achieved through the RGB time-division switching of the backlight module 2. Relying on the high-precision timing control capability of the backlight module 2, and matching the imaging characteristics of the color filter-free panel, the advantages of field-sequence display—high transmittance, high resolution, and low power consumption—are fully utilized.

[0087] The complete workflow of the display device is as follows: After the device is started, the system image processor divides the brightness level of each display zone of the screen in real time according to the current display content, generates the corresponding zone brightness signal Ctr1, and transmits it to the voltage generation circuit 40 of each backlight unit 1 of the backlight module 2. The voltage generation circuit 40 completes signal filtering, voltage conversion, and signal conditioning, and outputs a precise control voltage Vctr to the second delay control network 32 of each color channel. The multiplexer 10 receives the global enable signal STV1 and the channel switching signal STV2 output by the system, and outputs the three-color backlight enable signal EN in sequence according to the preset timing logic, driving the switch array 20 to conduct the three-color backlight LED string 200 in a time-division multiplexing manner.

[0088] During backlight signal transmission, the first delay control network 31 completes the fixed calibration of the inherent response deviation of the three color channels, and the second delay control network 32 completes dynamic timing drift compensation according to the brightness of the zones. The dual compensation mechanisms work together to ensure that the emission timing of the three color backlights is completely aligned under different zones and different brightness conditions. The high-speed time-division RGB backlight output by the backlight module 2 penetrates the grayscale image of the display panel 3 and synthesizes a complete, uniform, and color-accurate color image based on the persistence of vision effect of the human eye, ultimately achieving a high-quality display effect with low power consumption, high resolution, and high color consistency.

[0089] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A field sequential backlight driving circuit, characterized by, include: The multiplexer is configured to receive a global enable signal and a channel switching signal, and to sequentially output multiple backlight enable signals within the effective window of the global enable signal according to the channel switching signal. A switch array is connected to a multi-channel backlight string and the multiplexer. The switch array is used to turn on the corresponding backlight string in a time-division manner according to the multi-channel backlight enable signals received in sequence. A voltage generation circuit is configured to receive a partition brightness signal representing the brightness of a display partition, and convert the partition brightness signal into a control voltage, the amplitude of which is negatively correlated with the brightness represented by the partition brightness signal. The delay control network includes a first delay control network and a second delay control network. The first delay control network is connected to the voltage generation circuit and is used to provide a preset delay for the passing control voltage. The second delay control network is connected in series in at least one of the transmission paths of the backlight enable signal in the switch array. The second delay control network is used to provide a variable delay amount that is negatively correlated with the received control voltage for the passing backlight enable signal, so that the variable delay amount changes in a positive correlation with the brightness represented by the partition brightness signal.

2. The field sequential backlight driving circuit of claim 1, wherein, The switch array includes multiple switch circuits corresponding to multiple backlight strings. The control terminal of each switch circuit is connected to one output terminal of the multiplexer. Each switch circuit is connected in series in the power supply circuit of the corresponding backlight string so as to turn on the corresponding backlight string in a time-division manner according to the received backlight enable signal.

3. The field sequential backlight driving circuit of claim 2, wherein, In a static state, when the global enable signal is low, all the multiplexer backlight enable signals are set to low. When the global enable signal is high, the multiplexer enters the working state. Within the effective window when the global enable signal remains high, each edge transition of the channel switching signal triggers the multiplexer to perform a state transition, sequentially setting one backlight enable signal high to drive the corresponding switch circuit to conduct and light up the corresponding backlight string.

4. The field sequential backlight driving circuit of claim 1, wherein, The backlight strings mentioned above include red, green, and blue light strings; The multi-channel backlight enable signal includes a red enable signal, a green enable signal, and a blue enable signal; The transmission paths of the red enable signal, the green enable signal, and the blue enable signal are respectively connected in series with the delay control network corresponding to the color channel; The first delay control network corresponding to each color channel includes a first resistor and a first capacitor; The first end of the first resistor is connected to the output end of the voltage generation circuit, the second end of the first resistor is connected to the first end of the first capacitor to form the output end of the first delay control network, and the second end of the first capacitor is grounded. Wherein, the first resistance in the red enable signal path is less than the first resistance in the green enable signal path, and the first resistance in the green enable signal path is less than the first resistance in the blue enable signal path.

5. The field sequential backlight driving circuit of claim 4, wherein, The second delay control network for each color channel includes a variable resistance transistor and a second capacitor; The variable resistance transistor operates in the linear region. The gate of the variable resistance transistor is connected to the output terminal of the voltage generation circuit. The drain of the variable resistance transistor is connected to the output terminal of the first delay control network corresponding to the color channel. The source of the variable resistance transistor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is grounded.

6. The field sequential backlight driving circuit of claim 5, wherein, The voltage generation circuit includes: A low-pass filter, the input of which is used to receive the partition brightness signal, the partition brightness signal being a PWM signal whose duty cycle represents the brightness of the display partition, and the low-pass filter being used to convert the PWM signal into a DC voltage signal whose amplitude is positively correlated with the duty cycle of the PWM signal; An inverting amplifier is connected to the output of the low-pass filter. The inverting amplifier is used to receive the first reference voltage and the DC voltage signal, and output an intermediate voltage signal whose amplitude changes negatively with the DC voltage signal. The voltage conditioning circuit includes a voltage follower connected in series and a bidirectional clamping network. The voltage follower is used to isolate the inverting amplifier from the subsequent load, and the bidirectional clamping network is used to clamp the intermediate voltage signal within a preset voltage range defined by a second reference voltage and a third reference voltage to form the control voltage. The preset voltage range corresponds to the gate voltage range of the linear operating region of the variable resistor transistor.

7. The field sequential backlight driving circuit of claim 6, wherein, In the second delay control network corresponding to each color channel, the control terminal of the variable resistor transistor receives the independently biased control voltage.

8. The field sequential backlight driving circuit of claim 6, wherein, In the voltage generation circuit corresponding to each color channel, the first reference voltage and / or amplification factor of the inverting amplifier are different, so that different color channels generate control voltages with different amplitudes under the same partition brightness input, in order to compensate for the response time drift of backlight strings of different colors under different brightness.

9. A backlight module, characterized in that, It includes multiple backlight units, each of which includes multiple backlight LED strings and a field-sequence backlight driving circuit as described in any one of claims 1 to 8, wherein the field-sequence backlight driving circuit is connected to the multiple backlight LED strings.

10. A display device, characterized by comprising: It includes a display panel and a backlight module as described in claim 9, wherein the display panel and the backlight module are disposed opposite to each other.

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