Time sequence controller and control method thereof

Abstract

The application provides a timing controller and a control method thereof. The control method of the timing controller comprises: dividing a to-be-displayed picture into multiple sub-pictures based on picture content features, and determining a polarity inversion mode of each sub-picture; and based on column spatial distribution features and the polarity inversion mode of each sub-picture, outputting a polarity bit matched with the sub-picture row by row when each row synchronization clock arrives. The to-be-displayed picture is dynamically divided into sub-pictures based on the picture content features as the division basis, and the polarity inversion mode suitable for the sub-pictures is determined, so that the system can adaptively select a driving mode according to different regional features, thereby avoiding the contradiction between picture quality and power consumption caused by the global fixed polarity mode.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a timing controller and its control method. Background Technology

[0002] To prevent polarization aging of liquid crystal molecules, existing 1G1D (One Gate One Data) architecture LCD displays must employ polarity inversion driving technology. Currently, commonly used polarity inversion methods in the industry include 1-Dot inversion, column inversion, and 1+2line inversion.

[0003] However, the global fixed polarity mode cannot dynamically adapt to local features of the image, making it difficult to balance image quality and power consumption. Summary of the Invention

[0004] The main technical problem addressed in this application is to provide a timing controller and its control method, which solves the problem of image quality and power consumption contradiction caused by the global fixed polarity mode in the prior art.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: a control method for a timing controller, comprising: The screen to be displayed is divided into multiple sub-screens based on the characteristics of the screen content, and the polarity flipping method of each sub-screen is determined. Based on the column spatial distribution characteristics and polarity reversal method of each sub-screen, the polarity bit matching the sub-screen is output row by row when the synchronization clock arrives.

[0006] In some embodiments, based on the column spatial distribution characteristics and polarity inversion method of each sub-screen, when each row synchronization clock arrives, the polarity bit matching the sub-screen is output row by row, including: Responding to the sub-screen being a full-size column area, the polarity bits are output row by row based on the polarity flipping method; In response to the sub-picture being a column-sliced ​​area, the polarity bit is dynamically generated and output row by row based on the polarity flipping method of all sub-pictures within the same column-oriented window and the pixel row sequence occupied by each sub-picture.

[0007] In some embodiments, in response to a sub-picture being a column-sliced ​​region, polarity bits are dynamically generated and output row by row based on the polarity flipping method of all sub-pictures within the same column-oriented window and the pixel row sequence occupied by each sub-picture, including: The sub-pictures within the same column-oriented window are sorted according to the row scanning direction, and the polarity continuous row sequence of the entire column-oriented window is determined based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies; where each item in the polarity continuous row sequence represents the number of consecutive rows with the same polarity within the column-oriented window. The polarity bits are dynamically generated and output row by row, with the item values ​​in the continuous polarity row sequence as the target step size.

[0008] In some embodiments, polarity bits are dynamically generated and output row by row, with the item values ​​in the continuous polarity row sequence as the target step size, including: Initialize the target step counter to the first value of the polarity continuous row sequence, and accumulate the row number under the current polarity state by running the counter; In response to the run counter value being less than the target step counter value, output the polarity bit and maintain the current polarity state, and increment the run counter; In response to the run counter value being equal to the target step counter value, the polarity bit is output and the polarity state of the polarity status register is reversed, the run counter is reset, and the next item value of the sequence group is loaded into the target step counter; Continue until the values ​​of the consecutive polarity row sequence have been traversed.

[0009] In some embodiments, the control method for the timing controller further includes: Accumulate the net polarity value of the current frame in real time; Within a preset period, in response to the absolute value of the net cumulative polarity value exceeding a preset threshold, a polarity reversal command is output to reverse the polarity of the current frame in the next frame.

[0010] In some embodiments, the control method for the timing controller further includes: Cache the current row and at least three subsequent rows of image data; During the horizontal blank period, the cached current row image data and the current row polarity bit are synchronized and encapsulated into a data packet, and sent through the source driver chip interface.

[0011] To address the aforementioned technical problems, the second technical solution provided in this application is: a timing controller for executing the aforementioned control method for the timing controller, comprising: The image analysis module is used to divide the screen to be displayed into multiple sub-screens based on the characteristics of the screen content, and to determine the polarity sequence of each sub-screen. The polarity generation module is used to output the polarity bit that matches the sub-screen line by line when the synchronization clock arrives, based on the column spatial distribution characteristics and polarity flipping method of each sub-screen.

[0012] In some embodiments, the polarity generation module includes a judgment processing unit, a static mode register, and a variable step-size finite state machine; the judgment processing unit is used to analyze the column spatial distribution characteristics of each sub-screen, and is also used to: In response to the sub-screen being a full-width column area, the polarity inversion mode is output to the static mode register; In response to the sub-picture being a column-sliced ​​region, the sub-pictures within the same column-sliced ​​window are sorted according to the row scanning direction. Based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies, the polarity continuous row sequence is determined and output to the variable step size finite state machine. The static mode register receives polarity inversion mode and outputs the polarity bits line by line to a variable step size finite state machine. The variable-step finite state machine receives the polarity continuous row sequence and the polarity bit output by the static mode register. It then generates and outputs the final polarity bit row by row, using the item value of the polarity continuous row sequence as the target step size.

[0013] In some embodiments, the variable step size finite state machine includes a polarity state register, a target step size counter, a run counter, and a comparator; The polarity status register stores the current polarity status to output the polarity bit; The target step size counter receives a polarity continuous row sequence and uses the item values ​​of the polarity continuous row sequence as the target step size in turn. The running counter continuously counts the actual number of consecutive rows under the current polarity state. The comparator is used to compare the run counter value with the target step counter value in real time, and is also used for: In response to the run counter value being less than the target step counter value, maintain the current polarity state of the polarity status register and increment the run counter; In response to the run counter value being equal to the target step counter value, the current polarity state of the polarity status register is reversed, the run counter is reset, and the next value of the sequence group is loaded into the target step counter.

[0014] In some embodiments, the timing controller further includes a DC balancing module connected to the polarity generation module, for accumulating the net polarity value in real time, and outputting a polarity reversal command to the polarity generation module within a preset period when the absolute value of the net polarity value exceeds a preset threshold.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a timing controller and its control method. The control method of the timing controller includes: dividing the screen to be displayed into multiple sub-screens based on the screen content characteristics, and determining the polarity flipping method of each sub-screen; based on the column spatial distribution characteristics and polarity flipping method of each sub-screen, outputting the polarity bit matching the sub-screen row by row when each row synchronization clock arrives. By dynamically dividing the screen to be displayed into sub-screens based on the screen content characteristics and determining the polarity flipping method adapted to each sub-screen, the system can adaptively select the driving mode for different regional characteristics, thereby avoiding the contradiction between image quality and power consumption caused by a globally fixed polarity mode. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0017] Figure 1 This is a flowchart illustrating one embodiment of the timing controller control method provided in this application; Figure 2 This is a schematic diagram showing the division of an embodiment of the screen to be displayed provided in this application; Figure 3 yes Figure 1 Flowchart of the implementation method of step S1; Figure 4 yes Figure 1 A flowchart illustrating the implementation method of step S2; Figure 5 yes Figure 4 A flowchart illustrating an implementation method for step S22; Figure 6 yes Figure 5 A flowchart illustrating an implementation method for step S222; Figure 7 This is a schematic diagram of a module of an embodiment of the timing controller provided in this application; Figure 8 This is a schematic diagram of the workflow between the timing controller and the display panel provided in this application; Figure 9 This is a schematic diagram of the internal modules of an embodiment of the timing controller provided in this application; Figure 10 This is a working block diagram of an embodiment of the variable step size finite state machine provided in this application. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] The current global fixed polarity mode has the following problems: 1. The trade-off between image quality and power consumption: Inverted image quality: but frequent voltage jumps in the source driver IC data line lead to high dynamic power consumption and severe chip overheating. Column inversion: Low power consumption, but it is prone to causing common voltage (Vcom) fluctuations when displaying periodic patterns such as checkerboard, resulting in horizontal crosstalk and screen flicker. 1+2 line inversion: Generally applicable to VA screens. Vertical crosstalk occurs due to the large leakage current of TFTs (transistors) during column inversion.

[0024] 2. Limitations of global-driven approaches: Existing display driver solutions typically employ a single, fixed polarity inversion mode across the entire panel area. This makes it impossible to flexibly adapt to the local characteristics of the actual image (e.g., both static solid color backgrounds and complex dynamic videos on the same screen), resulting in unnecessary power consumption waste or local image quality degradation.

[0025] Please see Figures 1 to 3 , Figure 1 This is a flowchart illustrating one embodiment of the timing controller control method provided in this application. Figure 2 This is a schematic diagram illustrating the division of an embodiment of the screen to be displayed provided in this application. Figure 3 yes Figure 1 A flowchart of the implementation method of step S1.

[0026] To address the aforementioned technical problems, this application provides a control method for a timing controller, wherein the control method for the timing controller includes: Step S1: Divide the screen to be displayed into multiple sub-screens based on the characteristics of the screen content, and determine the polarity flipping method of each sub-screen; Step S2: Based on the column spatial distribution characteristics and polarity flipping method of each sub-screen, output the polarity bit that matches the sub-screen line by line when the synchronization clock arrives.

[0027] The screen to be displayed is dynamically divided into sub-screens based on the characteristics of the screen content, and the polarity flipping method adapted to the sub-screens is determined. This allows the system to adaptively select the driving mode for different regional characteristics, thereby avoiding the contradiction between image quality and power consumption caused by a globally fixed polarity mode.

[0028] Each sub-screen displays a different interface, or each sub-screen is applied to a different scenario.

[0029] Each sub-screen uses a differentiated inversion method based on the characteristics of the displayed content.

[0030] Content characteristics include static / dynamic display, content complexity, etc. That is, the screen to be displayed can be dynamically divided based on one or more content characteristics.

[0031] For example, in this application, the display screen is divided based on the complexity of the screen content.

[0032] For example, a screen to be displayed can be divided into three sub-screens based on the complexity of its content.

[0033] Sub-screen A: Corresponds to a static solid color display area (such as table text), using a column reversal method to reduce the power consumption and temperature of the source driver chip.

[0034] Sub-screen B: Corresponds to dynamic / complex content areas (such as landscape paintings), using a dot inversion method to suppress image blurring and improve display quality.

[0035] Sub-screen C: For areas with regular patterns (such as grids or stripes), a 2-dot inversion method is used to eliminate interline crosstalk.

[0036] Among them, sub-screen A is the full-size area in the column direction, while sub-screens B and C are respectively column-sliced ​​areas, and are located within the same column-oriented view window.

[0037] There is no limit to the number of sub-screens here; you can choose according to your actual needs.

[0038] For example, step S1: Dividing the screen to be displayed into multiple sub-screens based on the characteristics of the screen content, and determining the polarity flipping method of each sub-screen, including: like Figure 3 As shown, the screen to be displayed is divided according to the characteristics of the screen; it is determined whether the sub-screen is a regular pattern area. If so, the polarity sequence of the sub-screen is determined to be 2-dot inversion mode; otherwise, it is determined whether the sub-screen is a dynamic / complex content area. If so, the polarity sequence of the sub-screen is determined to be dot inversion mode; otherwise, the polarity sequence of the sub-screen is determined to be column inversion mode.

[0039] In other implementations, one or more content features can be used to dynamically divide the screen to be displayed.

[0040] The timing controller includes an image analysis module and a polarity generation module. The image analysis module is connected to the data input port to receive the data of the screen to be displayed, and the polarity generation module is connected to the output port of the image analysis module.

[0041] For example, the image analysis module detects the texture features of the screen to be displayed in real time through hardware operators, so as to divide the screen to be displayed into multiple sub-screens and assign an appropriate polarity flipping method to each sub-screen.

[0042] The polarity generation module generates periodic polarity sequences, such as all-positive or alternating positive and negative polarity sequences, through a static mode register based on the column spatial distribution characteristics and polarity flipping method of each sub-screen, or dynamically generates complex polarity sequences through a variable step-size finite state machine.

[0043] A polarity sequence refers to a continuous sequence in which the polarity state changes with each row (e.g., +-+-+-+-). In other words, a polarity sequence is composed of multiple polarity bits generated in the order of row scanning, and does not refer to generating the entire sequence at once (not a pre-stored complete data block). The polarity generation module calculates the polarity of each row in real time and outputs the polarity bits, which are the items in the generated polarity sequence.

[0044] The description of generating a periodic polar sequence does not mean that the entire sequence is generated at once, but rather that the generation method of the sequence (i.e., the generation logic of each polar bit) is periodic.

[0045] It should be noted that the polarity sequences in this application all refer to the vertical polarity sequences on a single data line.

[0046] The screen to be displayed contains at least one column-oriented window, and the column-oriented windows are arranged side by side along the row direction.

[0047] Each column-oriented window contains at least one sub-screen.

[0048] When a column-oriented window includes a sub-screen, that sub-screen is the full column-oriented area.

[0049] When a column-oriented window includes multiple sub-screens, each sub-screen is stacked along the column direction and is a column-oriented slice area.

[0050] Column direction: refers to the direction in which the data line extends (i.e., the column drive direction).

[0051] Line direction: refers to the direction in which the scan line extends (i.e., the line scan direction).

[0052] Full-view column: This means that the sub-screen displays the complete vertical content of a certain data column without truncation.

[0053] Column-oriented slice area: refers to a sub-screen that displays a partial slice of a specific data column.

[0054] The column distribution characteristics of sub-pictures are divided into two categories: Category 1: Sub-images covering the entire frame; The second category is sub-pictures of column-oriented slice regions.

[0055] The polarity generation methods differ for sub-pictures with different column distribution characteristics.

[0056] Please see Figure 4 and Figure 5 , Figure 4 yes Figure 1 A flowchart illustrating the implementation method of step S2. Figure 5 yes Figure 4 A flowchart illustrating step S22 of the implementation method.

[0057] In some implementations, step S2: based on the column spatial distribution characteristics and polarity inversion method of each sub-screen, when each row synchronization clock arrives, outputs the polarity bit matching the sub-screen row by row, including: Step S21: In response to the sub-screen being a full-size column area, output the polarity bits row by row based on the polarity flipping method; Step S22: In response to the sub-screen being a column-sliced ​​area, based on the polarity flipping method of all sub-screens within the same column-oriented window and the pixel row sequence occupied by each sub-screen, dynamically generate and output the polarity bit row by row.

[0058] After analyzing the column-oriented spatial distribution characteristics of each sub-picture, when a sub-picture occupies the entire column width (i.e., the full column-oriented area), the polarity generation module generates a periodic polarity sequence, such as an all-positive sequence or an alternating positive-negative sequence, through a static mode register based on the polarity flipping method assigned to the sub-picture. When a sub-picture is a column-oriented segmented region (a column-oriented slice region), the polarity generation module collects the polarity flipping methods of all sub-pictures within the same column-oriented window and the pixel row sequence occupied by each sub-picture, and dynamically generates a complex polarity sequence for that column-oriented window in real time through a variable-step finite state machine. In other words, when a column-oriented window includes multiple sub-pictures using different polarity flipping methods, it cannot be simply stored and output using a static mode register; a variable-step finite state machine is required for dynamic real-time output.

[0059] The pixel row sequence occupied by the sub-picture includes the number of pixel rows occupied by the sub-picture and the scanning order of these pixel rows. Based on the polarity flipping method of the sub-picture and the pixel rows it occupies, the polarity sequence corresponding to the sub-picture can be preset, thereby predicting the polarity sequence to be generated for the column-oriented window. Then, the polarity bits are dynamically output row by row to obtain the polarity sequence of the column-oriented window.

[0060] For example, suppose a columnar window consists of only sub-screen C and sub-screen B. Sub-screen C occupies the first 4 rows of pixels and is assigned a 2-dot inversion mode, with a corresponding polarity sequence of ++--; sub-screen B occupies the last 4 rows of pixels and is assigned a dot inversion mode, with a corresponding polarity sequence of +-+-. The polarity sequence to be generated by this columnar window is ++--+-+-, which is a non-periodic polarity sequence. It cannot be simply stored and output using a static mode register; a variable-step finite state machine is required for dynamic real-time output.

[0061] By using static mode registers to output polarity bits for sub-pictures in the full-width column region, the calculation process can be reduced; by dynamically generating non-periodic polarity sequences in real time for sub-pictures in the column slice region based on the polarity flipping method and the pixel row sequence occupied by all sub-pictures in the column window where the column slice region is located, the corresponding flipping method can be dynamically adapted according to the local features of the picture, balancing power consumption and display quality.

[0062] In some implementations, step S22: In response to the sub-picture being a column-sliced ​​region, based on the polarity flipping method of all sub-pictures within the same column-oriented window and the pixel row sequence occupied by each sub-picture, dynamically generate and output polarity bits row by row, including: Step S221: Sort the sub-pictures in the same column-oriented window according to the row scanning direction, and determine the polarity continuous row sequence of the entire column-oriented window based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies; wherein each item of the polarity continuous row sequence represents the number of consecutive rows with the same polarity in the column-oriented window. Step S222: Dynamically generate and output polarity bits row by row, with the item values ​​in the continuous polarity row sequence as the target step size.

[0063] The line scanning direction refers to the line scanning sequence of the display device from top to bottom or from bottom to top.

[0064] By sorting the sub-pictures within the same column-oriented window according to the row scanning direction, and based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies, the polarity sequence to be generated by the column-oriented window can be predicted. Based on this polarity sequence, the polarity continuous row sequence of the entire column-oriented window can be determined. For example, if the polarity sequence to be generated by the column-oriented window is ++--+-+-, then the polarity continuous row sequence is {2, 2, 1, 1, 1, 1}. From the polarity continuous row sequence, it can be seen that the first and second rows have the same polarity, the third and fourth rows have the same polarity, the first and third rows have different polarities, and adjacent rows in the last four rows have different polarities.

[0065] The polarity bits are dynamically generated row by row, with each value of the polarity continuous row sequence representing the target step size of the variable step size finite state machine, thereby generating the polarity sequence of the column-oriented window.

[0066] When dynamically generating a variable-step polarity sequence, the running counter tracks the number of rows where the current polarity has been maintained in real time. The target step-size counter is based on the number of consecutive polarity rows in each sub-screen. When the running counter reaches the target step-size, the polarity bit is output, the current polarity state is flipped (i.e., the flipped polarity state is output as the polarity bit of the next row), and the target step-size is updated. The polarity sequence generation is based on a variable-step finite state machine, and dynamic adjustment is achieved through real-time comparison between the target step-size counter and the running counter to ensure that the polarity sequence is synchronized with the displayed content.

[0067] By determining the number of consecutive polarity rows for each sub-screen, the system can accurately match the vertical characteristics of the sub-screen, thereby suppressing common voltage fluctuations and reducing horizontal crosstalk. By sorting the sub-screens in the same column within the window according to the row scanning direction, the polarity sequence is made consistent with the display order, thus avoiding display abnormalities caused by sequence misalignment. By dynamically generating a variable step size polarity sequence with the item value in the consecutive polarity row sequence determined by the polarity flipping method of each sub-screen and the pixel row sequence it occupies as the target step size, the non-periodic sequence can adapt to the characteristics of different sub-screens, thereby further reducing screen flicker.

[0068] Please see Figure 6 , Figure 6 yes Figure 5 A flowchart illustrating an implementation method for step S222.

[0069] In some implementations, step S222: dynamically generating and outputting polarity bits row by row, with the item values ​​in the consecutive polarity row sequence as the target step size, includes: Step S01: Initialize the target step counter to the first value of the polarity continuous row sequence, and accumulate the number of rows in the current polarity state by running the counter; Step S02: In response to the run counter value being less than the target step counter value, output the polarity bit and maintain the current polarity state, and increment the run counter; in response to the run counter value being equal to the target step counter value, output the polarity bit and reverse the polarity state of the polarity status register, reset the run counter, and load the next item value of the sequence group into the target step counter; Step S03: Continue until the values ​​of the consecutive polarity row sequence items have been traversed.

[0070] The target step counter stores the current number of consecutive rows with the current polarity, the running counter tracks the number of rows whose current polarity state has been maintained in real time, and the polarity state register stores the current polarity state. When the running counter value is less than the target step counter value, the polarity bit is output to maintain the current polarity state (i.e., the polarity state of the current row is the same as the polarity state of the next row), and the running counter is incremented to ensure the stable continuation of the current polarity state. When the running counter value equals the target step counter value, the polarity bit is output and the polarity state in the polarity state register is toggled (the polarity state of the current row is opposite to the polarity state of the next row), the running counter is reset, and the next value is loaded into the target step counter to achieve a smooth polarity switch. The above steps are repeated until the consecutive row values ​​with the current polarity are traversed, dynamically generating the polarity sequence of the column-oriented window.

[0071] In some implementations, the timing controller's control method further includes: accumulating the net polarity value of the current frame in real time; and within a preset period, when the absolute value of the net polarity value exceeds a preset threshold, outputting a polarity reversal command to reverse the current polarity in the next frame.

[0072] The DC balancing accumulation module, as the core internal component of the timing controller, receives polarity data output from the polarity generation module in real time. Positive polarity rows are recorded as +1, and negative polarity rows as -1, dynamically accumulating to form a net polarity accumulation value. The net polarity accumulation value is the number of positive polarity rows minus the number of negative polarity rows.

[0073] The preset cycle can be set to one frame display time or a fixed number of lines, such as 100 lines. The preset threshold can be set to values ​​such as 5, 10, or 15, depending on the panel charge characteristics.

[0074] By accumulating the net polarity value in real time, the system can accurately quantify the polarity deviation, which helps prevent polarization aging of liquid crystal molecules due to DC bias accumulation. When the absolute value of the net polarity value exceeds the threshold within a preset period, the system outputs a polarity reversal command, which allows the system to actively neutralize the charge when the deviation reaches the critical point, thus helping to avoid image distortion and flickering during long-term display. The current polarity is reversed in the next frame, keeping the polarity sequence in DC balance, which helps to improve display stability and extend the panel's lifespan.

[0075] In some implementations, the timing controller's control method further includes caching the current row and at least three subsequent rows of image data; during the horizontal blank period, the cached current row image data and the current row polarity bit are synchronized and encapsulated into a data packet, and sent through the source driver chip interface.

[0076] The row cache module is used to temporarily store the current row and at least three subsequent rows of image data.

[0077] During the horizontal blank period of the display timing, the packaging module encapsulates the cached current row image data and the current row polarity bit into a data packet and sends it through the source driver chip interface.

[0078] By caching the current row and at least three subsequent rows of image data, time is reserved for polarity bit generation; by synchronously encapsulating the cached current row image data and the generation of the current row polarity bit into a data packet, the polarity command and image data are precisely aligned, which helps reduce display errors; by sending data packets during the horizontal blank period, data transmission does not interfere with display refresh, which helps maintain display smoothness.

[0079] Please see Figures 7 to 10 , Figure 7 This is a schematic diagram of a module of an embodiment of the timing controller provided in this application. Figure 8 This is a schematic diagram of the workflow between the timing controller and the display panel provided in this application. Figure 9 This is a schematic diagram of the internal modules of an embodiment of the timing controller provided in this application. Figure 10 This is a working block diagram of an embodiment of the variable step size finite state machine provided in this application.

[0080] This application provides a timing controller, which includes an image analysis module and a polarity generation module. The image analysis module is used to divide the screen to be displayed into multiple sub-screens based on the characteristics of the screen content and to determine the polarity sequence of each sub-screen. The polarity generation module is used to output the polarity bit matching the sub-screen row by row when each row synchronization clock arrives, based on the column spatial distribution characteristics and polarity flipping method of each sub-screen.

[0081] The timing controller is used to receive external image data, transmit control signals and data to the source driver chip, and the source driver chip transmits source drive signals to the display panel.

[0082] The image analysis module receives the image data to be displayed and analyzes its content features, dynamically dividing the image into multiple sub-image regions. Based on the image content features, this module determines the polarity inversion method for each sub-image; for example, static solid-color areas are considered low-complexity and use column inversion, while dynamic video areas are considered high-complexity and use dot inversion. The polarity generation module, as a downstream processing unit, is signal-connected to the image analysis module and receives the column-oriented spatial distribution characteristics and polarity inversion method of the sub-images.

[0083] The working process is as follows: After the image analysis module completes the sub-screen division and polarity reversal mode determination, the polarity generation module calculates the sequence parameters based on the column spatial characteristics, generates the sequence, and outputs it synchronously within the row synchronization clock cycle. Polarity reversal modes include dot reversal, column reversal, or 2-dot reversal, which are defined as driving technologies that dynamically adjust the polarity of liquid crystal molecules according to the screen content to prevent polarization aging.

[0084] The image analysis module dynamically divides the screen into sub-screens and determines the polarity flipping method based on content features, enabling the timing controller to adapt to local features and achieve a dynamic balance between image quality and power consumption. The polarity generation module generates a matching polarity sequence based on column-oriented spatial distribution features and the polarity flipping method, avoiding common voltage fluctuations when displaying regular patterns, thus reducing crosstalk and screen flicker. Combining these features, the dynamic partitioning driving strategy effectively improves display quality in multiple scenarios, further enhancing the user's visual experience.

[0085] In some embodiments, the polarity generation module includes a judgment processing unit, a static mode register, and a variable step size finite state machine; the judgment processing unit is used to analyze the column spatial distribution characteristics of each sub-screen, and is also used to: in response to the sub-screen being a full-width column region, output the polarity flipping mode to the static mode register; in response to the sub-screen being a sliced ​​column region, sort the sub-screens in the same column window according to the row scanning direction, determine the polarity continuous row sequence based on the polarity flipping mode of each sub-screen and the pixel row sequence it occupies, and output it to the variable step size finite state machine.

[0086] The static mode register receives the polarity inversion mode and outputs the polarity bits row by row to the variable step size finite state machine. The variable step size finite state machine receives the polarity continuous row sequence and the polarity bits output by the static mode register, and generates and outputs the final polarity bits row by row, using the item value of the polarity continuous row sequence as the target step size.

[0087] The static mode register is used to generate periodic polarity sequences and output them to the variable step size finite state machine; the variable step size finite state machine is used to generate aperiodic polarity sequences in real time and output each polarity sequence synchronously.

[0088] The decision processing unit analyzes the vertical distribution of sub-screens in real time, i.e., the column-oriented spatial distribution characteristics. When a sub-screen exhibits a full-width column-oriented region characteristic, the decision processing unit transmits the polarity reversal method to the static mode register; when a sub-screen exhibits a slice-like column-oriented region characteristic, the decision processing unit determines the polarity continuous row sequence and transmits it to the variable-step finite state machine. The static mode register, as the periodic sequence generation unit, is located at the output of the decision processing unit. After receiving the full-width region instruction, it generates a fixed regular sequence (such as ++++++) and outputs it to the variable-step finite state machine to synchronize the polarity phase before outputting. The variable-step finite state machine, as the non-periodic sequence generation unit, generates irregular sequences (such as +-++--) in real time through an internal algorithm and outputs them synchronously within the row synchronization clock cycle.

[0089] A periodic polarity sequence is generated by a static mode register, enabling the entire column area to use a periodic polarity sequence. The output of the static mode register reduces the computational workload. An aperiodic polarity sequence is generated in real time using a variable-step finite state machine, allowing different flipping patterns to be displayed within the column window. By intelligently routing different sequence generation mechanisms through the judgment processing unit, the timing controller uses the optimal polarity sequence for the full-frame and slice areas, thereby achieving a dynamic balance between image quality and power consumption.

[0090] In some embodiments, such as Figure 9 and Figure 10As shown, the variable-step finite state machine includes a polarity state register, a target step size counter, a run counter, and a comparator. The polarity state register stores the current polarity state and outputs the polarity bit. The target step size counter receives a sequence of consecutive polarity rows and uses the value of each item in the sequence as the target step size. The run counter counts the actual number of consecutive rows in the current polarity state in real time. The comparator is used to compare the run counter value with the target step size counter value in real time, and is also used to: maintain the current polarity state of the polarity state register and increment the run counter in response to the run counter value being less than the target step size counter value; and reverse the current polarity state of the polarity state register, reset the run counter, and load the next item value of the sequence group into the target step size counter in response to the run counter value being equal to the target step size counter value.

[0091] The polarity status register serves as the core state storage unit, used to record the current polarity state (positive or negative) in real time. Its location is directly connected to the output of the comparator, ensuring that polarity inversion instructions can be transmitted quickly.

[0092] The target step counter serves as a dynamic parameter configuration unit, used to preset the number of rows that the current polarity should be maintained continuously.

[0093] The run counter, acting as a real-time accumulation unit, accumulates the actual number of rows whose current polarity has been maintained. Its output is connected to the comparison input of the comparator. The comparator, acting as a logic control unit, compares the run counter value with the target step counter value in real time. When the run counter value is less than the target step counter value, the comparator outputs a maintain current polarity instruction, causing the run counter to increment. When the run counter value equals the target step counter value, the comparator triggers the polarity status register to flip the polarity, simultaneously resetting the run counter and loading the next value of the polarity continuous row sequence into the target step counter to adjust the step size for the next cycle.

[0094] The run counter can be configured to accumulate using a synchronous clock, ensuring precise alignment with the line synchronous clock cycle. This design is based on the dynamic updating of the target step size, allowing the polarity sequence to naturally adapt to the vertical changes in the screen content.

[0095] Based on a variable-step finite state machine, using the polarity continuous row sequence as a reference, the current number of polarity continuous rows is accumulated in real time by a run counter: when the run counter value is less than the target step counter value, the polarity bit is output and the current polarity state is maintained, and the run counter is incremented; when the run counter value is equal to the target step counter value, the polarity bit of the current row is output, the polarity state of the polarity state register is reversed (that is, the polarity state of the current row is flipped to obtain the polarity state of the next row), the run counter is reset, and the next value of the polarity continuous row sequence is loaded into the target step counter; until all target step sizes are processed, a complete polarity sequence of a single data line within a frame is generated.

[0096] The number of terms in a polarity continuous row series is equal to the total number of polarity continuous periods. The value of the i-th term in a polarity continuous row series is the number of rows that maintain a single polarity continuously within the i-th polarity continuous period.

[0097] For example: the polarity sequence to be generated is +-++--+++---; Polar continuous periodic division: [+][-][++][--][+++][---]; Polar continuum series: [1, 1, 2, 2, 3, 3].

[0098] For example, the specific illustration is based on generating an increasing sequence of +-++--+++--- using a variable step-size finite state machine. The target step size is ordered as [1, 1, 2, 2, 3, 3].

[0099] Execution flow when each line synchronization clock (H-Sync) pulse arrives: Line 1 (H1): Target step size = 1. Polarity status register outputs +. Run counter reaches 1, target step size is met. Reset run counter, toggle polarity status of polarity status register to -, update target step size.

[0100] Line 2 (H2): Target step size = 1. Polarity status register outputs -. The run counter reaches 1, satisfying the target step size. At this point, a complete positive and negative cycle ends (i.e., the polarity sequence of the first two lines +-). Update the target step size, reset the run counter, and flip the polarity status of the polarity status register to + (i.e., flip the polarity status of the current line - to get the polarity status of the next line +).

[0101] Line 3 (H3): Target step size = 2. Polarity status register output +. Run counter = 1 (not full). Maintain the polarity status register as +.

[0102] Line 4 (H4): Target step size = 2. Polarity status register outputs +. The run counter reaches 2, satisfying the target step size. The run counter is reset, and the polarity status register is toggled to -.

[0103] Line 5 (H5): Target step size = 2. Polarity status register output -. Run counter = 1 (not full). Maintain the polarity status of the polarity status register as -.

[0104] Line 6 (H6): Target step size = 2. Polarity status register outputs -. Run counter reaches 2, satisfying the target step size. One round ends (i.e., the polarity sequence ++-- in lines 3 to 6), and the target step size is updated to 3. This process continues until all target step sizes are traversed to generate a complete polarity sequence for a single data line within a frame.

[0105] The polarity state register stores the current polarity state, enabling the system to precisely control the timing of polarity reversals and avoid response delays in liquid crystal molecules caused by sudden polarity changes. A target step size counter presets the current number of consecutive polarity rows, allowing the polarity sequence to dynamically adjust its step size based on the screen content, thus balancing performance and display quality. A running counter accumulates the actual number of rows, allowing the system to accurately count the number of consecutive polarity rows, achieving precise control of the polarity sequence. A comparator compares the running counter value and the target step size counter value in real time, enabling the system to automatically trigger polarity reversals and step size adjustments, thereby achieving the infinite extension of non-periodic polarity sequences.

[0106] In some embodiments, the timing controller further includes a DC balancing module connected to the polarity generation module, for accumulating the net polarity value in real time, and outputting a polarity reversal command to the polarity generation module within a preset period when the absolute value of the net polarity value exceeds a preset threshold.

[0107] The DC balancing module, as an internal auxiliary unit of the timing controller, is located between the output and input terminals of the polarity generation module, and achieves data interaction through signal connection. The DC balancing module has a built-in hardware accumulator that accumulates the polarity bit values ​​output by the polarity generation module in real time, with positive polarity bits corresponding to +1 and negative polarity bits corresponding to -1, forming a net cumulative polarity value. When the absolute value of the net cumulative polarity value exceeds a preset threshold within a preset period, the DC balancing module triggers an output polarity reversal command to the polarity generation module.

[0108] The working process is as follows: Driven by the row synchronization clock, the accumulator continuously accumulates the value of each polarity row in the polarity sequence; when the absolute value reaches the threshold, a polarity reversal instruction is immediately generated; after receiving the polarity reversal instruction, the polarity generation module adjusts the polarity sequence to be generated in the next frame to neutralize the charge accumulation. The preset period can be set to one or more frames or a fixed interval.

[0109] By continuously accumulating the net polarity value, the system can monitor the DC charge accumulation state of liquid crystal molecules, thereby preventing polarization aging caused by long-term DC bias. By responding to the absolute value of the net polarity accumulation exceeding a preset threshold within a preset period, the balance triggering mechanism is synchronized with the display frame cycle, reducing interference with the image display. By outputting a polarity reversal command to the polarity generation module, the polarity sequence can be automatically adjusted to neutralize charge accumulation, thus extending the lifespan of the LCD.

[0110] In some embodiments, the timing controller further includes a global reset module for resetting the variable step size finite state machine at the instant the vertical synchronization signal is emitted.

[0111] The target step counter bit width of a variable-step finite state machine is limited by the driver chip process and cannot be infinitely large. Without a timing-bound global reset mechanism, when the cumulative step value of the variable-step finite state machine exceeds the bit width, it will lead to counter overflow and polarity sequence breakage.

[0112] The global reset trigger point is deeply coupled with the frame scan timing. At the instant the vertical synchronization signal (V-sync) is emitted (i.e., the end of the current frame scan), a global reset is triggered, resetting all counters (target step size counter, running counter) to their initial state. This improves the issues of counter overflow and polarity sequence breakage. Simultaneously, the reset dynamically returns the net polarity accumulation value of the DC balancing module to zero, forming a closed-loop optimization with the DC balancing mechanism to avoid DC offset.

[0113] In some embodiments, the timing controller further includes a row cache module, which is used to cache the current row and at least three subsequent rows of image data to meet the computational latency requirements of dynamic polarity bit generation.

[0114] The dynamic generation of polarity bits requires computation time. If the raw image data is used directly, it will cause the polarity instructions to be misaligned with the image data (when the computation delay is greater than one line, the polarity bit generation of the current line will be later than the image data transmission) or display abnormalities (such as screen tearing). Cache at least three lines of data (the current line + the next two lines) to ensure that the polarity generation module has enough time to complete the variable step size sequence calculation.

[0115] In some embodiments, the timing controller further includes a receiving module configured to receive a video data stream from a graphics processing unit (GPU) or a system-on-a-chip (SoC). The video data stream is transmitted via the Embedded Display Port (eDP) protocol or the Mobile Industry Processor Interface Display Serial Interface (MIPI DSI) protocol.

[0116] The receiving module is connected to the image analysis module and the line buffer module respectively to transmit video data streams to the image analysis module and the line buffer module.

[0117] In some embodiments, the timing controller further includes a packaging module, which is connected to the outputs of the line buffer module and the polarity generation module, respectively. During the horizontal blank period, the packaging module maps the current line polarity bit (such as + / -) output by the polarity generation module to the polarity field (POL) position preset by the existing interface protocol (e.g., the independent control signal bit of the Mini-LVDS protocol or the differential data field of the ISP protocol). The packaging module encapsulates the current line image data and the current line polarity bit stored in the line buffer module into a data packet and sends it to the source driver chip to align the polarity bit with the image data in timing.

[0118] It reuses existing protocol fields (POL signal lines of Mini-LVDS or POL data fields of ISP) without adding extra pins or protocols; the horizontal blank period is a data transmission window reserved for the protocol, and the data packet encapsulation and transmission completely avoid the display refresh cycle; the polarity bit and image data are strictly synchronized at the receiving end of the source driver chip to avoid display abnormalities caused by timing offset.

[0119] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0120] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A control method of a timing controller, characterized by, include: The screen to be displayed is divided into multiple sub-screens based on the characteristics of the screen content, and the polarity flipping method of each sub-screen is determined. Based on the column spatial distribution characteristics and polarity reversal method of each sub-screen, when the synchronization clock arrives at each row, the polarity bit matching the sub-screen is output row by row.

2. The control method of a timing controller according to claim 1, wherein Based on the column spatial distribution characteristics and polarity inversion method of each sub-screen, when each row synchronization clock arrives, the polarity bit matching the sub-screen is output row by row, including: In response to the sub-screen being a full-width column area, the polarity bits are output row by row based on the polarity flipping method; In response to the sub-screen being a column-sliced ​​region, polarity bits are dynamically generated and output row by row based on the polarity flipping method of all sub-screens within the same column-oriented window and the pixel row sequence occupied by each sub-screen.

3. The control method of a timing controller according to claim 2, wherein In response to the sub-screen being a column-sliced ​​region, the polarity bits are dynamically generated and output row by row based on the polarity flipping method of all sub-screens within the same column-oriented window and the pixel row sequence occupied by each sub-screen, including: The sub-pictures within the same column-oriented window are sorted according to the row scanning direction, and the polarity continuous row sequence of the entire column-oriented window is determined based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies; wherein each item of the polarity continuous row sequence represents the number of consecutive rows with the same polarity within the column-oriented window; The polarity bits are dynamically generated and output row by row, with the item values ​​in the continuous polarity row sequence as the target step size.

4. The control method of a timing controller according to claim 3, wherein The step of dynamically generating and outputting polarity bits row by row, with the item values ​​in the consecutive polarity row sequence as the target step size, includes: Initialize the target step size counter to the first value of the polarity continuous row sequence, and accumulate the number of rows in the current polarity state by running the counter; In response to the running counter value being less than the target step counter value, the polarity bit is output and the current polarity state is maintained, and the running counter is incremented; In response to the running counter value being equal to the target step counter value, the polarity bit is output, the polarity state of the polarity status register is reversed, the running counter is reset, and the next item value of the sequence group is loaded into the target step counter; This continues until all values ​​in the polarity consecutive row sequence have been traversed.

5. The control method for the timing controller according to claim 2, characterized in that, The control method of the timing controller further includes: Accumulate the net polarity value of the current frame in real time; Within a preset period, in response to the absolute value of the net cumulative value of polarity exceeding a preset threshold, a polarity reversal command is output to reverse the polarity of the current frame in the next frame.

6. The control method of a timing controller according to claim 2, wherein The control method of the timing controller further includes: Cache the current row and at least three subsequent rows of image data; During the horizontal blank period, the cached current row image data and the current row polarity bit are synchronized and encapsulated into a data packet, and sent through the source driver chip interface.

7. A timing controller configured to execute the control method of the timing controller according to any one of claims 1 to 6. include: The image analysis module is used to divide the screen to be displayed into multiple sub-screens based on the characteristics of the screen content, and to determine the polarity sequence of each sub-screen; The polarity generation module is used to output the polarity bit that matches the sub-screen line by line when the synchronization clock arrives, based on the column spatial distribution characteristics and polarity flipping method of each sub-screen.

8. The timing controller of claim 7, wherein, The polarity generation module includes a judgment and processing unit, a static mode register, and a variable step-size finite state machine; the judgment and processing unit is used to analyze the column spatial distribution characteristics of each sub-screen, and is also used for: In response to the sub-screen being a full-width column area, the polarity inversion mode is output to the static mode register; In response to the sub-picture being a column-sliced ​​region, the sub-pictures within the same column-sliced ​​window are sorted according to the row scanning direction. Based on the polarity flipping method of each sub-picture and the pixel row sequence it occupies, a polarity continuous row sequence is determined and output to the variable step size finite state machine. The static mode register receives polarity inversion mode and outputs polarity bits row by row to the variable step size finite state machine; The variable-step finite state machine receives the polarity continuous row sequence and the polarity bit output by the static mode register, and generates and outputs the final polarity bit row by row, using the item value of the polarity continuous row sequence as the target step size.

9. The timing controller of claim 8, wherein, The variable step size finite state machine includes a polarity state register, a target step size counter, a running counter, and a comparator; The polarity status register stores the current polarity status to output the polarity bit; The target step size counter receives the polarity continuous row sequence and sequentially uses the item values ​​of the polarity continuous row sequence as the target step size; The running counter counts the actual number of consecutive rows in the current polarity state in real time. The comparator is used to compare the run counter value with the target step size counter value in real time, and is also used for: In response to the running counter value being less than the target step counter value, the current polarity state of the polarity status register is maintained, and the running counter is incremented; In response to the run counter value being equal to the target step counter value, the current polarity state of the polarity state register is reversed, the run counter is reset, and the next value of the sequence group is loaded into the target step counter.

10. The timing controller of claim 7, wherein, The timing controller also includes a DC balancing module connected to the polarity generation module, which is used to accumulate the net polarity value in real time, and within a preset period, when the absolute value of the net polarity value exceeds a preset threshold, outputs a polarity reversal command to the polarity generation module.

Images