Memory devices and memory operation methods
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2026-08-11
Smart Images
Figure CN122551839A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory operation method, and more particularly to a memory device capable of performing product operations. Background Technology
[0002] As computer processing speeds increase, the demands on memory speed and stability also rise. Given the diverse market demands, how to improve memory applications so that it can not only read and write data but also function as part of computational processing has become a major challenge. Summary of the Invention
[0003] This invention provides a memory operation method, comprising: obtaining an operation code for vector-matrix operations through a processing circuit, wherein the processing circuit is coupled to a memory array, the memory array includes multiple memory strings, and the operation code includes multiple operation bits; converting a first portion of these operation bits into a first conversion code, wherein the format of the first conversion code is different from the format of the operation code; and inputting the first conversion code and a second portion of these operation bits as input data to a corresponding memory string, so that the memory strings generate an output signal according to multiple weight values. Accordingly, by splitting the operation code into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.
[0004] In one embodiment, the first portion includes the most significant bit of these operands. Since higher-order bits are more susceptible to transmission noise and thus cause greater errors, converting the most significant bit can improve the noise reduction ratio during computation.
[0005] In one embodiment, the first portion of these operands is a higher bit compared to the second portion. As mentioned earlier, higher bits are more susceptible to transmission noise, resulting in greater errors; therefore, this approach improves the noise reduction ratio during computation.
[0006] In one embodiment, the number of bits in the first part accounts for 40% to 60% of the total number of operational bits. Accordingly, the data transmission time can be effectively controlled.
[0007] In one embodiment, the number of bits in the first part is greater than the number of bits in the second part. Accordingly, converting the first part into a unary coding format will more clearly demonstrate the characteristics of unary coding and reduce noise interference.
[0008] In one embodiment, the number of bits in the first part accounts for 70% to 95% of the total number of bits in the operation. Accordingly, the characteristics of unary coding can be more clearly utilized, and noise interference can be reduced.
[0009] In one embodiment, the method of using the first conversion code and the second portion of these operands as input data further includes: converting the second portion of these operands into a second conversion code, wherein the format of the first conversion code is the same as the format of the second conversion code. Accordingly, the noise reduction ratio during computation can be effectively improved.
[0010] In one embodiment, the first conversion encoding is in unary encoding format. Unary encoding format can reduce noise interference during signal transmission.
[0011] In one embodiment, the operation encoding format is binary encoding. The binary encoding format will ensure transmission efficiency.
[0012] In one embodiment, the memory operation method further includes: receiving a plurality of output currents from the memory arrays; and calculating a total current value of the output currents to obtain an output signal. By summing the current values of the memory arrays, vector matrix operations can be performed using the memory array.
[0013] Another aspect of the present invention provides a memory device comprising a memory array, a sensing circuit, and a processing circuit. The memory array is coupled to a plurality of word lines and a plurality of bit lines, and includes a plurality of memory strings. The sensing circuit is coupled to the memory array to obtain an output signal from the memory array. The processing circuit is coupled to the memory array and is used to generate an operational code based on operational data of a vector matrix operation, the operational code including a plurality of operational bits. The processing circuit is used to: convert a first portion of these operational bits into a first conversion code, wherein the format of the first conversion code is different from the format of the operational code; and input the first conversion code and a second portion of these operational bits as input data to a corresponding one of the memory strings, so that the memory strings generate an output signal according to a plurality of weight values. Accordingly, by splitting the operational code into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.
[0014] In one embodiment, the first portion includes the most significant bit of these operands. Since higher-order bits are more susceptible to transmission noise and thus cause greater errors, converting the most significant bit can improve the noise reduction ratio during computation.
[0015] In one embodiment, the first portion of these operands is a higher bit compared to the second portion. As mentioned earlier, higher bits are more susceptible to transmission noise, resulting in greater errors; therefore, this approach improves the noise reduction ratio during computation.
[0016] In one embodiment, the number of bits in the first part accounts for 40% to 60% of the total number of operational bits. Accordingly, the data transmission time can be effectively controlled.
[0017] In one embodiment, the number of bits in the first part is greater than the number of bits in the second part. Accordingly, converting the first part into a unary coding format will more clearly demonstrate the characteristics of unary coding and reduce noise interference.
[0018] In one embodiment, the number of bits in the first part accounts for 70% to 95% of the total number of bits in the operation. Accordingly, the characteristics of unary coding can be more clearly utilized, and noise interference can be reduced.
[0019] In one embodiment, the processing circuit is further configured to convert a second portion of these operational bits into a second conversion code, wherein the format of the first conversion code is the same as that of the second conversion code. This effectively improves the noise reduction ratio during computation.
[0020] In one embodiment, the first conversion encoding is in unary encoding format. Unary encoding format can reduce noise interference during signal transmission.
[0021] In one embodiment, the operation encoding format is binary encoding. The binary encoding format will ensure transmission efficiency.
[0022] In one embodiment, the memory operation method further includes: receiving a plurality of output currents from the memory arrays; and calculating a total current value of the output currents to obtain an output signal. By summing the current values of the memory arrays, vector matrix operations can be performed using the memory array. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a memory device according to a partial embodiment of the present invention.
[0024] Figure 2 This is a schematic diagram of a storage string according to a partial embodiment of the present invention.
[0025] Figure 3A This is a schematic diagram of the computational encoding according to some embodiments of the present invention.
[0026] Figure 3B This is a schematic diagram of the computational encoding according to some embodiments of the present invention.
[0027] Figure 4 This is a schematic diagram of the computational encoding according to some embodiments of the present invention.
[0028] Figure 5 This is a flowchart of a memory operation method according to a partial embodiment of the present invention.
[0029] Figure 6 This is a schematic diagram of a modified array according to a partial embodiment of the present invention.
[0030] Figure 7AThis is a schematic diagram illustrating the operation of a memory device according to a partial embodiment of the present invention.
[0031] Figure 7B This is a schematic diagram illustrating the operation of a memory device according to a partial embodiment of the present invention.
[0032] Explanation of reference numerals in the attached figures:
[0033] 100: Memory device
[0034] 110: Memory Array
[0035] 120: Processing circuit
[0036] 121: Control Circuit
[0037] 122: Encoding Circuit
[0038] 130: Sensing Circuit
[0039] 210: Calculation weight unit
[0040] 220: Balanced Weight Unit
[0041] 230: Serial weighted unit
[0042] 310A: Computational Data
[0043] 320A: Operational Encoding
[0044] 330A: Encoding Array
[0045] 310B: Computational data
[0046] 320B: Operational encoding
[0047] 330B: Encoded Array
[0048] 400: Operation code
[0049] 410: Part One
[0050] 420: Part Two
[0051] 600: Modify Array
[0052] 711-714: Available Areas
[0053] A0-A6: Operands
[0054] BL1-BLN: Bit lines
[0055] BLS: Bit Line
[0056] BLK: Storage Block
[0057] BLKS: Storage Blocks
[0058] CA1-CAP: Storage Unit
[0059] CB1-CBP: Storage Unit
[0060] CN1-CNP: Storage unit
[0061] CSL: Common Source Line
[0062] CX1-CXQ: Transistor Unit
[0063] CY1-CYQ: Transistor Units
[0064] CZ1-CZQ: Transistor Unit
[0065] D70: Calculation Data
[0066] D71-D74: Section Data
[0067] MR: Serial Storage
[0068] MR1-MRN: Storage Serial
[0069] RS1-RSN: Impedance element
[0070] S501-S504: Steps
[0071] WL11-1: Word Line
[0072] WL12-1: Word Line
[0073] WL13-1: Word Line
[0074] WL1P-1: Wordline
[0075] WL11-2: Word Line
[0076] WL12-2: Word Line
[0077] WL13-2: Word Line
[0078] WL1P-2: Wordline
[0079] WL11-N: Word Line
[0080] WL12-N: Word Line
[0081] WL13-N: Word Line
[0082] WL1P-N: Wordline
[0083] WL21-1: Word Line
[0084] WL22-1: Word Line
[0085] WL2Q-1: Word Line
[0086] WL21-2: Word Line
[0087] WL22-2: Word Line
[0088] WL2Q-2: Word Line
[0089] WL21-N: Word Line
[0090] WL22-N: Word Line
[0091] WL2Q-N: Word Line
[0092] WL31-WL3N: Word Lines Detailed Implementation
[0093] The following describes several embodiments of the present invention with reference to the accompanying drawings. For clarity, many practical details will be described in conjunction with the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some known and conventional structures and elements will be shown in the drawings in a simple schematic manner.
[0094] In this document, when an element is referred to as a "connection" or "coupled," it may mean an "electrical connection" or "electrical coupling." "Connection" or "coupled" can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as "first," "second," etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.
[0095] Figure 1 The diagram shown is a schematic of a memory device 100 according to a partial embodiment of the present invention. The memory device 100 is used to implement an in-memory computing (IMC) architecture and can perform vector-matrix multiplication (VMM), such as the multiply-and-accumulate (MAC) operation commonly used in artificial intelligence technology.
[0096] The memory device 100 includes a memory array 110, a processing circuit 120, and a sensing circuit 130. The memory array 110 is coupled to the processing circuit 120 via multiple word lines and multiple bit lines, and includes multiple memory blocks BLK. Each memory block BLK includes multiple memory strings MR, and each memory string MR includes multiple memory cells (or unit cells). In one embodiment, the memory string MR is a NAND flash memory.
[0097] Processing circuit 120 is coupled to memory array 110 via word lines and bit lines to provide relevant data for vector matrix operations. In one embodiment, processing circuit 120 may be divided into control circuit 121 and encoding circuit 122. Control circuit 121 is used to provide initial data for vector matrix operations, and encoding circuit 122 is used to encode this initial data for input to memory array 110. The composition of processing circuit 120 is not limited to... Figure 1 As shown in the diagram, in the following paragraphs, the actions of the processing circuit 120 can be performed by either the control circuit 121 or the encoding circuit 122.
[0098] When performing vector matrix operations, the processing circuit 120 provides the input values (hereinafter referred to as "operation data") of the vector matrix operation to the memory array 110 through word lines and bit lines, and the memory array 110 generates an output signal (such as output current) according to multiple internally preset weight values.
[0099] Sensing circuit 130 is coupled to memory array 110 to obtain an output signal from memory array 110. In one embodiment, sensing circuit 130 receives the output current of a plurality of memory arrays MR and calculates the total current value of all output currents to generate an output signal. In one embodiment, sensing circuit 130 also calculates the total impedance based on the total current as the output signal (i.e., the result of the calculation).
[0100] Figure 2 The diagram shown is a partial schematic of a storage serial array according to a partial embodiment of the present invention. Storage serial arrays MR1 to MRN can be applied to... Figure 1 Any of the storage blocks BLK shown. Figure 2 The storage strings MR1 to MRN shown are two-dimensional structures, but in other embodiments, the storage block BLK may also contain a three-dimensional storage string structure.
[0101] Please see Figure 1 and Figure 2As shown, the memory arrays MR1 to MRN each contain multiple memory cells CA1 to CAP, CB1 to CBP, and CN1 to CNP, each with a specific weight value. Taking a "multiply-accumulate" operation as an example, the "weight value" can be the product coefficient used in artificial intelligence / neural networks. This "weight value" can be determined by the conductance (or impedance) value of each memory cell, and the conductance value of a memory cell depends on its threshold voltage. By applying a voltage to each memory cell, the amount of charge in the floating gate can be controlled, thereby changing the threshold voltage.
[0102] Here Figure 2 Taking the structure shown as an example, the operation of the storage strings during vector matrix operations is further explained as follows: In one embodiment, the storage strings MR1 to MRN receive read voltages through bit lines BL1 to BLN, and simultaneously receive their respective operation data through word lines WL11-1 to WL1P-1, word lines WL11-2 to WL1P-2, and word lines WL11-N to WL1P-N (e.g., word line WL11-1 provides operation data to storage cell CA1, and word line WL11-2 provides operation data to storage cell CB1). The storage strings MR1 to MRN will generate cell currents according to internally set weight values, as well as the received read voltages and operation data. All cell currents will be output to the sensing circuit 130 through the common source line CSL to calculate the operation results. In one embodiment, the processing circuit 120 can generate an operation code (e.g., binary encoding) for each operation data as a digital voltage signal; details will be described in subsequent paragraphs.
[0103] In some embodiments, the aforementioned "weight values" can be divided into computational weight values, balancing weight values, and series weight values. The aforementioned storage units CA1-CAP, CB1-CBP, and CN1-CNP in the storage string serve as computational weight units 210 and are each assigned a computational weight value. Each storage string may also include at least one balancing weight unit 220 and at least one series weight unit 230. The balancing weight unit 220 is used to adjust the equivalent impedance value of each storage string and can be used to adjust the standard deviation of the distribution of all weight values. The impedance of the series weight unit 230 depends on the overall impedance of each storage string, ensuring that each storage string has a basic impedance value. In other words, the balancing weight unit 220 and the series weight unit 230 are not directly used for multiplication operations, but rather to adjust the overall impedance of the storage strings to make the computational results of the sensing circuit 130 more accurate.
[0104] Specifically, the computational weight unit 210 and the balancing weight unit 220 can be implemented using the same type of storage unit, such as... Figure 2The transistor units CX1~CXQ, CY1~CYQ, and CZ1~CZQ are labeled. The balancing weight units 220 in the storage serial array can also receive their respective setting signals via their respective word lines WL21-1~WL2Q-1, WL21-2~WL2Q-2, and WL21-N~WL2Q-N to set their respective balancing weight values. The series weight units 230 can be implemented by impedance elements RS1~RSN (e.g., resistors) and can receive their respective setting signals via their respective word lines WL31~WL3N to set their respective series weight values.
[0105] For ease of understanding, the input method of the "operation data" (i.e., the input values of vector matrix operations) to the processing circuit 120 is described here. The processing circuit 120 converts the operation data into operation codes, and each operation code contains multiple operation bits. The processing circuit 120 inputs the operation codes into the corresponding memory strings for operation. For example, if the operation data for vector matrix operations contains multiple values such as "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", then the processing circuit 120 can convert each operation data into a code of a specific format and apply it as a digital voltage signal to the corresponding memory string.
[0106] The operational codes generated by the processing circuit 120 can be represented by an encoding array. Figure 3A The diagram shows a schematic of an encoding array 330A according to a partial embodiment of the present invention. In this embodiment, the operational data 310A is "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", and the processing circuit 120 converts the operational data 310A into a binary encoded format. For example, when the "9" in the operational data 310A is converted into a binary encoded format, the corresponding operational code 320A is "1, 0, 0, 1", containing four operational bits, and all operational codes can be organized into an encoding array 330A. During the operation, the processing circuit 120 inputs each operational bit in each operational code into the corresponding storage string column, using each column of the encoding array 330A as a unit.
[0107] However, due to the imperfect characteristics of electronic components and noise in signal transmission, the calculation results of vector matrix operations will contain errors. Binary encoded data is highly sensitive to noise during computation, easily leading to excessively large errors in the results. Therefore, in some embodiments, the processing circuit 120 converts the computation data into a "Unary Code (or Thermometer Code)" format. This format can reduce the problem of serious misinterpretation caused by slight transmission errors during data transmission.
[0108] Unary encoding uses the number of 1 bits to represent a value. Therefore, even if a few bits are erroneous during data transmission, the actual value read will not differ too much from the true value. Figure 3B The diagram shows a schematic of an encoding array 330B according to a partial embodiment of the present invention. In this embodiment, the operational data 310B is also "9, 4, 11, 10, 6, 4, 10, 4, 9, 10, 15, 9, 12, 9, 14, 9, 12, 11, 7, 5", but the processing circuit 120 converts the operational data 310B into a unary encoding format. For example, when the "9" in the operational data 310B is converted into unary encoding, its operational encoding 320B is "0000000111111111", containing 9 encoding bits "1". All operational encodings 320B can be organized into an encoding array 330B, and each column of the encoding array 330B will correspond to one piece of operational data.
[0109] Taking the aforementioned embodiment as an example, when the computation is encoded in a unary coding format, the impact of transmission noise can be reduced by 5.68 times, thus reducing the error in the computation result. However, since the unary coding format has a large number of bits (e.g., 16 bits), it is also more time-consuming to transmit. In other words, the unary coding format has an advantage in dealing with noise, but a disadvantage in transmission time.
[0110] This invention divides the computational encoding into multiple parts for processing, in order to balance noise reduction ratio and transmission efficiency. Figure 4 The diagram shows a schematic of an operational code 400 according to a partial embodiment of the present invention. The operational code 400 includes a plurality of operational bits A0 to A6. In one embodiment, the operational code 400 / operational bits A0 to A6 are in binary code format, but the present invention is not limited thereto, and the processing circuit 120 may also organize the operational bits of the operational code 400 into octal, decimal or hexadecimal format.
[0111] The operands A0 to A6 can be divided into a first part 410 and a second part 420. For example, if the operation code is "1010011", then the first part 410 can be the first four operands A6 to A3 "1010", and the second part is the last three operands A2 to A0 "011". The number of bits contained in the first part 410 and the second part 420 can be set according to the requirements.
[0112] The processing circuit 120 converts the first part 410 into another format (e.g., unary encoding), while the second part 420 can retain its original format, or the processing circuit 120 can also convert the second part 420 into another format. Accordingly, by splitting the operation bits A0 to A6 into multiple parts, the noise reduction ratio can be improved while ensuring transmission efficiency.
[0113] For example, the decimal arithmetic data "83" corresponds to the binary code "1010011". If the complete arithmetic code "1010011" is directly converted to unary code format, it will have at least 83 bits (because it requires 83 "1"s). If the arithmetic code "1010011" is split into a first part 410 ("1010") and a second part 420 ("011"), the four arithmetic bits "1010" in the first part 410 correspond to the decimal value "10", that is, the unary code is "1111111111". Similarly, the three arithmetic bits "011" in the second part 420 correspond to the decimal value "3", that is, the unary code is "0000000111". Therefore, if the arithmetic data is divided into two parts and converted to unary codes respectively, it will only require a minimum of 13 bits (10 "1"s and 3 "1"s). Therefore, it can be seen that splitting the operation bits A0 to A6 into multiple parts can effectively reduce the time required for data transmission, that is, reduce the number of bits that need to be transmitted.
[0114] For ease of explanation, here we will use Figure 5 The diagram illustrates the memory operation method of the present invention. Please refer to the accompanying documentation. Figure 1 , Figure 4 and Figure 5 In step S501, the processing circuit 120 obtains at least one piece of operation data (e.g., "83") for vector matrix operation and converts the operation data into operation code 400, which includes multiple operation bits A0 to A6. In other embodiments, the processing circuit 120 may generate multiple operation codes for multiple operation data simultaneously.
[0115] In step S502, the processing circuit 120 divides the operation bits A0 to A6 into multiple parts, for example... Figure 4 The first portion 410 and the second portion 420 are shown. In some embodiments, the number of bits included in the first portion 410 and the second portion 420 can be adjusted as needed, and the method of splitting the operation bits can be preset in the processing circuit 120.
[0116] In step S503, the processing circuit 120 converts the first part 410 into a first conversion code, and the format of the first conversion code is different from the format of the original operation code. For example, the binary code "1010" is converted into a unary code (i.e., 10 "1"s).
[0117] In step S504, the processing circuit 120 inputs the first conversion code and the second part 420 as input data into the storage string MR, so that the storage string MR generates an output signal according to multiple internally set weight values. The processing circuit 120 can selectively convert the second part 420, for example, it can maintain the binary encoding format or convert it to the unary encoding format.
[0118] When performing the aforementioned step S503, the processing circuit 120 can maintain the encoding format of the second part 420 (e.g., binary encoding). In other words, the input data in step S504 will contain encodings of multiple different encoding formats.
[0119] Continuing from the above, in other embodiments, when performing the aforementioned step S503, the processing circuit 120 can convert the second part 420 into a second conversion code, and the format of the second conversion code is the same as that of the first conversion code. For example, the binary arithmetic code "011" is converted into a unary code (i.e., three "1"s). In other words, all the encodings of the input data in step S504 will be in the same encoding format. Accordingly, the noise reduction ratio during operation can be effectively improved.
[0120] In some embodiments, the first portion 410 of the operands A0 to A6 includes the most significant bit (MSB). For example, if the operands A0 to A6 are "1010011", then the first portion 410 includes at least the most significant bit (i.e., the first "1" on the left). Since higher bits are more susceptible to transmission noise and thus cause greater errors, converting the most significant bit can improve the noise reduction ratio during computation.
[0121] In some embodiments, the first part 410 of the operands A0 to A6 is a higher bit compared to the second part 420. Taking operands A0 to A6 as "1010011" as an example, the first part 410 consists of the first four operands "1010", and the second part 420 consists of the last three operands "011". In other words, each operand in the first part 410 is a higher bit than each operand in the second part 420. As mentioned earlier, higher bits are more susceptible to transmission noise, resulting in greater errors; therefore, this method can improve the noise reduction ratio during computation.
[0122] In some embodiments, the number of bits in the first part 410 and the second part 420 is similar. This allows for effective control of data transmission time. Taking the operands A0 to A6 as "1010011" as an example, the number of bits in the first part 410 (4 bits) accounts for 40% to 60% of all operands (7 bits). In other words, neither the first part 410 nor the second part 420 occupies an excessively large proportion. Therefore, even when both the first part 410 and the second part 420 are converted to a unary encoded format, the number of bits in each part after conversion will not be excessive, thus ensuring transmission speed and efficiency.
[0123] In other embodiments, the number of bits in the first part 410 is greater than the number of bits in the second part 420. Taking the operands A0 to A6 as "1010011" as an example, the first six operands "101001" can be used as the first part, and the last operand "1" can be used as the second part. Accordingly, after converting the first part into a unary encoding format, the characteristics of unary encoding can be more clearly utilized, and noise interference can be reduced. In one embodiment, the number of bits in the first part accounts for 70% to 95% of all operands.
[0124] Please see Figure 1 and Figure 3B As shown, in some embodiments, the processing circuit 120 can perform... Figure 5 Before proceeding with the method, the encoding array 330B formed by the operational encoding 320B is adjusted to make the distribution of bits "1" in the array more even. If the distribution of bits "1" in the array is more even, the standard deviation of the storage string distribution will be smaller, and the calculation results of the sensing circuit 130 will be more accurate.
[0125] Figure 6 This is a schematic diagram of a modified array 600 according to a partial embodiment of the present invention. In one embodiment, the processing circuit 120 is used to adjust the arrangement order of bits in each row of the encoding array 330B to reduce the distribution difference of bits "1" or bits "0" in the encoding array 330B. The adjusted encoding array 330B is the modified array 600.
[0126] Please refer to the accompanying text. Figure 1 , Figure 3B and Figure 6 Specifically, the processing circuit 120 directs all "bit 1s" in the odd-numbered rows of the encoding array 330B toward the first direction (e.g., ...). Figure 3B Move to the right; simultaneously, move all "bit 1" bits in the even-numbered rows of the encoding array 330B to the second direction (e.g., to the right); Figure 3BThe left side is moved, and the first and second directions are reversed to produce modified array 600. Accordingly, the degree of difference between each row of modified array 600 will be less than the degree of difference between each row of the original encoded array 330B.
[0127] In some embodiments, the processing circuitry can flexibly select the memory blocks to use based on the available space in the memory array 110. See also... Figure 1 , Figure 7A and Figure 7B As shown, Figure 7A and Figure 7B The following is another embodiment of the present invention, wherein Figure 7B This is a simplified partial schematic diagram of the memory array 110. The memory array 110 is coupled to multiple bit lines (BLS) and contains multiple memory blocks (BLKS). These memory blocks (BLKS) are located in multiple available regions 711 to 714, and available regions 711 to 712 are not adjacent to available regions 713 to 714. The processing circuit 120 can select multiple different available regions as computing regions to effectively utilize all the space within the memory array 110.
[0128] As mentioned above, since the computation area contains multiple different available areas, therefore, when executing the aforementioned... Figure 5 Before the memory operation method, the processing circuit 120 divides the operation data D70 into multiple data segments D71 to D74, and the number of data segments corresponds to the number of available regions 711 to 714. Then, the processing circuit 120 sequentially provides the data segments D71 to D74 to the storage string of the storage blocks BLKS in the available regions 711 to 714 according to the index order of the multiple storage blocks BLKS, so as to perform vector matrix operations.
[0129] The elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of textual description or graphical presentation in this invention.
[0130] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A memory operation method, comprising: An operation code for a vector matrix operation is obtained through a processing circuit, wherein the processing circuit is coupled to a memory array, the memory array contains multiple memory columns, and the operation code contains multiple operation bits. A first portion of these operands is converted into a first conversion code, wherein the format of the first conversion code differs from the format of the operand code; and The first conversion code and a second portion of these operational bits are input as input data to a corresponding one of these memory strings, so that these memory strings generate an output signal according to multiple weight values.
2. The memory operation method of claim 1, wherein the first portion comprises a most significant bit of the operands.
3. The memory operation method according to claim 2, wherein the first portion of the operation bit is a higher bit compared to the second portion.
4. The memory operation method according to claim 1, wherein the number of bits in the first part accounts for 40% to 60% of the number of operational bits.
5. The memory operation method according to claim 1, wherein the number of bits in the first part is greater than the number of bits in the second part.
6. The memory operation method according to claim 5, wherein the number of bits in the first portion accounts for 70% to 95% of the number of operand bits.
7. The memory operation method according to claim 1, wherein the method of using the first conversion code and the second portion of these operational bits as the input data further comprises: The second part of these operands is converted into a second conversion code, wherein the format of the first conversion code is the same as that of the second conversion code.
8. The memory operation method according to claim 1, wherein the format of the first conversion encoding is unary encoding.
9. The memory operation method according to claim 1, wherein the format of the operation encoding is binary encoding.
10. The memory operation method according to claim 1, further comprising: Receives multiple output currents from these storage serial lines; and Calculate the total current value of these output currents to obtain the output signal.
11. A memory device comprising: A memory array coupled to multiple word lines and multiple bit lines, and containing multiple memory serial lines; A sensing circuit is coupled to the memory array to obtain an output signal from the memory array; as well as A processing circuit, coupled to the memory array, is used to generate an operation code based on an operation data of a vector matrix operation, wherein the operation code contains a plurality of operation bits; This processing circuit is also used for: A first portion of these operands is converted into a first conversion code, wherein the format of the first conversion code is different from the format of the operand code; as well as The first conversion code and a second portion of these operational bits are input as input data to a corresponding one of these memory strings, so that these memory strings generate the output signal according to multiple weight values.
12. The memory device of claim 11, wherein the first portion includes a most significant bit of the operands.
13. The memory device of claim 12, wherein the first portion of the operational bits is a higher bit compared to the second portion.
14. The memory device of claim 11, wherein the number of bits in the first portion accounts for 40% to 60% of the number of operational bits.
15. The memory device of claim 11, wherein the number of bits in the first portion is greater than the number of bits in the second portion.
16. The memory device of claim 15, wherein the number of bits in the first portion accounts for 70% to 95% of the number of operational bits.
17. The memory device of claim 11, wherein the processing circuitry is further configured to: The second part of these operands is converted into a second conversion code, wherein the format of the first conversion code is the same as that of the second conversion code.
18. The memory device of claim 11, wherein the format of the first conversion encoding is unary encoding.
19. The memory device according to claim 11, wherein the format of the operation encoding is binary encoding.
20. The memory device of claim 11, wherein the sensing circuit is further configured to: Receives multiple output currents from these storage serial lines; and Calculate the total current value of these output currents to obtain the output signal.